drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DP83867 PHY
   4  *
   5  * Copyright (C) 2015 Texas Instruments Inc.
   6  */
   7
   8 #include <linux/ethtool.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/delay.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17
  18 #include <dt-bindings/net/ti-dp83867.h>
  19
  20 #define DP83867_PHY_ID          0x2000a231
  21 #define DP83867_DEVADDR         0x1f
  22
  23 #define MII_DP83867_PHYCTRL     0x10
  24 #define MII_DP83867_MICR        0x12
  25 #define MII_DP83867_ISR         0x13
  26 #define DP83867_CFG2            0x14
  27 #define DP83867_CFG3            0x1e
  28 #define DP83867_CTRL            0x1f
  29
  30 /* Extended Registers */
  31 #define DP83867_FLD_THR_CFG     0x002e
  32 #define DP83867_CFG4            0x0031
  33 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  34 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  35 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  36 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  37 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  38
  39 #define DP83867_RGMIICTL        0x0032
  40 #define DP83867_STRAP_STS1      0x006E
  41 #define DP83867_STRAP_STS2      0x006f
  42 #define DP83867_RGMIIDCTL       0x0086
  43 #define DP83867_RXFCFG          0x0134
  44 #define DP83867_RXFPMD1 0x0136
  45 #define DP83867_RXFPMD2 0x0137
  46 #define DP83867_RXFPMD3 0x0138
  47 #define DP83867_RXFSOP1 0x0139
  48 #define DP83867_RXFSOP2 0x013A
  49 #define DP83867_RXFSOP3 0x013B
  50 #define DP83867_IO_MUX_CFG      0x0170
  51 #define DP83867_SGMIICTL        0x00D3
  52 #define DP83867_10M_SGMII_CFG   0x016F
  53 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  54
  55 #define DP83867_SW_RESET        BIT(15)
  56 #define DP83867_SW_RESTART      BIT(14)
  57
  58 /* MICR Interrupt bits */
  59 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  60 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  61 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  62 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  63 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  64 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  65 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  66 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  67 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  68 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  69 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  70 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  71
  72 /* RGMIICTL bits */
  73 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  74 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  75
  76 /* SGMIICTL bits */
  77 #define DP83867_SGMII_TYPE              BIT(14)
  78
  79 /* RXFCFG bits*/
  80 #define DP83867_WOL_MAGIC_EN            BIT(0)
  81 #define DP83867_WOL_BCAST_EN            BIT(2)
  82 #define DP83867_WOL_UCAST_EN            BIT(4)
  83 #define DP83867_WOL_SEC_EN              BIT(5)
  84 #define DP83867_WOL_ENH_MAC             BIT(7)
  85
  86 /* STRAP_STS1 bits */
  87 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  88
  89 /* STRAP_STS2 bits */
  90 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  91 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  92 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  93 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  94 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  95 #define DP83867_STRAP_STS2_STRAP_FLD            BIT(10)
  96
  97 /* PHY CTRL bits */
  98 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT       14
  99 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT       12
 100 #define DP83867_PHYCR_FIFO_DEPTH_MAX            0x03
 101 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK        GENMASK(15, 14)
 102 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK        GENMASK(13, 12)
 103 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
 104 #define DP83867_PHYCR_FORCE_LINK_GOOD           BIT(10)
 105
 106 /* RGMIIDCTL bits */
 107 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
 108 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
 109 #define DP83867_RGMII_TX_CLK_DELAY_INV  (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
 110 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
 111 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT        0
 112 #define DP83867_RGMII_RX_CLK_DELAY_INV  (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
 113
 114
 115 /* IO_MUX_CFG bits */
 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
 117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
 118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 119 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 120 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
 121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 122
 123 /* CFG3 bits */
 124 #define DP83867_CFG3_INT_OE                     BIT(7)
 125 #define DP83867_CFG3_ROBUST_AUTO_MDIX           BIT(9)
 126
 127 /* CFG4 bits */
 128 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
 129
 130 /* FLD_THR_CFG */
 131 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK        0x7
 132
 133 enum {
 134         DP83867_PORT_MIRROING_KEEP,
 135         DP83867_PORT_MIRROING_EN,
 136         DP83867_PORT_MIRROING_DIS,
 137 };
 138
 139 struct dp83867_private {
 140         u32 rx_id_delay;
 141         u32 tx_id_delay;
 142         u32 tx_fifo_depth;
 143         u32 rx_fifo_depth;
 144         int io_impedance;
 145         int port_mirroring;
 146         bool rxctrl_strap_quirk;
 147         bool set_clk_output;
 148         u32 clk_output_sel;
 149         bool sgmii_ref_clk_en;
 150 };
 151
 152 static int dp83867_ack_interrupt(struct phy_device *phydev)
 153 {
 154         int err = phy_read(phydev, MII_DP83867_ISR);
 155
 156         if (err < 0)
 157                 return err;
 158
 159         return 0;
 160 }
 161
 162 static int dp83867_set_wol(struct phy_device *phydev,
 163                            struct ethtool_wolinfo *wol)
 164 {
 165         struct net_device *ndev = phydev->attached_dev;
 166         u16 val_rxcfg, val_micr;
 167         u8 *mac;
 168
 169         val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 170         val_micr = phy_read(phydev, MII_DP83867_MICR);
 171
 172         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
 173                             WAKE_BCAST)) {
 174                 val_rxcfg |= DP83867_WOL_ENH_MAC;
 175                 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
 176
 177                 if (wol->wolopts & WAKE_MAGIC) {
 178                         mac = (u8 *)ndev->dev_addr;
 179
 180                         if (!is_valid_ether_addr(mac))
 181                                 return -EINVAL;
 182
 183                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
 184                                       (mac[1] << 8 | mac[0]));
 185                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
 186                                       (mac[3] << 8 | mac[2]));
 187                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
 188                                       (mac[5] << 8 | mac[4]));
 189
 190                         val_rxcfg |= DP83867_WOL_MAGIC_EN;
 191                 } else {
 192                         val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
 193                 }
 194
 195                 if (wol->wolopts & WAKE_MAGICSECURE) {
 196                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 197                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 198                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 199                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 200                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 201                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 202
 203                         val_rxcfg |= DP83867_WOL_SEC_EN;
 204                 } else {
 205                         val_rxcfg &= ~DP83867_WOL_SEC_EN;
 206                 }
 207
 208                 if (wol->wolopts & WAKE_UCAST)
 209                         val_rxcfg |= DP83867_WOL_UCAST_EN;
 210                 else
 211                         val_rxcfg &= ~DP83867_WOL_UCAST_EN;
 212
 213                 if (wol->wolopts & WAKE_BCAST)
 214                         val_rxcfg |= DP83867_WOL_BCAST_EN;
 215                 else
 216                         val_rxcfg &= ~DP83867_WOL_BCAST_EN;
 217         } else {
 218                 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
 219                 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
 220         }
 221
 222         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
 223         phy_write(phydev, MII_DP83867_MICR, val_micr);
 224
 225         return 0;
 226 }
 227
 228 static void dp83867_get_wol(struct phy_device *phydev,
 229                             struct ethtool_wolinfo *wol)
 230 {
 231         u16 value, sopass_val;
 232
 233         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
 234                         WAKE_MAGICSECURE);
 235         wol->wolopts = 0;
 236
 237         value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 238
 239         if (value & DP83867_WOL_UCAST_EN)
 240                 wol->wolopts |= WAKE_UCAST;
 241
 242         if (value & DP83867_WOL_BCAST_EN)
 243                 wol->wolopts |= WAKE_BCAST;
 244
 245         if (value & DP83867_WOL_MAGIC_EN)
 246                 wol->wolopts |= WAKE_MAGIC;
 247
 248         if (value & DP83867_WOL_SEC_EN) {
 249                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 250                                           DP83867_RXFSOP1);
 251                 wol->sopass[0] = (sopass_val & 0xff);
 252                 wol->sopass[1] = (sopass_val >> 8);
 253
 254                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 255                                           DP83867_RXFSOP2);
 256                 wol->sopass[2] = (sopass_val & 0xff);
 257                 wol->sopass[3] = (sopass_val >> 8);
 258
 259                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 260                                           DP83867_RXFSOP3);
 261                 wol->sopass[4] = (sopass_val & 0xff);
 262                 wol->sopass[5] = (sopass_val >> 8);
 263
 264                 wol->wolopts |= WAKE_MAGICSECURE;
 265         }
 266
 267         if (!(value & DP83867_WOL_ENH_MAC))
 268                 wol->wolopts = 0;
 269 }
 270
 271 static int dp83867_config_intr(struct phy_device *phydev)
 272 {
 273         int micr_status;
 274
 275         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 276                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 277                 if (micr_status < 0)
 278                         return micr_status;
 279
 280                 micr_status |=
 281                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 282                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 283                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 284                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 285                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 286                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 287
 288                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 289         }
 290
 291         micr_status = 0x0;
 292         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 293 }
 294
 295 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 296 {
 297         struct dp83867_private *dp83867 =
 298                 (struct dp83867_private *)phydev->priv;
 299
 300         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 301                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 302                                  DP83867_CFG4_PORT_MIRROR_EN);
 303         else
 304                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 305                                    DP83867_CFG4_PORT_MIRROR_EN);
 306         return 0;
 307 }
 308
 309 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
 310 {
 311         struct dp83867_private *dp83867 = phydev->priv;
 312
 313         /* Existing behavior was to use default pin strapping delay in rgmii
 314          * mode, but rgmii should have meant no delay.  Warn existing users.
 315          */
 316         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 317                 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 318                                              DP83867_STRAP_STS2);
 319                 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 320                                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 321                 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 322                                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 323
 324                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 325                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 326                         phydev_warn(phydev,
 327                                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 328                                     "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
 329                                     txskew, rxskew);
 330         }
 331
 332         /* RX delay *must* be specified if internal delay of RX is used. */
 333         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 334              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
 335              dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
 336                 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
 337                 return -EINVAL;
 338         }
 339
 340         /* TX delay *must* be specified if internal delay of TX is used. */
 341         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 342              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
 343              dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
 344                 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
 345                 return -EINVAL;
 346         }
 347
 348         return 0;
 349 }
 350
 351 #ifdef CONFIG_OF_MDIO
 352 static int dp83867_of_init(struct phy_device *phydev)
 353 {
 354         struct dp83867_private *dp83867 = phydev->priv;
 355         struct device *dev = &phydev->mdio.dev;
 356         struct device_node *of_node = dev->of_node;
 357         int ret;
 358
 359         if (!of_node)
 360                 return -ENODEV;
 361
 362         /* Optional configuration */
 363         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 364                                    &dp83867->clk_output_sel);
 365         /* If not set, keep default */
 366         if (!ret) {
 367                 dp83867->set_clk_output = true;
 368                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 369                  * DP83867_CLK_O_SEL_OFF.
 370                  */
 371                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 372                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 373                         phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
 374                                    dp83867->clk_output_sel);
 375                         return -EINVAL;
 376                 }
 377         }
 378
 379         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 380                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 381         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 382                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 383         else
 384                 dp83867->io_impedance = -1; /* leave at default */
 385
 386         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 387                                         "ti,dp83867-rxctrl-strap-quirk");
 388
 389         dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
 390                                         "ti,sgmii-ref-clock-output-enable");
 391
 392
 393         dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
 394         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 395                                    &dp83867->rx_id_delay);
 396         if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 397                 phydev_err(phydev,
 398                            "ti,rx-internal-delay value of %u out of range\n",
 399                            dp83867->rx_id_delay);
 400                 return -EINVAL;
 401         }
 402
 403         dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
 404         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 405                                    &dp83867->tx_id_delay);
 406         if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 407                 phydev_err(phydev,
 408                            "ti,tx-internal-delay value of %u out of range\n",
 409                            dp83867->tx_id_delay);
 410                 return -EINVAL;
 411         }
 412
 413         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 414                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 415
 416         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 417                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 418
 419         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 420                                    &dp83867->tx_fifo_depth);
 421         if (ret) {
 422                 ret = of_property_read_u32(of_node, "tx-fifo-depth",
 423                                            &dp83867->tx_fifo_depth);
 424                 if (ret)
 425                         dp83867->tx_fifo_depth =
 426                                         DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 427         }
 428
 429         if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 430                 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
 431                            dp83867->tx_fifo_depth);
 432                 return -EINVAL;
 433         }
 434
 435         ret = of_property_read_u32(of_node, "rx-fifo-depth",
 436                                    &dp83867->rx_fifo_depth);
 437         if (ret)
 438                 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 439
 440         if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 441                 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
 442                            dp83867->rx_fifo_depth);
 443                 return -EINVAL;
 444         }
 445
 446         return 0;
 447 }
 448 #else
 449 static int dp83867_of_init(struct phy_device *phydev)
 450 {
 451         return 0;
 452 }
 453 #endif /* CONFIG_OF_MDIO */
 454
 455 static int dp83867_probe(struct phy_device *phydev)
 456 {
 457         struct dp83867_private *dp83867;
 458
 459         dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 460                                GFP_KERNEL);
 461         if (!dp83867)
 462                 return -ENOMEM;
 463
 464         phydev->priv = dp83867;
 465
 466         return dp83867_of_init(phydev);
 467 }
 468
 469 static int dp83867_config_init(struct phy_device *phydev)
 470 {
 471         struct dp83867_private *dp83867 = phydev->priv;
 472         int ret, val, bs;
 473         u16 delay;
 474
 475         ret = dp83867_verify_rgmii_cfg(phydev);
 476         if (ret)
 477                 return ret;
 478
 479         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 480         if (dp83867->rxctrl_strap_quirk)
 481                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 482                                    BIT(7));
 483
 484         bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
 485         if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
 486                 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
 487                  * be set to 0x2. This may causes the PHY link to be unstable -
 488                  * the default value 0x1 need to be restored.
 489                  */
 490                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 491                                      DP83867_FLD_THR_CFG,
 492                                      DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
 493                                      0x1);
 494                 if (ret)
 495                         return ret;
 496         }
 497
 498         if (phy_interface_is_rgmii(phydev) ||
 499             phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 500                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 501                 if (val < 0)
 502                         return val;
 503
 504                 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
 505                 val |= (dp83867->tx_fifo_depth <<
 506                         DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
 507
 508                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 509                         val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
 510                         val |= (dp83867->rx_fifo_depth <<
 511                                 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
 512                 }
 513
 514                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 515                 if (ret)
 516                         return ret;
 517         }
 518
 519         if (phy_interface_is_rgmii(phydev)) {
 520                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 521                 if (val < 0)
 522                         return val;
 523
 524                 /* The code below checks if "port mirroring" N/A MODE4 has been
 525                  * enabled during power on bootstrap.
 526                  *
 527                  * Such N/A mode enabled by mistake can put PHY IC in some
 528                  * internal testing mode and disable RGMII transmission.
 529                  *
 530                  * In this particular case one needs to check STRAP_STS1
 531                  * register's bit 11 (marked as RESERVED).
 532                  */
 533
 534                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 535                 if (bs & DP83867_STRAP_STS1_RESERVED)
 536                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 537
 538                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 539                 if (ret)
 540                         return ret;
 541
 542                 /* If rgmii mode with no internal delay is selected, we do NOT use
 543                  * aligned mode as one might expect.  Instead we use the PHY's default
 544                  * based on pin strapping.  And the "mode 0" default is to *use*
 545                  * internal delay with a value of 7 (2.00 ns).
 546                  *
 547                  * Set up RGMII delays
 548                  */
 549                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 550
 551                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 552                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 553                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 554
 555                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 556                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 557
 558                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 559                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 560
 561                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 562
 563                 delay = 0;
 564                 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
 565                         delay |= dp83867->rx_id_delay;
 566                 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
 567                         delay |= dp83867->tx_id_delay <<
 568                                  DP83867_RGMII_TX_CLK_DELAY_SHIFT;
 569
 570                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 571                               delay);
 572         }
 573
 574         /* If specified, set io impedance */
 575         if (dp83867->io_impedance >= 0)
 576                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 577                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 578                                dp83867->io_impedance);
 579
 580         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 581                 /* For support SPEED_10 in SGMII mode
 582                  * DP83867_10M_SGMII_RATE_ADAPT bit
 583                  * has to be cleared by software. That
 584                  * does not affect SPEED_100 and
 585                  * SPEED_1000.
 586                  */
 587                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 588                                      DP83867_10M_SGMII_CFG,
 589                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 590                                      0);
 591                 if (ret)
 592                         return ret;
 593
 594                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 595                  * are 01). That is not enough to finalize autoneg on some
 596                  * devices. Increase this timer duration to maximum 16ms.
 597                  */
 598                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 599                                      DP83867_CFG4,
 600                                      DP83867_CFG4_SGMII_ANEG_MASK,
 601                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 602
 603                 if (ret)
 604                         return ret;
 605
 606                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
 607                 /* SGMII type is set to 4-wire mode by default.
 608                  * If we place appropriate property in dts (see above)
 609                  * switch on 6-wire mode.
 610                  */
 611                 if (dp83867->sgmii_ref_clk_en)
 612                         val |= DP83867_SGMII_TYPE;
 613                 else
 614                         val &= ~DP83867_SGMII_TYPE;
 615                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
 616         }
 617
 618         val = phy_read(phydev, DP83867_CFG3);
 619         /* Enable Interrupt output INT_OE in CFG3 register */
 620         if (phy_interrupt_is_valid(phydev))
 621                 val |= DP83867_CFG3_INT_OE;
 622
 623         val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
 624         phy_write(phydev, DP83867_CFG3, val);
 625
 626         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 627                 dp83867_config_port_mirroring(phydev);
 628
 629         /* Clock output selection if muxing property is set */
 630         if (dp83867->set_clk_output) {
 631                 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 632
 633                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 634                         val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 635                 } else {
 636                         mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 637                         val = dp83867->clk_output_sel <<
 638                               DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 639                 }
 640
 641                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 642                                mask, val);
 643         }
 644
 645         return 0;
 646 }
 647
 648 static int dp83867_phy_reset(struct phy_device *phydev)
 649 {
 650         int err;
 651
 652         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 653         if (err < 0)
 654                 return err;
 655
 656         usleep_range(10, 20);
 657
 658         /* After reset FORCE_LINK_GOOD bit is set. Although the
 659          * default value should be unset. Disable FORCE_LINK_GOOD
 660          * for the phy to work properly.
 661          */
 662         return phy_modify(phydev, MII_DP83867_PHYCTRL,
 663                          DP83867_PHYCR_FORCE_LINK_GOOD, 0);
 664 }
 665
 666 static struct phy_driver dp83867_driver[] = {
 667         {
 668                 .phy_id         = DP83867_PHY_ID,
 669                 .phy_id_mask    = 0xfffffff0,
 670                 .name           = "TI DP83867",
 671                 /* PHY_GBIT_FEATURES */
 672
 673                 .probe          = dp83867_probe,
 674                 .config_init    = dp83867_config_init,
 675                 .soft_reset     = dp83867_phy_reset,
 676
 677                 .get_wol        = dp83867_get_wol,
 678                 .set_wol        = dp83867_set_wol,
 679
 680                 /* IRQ related */
 681                 .ack_interrupt  = dp83867_ack_interrupt,
 682                 .config_intr    = dp83867_config_intr,
 683
 684                 .suspend        = genphy_suspend,
 685                 .resume         = genphy_resume,
 686         },
 687 };
 688 module_phy_driver(dp83867_driver);
 689
 690 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 691         { DP83867_PHY_ID, 0xfffffff0 },
 692         { }
 693 };
 694
 695 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 696
 697 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 698 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 699 MODULE_LICENSE("GPL v2");