1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Texas Instruments DP83867 PHY
5 * Copyright (C) 2015 Texas Instruments Inc.
8 #include <linux/ethtool.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/delay.h>
16 #include <dt-bindings/net/ti-dp83867.h>
18 #define DP83867_PHY_ID 0x2000a231
19 #define DP83867_DEVADDR 0x1f
21 #define MII_DP83867_PHYCTRL 0x10
22 #define MII_DP83867_MICR 0x12
23 #define MII_DP83867_ISR 0x13
24 #define DP83867_CTRL 0x1f
25 #define DP83867_CFG3 0x1e
27 /* Extended Registers */
28 #define DP83867_CFG4 0x0031
29 #define DP83867_RGMIICTL 0x0032
30 #define DP83867_STRAP_STS1 0x006E
31 #define DP83867_RGMIIDCTL 0x0086
32 #define DP83867_IO_MUX_CFG 0x0170
34 #define DP83867_SW_RESET BIT(15)
35 #define DP83867_SW_RESTART BIT(14)
37 /* MICR Interrupt bits */
38 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
39 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
40 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
41 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
42 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
43 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
44 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
45 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
46 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
47 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
48 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
49 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
52 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
53 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
56 #define DP83867_STRAP_STS1_RESERVED BIT(11)
59 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
60 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
61 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
64 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
67 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
69 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
70 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
71 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
72 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
75 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
78 DP83867_PORT_MIRROING_KEEP,
79 DP83867_PORT_MIRROING_EN,
80 DP83867_PORT_MIRROING_DIS,
83 struct dp83867_private {
89 bool rxctrl_strap_quirk;
93 static int dp83867_ack_interrupt(struct phy_device *phydev)
95 int err = phy_read(phydev, MII_DP83867_ISR);
103 static int dp83867_config_intr(struct phy_device *phydev)
107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
108 micr_status = phy_read(phydev, MII_DP83867_MICR);
113 (MII_DP83867_MICR_AN_ERR_INT_EN |
114 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
115 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
116 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
117 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
118 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
120 return phy_write(phydev, MII_DP83867_MICR, micr_status);
124 return phy_write(phydev, MII_DP83867_MICR, micr_status);
127 static int dp83867_config_port_mirroring(struct phy_device *phydev)
129 struct dp83867_private *dp83867 =
130 (struct dp83867_private *)phydev->priv;
132 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
133 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
134 DP83867_CFG4_PORT_MIRROR_EN);
136 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
137 DP83867_CFG4_PORT_MIRROR_EN);
141 #ifdef CONFIG_OF_MDIO
142 static int dp83867_of_init(struct phy_device *phydev)
144 struct dp83867_private *dp83867 = phydev->priv;
145 struct device *dev = &phydev->mdio.dev;
146 struct device_node *of_node = dev->of_node;
152 dp83867->io_impedance = -EINVAL;
154 /* Optional configuration */
155 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
156 &dp83867->clk_output_sel);
157 if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
158 /* Keep the default value if ti,clk-output-sel is not set
161 dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
163 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
164 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
165 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
166 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
168 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
169 "ti,dp83867-rxctrl-strap-quirk");
171 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
172 &dp83867->rx_id_delay);
174 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
175 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
178 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
179 &dp83867->tx_id_delay);
181 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
182 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
185 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
186 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
188 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
189 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
191 return of_property_read_u32(of_node, "ti,fifo-depth",
192 &dp83867->fifo_depth);
195 static int dp83867_of_init(struct phy_device *phydev)
199 #endif /* CONFIG_OF_MDIO */
201 static int dp83867_config_init(struct phy_device *phydev)
203 struct dp83867_private *dp83867;
208 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
213 phydev->priv = dp83867;
214 ret = dp83867_of_init(phydev);
218 dp83867 = (struct dp83867_private *)phydev->priv;
221 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
222 if (dp83867->rxctrl_strap_quirk)
223 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
226 if (phy_interface_is_rgmii(phydev)) {
227 val = phy_read(phydev, MII_DP83867_PHYCTRL);
230 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
231 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
233 /* The code below checks if "port mirroring" N/A MODE4 has been
234 * enabled during power on bootstrap.
236 * Such N/A mode enabled by mistake can put PHY IC in some
237 * internal testing mode and disable RGMII transmission.
239 * In this particular case one needs to check STRAP_STS1
240 * register's bit 11 (marked as RESERVED).
243 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
244 if (bs & DP83867_STRAP_STS1_RESERVED)
245 val &= ~DP83867_PHYCR_RESERVED_MASK;
247 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
252 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
253 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
254 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
256 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
257 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
259 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
260 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
262 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
263 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
265 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
267 delay = (dp83867->rx_id_delay |
268 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
270 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
273 if (dp83867->io_impedance >= 0)
274 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
275 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
276 dp83867->io_impedance &
277 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
280 /* Enable Interrupt output INT_OE in CFG3 register */
281 if (phy_interrupt_is_valid(phydev)) {
282 val = phy_read(phydev, DP83867_CFG3);
284 phy_write(phydev, DP83867_CFG3, val);
287 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
288 dp83867_config_port_mirroring(phydev);
290 /* Clock output selection if muxing property is set */
291 if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
292 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
293 DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
294 dp83867->clk_output_sel <<
295 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
300 static int dp83867_phy_reset(struct phy_device *phydev)
304 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
308 usleep_range(10, 20);
310 return dp83867_config_init(phydev);
313 static struct phy_driver dp83867_driver[] = {
315 .phy_id = DP83867_PHY_ID,
316 .phy_id_mask = 0xfffffff0,
317 .name = "TI DP83867",
318 .features = PHY_GBIT_FEATURES,
320 .config_init = dp83867_config_init,
321 .soft_reset = dp83867_phy_reset,
324 .ack_interrupt = dp83867_ack_interrupt,
325 .config_intr = dp83867_config_intr,
327 .suspend = genphy_suspend,
328 .resume = genphy_resume,
331 module_phy_driver(dp83867_driver);
333 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
334 { DP83867_PHY_ID, 0xfffffff0 },
338 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
340 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
341 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
342 MODULE_LICENSE("GPL v2");