2 * Driver for the Texas Instruments DP83867 PHY
4 * Copyright (C) 2015 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/ethtool.h>
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/module.h>
21 #include <linux/phy.h>
23 #include <dt-bindings/net/ti-dp83867.h>
25 #define DP83867_PHY_ID 0x2000a231
26 #define DP83867_DEVADDR 0x1f
28 #define MII_DP83867_PHYCTRL 0x10
29 #define MII_DP83867_MICR 0x12
30 #define MII_DP83867_ISR 0x13
31 #define DP83867_CTRL 0x1f
32 #define DP83867_CFG3 0x1e
34 /* Extended Registers */
35 #define DP83867_CFG4 0x0031
36 #define DP83867_RGMIICTL 0x0032
37 #define DP83867_STRAP_STS1 0x006E
38 #define DP83867_RGMIIDCTL 0x0086
39 #define DP83867_IO_MUX_CFG 0x0170
41 #define DP83867_SW_RESET BIT(15)
42 #define DP83867_SW_RESTART BIT(14)
44 /* MICR Interrupt bits */
45 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
46 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
47 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
48 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
49 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
50 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
51 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
52 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
53 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
54 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
55 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
56 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
59 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
60 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
63 #define DP83867_STRAP_STS1_RESERVED BIT(11)
66 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
67 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
68 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
71 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
74 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
76 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
77 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
80 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
83 DP83867_PORT_MIRROING_KEEP,
84 DP83867_PORT_MIRROING_EN,
85 DP83867_PORT_MIRROING_DIS,
88 struct dp83867_private {
96 static int dp83867_ack_interrupt(struct phy_device *phydev)
98 int err = phy_read(phydev, MII_DP83867_ISR);
106 static int dp83867_config_intr(struct phy_device *phydev)
110 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
111 micr_status = phy_read(phydev, MII_DP83867_MICR);
116 (MII_DP83867_MICR_AN_ERR_INT_EN |
117 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
118 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
119 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
120 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
121 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
123 return phy_write(phydev, MII_DP83867_MICR, micr_status);
127 return phy_write(phydev, MII_DP83867_MICR, micr_status);
130 static int dp83867_config_port_mirroring(struct phy_device *phydev)
132 struct dp83867_private *dp83867 =
133 (struct dp83867_private *)phydev->priv;
136 val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR);
138 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
139 val |= DP83867_CFG4_PORT_MIRROR_EN;
141 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
143 phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR, val);
148 #ifdef CONFIG_OF_MDIO
149 static int dp83867_of_init(struct phy_device *phydev)
151 struct dp83867_private *dp83867 = phydev->priv;
152 struct device *dev = &phydev->mdio.dev;
153 struct device_node *of_node = dev->of_node;
159 dp83867->io_impedance = -EINVAL;
161 /* Optional configuration */
162 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
163 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
164 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
165 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
167 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
168 &dp83867->rx_id_delay);
170 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
171 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
174 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
175 &dp83867->tx_id_delay);
177 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
178 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
181 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
182 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
184 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
185 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
187 return of_property_read_u32(of_node, "ti,fifo-depth",
188 &dp83867->fifo_depth);
191 static int dp83867_of_init(struct phy_device *phydev)
195 #endif /* CONFIG_OF_MDIO */
197 static int dp83867_config_init(struct phy_device *phydev)
199 struct dp83867_private *dp83867;
204 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
209 phydev->priv = dp83867;
210 ret = dp83867_of_init(phydev);
214 dp83867 = (struct dp83867_private *)phydev->priv;
217 if (phy_interface_is_rgmii(phydev)) {
218 val = phy_read(phydev, MII_DP83867_PHYCTRL);
221 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
222 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
224 /* The code below checks if "port mirroring" N/A MODE4 has been
225 * enabled during power on bootstrap.
227 * Such N/A mode enabled by mistake can put PHY IC in some
228 * internal testing mode and disable RGMII transmission.
230 * In this particular case one needs to check STRAP_STS1
231 * register's bit 11 (marked as RESERVED).
234 bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
236 if (bs & DP83867_STRAP_STS1_RESERVED)
237 val &= ~DP83867_PHYCR_RESERVED_MASK;
239 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
244 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
245 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
246 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
249 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
250 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
252 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
253 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
255 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
256 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
258 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
259 DP83867_DEVADDR, val);
261 delay = (dp83867->rx_id_delay |
262 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
264 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
265 DP83867_DEVADDR, delay);
267 if (dp83867->io_impedance >= 0) {
268 val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
271 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
272 val |= dp83867->io_impedance &
273 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
275 phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
276 DP83867_DEVADDR, val);
280 /* Enable Interrupt output INT_OE in CFG3 register */
281 if (phy_interrupt_is_valid(phydev)) {
282 val = phy_read(phydev, DP83867_CFG3);
284 phy_write(phydev, DP83867_CFG3, val);
287 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
288 dp83867_config_port_mirroring(phydev);
293 static int dp83867_phy_reset(struct phy_device *phydev)
297 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
301 return dp83867_config_init(phydev);
304 static struct phy_driver dp83867_driver[] = {
306 .phy_id = DP83867_PHY_ID,
307 .phy_id_mask = 0xfffffff0,
308 .name = "TI DP83867",
309 .features = PHY_GBIT_FEATURES,
310 .flags = PHY_HAS_INTERRUPT,
312 .config_init = dp83867_config_init,
313 .soft_reset = dp83867_phy_reset,
316 .ack_interrupt = dp83867_ack_interrupt,
317 .config_intr = dp83867_config_intr,
319 .config_aneg = genphy_config_aneg,
320 .read_status = genphy_read_status,
321 .suspend = genphy_suspend,
322 .resume = genphy_resume,
325 module_phy_driver(dp83867_driver);
327 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
328 { DP83867_PHY_ID, 0xfffffff0 },
332 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
334 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
335 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
336 MODULE_LICENSE("GPL");