drivers/net/phy/dp83822.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
   3  *
   4  * Copyright (C) 2017 Texas Instruments Inc.
   5  */
   6
   7 #include <linux/ethtool.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/netdevice.h>
  15
  16 #define DP83822_PHY_ID          0x2000a240
  17 #define DP83825S_PHY_ID         0x2000a140
  18 #define DP83825I_PHY_ID         0x2000a150
  19 #define DP83825CM_PHY_ID        0x2000a160
  20 #define DP83825CS_PHY_ID        0x2000a170
  21 #define DP83826C_PHY_ID         0x2000a130
  22 #define DP83826NC_PHY_ID        0x2000a110
  23
  24 #define DP83822_DEVADDR         0x1f
  25
  26 #define MII_DP83822_CTRL_2      0x0a
  27 #define MII_DP83822_PHYSTS      0x10
  28 #define MII_DP83822_PHYSCR      0x11
  29 #define MII_DP83822_MISR1       0x12
  30 #define MII_DP83822_MISR2       0x13
  31 #define MII_DP83822_FCSCR       0x14
  32 #define MII_DP83822_RCSR        0x17
  33 #define MII_DP83822_RESET_CTRL  0x1f
  34 #define MII_DP83822_GENCFG      0x465
  35 #define MII_DP83822_SOR1        0x467
  36
  37 /* GENCFG */
  38 #define DP83822_SIG_DET_LOW     BIT(0)
  39
  40 /* Control Register 2 bits */
  41 #define DP83822_FX_ENABLE       BIT(14)
  42
  43 #define DP83822_HW_RESET        BIT(15)
  44 #define DP83822_SW_RESET        BIT(14)
  45
  46 /* PHY STS bits */
  47 #define DP83822_PHYSTS_DUPLEX                   BIT(2)
  48 #define DP83822_PHYSTS_10                       BIT(1)
  49 #define DP83822_PHYSTS_LINK                     BIT(0)
  50
  51 /* PHYSCR Register Fields */
  52 #define DP83822_PHYSCR_INT_OE           BIT(0) /* Interrupt Output Enable */
  53 #define DP83822_PHYSCR_INTEN            BIT(1) /* Interrupt Enable */
  54
  55 /* MISR1 bits */
  56 #define DP83822_RX_ERR_HF_INT_EN        BIT(0)
  57 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
  58 #define DP83822_ANEG_COMPLETE_INT_EN    BIT(2)
  59 #define DP83822_DUP_MODE_CHANGE_INT_EN  BIT(3)
  60 #define DP83822_SPEED_CHANGED_INT_EN    BIT(4)
  61 #define DP83822_LINK_STAT_INT_EN        BIT(5)
  62 #define DP83822_ENERGY_DET_INT_EN       BIT(6)
  63 #define DP83822_LINK_QUAL_INT_EN        BIT(7)
  64
  65 /* MISR2 bits */
  66 #define DP83822_JABBER_DET_INT_EN       BIT(0)
  67 #define DP83822_WOL_PKT_INT_EN          BIT(1)
  68 #define DP83822_SLEEP_MODE_INT_EN       BIT(2)
  69 #define DP83822_MDI_XOVER_INT_EN        BIT(3)
  70 #define DP83822_LB_FIFO_INT_EN          BIT(4)
  71 #define DP83822_PAGE_RX_INT_EN          BIT(5)
  72 #define DP83822_ANEG_ERR_INT_EN         BIT(6)
  73 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
  74
  75 /* INT_STAT1 bits */
  76 #define DP83822_WOL_INT_EN      BIT(4)
  77 #define DP83822_WOL_INT_STAT    BIT(12)
  78
  79 #define MII_DP83822_RXSOP1      0x04a5
  80 #define MII_DP83822_RXSOP2      0x04a6
  81 #define MII_DP83822_RXSOP3      0x04a7
  82
  83 /* WoL Registers */
  84 #define MII_DP83822_WOL_CFG     0x04a0
  85 #define MII_DP83822_WOL_STAT    0x04a1
  86 #define MII_DP83822_WOL_DA1     0x04a2
  87 #define MII_DP83822_WOL_DA2     0x04a3
  88 #define MII_DP83822_WOL_DA3     0x04a4
  89
  90 /* WoL bits */
  91 #define DP83822_WOL_MAGIC_EN    BIT(0)
  92 #define DP83822_WOL_SECURE_ON   BIT(5)
  93 #define DP83822_WOL_EN          BIT(7)
  94 #define DP83822_WOL_INDICATION_SEL BIT(8)
  95 #define DP83822_WOL_CLR_INDICATION BIT(11)
  96
  97 /* RSCR bits */
  98 #define DP83822_RX_CLK_SHIFT    BIT(12)
  99 #define DP83822_TX_CLK_SHIFT    BIT(11)
 100
 101 /* SOR1 mode */
 102 #define DP83822_STRAP_MODE1     0
 103 #define DP83822_STRAP_MODE2     BIT(0)
 104 #define DP83822_STRAP_MODE3     BIT(1)
 105 #define DP83822_STRAP_MODE4     GENMASK(1, 0)
 106
 107 #define DP83822_COL_STRAP_MASK  GENMASK(11, 10)
 108 #define DP83822_COL_SHIFT       10
 109 #define DP83822_RX_ER_STR_MASK  GENMASK(9, 8)
 110 #define DP83822_RX_ER_SHIFT     8
 111
 112 #define MII_DP83822_FIBER_ADVERTISE    (ADVERTISED_TP | ADVERTISED_MII | \
 113                                         ADVERTISED_FIBRE | \
 114                                         ADVERTISED_Pause | ADVERTISED_Asym_Pause)
 115
 116 struct dp83822_private {
 117         bool fx_signal_det_low;
 118         int fx_enabled;
 119         u16 fx_sd_enable;
 120 };
 121
 122 static int dp83822_ack_interrupt(struct phy_device *phydev)
 123 {
 124         int err;
 125
 126         err = phy_read(phydev, MII_DP83822_MISR1);
 127         if (err < 0)
 128                 return err;
 129
 130         err = phy_read(phydev, MII_DP83822_MISR2);
 131         if (err < 0)
 132                 return err;
 133
 134         return 0;
 135 }
 136
 137 static int dp83822_set_wol(struct phy_device *phydev,
 138                            struct ethtool_wolinfo *wol)
 139 {
 140         struct net_device *ndev = phydev->attached_dev;
 141         u16 value;
 142         const u8 *mac;
 143
 144         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
 145                 mac = (const u8 *)ndev->dev_addr;
 146
 147                 if (!is_valid_ether_addr(mac))
 148                         return -EINVAL;
 149
 150                 /* MAC addresses start with byte 5, but stored in mac[0].
 151                  * 822 PHYs store bytes 4|5, 2|3, 0|1
 152                  */
 153                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
 154                               (mac[1] << 8) | mac[0]);
 155                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
 156                               (mac[3] << 8) | mac[2]);
 157                 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
 158                               (mac[5] << 8) | mac[4]);
 159
 160                 value = phy_read_mmd(phydev, DP83822_DEVADDR,
 161                                      MII_DP83822_WOL_CFG);
 162                 if (wol->wolopts & WAKE_MAGIC)
 163                         value |= DP83822_WOL_MAGIC_EN;
 164                 else
 165                         value &= ~DP83822_WOL_MAGIC_EN;
 166
 167                 if (wol->wolopts & WAKE_MAGICSECURE) {
 168                         phy_write_mmd(phydev, DP83822_DEVADDR,
 169                                       MII_DP83822_RXSOP1,
 170                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 171                         phy_write_mmd(phydev, DP83822_DEVADDR,
 172                                       MII_DP83822_RXSOP2,
 173                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 174                         phy_write_mmd(phydev, DP83822_DEVADDR,
 175                                       MII_DP83822_RXSOP3,
 176                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 177                         value |= DP83822_WOL_SECURE_ON;
 178                 } else {
 179                         value &= ~DP83822_WOL_SECURE_ON;
 180                 }
 181
 182                 /* Clear any pending WoL interrupt */
 183                 phy_read(phydev, MII_DP83822_MISR2);
 184
 185                 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
 186                          DP83822_WOL_CLR_INDICATION;
 187
 188                 return phy_write_mmd(phydev, DP83822_DEVADDR,
 189                                      MII_DP83822_WOL_CFG, value);
 190         } else {
 191                 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
 192                                           MII_DP83822_WOL_CFG, DP83822_WOL_EN);
 193         }
 194 }
 195
 196 static void dp83822_get_wol(struct phy_device *phydev,
 197                             struct ethtool_wolinfo *wol)
 198 {
 199         int value;
 200         u16 sopass_val;
 201
 202         wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
 203         wol->wolopts = 0;
 204
 205         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 206
 207         if (value & DP83822_WOL_MAGIC_EN)
 208                 wol->wolopts |= WAKE_MAGIC;
 209
 210         if (value & DP83822_WOL_SECURE_ON) {
 211                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 212                                           MII_DP83822_RXSOP1);
 213                 wol->sopass[0] = (sopass_val & 0xff);
 214                 wol->sopass[1] = (sopass_val >> 8);
 215
 216                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 217                                           MII_DP83822_RXSOP2);
 218                 wol->sopass[2] = (sopass_val & 0xff);
 219                 wol->sopass[3] = (sopass_val >> 8);
 220
 221                 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
 222                                           MII_DP83822_RXSOP3);
 223                 wol->sopass[4] = (sopass_val & 0xff);
 224                 wol->sopass[5] = (sopass_val >> 8);
 225
 226                 wol->wolopts |= WAKE_MAGICSECURE;
 227         }
 228
 229         /* WoL is not enabled so set wolopts to 0 */
 230         if (!(value & DP83822_WOL_EN))
 231                 wol->wolopts = 0;
 232 }
 233
 234 static int dp83822_config_intr(struct phy_device *phydev)
 235 {
 236         struct dp83822_private *dp83822 = phydev->priv;
 237         int misr_status;
 238         int physcr_status;
 239         int err;
 240
 241         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 242                 misr_status = phy_read(phydev, MII_DP83822_MISR1);
 243                 if (misr_status < 0)
 244                         return misr_status;
 245
 246                 misr_status |= (DP83822_RX_ERR_HF_INT_EN |
 247                                 DP83822_FALSE_CARRIER_HF_INT_EN |
 248                                 DP83822_LINK_STAT_INT_EN |
 249                                 DP83822_ENERGY_DET_INT_EN |
 250                                 DP83822_LINK_QUAL_INT_EN);
 251
 252                 if (!dp83822->fx_enabled)
 253                         misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
 254                                        DP83822_DUP_MODE_CHANGE_INT_EN |
 255                                        DP83822_SPEED_CHANGED_INT_EN;
 256
 257
 258                 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
 259                 if (err < 0)
 260                         return err;
 261
 262                 misr_status = phy_read(phydev, MII_DP83822_MISR2);
 263                 if (misr_status < 0)
 264                         return misr_status;
 265
 266                 misr_status |= (DP83822_JABBER_DET_INT_EN |
 267                                 DP83822_SLEEP_MODE_INT_EN |
 268                                 DP83822_LB_FIFO_INT_EN |
 269                                 DP83822_PAGE_RX_INT_EN |
 270                                 DP83822_EEE_ERROR_CHANGE_INT_EN);
 271
 272                 if (!dp83822->fx_enabled)
 273                         misr_status |= DP83822_MDI_XOVER_INT_EN |
 274                                        DP83822_ANEG_ERR_INT_EN |
 275                                        DP83822_WOL_PKT_INT_EN;
 276
 277                 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
 278                 if (err < 0)
 279                         return err;
 280
 281                 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
 282                 if (physcr_status < 0)
 283                         return physcr_status;
 284
 285                 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
 286
 287         } else {
 288                 err = phy_write(phydev, MII_DP83822_MISR1, 0);
 289                 if (err < 0)
 290                         return err;
 291
 292                 err = phy_write(phydev, MII_DP83822_MISR1, 0);
 293                 if (err < 0)
 294                         return err;
 295
 296                 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
 297                 if (physcr_status < 0)
 298                         return physcr_status;
 299
 300                 physcr_status &= ~DP83822_PHYSCR_INTEN;
 301         }
 302
 303         return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
 304 }
 305
 306 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
 307 {
 308         int irq_status;
 309
 310         /* The MISR1 and MISR2 registers are holding the interrupt status in
 311          * the upper half (15:8), while the lower half (7:0) is used for
 312          * controlling the interrupt enable state of those individual interrupt
 313          * sources. To determine the possible interrupt sources, just read the
 314          * MISR* register and use it directly to know which interrupts have
 315          * been enabled previously or not.
 316          */
 317         irq_status = phy_read(phydev, MII_DP83822_MISR1);
 318         if (irq_status < 0) {
 319                 phy_error(phydev);
 320                 return IRQ_NONE;
 321         }
 322         if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
 323                 goto trigger_machine;
 324
 325         irq_status = phy_read(phydev, MII_DP83822_MISR2);
 326         if (irq_status < 0) {
 327                 phy_error(phydev);
 328                 return IRQ_NONE;
 329         }
 330         if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
 331                 goto trigger_machine;
 332
 333         return IRQ_NONE;
 334
 335 trigger_machine:
 336         phy_trigger_machine(phydev);
 337
 338         return IRQ_HANDLED;
 339 }
 340
 341 static int dp8382x_disable_wol(struct phy_device *phydev)
 342 {
 343         int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
 344                     DP83822_WOL_SECURE_ON;
 345
 346         return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
 347                                   MII_DP83822_WOL_CFG, value);
 348 }
 349
 350 static int dp83822_read_status(struct phy_device *phydev)
 351 {
 352         struct dp83822_private *dp83822 = phydev->priv;
 353         int status = phy_read(phydev, MII_DP83822_PHYSTS);
 354         int ctrl2;
 355         int ret;
 356
 357         if (dp83822->fx_enabled) {
 358                 if (status & DP83822_PHYSTS_LINK) {
 359                         phydev->speed = SPEED_UNKNOWN;
 360                         phydev->duplex = DUPLEX_UNKNOWN;
 361                 } else {
 362                         ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
 363                         if (ctrl2 < 0)
 364                                 return ctrl2;
 365
 366                         if (!(ctrl2 & DP83822_FX_ENABLE)) {
 367                                 ret = phy_write(phydev, MII_DP83822_CTRL_2,
 368                                                 DP83822_FX_ENABLE | ctrl2);
 369                                 if (ret < 0)
 370                                         return ret;
 371                         }
 372                 }
 373         }
 374
 375         ret = genphy_read_status(phydev);
 376         if (ret)
 377                 return ret;
 378
 379         if (status < 0)
 380                 return status;
 381
 382         if (status & DP83822_PHYSTS_DUPLEX)
 383                 phydev->duplex = DUPLEX_FULL;
 384         else
 385                 phydev->duplex = DUPLEX_HALF;
 386
 387         if (status & DP83822_PHYSTS_10)
 388                 phydev->speed = SPEED_10;
 389         else
 390                 phydev->speed = SPEED_100;
 391
 392         return 0;
 393 }
 394
 395 static int dp83822_config_init(struct phy_device *phydev)
 396 {
 397         struct dp83822_private *dp83822 = phydev->priv;
 398         struct device *dev = &phydev->mdio.dev;
 399         int rgmii_delay;
 400         s32 rx_int_delay;
 401         s32 tx_int_delay;
 402         int err = 0;
 403         int bmcr;
 404
 405         if (phy_interface_is_rgmii(phydev)) {
 406                 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
 407                                                       true);
 408
 409                 if (rx_int_delay <= 0)
 410                         rgmii_delay = 0;
 411                 else
 412                         rgmii_delay = DP83822_RX_CLK_SHIFT;
 413
 414                 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
 415                                                       false);
 416                 if (tx_int_delay <= 0)
 417                         rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
 418                 else
 419                         rgmii_delay |= DP83822_TX_CLK_SHIFT;
 420
 421                 if (rgmii_delay) {
 422                         err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
 423                                                MII_DP83822_RCSR, rgmii_delay);
 424                         if (err)
 425                                 return err;
 426                 }
 427         }
 428
 429         if (dp83822->fx_enabled) {
 430                 err = phy_modify(phydev, MII_DP83822_CTRL_2,
 431                                  DP83822_FX_ENABLE, 1);
 432                 if (err < 0)
 433                         return err;
 434
 435                 /* Only allow advertising what this PHY supports */
 436                 linkmode_and(phydev->advertising, phydev->advertising,
 437                              phydev->supported);
 438
 439                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 440                                  phydev->supported);
 441                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 442                                  phydev->advertising);
 443                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 444                                  phydev->supported);
 445                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 446                                  phydev->supported);
 447                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
 448                                  phydev->advertising);
 449                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
 450                                  phydev->advertising);
 451
 452                 /* Auto neg is not supported in fiber mode */
 453                 bmcr = phy_read(phydev, MII_BMCR);
 454                 if (bmcr < 0)
 455                         return bmcr;
 456
 457                 if (bmcr & BMCR_ANENABLE) {
 458                         err =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
 459                         if (err < 0)
 460                                 return err;
 461                 }
 462                 phydev->autoneg = AUTONEG_DISABLE;
 463                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 464                                    phydev->supported);
 465                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 466                                    phydev->advertising);
 467
 468                 /* Setup fiber advertisement */
 469                 err = phy_modify_changed(phydev, MII_ADVERTISE,
 470                                          MII_DP83822_FIBER_ADVERTISE,
 471                                          MII_DP83822_FIBER_ADVERTISE);
 472
 473                 if (err < 0)
 474                         return err;
 475
 476                 if (dp83822->fx_signal_det_low) {
 477                         err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
 478                                                MII_DP83822_GENCFG,
 479                                                DP83822_SIG_DET_LOW);
 480                         if (err)
 481                                 return err;
 482                 }
 483         }
 484         return dp8382x_disable_wol(phydev);
 485 }
 486
 487 static int dp8382x_config_init(struct phy_device *phydev)
 488 {
 489         return dp8382x_disable_wol(phydev);
 490 }
 491
 492 static int dp83822_phy_reset(struct phy_device *phydev)
 493 {
 494         int err;
 495
 496         err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
 497         if (err < 0)
 498                 return err;
 499
 500         return phydev->drv->config_init(phydev);
 501 }
 502
 503 #ifdef CONFIG_OF_MDIO
 504 static int dp83822_of_init(struct phy_device *phydev)
 505 {
 506         struct dp83822_private *dp83822 = phydev->priv;
 507         struct device *dev = &phydev->mdio.dev;
 508
 509         /* Signal detection for the PHY is only enabled if the FX_EN and the
 510          * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
 511          * is strapped otherwise signal detection is disabled for the PHY.
 512          */
 513         if (dp83822->fx_enabled && dp83822->fx_sd_enable)
 514                 dp83822->fx_signal_det_low = device_property_present(dev,
 515                                                                      "ti,link-loss-low");
 516         if (!dp83822->fx_enabled)
 517                 dp83822->fx_enabled = device_property_present(dev,
 518                                                               "ti,fiber-mode");
 519
 520         return 0;
 521 }
 522 #else
 523 static int dp83822_of_init(struct phy_device *phydev)
 524 {
 525         return 0;
 526 }
 527 #endif /* CONFIG_OF_MDIO */
 528
 529 static int dp83822_read_straps(struct phy_device *phydev)
 530 {
 531         struct dp83822_private *dp83822 = phydev->priv;
 532         int fx_enabled, fx_sd_enable;
 533         int val;
 534
 535         val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
 536         if (val < 0)
 537                 return val;
 538
 539         fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
 540         if (fx_enabled == DP83822_STRAP_MODE2 ||
 541             fx_enabled == DP83822_STRAP_MODE3)
 542                 dp83822->fx_enabled = 1;
 543
 544         if (dp83822->fx_enabled) {
 545                 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
 546                 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
 547                     fx_sd_enable == DP83822_STRAP_MODE4)
 548                         dp83822->fx_sd_enable = 1;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int dp83822_probe(struct phy_device *phydev)
 555 {
 556         struct dp83822_private *dp83822;
 557         int ret;
 558
 559         dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
 560                                GFP_KERNEL);
 561         if (!dp83822)
 562                 return -ENOMEM;
 563
 564         phydev->priv = dp83822;
 565
 566         ret = dp83822_read_straps(phydev);
 567         if (ret)
 568                 return ret;
 569
 570         dp83822_of_init(phydev);
 571
 572         return 0;
 573 }
 574
 575 static int dp83822_suspend(struct phy_device *phydev)
 576 {
 577         int value;
 578
 579         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 580
 581         if (!(value & DP83822_WOL_EN))
 582                 genphy_suspend(phydev);
 583
 584         return 0;
 585 }
 586
 587 static int dp83822_resume(struct phy_device *phydev)
 588 {
 589         int value;
 590
 591         genphy_resume(phydev);
 592
 593         value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
 594
 595         phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
 596                       DP83822_WOL_CLR_INDICATION);
 597
 598         return 0;
 599 }
 600
 601 #define DP83822_PHY_DRIVER(_id, _name)                          \
 602         {                                                       \
 603                 PHY_ID_MATCH_MODEL(_id),                        \
 604                 .name           = (_name),                      \
 605                 /* PHY_BASIC_FEATURES */                        \
 606                 .probe          = dp83822_probe,                \
 607                 .soft_reset     = dp83822_phy_reset,            \
 608                 .config_init    = dp83822_config_init,          \
 609                 .read_status    = dp83822_read_status,          \
 610                 .get_wol = dp83822_get_wol,                     \
 611                 .set_wol = dp83822_set_wol,                     \
 612                 .ack_interrupt = dp83822_ack_interrupt,         \
 613                 .config_intr = dp83822_config_intr,             \
 614                 .handle_interrupt = dp83822_handle_interrupt,   \
 615                 .suspend = dp83822_suspend,                     \
 616                 .resume = dp83822_resume,                       \
 617         }
 618
 619 #define DP8382X_PHY_DRIVER(_id, _name)                          \
 620         {                                                       \
 621                 PHY_ID_MATCH_MODEL(_id),                        \
 622                 .name           = (_name),                      \
 623                 /* PHY_BASIC_FEATURES */                        \
 624                 .soft_reset     = dp83822_phy_reset,            \
 625                 .config_init    = dp8382x_config_init,          \
 626                 .get_wol = dp83822_get_wol,                     \
 627                 .set_wol = dp83822_set_wol,                     \
 628                 .ack_interrupt = dp83822_ack_interrupt,         \
 629                 .config_intr = dp83822_config_intr,             \
 630                 .handle_interrupt = dp83822_handle_interrupt,   \
 631                 .suspend = dp83822_suspend,                     \
 632                 .resume = dp83822_resume,                       \
 633         }
 634
 635 static struct phy_driver dp83822_driver[] = {
 636         DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
 637         DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
 638         DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
 639         DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
 640         DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
 641         DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
 642         DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
 643 };
 644 module_phy_driver(dp83822_driver);
 645
 646 static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
 647         { DP83822_PHY_ID, 0xfffffff0 },
 648         { DP83825I_PHY_ID, 0xfffffff0 },
 649         { DP83826C_PHY_ID, 0xfffffff0 },
 650         { DP83826NC_PHY_ID, 0xfffffff0 },
 651         { DP83825S_PHY_ID, 0xfffffff0 },
 652         { DP83825CM_PHY_ID, 0xfffffff0 },
 653         { DP83825CS_PHY_ID, 0xfffffff0 },
 654         { },
 655 };
 656 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
 657
 658 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
 659 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 660 MODULE_LICENSE("GPL v2");