1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
4 * Copyright (C) 2017 Texas Instruments Inc.
7 #include <linux/ethtool.h>
8 #include <linux/etherdevice.h>
9 #include <linux/kernel.h>
10 #include <linux/mii.h>
11 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/netdevice.h>
16 #define DP83822_PHY_ID 0x2000a240
17 #define DP83825S_PHY_ID 0x2000a140
18 #define DP83825I_PHY_ID 0x2000a150
19 #define DP83825CM_PHY_ID 0x2000a160
20 #define DP83825CS_PHY_ID 0x2000a170
21 #define DP83826C_PHY_ID 0x2000a130
22 #define DP83826NC_PHY_ID 0x2000a110
24 #define DP83822_DEVADDR 0x1f
26 #define MII_DP83822_CTRL_2 0x0a
27 #define MII_DP83822_PHYSTS 0x10
28 #define MII_DP83822_PHYSCR 0x11
29 #define MII_DP83822_MISR1 0x12
30 #define MII_DP83822_MISR2 0x13
31 #define MII_DP83822_FCSCR 0x14
32 #define MII_DP83822_RCSR 0x17
33 #define MII_DP83822_RESET_CTRL 0x1f
34 #define MII_DP83822_GENCFG 0x465
35 #define MII_DP83822_SOR1 0x467
38 #define DP83822_SIG_DET_LOW BIT(0)
40 /* Control Register 2 bits */
41 #define DP83822_FX_ENABLE BIT(14)
43 #define DP83822_HW_RESET BIT(15)
44 #define DP83822_SW_RESET BIT(14)
47 #define DP83822_PHYSTS_DUPLEX BIT(2)
48 #define DP83822_PHYSTS_10 BIT(1)
49 #define DP83822_PHYSTS_LINK BIT(0)
51 /* PHYSCR Register Fields */
52 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
53 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
56 #define DP83822_RX_ERR_HF_INT_EN BIT(0)
57 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
58 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
59 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
60 #define DP83822_SPEED_CHANGED_INT_EN BIT(4)
61 #define DP83822_LINK_STAT_INT_EN BIT(5)
62 #define DP83822_ENERGY_DET_INT_EN BIT(6)
63 #define DP83822_LINK_QUAL_INT_EN BIT(7)
66 #define DP83822_JABBER_DET_INT_EN BIT(0)
67 #define DP83822_WOL_PKT_INT_EN BIT(1)
68 #define DP83822_SLEEP_MODE_INT_EN BIT(2)
69 #define DP83822_MDI_XOVER_INT_EN BIT(3)
70 #define DP83822_LB_FIFO_INT_EN BIT(4)
71 #define DP83822_PAGE_RX_INT_EN BIT(5)
72 #define DP83822_ANEG_ERR_INT_EN BIT(6)
73 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
76 #define DP83822_WOL_INT_EN BIT(4)
77 #define DP83822_WOL_INT_STAT BIT(12)
79 #define MII_DP83822_RXSOP1 0x04a5
80 #define MII_DP83822_RXSOP2 0x04a6
81 #define MII_DP83822_RXSOP3 0x04a7
84 #define MII_DP83822_WOL_CFG 0x04a0
85 #define MII_DP83822_WOL_STAT 0x04a1
86 #define MII_DP83822_WOL_DA1 0x04a2
87 #define MII_DP83822_WOL_DA2 0x04a3
88 #define MII_DP83822_WOL_DA3 0x04a4
91 #define DP83822_WOL_MAGIC_EN BIT(0)
92 #define DP83822_WOL_SECURE_ON BIT(5)
93 #define DP83822_WOL_EN BIT(7)
94 #define DP83822_WOL_INDICATION_SEL BIT(8)
95 #define DP83822_WOL_CLR_INDICATION BIT(11)
98 #define DP83822_RX_CLK_SHIFT BIT(12)
99 #define DP83822_TX_CLK_SHIFT BIT(11)
102 #define DP83822_STRAP_MODE1 0
103 #define DP83822_STRAP_MODE2 BIT(0)
104 #define DP83822_STRAP_MODE3 BIT(1)
105 #define DP83822_STRAP_MODE4 GENMASK(1, 0)
107 #define DP83822_COL_STRAP_MASK GENMASK(11, 10)
108 #define DP83822_COL_SHIFT 10
109 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
110 #define DP83822_RX_ER_SHIFT 8
112 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
114 ADVERTISED_Pause | ADVERTISED_Asym_Pause)
116 struct dp83822_private {
117 bool fx_signal_det_low;
122 static int dp83822_set_wol(struct phy_device *phydev,
123 struct ethtool_wolinfo *wol)
125 struct net_device *ndev = phydev->attached_dev;
129 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
130 mac = (const u8 *)ndev->dev_addr;
132 if (!is_valid_ether_addr(mac))
135 /* MAC addresses start with byte 5, but stored in mac[0].
136 * 822 PHYs store bytes 4|5, 2|3, 0|1
138 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
139 (mac[1] << 8) | mac[0]);
140 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
141 (mac[3] << 8) | mac[2]);
142 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
143 (mac[5] << 8) | mac[4]);
145 value = phy_read_mmd(phydev, DP83822_DEVADDR,
146 MII_DP83822_WOL_CFG);
147 if (wol->wolopts & WAKE_MAGIC)
148 value |= DP83822_WOL_MAGIC_EN;
150 value &= ~DP83822_WOL_MAGIC_EN;
152 if (wol->wolopts & WAKE_MAGICSECURE) {
153 phy_write_mmd(phydev, DP83822_DEVADDR,
155 (wol->sopass[1] << 8) | wol->sopass[0]);
156 phy_write_mmd(phydev, DP83822_DEVADDR,
158 (wol->sopass[3] << 8) | wol->sopass[2]);
159 phy_write_mmd(phydev, DP83822_DEVADDR,
161 (wol->sopass[5] << 8) | wol->sopass[4]);
162 value |= DP83822_WOL_SECURE_ON;
164 value &= ~DP83822_WOL_SECURE_ON;
167 /* Clear any pending WoL interrupt */
168 phy_read(phydev, MII_DP83822_MISR2);
170 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
171 DP83822_WOL_CLR_INDICATION;
173 return phy_write_mmd(phydev, DP83822_DEVADDR,
174 MII_DP83822_WOL_CFG, value);
176 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
177 MII_DP83822_WOL_CFG, DP83822_WOL_EN);
181 static void dp83822_get_wol(struct phy_device *phydev,
182 struct ethtool_wolinfo *wol)
187 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
190 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
192 if (value & DP83822_WOL_MAGIC_EN)
193 wol->wolopts |= WAKE_MAGIC;
195 if (value & DP83822_WOL_SECURE_ON) {
196 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
198 wol->sopass[0] = (sopass_val & 0xff);
199 wol->sopass[1] = (sopass_val >> 8);
201 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
203 wol->sopass[2] = (sopass_val & 0xff);
204 wol->sopass[3] = (sopass_val >> 8);
206 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
208 wol->sopass[4] = (sopass_val & 0xff);
209 wol->sopass[5] = (sopass_val >> 8);
211 wol->wolopts |= WAKE_MAGICSECURE;
214 /* WoL is not enabled so set wolopts to 0 */
215 if (!(value & DP83822_WOL_EN))
219 static int dp83822_config_intr(struct phy_device *phydev)
221 struct dp83822_private *dp83822 = phydev->priv;
226 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
227 misr_status = phy_read(phydev, MII_DP83822_MISR1);
231 misr_status |= (DP83822_RX_ERR_HF_INT_EN |
232 DP83822_FALSE_CARRIER_HF_INT_EN |
233 DP83822_LINK_STAT_INT_EN |
234 DP83822_ENERGY_DET_INT_EN |
235 DP83822_LINK_QUAL_INT_EN);
237 if (!dp83822->fx_enabled)
238 misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
239 DP83822_DUP_MODE_CHANGE_INT_EN |
240 DP83822_SPEED_CHANGED_INT_EN;
243 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
247 misr_status = phy_read(phydev, MII_DP83822_MISR2);
251 misr_status |= (DP83822_JABBER_DET_INT_EN |
252 DP83822_SLEEP_MODE_INT_EN |
253 DP83822_LB_FIFO_INT_EN |
254 DP83822_PAGE_RX_INT_EN |
255 DP83822_EEE_ERROR_CHANGE_INT_EN);
257 if (!dp83822->fx_enabled)
258 misr_status |= DP83822_MDI_XOVER_INT_EN |
259 DP83822_ANEG_ERR_INT_EN |
260 DP83822_WOL_PKT_INT_EN;
262 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
266 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
267 if (physcr_status < 0)
268 return physcr_status;
270 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
273 err = phy_write(phydev, MII_DP83822_MISR1, 0);
277 err = phy_write(phydev, MII_DP83822_MISR1, 0);
281 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
282 if (physcr_status < 0)
283 return physcr_status;
285 physcr_status &= ~DP83822_PHYSCR_INTEN;
288 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
291 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
293 bool trigger_machine = false;
296 /* The MISR1 and MISR2 registers are holding the interrupt status in
297 * the upper half (15:8), while the lower half (7:0) is used for
298 * controlling the interrupt enable state of those individual interrupt
299 * sources. To determine the possible interrupt sources, just read the
300 * MISR* register and use it directly to know which interrupts have
301 * been enabled previously or not.
303 irq_status = phy_read(phydev, MII_DP83822_MISR1);
304 if (irq_status < 0) {
308 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
309 trigger_machine = true;
311 irq_status = phy_read(phydev, MII_DP83822_MISR2);
312 if (irq_status < 0) {
316 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
317 trigger_machine = true;
319 if (!trigger_machine)
322 phy_trigger_machine(phydev);
327 static int dp8382x_disable_wol(struct phy_device *phydev)
329 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,
330 DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
331 DP83822_WOL_SECURE_ON);
334 static int dp83822_read_status(struct phy_device *phydev)
336 struct dp83822_private *dp83822 = phydev->priv;
337 int status = phy_read(phydev, MII_DP83822_PHYSTS);
341 if (dp83822->fx_enabled) {
342 if (status & DP83822_PHYSTS_LINK) {
343 phydev->speed = SPEED_UNKNOWN;
344 phydev->duplex = DUPLEX_UNKNOWN;
346 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
350 if (!(ctrl2 & DP83822_FX_ENABLE)) {
351 ret = phy_write(phydev, MII_DP83822_CTRL_2,
352 DP83822_FX_ENABLE | ctrl2);
359 ret = genphy_read_status(phydev);
366 if (status & DP83822_PHYSTS_DUPLEX)
367 phydev->duplex = DUPLEX_FULL;
369 phydev->duplex = DUPLEX_HALF;
371 if (status & DP83822_PHYSTS_10)
372 phydev->speed = SPEED_10;
374 phydev->speed = SPEED_100;
379 static int dp83822_config_init(struct phy_device *phydev)
381 struct dp83822_private *dp83822 = phydev->priv;
382 struct device *dev = &phydev->mdio.dev;
389 if (phy_interface_is_rgmii(phydev)) {
390 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
393 if (rx_int_delay <= 0)
396 rgmii_delay = DP83822_RX_CLK_SHIFT;
398 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
400 if (tx_int_delay <= 0)
401 rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
403 rgmii_delay |= DP83822_TX_CLK_SHIFT;
406 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
407 MII_DP83822_RCSR, rgmii_delay);
413 if (dp83822->fx_enabled) {
414 err = phy_modify(phydev, MII_DP83822_CTRL_2,
415 DP83822_FX_ENABLE, 1);
419 /* Only allow advertising what this PHY supports */
420 linkmode_and(phydev->advertising, phydev->advertising,
423 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
425 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
426 phydev->advertising);
427 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
429 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
431 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
432 phydev->advertising);
433 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
434 phydev->advertising);
436 /* Auto neg is not supported in fiber mode */
437 bmcr = phy_read(phydev, MII_BMCR);
441 if (bmcr & BMCR_ANENABLE) {
442 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
446 phydev->autoneg = AUTONEG_DISABLE;
447 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
449 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
450 phydev->advertising);
452 /* Setup fiber advertisement */
453 err = phy_modify_changed(phydev, MII_ADVERTISE,
454 MII_DP83822_FIBER_ADVERTISE,
455 MII_DP83822_FIBER_ADVERTISE);
460 if (dp83822->fx_signal_det_low) {
461 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
463 DP83822_SIG_DET_LOW);
468 return dp8382x_disable_wol(phydev);
471 static int dp8382x_config_init(struct phy_device *phydev)
473 return dp8382x_disable_wol(phydev);
476 static int dp83822_phy_reset(struct phy_device *phydev)
480 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
484 return phydev->drv->config_init(phydev);
487 #ifdef CONFIG_OF_MDIO
488 static int dp83822_of_init(struct phy_device *phydev)
490 struct dp83822_private *dp83822 = phydev->priv;
491 struct device *dev = &phydev->mdio.dev;
493 /* Signal detection for the PHY is only enabled if the FX_EN and the
494 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
495 * is strapped otherwise signal detection is disabled for the PHY.
497 if (dp83822->fx_enabled && dp83822->fx_sd_enable)
498 dp83822->fx_signal_det_low = device_property_present(dev,
500 if (!dp83822->fx_enabled)
501 dp83822->fx_enabled = device_property_present(dev,
507 static int dp83822_of_init(struct phy_device *phydev)
511 #endif /* CONFIG_OF_MDIO */
513 static int dp83822_read_straps(struct phy_device *phydev)
515 struct dp83822_private *dp83822 = phydev->priv;
516 int fx_enabled, fx_sd_enable;
519 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
523 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
524 if (fx_enabled == DP83822_STRAP_MODE2 ||
525 fx_enabled == DP83822_STRAP_MODE3)
526 dp83822->fx_enabled = 1;
528 if (dp83822->fx_enabled) {
529 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
530 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
531 fx_sd_enable == DP83822_STRAP_MODE4)
532 dp83822->fx_sd_enable = 1;
538 static int dp83822_probe(struct phy_device *phydev)
540 struct dp83822_private *dp83822;
543 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
548 phydev->priv = dp83822;
550 ret = dp83822_read_straps(phydev);
554 dp83822_of_init(phydev);
556 if (dp83822->fx_enabled)
557 phydev->port = PORT_FIBRE;
562 static int dp83822_suspend(struct phy_device *phydev)
566 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
568 if (!(value & DP83822_WOL_EN))
569 genphy_suspend(phydev);
574 static int dp83822_resume(struct phy_device *phydev)
578 genphy_resume(phydev);
580 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
582 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
583 DP83822_WOL_CLR_INDICATION);
588 #define DP83822_PHY_DRIVER(_id, _name) \
590 PHY_ID_MATCH_MODEL(_id), \
592 /* PHY_BASIC_FEATURES */ \
593 .probe = dp83822_probe, \
594 .soft_reset = dp83822_phy_reset, \
595 .config_init = dp83822_config_init, \
596 .read_status = dp83822_read_status, \
597 .get_wol = dp83822_get_wol, \
598 .set_wol = dp83822_set_wol, \
599 .config_intr = dp83822_config_intr, \
600 .handle_interrupt = dp83822_handle_interrupt, \
601 .suspend = dp83822_suspend, \
602 .resume = dp83822_resume, \
605 #define DP8382X_PHY_DRIVER(_id, _name) \
607 PHY_ID_MATCH_MODEL(_id), \
609 /* PHY_BASIC_FEATURES */ \
610 .soft_reset = dp83822_phy_reset, \
611 .config_init = dp8382x_config_init, \
612 .get_wol = dp83822_get_wol, \
613 .set_wol = dp83822_set_wol, \
614 .config_intr = dp83822_config_intr, \
615 .handle_interrupt = dp83822_handle_interrupt, \
616 .suspend = dp83822_suspend, \
617 .resume = dp83822_resume, \
620 static struct phy_driver dp83822_driver[] = {
621 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
622 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
623 DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
624 DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
625 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
626 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
627 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
629 module_phy_driver(dp83822_driver);
631 static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
632 { DP83822_PHY_ID, 0xfffffff0 },
633 { DP83825I_PHY_ID, 0xfffffff0 },
634 { DP83826C_PHY_ID, 0xfffffff0 },
635 { DP83826NC_PHY_ID, 0xfffffff0 },
636 { DP83825S_PHY_ID, 0xfffffff0 },
637 { DP83825CM_PHY_ID, 0xfffffff0 },
638 { DP83825CS_PHY_ID, 0xfffffff0 },
641 MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
643 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
644 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
645 MODULE_LICENSE("GPL v2");