2 * Broadcom BCM7xxx internal transceivers support.
4 * Copyright (C) 2014-2017 Broadcom
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/delay.h>
15 #include "bcm-phy-lib.h"
16 #include <linux/bitops.h>
17 #include <linux/brcmphy.h>
18 #include <linux/mdio.h>
20 /* Broadcom BCM7xxx internal PHY registers */
22 /* EPHY only register definitions */
23 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
24 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
25 #define MII_BCM7XXX_100TX_DISC 0x14
26 #define MII_BCM7XXX_AUX_MODE 0x1d
27 #define MII_BCM7XXX_64CLK_MDIO BIT(12)
28 #define MII_BCM7XXX_TEST 0x1f
29 #define MII_BCM7XXX_SHD_MODE_2 BIT(2)
30 #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
31 #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
32 #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
33 #define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
34 #define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
35 #define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
36 #define MII_BCM7XXX_SHD_3_AN_STAT 0xb
37 #define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
38 #define MII_BCM7XXX_AN_EEE_EN BIT(1)
39 #define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
40 #define MII_BCM7XXX_EEE_THRESH_DEF 0x50
41 #define MII_BCM7XXX_SHD_3_TL4 0x23
42 #define MII_BCM7XXX_TL4_RST_MSK (BIT(2) | BIT(1))
44 /* 28nm only register definitions */
45 #define MISC_ADDR(base, channel) base, channel
47 #define DSP_TAP10 MISC_ADDR(0x0a, 0)
48 #define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
49 #define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
50 #define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
52 #define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
53 #define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
54 #define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
55 #define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
56 #define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
57 #define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
58 #define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
59 #define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
61 struct bcm7xxx_phy_priv {
65 static void r_rc_cal_reset(struct phy_device *phydev)
67 /* Reset R_CAL/RC_CAL Engine */
68 bcm_phy_write_exp(phydev, 0x00b0, 0x0010);
70 /* Disable Reset R_AL/RC_CAL Engine */
71 bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
74 static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
76 /* Increase VCO range to prevent unlocking problem of PLL at low
79 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
81 /* Change Ki to 011 */
82 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
84 /* Disable loading of TVCO buffer to bandgap, set bandgap trim
87 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
89 /* Adjust bias current trim by -3 */
90 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
92 /* Switch to CORE_BASE1E */
93 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
95 r_rc_cal_reset(phydev);
97 /* write AFE_RXCONFIG_0 */
98 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
100 /* write AFE_RXCONFIG_1 */
101 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
103 /* write AFE_RX_LP_COUNTER */
104 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
106 /* write AFE_HPF_TRIM_OTHERS */
107 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
109 /* write AFTE_TX_CONFIG */
110 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
115 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
118 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
121 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
123 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
124 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
126 /* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
127 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
129 /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
130 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
132 /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
133 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
135 /* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
136 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
138 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
139 * offset for HT=0 code
141 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
143 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
144 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
146 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
147 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
149 /* Reset R_CAL/RC_CAL engine */
150 r_rc_cal_reset(phydev);
155 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
157 /* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
158 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
160 /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
161 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
163 /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
164 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
166 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
167 * offset for HT=0 code
169 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
171 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
172 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
174 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
175 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
177 /* Reset R_CAL/RC_CAL engine */
178 r_rc_cal_reset(phydev);
183 static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
185 /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
186 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
188 /* Cut master bias current by 2% to compensate for RC_CAL offset */
189 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
191 /* Improve hybrid leakage */
192 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
194 /* Change rx_on_tune 8 to 0xf */
195 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
197 /* Change 100Tx EEE bandwidth */
198 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
200 /* Enable ffe zero detection for Vitesse interoperability */
201 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
203 r_rc_cal_reset(phydev);
208 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
210 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
211 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
215 /* Newer devices have moved the revision information back into a
216 * standard location in MII_PHYS_ID[23]
219 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
221 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
222 phydev_name(phydev), phydev->drv->name, rev, patch);
224 /* Dummy read to a register to workaround an issue upon reset where the
225 * internal inverter may not allow the first MDIO transaction to pass
226 * the MDIO management controller and make us return 0xffff for such
229 phy_read(phydev, MII_BMSR);
233 ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
236 ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
240 /* Rev G0 introduces a roll over */
242 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
245 ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
254 ret = bcm_phy_downshift_get(phydev, &count);
258 /* Only enable EEE if Wirespeed/downshift is disabled */
259 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
263 return bcm_phy_enable_apd(phydev, true);
266 static int bcm7xxx_28nm_resume(struct phy_device *phydev)
270 /* Re-apply workarounds coming out suspend/resume */
271 ret = bcm7xxx_28nm_config_init(phydev);
275 /* 28nm Gigabit PHYs come out of reset without any half-duplex
276 * or "hub" compliant advertised mode, fix that. This does not
277 * cause any problems with the PHY library since genphy_config_aneg()
278 * gracefully handles auto-negotiated and forced modes.
280 return genphy_config_aneg(phydev);
283 static int phy_set_clr_bits(struct phy_device *dev, int location,
284 int set_mask, int clr_mask)
288 v = phy_read(dev, location);
295 ret = phy_write(dev, location, v);
302 static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
306 /* set shadow mode 2 */
307 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
308 MII_BCM7XXX_SHD_MODE_2, 0);
312 /* Set current trim values INT_trim = -1, Ext_trim =0 */
313 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
315 goto reset_shadow_mode;
318 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
319 MII_BCM7XXX_SHD_3_TL4);
321 goto reset_shadow_mode;
322 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
323 MII_BCM7XXX_TL4_RST_MSK, 0);
325 goto reset_shadow_mode;
327 /* Cal reset disable */
328 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
329 MII_BCM7XXX_SHD_3_TL4);
331 goto reset_shadow_mode;
332 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
333 0, MII_BCM7XXX_TL4_RST_MSK);
335 goto reset_shadow_mode;
338 /* reset shadow mode 2 */
339 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
340 MII_BCM7XXX_SHD_MODE_2);
347 /* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
348 static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
352 /* set shadow mode 1 */
353 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
354 MII_BRCM_FET_BT_SRE, 0);
358 /* Enable auto-power down */
359 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
360 MII_BRCM_FET_SHDW_AS2_APDE, 0);
364 /* reset shadow mode 1 */
365 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
366 MII_BRCM_FET_BT_SRE);
373 static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
377 /* set shadow mode 2 */
378 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
379 MII_BCM7XXX_SHD_MODE_2, 0);
383 /* Advertise supported modes */
384 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
385 MII_BCM7XXX_SHD_3_AN_EEE_ADV);
387 goto reset_shadow_mode;
388 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
391 goto reset_shadow_mode;
393 /* Restore Defaults */
394 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
395 MII_BCM7XXX_SHD_3_PCS_CTRL_2);
397 goto reset_shadow_mode;
398 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
399 MII_BCM7XXX_PCS_CTRL_2_DEF);
401 goto reset_shadow_mode;
403 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
404 MII_BCM7XXX_SHD_3_EEE_THRESH);
406 goto reset_shadow_mode;
407 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
408 MII_BCM7XXX_EEE_THRESH_DEF);
410 goto reset_shadow_mode;
412 /* Enable EEE autonegotiation */
413 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
414 MII_BCM7XXX_SHD_3_AN_STAT);
416 goto reset_shadow_mode;
417 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
418 (MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
420 goto reset_shadow_mode;
423 /* reset shadow mode 2 */
424 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
425 MII_BCM7XXX_SHD_MODE_2);
429 /* Restart autoneg */
430 phy_write(phydev, MII_BMCR,
431 (BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
436 static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
438 u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
441 pr_info_once("%s: %s PHY revision: 0x%02x\n",
442 phydev_name(phydev), phydev->drv->name, rev);
444 /* Dummy read to a register to workaround a possible issue upon reset
445 * where the internal inverter may not allow the first MDIO transaction
446 * to pass the MDIO management controller and make us return 0xffff for
449 phy_read(phydev, MII_BMSR);
451 /* Apply AFE software work-around if necessary */
453 ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev);
458 ret = bcm7xxx_28nm_ephy_eee_enable(phydev);
462 return bcm7xxx_28nm_ephy_apd_enable(phydev);
465 static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
469 /* Re-apply workarounds coming out suspend/resume */
470 ret = bcm7xxx_28nm_ephy_config_init(phydev);
474 return genphy_config_aneg(phydev);
477 static int bcm7xxx_config_init(struct phy_device *phydev)
481 /* Enable 64 clock MDIO */
482 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
483 phy_read(phydev, MII_BCM7XXX_AUX_MODE);
485 /* set shadow mode 2 */
486 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
487 MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
491 /* set iddq_clkbias */
492 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
495 /* reset iddq_clkbias */
496 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
498 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
500 /* reset shadow mode 2 */
501 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
508 /* Workaround for putting the PHY in IDDQ mode, required
509 * for all BCM7XXX 40nm and 65nm PHYs
511 static int bcm7xxx_suspend(struct phy_device *phydev)
514 static const struct bcm7xxx_regs {
517 } bcm7xxx_suspend_cfg[] = {
518 { MII_BCM7XXX_TEST, 0x008b },
519 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
520 { MII_BCM7XXX_100TX_DISC, 0x7000 },
521 { MII_BCM7XXX_TEST, 0x000f },
522 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
523 { MII_BCM7XXX_TEST, 0x000b },
527 for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
528 ret = phy_write(phydev,
529 bcm7xxx_suspend_cfg[i].reg,
530 bcm7xxx_suspend_cfg[i].value);
538 static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
539 struct ethtool_tunable *tuna,
543 case ETHTOOL_PHY_DOWNSHIFT:
544 return bcm_phy_downshift_get(phydev, (u8 *)data);
550 static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
551 struct ethtool_tunable *tuna,
554 u8 count = *(u8 *)data;
558 case ETHTOOL_PHY_DOWNSHIFT:
559 ret = bcm_phy_downshift_set(phydev, count);
568 /* Disable EEE advertisment since this prevents the PHY
569 * from successfully linking up, trigger auto-negotiation restart
570 * to let the MAC decide what to do.
572 ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
576 return genphy_restart_aneg(phydev);
579 static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
580 struct ethtool_stats *stats, u64 *data)
582 struct bcm7xxx_phy_priv *priv = phydev->priv;
584 bcm_phy_get_stats(phydev, priv->stats, stats, data);
587 static int bcm7xxx_28nm_probe(struct phy_device *phydev)
589 struct bcm7xxx_phy_priv *priv;
591 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
597 priv->stats = devm_kcalloc(&phydev->mdio.dev,
598 bcm_phy_get_sset_count(phydev), sizeof(u64),
606 #define BCM7XXX_28NM_GPHY(_oui, _name) \
609 .phy_id_mask = 0xfffffff0, \
611 .features = PHY_GBIT_FEATURES, \
612 .flags = PHY_IS_INTERNAL, \
613 .config_init = bcm7xxx_28nm_config_init, \
614 .resume = bcm7xxx_28nm_resume, \
615 .get_tunable = bcm7xxx_28nm_get_tunable, \
616 .set_tunable = bcm7xxx_28nm_set_tunable, \
617 .get_sset_count = bcm_phy_get_sset_count, \
618 .get_strings = bcm_phy_get_strings, \
619 .get_stats = bcm7xxx_28nm_get_phy_stats, \
620 .probe = bcm7xxx_28nm_probe, \
623 #define BCM7XXX_28NM_EPHY(_oui, _name) \
626 .phy_id_mask = 0xfffffff0, \
628 .features = PHY_BASIC_FEATURES, \
629 .flags = PHY_IS_INTERNAL, \
630 .config_init = bcm7xxx_28nm_ephy_config_init, \
631 .resume = bcm7xxx_28nm_ephy_resume, \
632 .get_sset_count = bcm_phy_get_sset_count, \
633 .get_strings = bcm_phy_get_strings, \
634 .get_stats = bcm7xxx_28nm_get_phy_stats, \
635 .probe = bcm7xxx_28nm_probe, \
638 #define BCM7XXX_40NM_EPHY(_oui, _name) \
641 .phy_id_mask = 0xfffffff0, \
643 .features = PHY_BASIC_FEATURES, \
644 .flags = PHY_IS_INTERNAL, \
645 .config_init = bcm7xxx_config_init, \
646 .suspend = bcm7xxx_suspend, \
647 .resume = bcm7xxx_config_init, \
650 static struct phy_driver bcm7xxx_driver[] = {
651 BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
652 BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
653 BCM7XXX_28NM_EPHY(PHY_ID_BCM7268, "Broadcom BCM7268"),
654 BCM7XXX_28NM_EPHY(PHY_ID_BCM7271, "Broadcom BCM7271"),
655 BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
656 BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
657 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
658 BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
659 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
660 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
661 BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
662 BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
663 BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
664 BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
665 BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
666 BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
669 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
670 { PHY_ID_BCM7250, 0xfffffff0, },
671 { PHY_ID_BCM7260, 0xfffffff0, },
672 { PHY_ID_BCM7268, 0xfffffff0, },
673 { PHY_ID_BCM7271, 0xfffffff0, },
674 { PHY_ID_BCM7278, 0xfffffff0, },
675 { PHY_ID_BCM7364, 0xfffffff0, },
676 { PHY_ID_BCM7366, 0xfffffff0, },
677 { PHY_ID_BCM7346, 0xfffffff0, },
678 { PHY_ID_BCM7362, 0xfffffff0, },
679 { PHY_ID_BCM7425, 0xfffffff0, },
680 { PHY_ID_BCM7429, 0xfffffff0, },
681 { PHY_ID_BCM74371, 0xfffffff0, },
682 { PHY_ID_BCM7439, 0xfffffff0, },
683 { PHY_ID_BCM7435, 0xfffffff0, },
684 { PHY_ID_BCM7445, 0xfffffff0, },
688 module_phy_driver(bcm7xxx_driver);
690 MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
692 MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
693 MODULE_LICENSE("GPL");
694 MODULE_AUTHOR("Broadcom Corporation");