1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2017 Broadcom
6 #include "bcm-phy-lib.h"
7 #include <linux/bitfield.h>
8 #include <linux/brcmphy.h>
9 #include <linux/export.h>
10 #include <linux/mdio.h>
11 #include <linux/module.h>
12 #include <linux/phy.h>
13 #include <linux/ethtool.h>
14 #include <linux/ethtool_netlink.h>
16 #define MII_BCM_CHANNEL_WIDTH 0x2000
17 #define BCM_CL45VEN_EEE_ADV 0x3c
19 int __bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
23 rc = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
27 return __phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
29 EXPORT_SYMBOL_GPL(__bcm_phy_write_exp);
31 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
35 phy_lock_mdio_bus(phydev);
36 rc = __bcm_phy_write_exp(phydev, reg, val);
37 phy_unlock_mdio_bus(phydev);
41 EXPORT_SYMBOL_GPL(bcm_phy_write_exp);
43 int __bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
47 val = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
51 val = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
53 /* Restore default value. It's O.K. if this write fails. */
54 __phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
58 EXPORT_SYMBOL_GPL(__bcm_phy_read_exp);
60 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
64 phy_lock_mdio_bus(phydev);
65 rc = __bcm_phy_read_exp(phydev, reg);
66 phy_unlock_mdio_bus(phydev);
70 EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
72 int __bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
76 ret = __phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
80 ret = __phy_read(phydev, MII_BCM54XX_EXP_DATA);
84 new = (ret & ~mask) | set;
88 return __phy_write(phydev, MII_BCM54XX_EXP_DATA, new);
90 EXPORT_SYMBOL_GPL(__bcm_phy_modify_exp);
92 int bcm_phy_modify_exp(struct phy_device *phydev, u16 reg, u16 mask, u16 set)
96 phy_lock_mdio_bus(phydev);
97 ret = __bcm_phy_modify_exp(phydev, reg, mask, set);
98 phy_unlock_mdio_bus(phydev);
102 EXPORT_SYMBOL_GPL(bcm_phy_modify_exp);
104 int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
106 /* The register must be written to both the Shadow Register Select and
107 * the Shadow Read Register Selector
109 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK |
110 regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
111 return phy_read(phydev, MII_BCM54XX_AUX_CTL);
113 EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
115 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
117 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
119 EXPORT_SYMBOL(bcm54xx_auxctl_write);
121 int bcm_phy_write_misc(struct phy_device *phydev,
122 u16 reg, u16 chl, u16 val)
127 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
128 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
132 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
133 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
134 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
138 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
139 rc = bcm_phy_write_exp(phydev, tmp, val);
143 EXPORT_SYMBOL_GPL(bcm_phy_write_misc);
145 int bcm_phy_read_misc(struct phy_device *phydev,
151 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
152 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
156 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
157 tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
158 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
162 tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
163 rc = bcm_phy_read_exp(phydev, tmp);
167 EXPORT_SYMBOL_GPL(bcm_phy_read_misc);
169 int bcm_phy_ack_intr(struct phy_device *phydev)
173 /* Clear pending interrupts. */
174 reg = phy_read(phydev, MII_BCM54XX_ISR);
180 EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);
182 int bcm_phy_config_intr(struct phy_device *phydev)
186 reg = phy_read(phydev, MII_BCM54XX_ECR);
190 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
191 err = bcm_phy_ack_intr(phydev);
195 reg &= ~MII_BCM54XX_ECR_IM;
196 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
198 reg |= MII_BCM54XX_ECR_IM;
199 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
203 err = bcm_phy_ack_intr(phydev);
207 EXPORT_SYMBOL_GPL(bcm_phy_config_intr);
209 irqreturn_t bcm_phy_handle_interrupt(struct phy_device *phydev)
211 int irq_status, irq_mask;
213 irq_status = phy_read(phydev, MII_BCM54XX_ISR);
214 if (irq_status < 0) {
219 /* If a bit from the Interrupt Mask register is set, the corresponding
220 * bit from the Interrupt Status register is masked. So read the IMR
221 * and then flip the bits to get the list of possible interrupt
224 irq_mask = phy_read(phydev, MII_BCM54XX_IMR);
229 irq_mask = ~irq_mask;
231 if (!(irq_status & irq_mask))
234 phy_trigger_machine(phydev);
238 EXPORT_SYMBOL_GPL(bcm_phy_handle_interrupt);
240 int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
242 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
243 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
245 EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);
247 int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
250 return phy_write(phydev, MII_BCM54XX_SHD,
251 MII_BCM54XX_SHD_WRITE |
252 MII_BCM54XX_SHD_VAL(shadow) |
253 MII_BCM54XX_SHD_DATA(val));
255 EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);
257 int __bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
261 val = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
265 return __phy_read(phydev, MII_BCM54XX_RDB_DATA);
267 EXPORT_SYMBOL_GPL(__bcm_phy_read_rdb);
269 int bcm_phy_read_rdb(struct phy_device *phydev, u16 rdb)
273 phy_lock_mdio_bus(phydev);
274 ret = __bcm_phy_read_rdb(phydev, rdb);
275 phy_unlock_mdio_bus(phydev);
279 EXPORT_SYMBOL_GPL(bcm_phy_read_rdb);
281 int __bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
285 ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
289 return __phy_write(phydev, MII_BCM54XX_RDB_DATA, val);
291 EXPORT_SYMBOL_GPL(__bcm_phy_write_rdb);
293 int bcm_phy_write_rdb(struct phy_device *phydev, u16 rdb, u16 val)
297 phy_lock_mdio_bus(phydev);
298 ret = __bcm_phy_write_rdb(phydev, rdb, val);
299 phy_unlock_mdio_bus(phydev);
303 EXPORT_SYMBOL_GPL(bcm_phy_write_rdb);
305 int __bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
309 ret = __phy_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
313 ret = __phy_read(phydev, MII_BCM54XX_RDB_DATA);
317 new = (ret & ~mask) | set;
321 return __phy_write(phydev, MII_BCM54XX_RDB_DATA, new);
323 EXPORT_SYMBOL_GPL(__bcm_phy_modify_rdb);
325 int bcm_phy_modify_rdb(struct phy_device *phydev, u16 rdb, u16 mask, u16 set)
329 phy_lock_mdio_bus(phydev);
330 ret = __bcm_phy_modify_rdb(phydev, rdb, mask, set);
331 phy_unlock_mdio_bus(phydev);
335 EXPORT_SYMBOL_GPL(bcm_phy_modify_rdb);
337 int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
342 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
346 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
347 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
350 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
355 val &= BCM_APD_CLR_MASK;
357 if (phydev->autoneg == AUTONEG_ENABLE)
358 val |= BCM54XX_SHD_APD_EN;
360 val |= BCM_NO_ANEG_APD_EN;
362 /* Enable energy detect single link pulse for easy wakeup */
363 val |= BCM_APD_SINGLELP_EN;
365 /* Enable Auto Power-Down (APD) for the PHY */
366 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
368 EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);
370 int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
374 /* Enable EEE at PHY level */
375 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL);
380 val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
382 val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X);
384 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val);
387 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV);
392 val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
394 val &= ~(MDIO_EEE_100TX | MDIO_EEE_1000T);
396 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val);
400 EXPORT_SYMBOL_GPL(bcm_phy_set_eee);
402 int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
406 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
410 /* Check if wirespeed is enabled or not */
411 if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) {
412 *count = DOWNSHIFT_DEV_DISABLE;
416 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
420 /* Downgrade after one link attempt */
421 if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) {
424 /* Downgrade after configured retry count */
425 val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
426 val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK;
427 *count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET;
432 EXPORT_SYMBOL_GPL(bcm_phy_downshift_get);
434 int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
436 int val = 0, ret = 0;
438 /* Range check the number given */
439 if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET >
440 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK &&
441 count != DOWNSHIFT_DEV_DEFAULT_COUNT) {
445 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
449 /* Se the write enable bit */
450 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
452 if (count == DOWNSHIFT_DEV_DISABLE) {
453 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
454 return bcm54xx_auxctl_write(phydev,
455 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
458 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
459 ret = bcm54xx_auxctl_write(phydev,
460 MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
466 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
467 val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK <<
468 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT |
469 BCM54XX_SHD_SCR2_WSPD_RTRY_DIS);
473 val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS;
475 case DOWNSHIFT_DEV_DEFAULT_COUNT:
476 val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
479 val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) <<
480 BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
484 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
486 EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
488 struct bcm_phy_hw_stat {
495 /* Counters freeze at either 0xffff or 0xff, better than nothing */
496 static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
497 { "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
498 { "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
499 { "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
500 { "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
501 { "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
504 int bcm_phy_get_sset_count(struct phy_device *phydev)
506 return ARRAY_SIZE(bcm_phy_hw_stats);
508 EXPORT_SYMBOL_GPL(bcm_phy_get_sset_count);
510 void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
514 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
515 strlcpy(data + i * ETH_GSTRING_LEN,
516 bcm_phy_hw_stats[i].string, ETH_GSTRING_LEN);
518 EXPORT_SYMBOL_GPL(bcm_phy_get_strings);
520 /* Caller is supposed to provide appropriate storage for the library code to
521 * access the shadow copy
523 static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
526 struct bcm_phy_hw_stat stat = bcm_phy_hw_stats[i];
530 val = phy_read(phydev, stat.reg);
535 val = val & ((1 << stat.bits) - 1);
543 void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
544 struct ethtool_stats *stats, u64 *data)
548 for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
549 data[i] = bcm_phy_get_stat(phydev, shadow, i);
551 EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
553 void bcm_phy_r_rc_cal_reset(struct phy_device *phydev)
555 /* Reset R_CAL/RC_CAL Engine */
556 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010);
558 /* Disable Reset R_AL/RC_CAL Engine */
559 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000);
561 EXPORT_SYMBOL_GPL(bcm_phy_r_rc_cal_reset);
563 int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev)
565 /* Increase VCO range to prevent unlocking problem of PLL at low
568 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
570 /* Change Ki to 011 */
571 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
573 /* Disable loading of TVCO buffer to bandgap, set bandgap trim
576 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
578 /* Adjust bias current trim by -3 */
579 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
581 /* Switch to CORE_BASE1E */
582 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
584 bcm_phy_r_rc_cal_reset(phydev);
586 /* write AFE_RXCONFIG_0 */
587 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
589 /* write AFE_RXCONFIG_1 */
590 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
592 /* write AFE_RX_LP_COUNTER */
593 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
595 /* write AFE_HPF_TRIM_OTHERS */
596 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
598 /* write AFTE_TX_CONFIG */
599 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
603 EXPORT_SYMBOL_GPL(bcm_phy_28nm_a0b0_afe_config_init);
605 int bcm_phy_enable_jumbo(struct phy_device *phydev)
609 ret = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL);
613 /* Enable extended length packet reception */
614 ret = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
615 ret | MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN);
619 /* Enable the elastic FIFO for raising the transmission limit from
620 * 4.5KB to 10KB, at the expense of an additional 16 ns in propagation
623 return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE);
625 EXPORT_SYMBOL_GPL(bcm_phy_enable_jumbo);
627 static int __bcm_phy_enable_rdb_access(struct phy_device *phydev)
629 return __bcm_phy_write_exp(phydev, BCM54XX_EXP_REG7E, 0);
632 static int __bcm_phy_enable_legacy_access(struct phy_device *phydev)
634 return __bcm_phy_write_rdb(phydev, BCM54XX_RDB_REG0087,
635 BCM54XX_ACCESS_MODE_LEGACY_EN);
638 static int _bcm_phy_cable_test_start(struct phy_device *phydev, bool is_rdb)
643 /* Auto-negotiation must be enabled for cable diagnostics to work, but
644 * don't advertise any capabilities.
646 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
647 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
648 phy_write(phydev, MII_CTRL1000, 0);
650 phy_lock_mdio_bus(phydev);
652 ret = __bcm_phy_enable_legacy_access(phydev);
657 mask = BCM54XX_ECD_CTRL_CROSS_SHORT_DIS | BCM54XX_ECD_CTRL_UNIT_MASK;
658 set = BCM54XX_ECD_CTRL_RUN | BCM54XX_ECD_CTRL_BREAK_LINK |
659 FIELD_PREP(BCM54XX_ECD_CTRL_UNIT_MASK,
660 BCM54XX_ECD_CTRL_UNIT_CM);
662 ret = __bcm_phy_modify_exp(phydev, BCM54XX_EXP_ECD_CTRL, mask, set);
665 /* re-enable the RDB access even if there was an error */
667 ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
669 phy_unlock_mdio_bus(phydev);
674 static int bcm_phy_cable_test_report_trans(int result)
677 case BCM54XX_ECD_FAULT_TYPE_OK:
678 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
679 case BCM54XX_ECD_FAULT_TYPE_OPEN:
680 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
681 case BCM54XX_ECD_FAULT_TYPE_SAME_SHORT:
682 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
683 case BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT:
684 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
685 case BCM54XX_ECD_FAULT_TYPE_INVALID:
686 case BCM54XX_ECD_FAULT_TYPE_BUSY:
688 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
692 static bool bcm_phy_distance_valid(int result)
695 case BCM54XX_ECD_FAULT_TYPE_OPEN:
696 case BCM54XX_ECD_FAULT_TYPE_SAME_SHORT:
697 case BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT:
703 static int bcm_phy_report_length(struct phy_device *phydev, int pair)
707 val = __bcm_phy_read_exp(phydev,
708 BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS + pair);
712 if (val == BCM54XX_ECD_LENGTH_RESULTS_INVALID)
715 ethnl_cable_test_fault_length(phydev, pair, val);
720 static int _bcm_phy_cable_test_get_status(struct phy_device *phydev,
721 bool *finished, bool is_rdb)
723 int pair_a, pair_b, pair_c, pair_d, ret;
727 phy_lock_mdio_bus(phydev);
730 ret = __bcm_phy_enable_legacy_access(phydev);
735 ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_CTRL);
739 if (ret & BCM54XX_ECD_CTRL_IN_PROGRESS) {
744 ret = __bcm_phy_read_exp(phydev, BCM54XX_EXP_ECD_FAULT_TYPE);
748 pair_a = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK, ret);
749 pair_b = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK, ret);
750 pair_c = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK, ret);
751 pair_d = FIELD_GET(BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK, ret);
753 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
754 bcm_phy_cable_test_report_trans(pair_a));
755 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
756 bcm_phy_cable_test_report_trans(pair_b));
757 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
758 bcm_phy_cable_test_report_trans(pair_c));
759 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
760 bcm_phy_cable_test_report_trans(pair_d));
762 if (bcm_phy_distance_valid(pair_a))
763 bcm_phy_report_length(phydev, 0);
764 if (bcm_phy_distance_valid(pair_b))
765 bcm_phy_report_length(phydev, 1);
766 if (bcm_phy_distance_valid(pair_c))
767 bcm_phy_report_length(phydev, 2);
768 if (bcm_phy_distance_valid(pair_d))
769 bcm_phy_report_length(phydev, 3);
774 /* re-enable the RDB access even if there was an error */
776 ret = __bcm_phy_enable_rdb_access(phydev) ? : ret;
778 phy_unlock_mdio_bus(phydev);
783 int bcm_phy_cable_test_start(struct phy_device *phydev)
785 return _bcm_phy_cable_test_start(phydev, false);
787 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_start);
789 int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished)
791 return _bcm_phy_cable_test_get_status(phydev, finished, false);
793 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_get_status);
795 /* We assume that all PHYs which support RDB access can be switched to legacy
796 * mode. If, in the future, this is not true anymore, we have to re-implement
797 * this with RDB access.
799 int bcm_phy_cable_test_start_rdb(struct phy_device *phydev)
801 return _bcm_phy_cable_test_start(phydev, true);
803 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_start_rdb);
805 int bcm_phy_cable_test_get_status_rdb(struct phy_device *phydev,
808 return _bcm_phy_cable_test_get_status(phydev, finished, true);
810 EXPORT_SYMBOL_GPL(bcm_phy_cable_test_get_status_rdb);
812 MODULE_DESCRIPTION("Broadcom PHY Library");
813 MODULE_LICENSE("GPL v2");
814 MODULE_AUTHOR("Broadcom Corporation");