1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/at803x.c
5 * Driver for Atheros 803x PHY
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
10 #include <linux/phy.h>
11 #include <linux/module.h>
12 #include <linux/string.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/of_gpio.h>
16 #include <linux/gpio/consumer.h>
18 #define AT803X_INTR_ENABLE 0x12
19 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
20 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
21 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
22 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
23 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
24 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
25 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
26 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
27 #define AT803X_INTR_ENABLE_WOL BIT(0)
29 #define AT803X_INTR_STATUS 0x13
31 #define AT803X_SMART_SPEED 0x14
32 #define AT803X_LED_CONTROL 0x18
34 #define AT803X_DEVICE_ADDR 0x03
35 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
36 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
37 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
38 #define AT803X_REG_CHIP_CONFIG 0x1f
39 #define AT803X_BT_BX_REG_SEL 0x8000
41 #define AT803X_DEBUG_ADDR 0x1D
42 #define AT803X_DEBUG_DATA 0x1E
44 #define AT803X_MODE_CFG_MASK 0x0F
45 #define AT803X_MODE_CFG_SGMII 0x01
47 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
48 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
50 #define AT803X_DEBUG_REG_0 0x00
51 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
53 #define AT803X_DEBUG_REG_5 0x05
54 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
56 #define ATH8030_PHY_ID 0x004dd076
57 #define ATH8031_PHY_ID 0x004dd074
58 #define ATH8035_PHY_ID 0x004dd072
59 #define AT803X_PHY_ID_MASK 0xffffffef
61 MODULE_DESCRIPTION("Atheros 803x PHY driver");
62 MODULE_AUTHOR("Matus Ujhelyi");
63 MODULE_LICENSE("GPL");
69 struct at803x_context {
78 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
82 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
86 return phy_read(phydev, AT803X_DEBUG_DATA);
89 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
95 ret = at803x_debug_reg_read(phydev, reg);
103 return phy_write(phydev, AT803X_DEBUG_DATA, val);
106 static int at803x_enable_rx_delay(struct phy_device *phydev)
108 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
109 AT803X_DEBUG_RX_CLK_DLY_EN);
112 static int at803x_enable_tx_delay(struct phy_device *phydev)
114 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
115 AT803X_DEBUG_TX_CLK_DLY_EN);
118 static int at803x_disable_rx_delay(struct phy_device *phydev)
120 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
121 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
124 static int at803x_disable_tx_delay(struct phy_device *phydev)
126 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
127 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
130 /* save relevant PHY registers to private copy */
131 static void at803x_context_save(struct phy_device *phydev,
132 struct at803x_context *context)
134 context->bmcr = phy_read(phydev, MII_BMCR);
135 context->advertise = phy_read(phydev, MII_ADVERTISE);
136 context->control1000 = phy_read(phydev, MII_CTRL1000);
137 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
138 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
139 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
142 /* restore relevant PHY registers from private copy */
143 static void at803x_context_restore(struct phy_device *phydev,
144 const struct at803x_context *context)
146 phy_write(phydev, MII_BMCR, context->bmcr);
147 phy_write(phydev, MII_ADVERTISE, context->advertise);
148 phy_write(phydev, MII_CTRL1000, context->control1000);
149 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
150 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
151 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
154 static int at803x_set_wol(struct phy_device *phydev,
155 struct ethtool_wolinfo *wol)
157 struct net_device *ndev = phydev->attached_dev;
161 unsigned int i, offsets[] = {
162 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
163 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
164 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
170 if (wol->wolopts & WAKE_MAGIC) {
171 mac = (const u8 *) ndev->dev_addr;
173 if (!is_valid_ether_addr(mac))
176 for (i = 0; i < 3; i++)
177 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
178 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
180 value = phy_read(phydev, AT803X_INTR_ENABLE);
181 value |= AT803X_INTR_ENABLE_WOL;
182 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
185 value = phy_read(phydev, AT803X_INTR_STATUS);
187 value = phy_read(phydev, AT803X_INTR_ENABLE);
188 value &= (~AT803X_INTR_ENABLE_WOL);
189 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
192 value = phy_read(phydev, AT803X_INTR_STATUS);
198 static void at803x_get_wol(struct phy_device *phydev,
199 struct ethtool_wolinfo *wol)
203 wol->supported = WAKE_MAGIC;
206 value = phy_read(phydev, AT803X_INTR_ENABLE);
207 if (value & AT803X_INTR_ENABLE_WOL)
208 wol->wolopts |= WAKE_MAGIC;
211 static int at803x_suspend(struct phy_device *phydev)
216 value = phy_read(phydev, AT803X_INTR_ENABLE);
217 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
220 value = BMCR_ISOLATE;
224 phy_modify(phydev, MII_BMCR, 0, value);
229 static int at803x_resume(struct phy_device *phydev)
231 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
234 static int at803x_probe(struct phy_device *phydev)
236 struct device *dev = &phydev->mdio.dev;
237 struct at803x_priv *priv;
239 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
248 static int at803x_config_init(struct phy_device *phydev)
252 /* The RX and TX delay default is:
253 * after HW reset: RX delay enabled and TX delay disabled
254 * after SW reset: RX delay enabled, while TX delay retains the
255 * value before reset.
257 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
258 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
259 ret = at803x_enable_rx_delay(phydev);
261 ret = at803x_disable_rx_delay(phydev);
265 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
266 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
267 ret = at803x_enable_tx_delay(phydev);
269 ret = at803x_disable_tx_delay(phydev);
274 static int at803x_ack_interrupt(struct phy_device *phydev)
278 err = phy_read(phydev, AT803X_INTR_STATUS);
280 return (err < 0) ? err : 0;
283 static int at803x_config_intr(struct phy_device *phydev)
288 value = phy_read(phydev, AT803X_INTR_ENABLE);
290 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
291 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
292 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
293 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
294 value |= AT803X_INTR_ENABLE_LINK_FAIL;
295 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
297 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
300 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
305 static void at803x_link_change_notify(struct phy_device *phydev)
308 * Conduct a hardware reset for AT8030 every time a link loss is
309 * signalled. This is necessary to circumvent a hardware bug that
310 * occurs when the cable is unplugged while TX packets are pending
311 * in the FIFO. In such cases, the FIFO enters an error mode it
312 * cannot recover from by software.
314 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
315 struct at803x_context context;
317 at803x_context_save(phydev, &context);
319 phy_device_reset(phydev, 1);
321 phy_device_reset(phydev, 0);
324 at803x_context_restore(phydev, &context);
326 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
330 static int at803x_aneg_done(struct phy_device *phydev)
334 int aneg_done = genphy_aneg_done(phydev);
335 if (aneg_done != BMSR_ANEGCOMPLETE)
339 * in SGMII mode, if copper side autoneg is successful,
340 * also check SGMII side autoneg result
342 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
343 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
346 /* switch to SGMII/fiber page */
347 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
349 /* check if the SGMII link is OK. */
350 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
351 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
354 /* switch back to copper page */
355 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
360 static struct phy_driver at803x_driver[] = {
363 .phy_id = ATH8035_PHY_ID,
364 .name = "Atheros 8035 ethernet",
365 .phy_id_mask = AT803X_PHY_ID_MASK,
366 .probe = at803x_probe,
367 .config_init = at803x_config_init,
368 .set_wol = at803x_set_wol,
369 .get_wol = at803x_get_wol,
370 .suspend = at803x_suspend,
371 .resume = at803x_resume,
372 /* PHY_GBIT_FEATURES */
373 .ack_interrupt = at803x_ack_interrupt,
374 .config_intr = at803x_config_intr,
377 .phy_id = ATH8030_PHY_ID,
378 .name = "Atheros 8030 ethernet",
379 .phy_id_mask = AT803X_PHY_ID_MASK,
380 .probe = at803x_probe,
381 .config_init = at803x_config_init,
382 .link_change_notify = at803x_link_change_notify,
383 .set_wol = at803x_set_wol,
384 .get_wol = at803x_get_wol,
385 .suspend = at803x_suspend,
386 .resume = at803x_resume,
387 /* PHY_BASIC_FEATURES */
388 .ack_interrupt = at803x_ack_interrupt,
389 .config_intr = at803x_config_intr,
392 .phy_id = ATH8031_PHY_ID,
393 .name = "Atheros 8031 ethernet",
394 .phy_id_mask = AT803X_PHY_ID_MASK,
395 .probe = at803x_probe,
396 .config_init = at803x_config_init,
397 .set_wol = at803x_set_wol,
398 .get_wol = at803x_get_wol,
399 .suspend = at803x_suspend,
400 .resume = at803x_resume,
401 /* PHY_GBIT_FEATURES */
402 .aneg_done = at803x_aneg_done,
403 .ack_interrupt = &at803x_ack_interrupt,
404 .config_intr = &at803x_config_intr,
407 module_phy_driver(at803x_driver);
409 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
410 { ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
411 { ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
412 { ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
416 MODULE_DEVICE_TABLE(mdio, atheros_tbl);