1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/at803x.c
5 * Driver for Qualcomm Atheros AR803x PHY
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
10 #include <linux/phy.h>
11 #include <linux/module.h>
12 #include <linux/string.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/of_gpio.h>
17 #include <linux/bitfield.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/regulator/of_regulator.h>
20 #include <linux/regulator/driver.h>
21 #include <linux/regulator/consumer.h>
22 #include <dt-bindings/net/qca-ar803x.h>
24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
25 #define AT803X_SFC_ASSERT_CRS BIT(11)
26 #define AT803X_SFC_FORCE_LINK BIT(10)
27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
29 #define AT803X_SFC_MANUAL_MDIX 0x1
30 #define AT803X_SFC_MANUAL_MDI 0x0
31 #define AT803X_SFC_SQE_TEST BIT(2)
32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1)
33 #define AT803X_SFC_DISABLE_JABBER BIT(0)
35 #define AT803X_SPECIFIC_STATUS 0x11
36 #define AT803X_SS_SPEED_MASK (3 << 14)
37 #define AT803X_SS_SPEED_1000 (2 << 14)
38 #define AT803X_SS_SPEED_100 (1 << 14)
39 #define AT803X_SS_SPEED_10 (0 << 14)
40 #define AT803X_SS_DUPLEX BIT(13)
41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
42 #define AT803X_SS_MDIX BIT(6)
44 #define AT803X_INTR_ENABLE 0x12
45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
53 #define AT803X_INTR_ENABLE_WOL BIT(0)
55 #define AT803X_INTR_STATUS 0x13
57 #define AT803X_SMART_SPEED 0x14
58 #define AT803X_SMART_SPEED_ENABLE BIT(5)
59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
61 #define AT803X_CDT 0x16
62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
63 #define AT803X_CDT_ENABLE_TEST BIT(0)
64 #define AT803X_CDT_STATUS 0x1c
65 #define AT803X_CDT_STATUS_STAT_NORMAL 0
66 #define AT803X_CDT_STATUS_STAT_SHORT 1
67 #define AT803X_CDT_STATUS_STAT_OPEN 2
68 #define AT803X_CDT_STATUS_STAT_FAIL 3
69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
71 #define AT803X_LED_CONTROL 0x18
73 #define AT803X_DEVICE_ADDR 0x03
74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
77 #define AT803X_REG_CHIP_CONFIG 0x1f
78 #define AT803X_BT_BX_REG_SEL 0x8000
80 #define AT803X_DEBUG_ADDR 0x1D
81 #define AT803X_DEBUG_DATA 0x1E
83 #define AT803X_MODE_CFG_MASK 0x0F
84 #define AT803X_MODE_CFG_SGMII 0x01
86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200
89 #define AT803X_DEBUG_REG_0 0x00
90 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
92 #define AT803X_DEBUG_REG_5 0x05
93 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
95 #define AT803X_DEBUG_REG_1F 0x1F
96 #define AT803X_DEBUG_PLL_ON BIT(2)
97 #define AT803X_DEBUG_RGMII_1V8 BIT(3)
99 /* AT803x supports either the XTAL input pad, an internal PLL or the
100 * DSP as clock reference for the clock output pad. The XTAL reference
101 * is only used for 25 MHz output, all other frequencies need the PLL.
102 * The DSP as a clock reference is used in synchronous ethernet
105 * By default the PLL is only enabled if there is a link. Otherwise
106 * the PHY will go into low power state and disabled the PLL. You can
107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
110 #define AT803X_MMD7_CLK25M 0x8016
111 #define AT803X_CLK_OUT_MASK GENMASK(4, 2)
112 #define AT803X_CLK_OUT_25MHZ_XTAL 0
113 #define AT803X_CLK_OUT_25MHZ_DSP 1
114 #define AT803X_CLK_OUT_50MHZ_PLL 2
115 #define AT803X_CLK_OUT_50MHZ_DSP 3
116 #define AT803X_CLK_OUT_62_5MHZ_PLL 4
117 #define AT803X_CLK_OUT_62_5MHZ_DSP 5
118 #define AT803X_CLK_OUT_125MHZ_PLL 6
119 #define AT803X_CLK_OUT_125MHZ_DSP 7
121 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
122 * but doesn't support choosing between XTAL/PLL and DSP.
124 #define AT8035_CLK_OUT_MASK GENMASK(4, 3)
126 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
127 #define AT803X_CLK_OUT_STRENGTH_FULL 0
128 #define AT803X_CLK_OUT_STRENGTH_HALF 1
129 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2
131 #define AT803X_DEFAULT_DOWNSHIFT 5
132 #define AT803X_MIN_DOWNSHIFT 2
133 #define AT803X_MAX_DOWNSHIFT 9
135 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b
136 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c
137 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d
138 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
140 #define ATH9331_PHY_ID 0x004dd041
141 #define ATH8030_PHY_ID 0x004dd076
142 #define ATH8031_PHY_ID 0x004dd074
143 #define ATH8032_PHY_ID 0x004dd023
144 #define ATH8035_PHY_ID 0x004dd072
145 #define AT8030_PHY_ID_MASK 0xffffffef
147 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
148 MODULE_AUTHOR("Matus Ujhelyi");
149 MODULE_LICENSE("GPL");
153 #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
154 #define AT803X_DISABLE_SMARTEEE BIT(1)
157 u8 smarteee_lpi_tw_1g;
158 u8 smarteee_lpi_tw_100m;
159 struct regulator_dev *vddio_rdev;
160 struct regulator_dev *vddh_rdev;
161 struct regulator *vddio;
164 struct at803x_context {
173 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
177 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
181 return phy_read(phydev, AT803X_DEBUG_DATA);
184 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
190 ret = at803x_debug_reg_read(phydev, reg);
198 return phy_write(phydev, AT803X_DEBUG_DATA, val);
201 static int at803x_enable_rx_delay(struct phy_device *phydev)
203 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
204 AT803X_DEBUG_RX_CLK_DLY_EN);
207 static int at803x_enable_tx_delay(struct phy_device *phydev)
209 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
210 AT803X_DEBUG_TX_CLK_DLY_EN);
213 static int at803x_disable_rx_delay(struct phy_device *phydev)
215 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
216 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
219 static int at803x_disable_tx_delay(struct phy_device *phydev)
221 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
222 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
225 /* save relevant PHY registers to private copy */
226 static void at803x_context_save(struct phy_device *phydev,
227 struct at803x_context *context)
229 context->bmcr = phy_read(phydev, MII_BMCR);
230 context->advertise = phy_read(phydev, MII_ADVERTISE);
231 context->control1000 = phy_read(phydev, MII_CTRL1000);
232 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
233 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
234 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
237 /* restore relevant PHY registers from private copy */
238 static void at803x_context_restore(struct phy_device *phydev,
239 const struct at803x_context *context)
241 phy_write(phydev, MII_BMCR, context->bmcr);
242 phy_write(phydev, MII_ADVERTISE, context->advertise);
243 phy_write(phydev, MII_CTRL1000, context->control1000);
244 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
245 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
246 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
249 static int at803x_set_wol(struct phy_device *phydev,
250 struct ethtool_wolinfo *wol)
252 struct net_device *ndev = phydev->attached_dev;
256 unsigned int i, offsets[] = {
257 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
258 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
259 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
265 if (wol->wolopts & WAKE_MAGIC) {
266 mac = (const u8 *) ndev->dev_addr;
268 if (!is_valid_ether_addr(mac))
271 for (i = 0; i < 3; i++)
272 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
273 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
275 value = phy_read(phydev, AT803X_INTR_ENABLE);
276 value |= AT803X_INTR_ENABLE_WOL;
277 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
280 value = phy_read(phydev, AT803X_INTR_STATUS);
282 value = phy_read(phydev, AT803X_INTR_ENABLE);
283 value &= (~AT803X_INTR_ENABLE_WOL);
284 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
287 value = phy_read(phydev, AT803X_INTR_STATUS);
293 static void at803x_get_wol(struct phy_device *phydev,
294 struct ethtool_wolinfo *wol)
298 wol->supported = WAKE_MAGIC;
301 value = phy_read(phydev, AT803X_INTR_ENABLE);
302 if (value & AT803X_INTR_ENABLE_WOL)
303 wol->wolopts |= WAKE_MAGIC;
306 static int at803x_suspend(struct phy_device *phydev)
311 value = phy_read(phydev, AT803X_INTR_ENABLE);
312 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
315 value = BMCR_ISOLATE;
319 phy_modify(phydev, MII_BMCR, 0, value);
324 static int at803x_resume(struct phy_device *phydev)
326 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
329 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
330 unsigned int selector)
332 struct phy_device *phydev = rdev_get_drvdata(rdev);
335 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
336 0, AT803X_DEBUG_RGMII_1V8);
338 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
339 AT803X_DEBUG_RGMII_1V8, 0);
342 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
344 struct phy_device *phydev = rdev_get_drvdata(rdev);
347 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
351 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
354 static const struct regulator_ops vddio_regulator_ops = {
355 .list_voltage = regulator_list_voltage_table,
356 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
357 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
360 static const unsigned int vddio_voltage_table[] = {
365 static const struct regulator_desc vddio_desc = {
367 .of_match = of_match_ptr("vddio-regulator"),
368 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
369 .volt_table = vddio_voltage_table,
370 .ops = &vddio_regulator_ops,
371 .type = REGULATOR_VOLTAGE,
372 .owner = THIS_MODULE,
375 static const struct regulator_ops vddh_regulator_ops = {
378 static const struct regulator_desc vddh_desc = {
380 .of_match = of_match_ptr("vddh-regulator"),
383 .ops = &vddh_regulator_ops,
384 .type = REGULATOR_VOLTAGE,
385 .owner = THIS_MODULE,
388 static int at8031_register_regulators(struct phy_device *phydev)
390 struct at803x_priv *priv = phydev->priv;
391 struct device *dev = &phydev->mdio.dev;
392 struct regulator_config config = { };
395 config.driver_data = phydev;
397 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
398 if (IS_ERR(priv->vddio_rdev)) {
399 phydev_err(phydev, "failed to register VDDIO regulator\n");
400 return PTR_ERR(priv->vddio_rdev);
403 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
404 if (IS_ERR(priv->vddh_rdev)) {
405 phydev_err(phydev, "failed to register VDDH regulator\n");
406 return PTR_ERR(priv->vddh_rdev);
412 static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
414 return (phydev->phy_id & phydev->drv->phy_id_mask)
415 == (phy_id & phydev->drv->phy_id_mask);
418 static int at803x_parse_dt(struct phy_device *phydev)
420 struct device_node *node = phydev->mdio.dev.of_node;
421 struct at803x_priv *priv = phydev->priv;
422 u32 freq, strength, tw;
426 if (!IS_ENABLED(CONFIG_OF_MDIO))
429 if (of_property_read_bool(node, "qca,disable-smarteee"))
430 priv->flags |= AT803X_DISABLE_SMARTEEE;
432 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
433 if (!tw || tw > 255) {
434 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
437 priv->smarteee_lpi_tw_1g = tw;
440 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
441 if (!tw || tw > 255) {
442 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
445 priv->smarteee_lpi_tw_100m = tw;
448 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
452 sel = AT803X_CLK_OUT_25MHZ_XTAL;
455 sel = AT803X_CLK_OUT_50MHZ_PLL;
458 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
461 sel = AT803X_CLK_OUT_125MHZ_PLL;
464 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
468 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
469 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
471 /* Fixup for the AR8030/AR8035. This chip has another mask and
472 * doesn't support the DSP reference. Eg. the lowest bit of the
473 * mask. The upper two bits select the same frequencies. Mask
474 * the lowest bit here.
477 * There was no datasheet for the AR8030 available so this is
478 * just a guess. But the AR8035 is listed as pin compatible
479 * to the AR8030 so there might be a good chance it works on
482 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) ||
483 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) {
484 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
485 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
489 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
491 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
493 case AR803X_STRENGTH_FULL:
494 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
496 case AR803X_STRENGTH_HALF:
497 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
499 case AR803X_STRENGTH_QUARTER:
500 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
503 phydev_err(phydev, "invalid qca,clk-out-strength\n");
508 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
511 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
512 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
513 priv->flags |= AT803X_KEEP_PLL_ENABLED;
515 ret = at8031_register_regulators(phydev);
519 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
521 if (IS_ERR(priv->vddio)) {
522 phydev_err(phydev, "failed to get VDDIO regulator\n");
523 return PTR_ERR(priv->vddio);
526 ret = regulator_enable(priv->vddio);
534 static int at803x_probe(struct phy_device *phydev)
536 struct device *dev = &phydev->mdio.dev;
537 struct at803x_priv *priv;
539 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
545 return at803x_parse_dt(phydev);
548 static void at803x_remove(struct phy_device *phydev)
550 struct at803x_priv *priv = phydev->priv;
553 regulator_disable(priv->vddio);
556 static int at803x_smarteee_config(struct phy_device *phydev)
558 struct at803x_priv *priv = phydev->priv;
559 u16 mask = 0, val = 0;
562 if (priv->flags & AT803X_DISABLE_SMARTEEE)
563 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
564 AT803X_MMD3_SMARTEEE_CTL3,
565 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
567 if (priv->smarteee_lpi_tw_1g) {
569 val |= priv->smarteee_lpi_tw_1g << 8;
571 if (priv->smarteee_lpi_tw_100m) {
573 val |= priv->smarteee_lpi_tw_100m;
578 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
583 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
584 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
585 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
588 static int at803x_clk_out_config(struct phy_device *phydev)
590 struct at803x_priv *priv = phydev->priv;
592 if (!priv->clk_25m_mask)
595 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
596 priv->clk_25m_mask, priv->clk_25m_reg);
599 static int at8031_pll_config(struct phy_device *phydev)
601 struct at803x_priv *priv = phydev->priv;
603 /* The default after hardware reset is PLL OFF. After a soft reset, the
604 * values are retained.
606 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
607 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
608 0, AT803X_DEBUG_PLL_ON);
610 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
611 AT803X_DEBUG_PLL_ON, 0);
614 static int at803x_config_init(struct phy_device *phydev)
618 /* The RX and TX delay default is:
619 * after HW reset: RX delay enabled and TX delay disabled
620 * after SW reset: RX delay enabled, while TX delay retains the
621 * value before reset.
623 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
624 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
625 ret = at803x_enable_rx_delay(phydev);
627 ret = at803x_disable_rx_delay(phydev);
631 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
632 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
633 ret = at803x_enable_tx_delay(phydev);
635 ret = at803x_disable_tx_delay(phydev);
639 ret = at803x_smarteee_config(phydev);
643 ret = at803x_clk_out_config(phydev);
647 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
648 ret = at8031_pll_config(phydev);
653 /* Ar803x extended next page bit is enabled by default. Cisco
654 * multigig switches read this bit and attempt to negotiate 10Gbps
655 * rates even if the next page bit is disabled. This is incorrect
656 * behaviour but we still need to accommodate it. XNP is only needed
657 * for 10Gbps support, so disable XNP.
659 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
662 static int at803x_ack_interrupt(struct phy_device *phydev)
666 err = phy_read(phydev, AT803X_INTR_STATUS);
668 return (err < 0) ? err : 0;
671 static int at803x_config_intr(struct phy_device *phydev)
676 value = phy_read(phydev, AT803X_INTR_ENABLE);
678 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
679 /* Clear any pending interrupts */
680 err = at803x_ack_interrupt(phydev);
684 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
685 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
686 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
687 value |= AT803X_INTR_ENABLE_LINK_FAIL;
688 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
690 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
692 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
696 /* Clear any pending interrupts */
697 err = at803x_ack_interrupt(phydev);
703 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
705 int irq_status, int_enabled;
707 irq_status = phy_read(phydev, AT803X_INTR_STATUS);
708 if (irq_status < 0) {
713 /* Read the current enabled interrupts */
714 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
715 if (int_enabled < 0) {
720 /* See if this was one of our enabled interrupts */
721 if (!(irq_status & int_enabled))
724 phy_trigger_machine(phydev);
729 static void at803x_link_change_notify(struct phy_device *phydev)
732 * Conduct a hardware reset for AT8030 every time a link loss is
733 * signalled. This is necessary to circumvent a hardware bug that
734 * occurs when the cable is unplugged while TX packets are pending
735 * in the FIFO. In such cases, the FIFO enters an error mode it
736 * cannot recover from by software.
738 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
739 struct at803x_context context;
741 at803x_context_save(phydev, &context);
743 phy_device_reset(phydev, 1);
745 phy_device_reset(phydev, 0);
748 at803x_context_restore(phydev, &context);
750 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
754 static int at803x_aneg_done(struct phy_device *phydev)
758 int aneg_done = genphy_aneg_done(phydev);
759 if (aneg_done != BMSR_ANEGCOMPLETE)
763 * in SGMII mode, if copper side autoneg is successful,
764 * also check SGMII side autoneg result
766 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
767 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
770 /* switch to SGMII/fiber page */
771 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
773 /* check if the SGMII link is OK. */
774 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
775 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
778 /* switch back to copper page */
779 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
784 static int at803x_read_status(struct phy_device *phydev)
786 int ss, err, old_link = phydev->link;
788 /* Update the link, but return if there was an error */
789 err = genphy_update_link(phydev);
793 /* why bother the PHY if nothing can have changed */
794 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
797 phydev->speed = SPEED_UNKNOWN;
798 phydev->duplex = DUPLEX_UNKNOWN;
800 phydev->asym_pause = 0;
802 err = genphy_read_lpa(phydev);
806 /* Read the AT8035 PHY-Specific Status register, which indicates the
807 * speed and duplex that the PHY is actually using, irrespective of
808 * whether we are in autoneg mode or not.
810 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
814 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
817 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
821 switch (ss & AT803X_SS_SPEED_MASK) {
822 case AT803X_SS_SPEED_10:
823 phydev->speed = SPEED_10;
825 case AT803X_SS_SPEED_100:
826 phydev->speed = SPEED_100;
828 case AT803X_SS_SPEED_1000:
829 phydev->speed = SPEED_1000;
832 if (ss & AT803X_SS_DUPLEX)
833 phydev->duplex = DUPLEX_FULL;
835 phydev->duplex = DUPLEX_HALF;
837 if (ss & AT803X_SS_MDIX)
838 phydev->mdix = ETH_TP_MDI_X;
840 phydev->mdix = ETH_TP_MDI;
842 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
843 case AT803X_SFC_MANUAL_MDI:
844 phydev->mdix_ctrl = ETH_TP_MDI;
846 case AT803X_SFC_MANUAL_MDIX:
847 phydev->mdix_ctrl = ETH_TP_MDI_X;
849 case AT803X_SFC_AUTOMATIC_CROSSOVER:
850 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
855 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
856 phy_resolve_aneg_pause(phydev);
861 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
867 val = AT803X_SFC_MANUAL_MDI;
870 val = AT803X_SFC_MANUAL_MDIX;
872 case ETH_TP_MDI_AUTO:
873 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
879 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
880 AT803X_SFC_MDI_CROSSOVER_MODE_M,
881 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
884 static int at803x_config_aneg(struct phy_device *phydev)
888 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
892 /* Changes of the midx bits are disruptive to the normal operation;
893 * therefore any changes to these registers must be followed by a
894 * software reset to take effect.
897 ret = genphy_soft_reset(phydev);
902 return genphy_config_aneg(phydev);
905 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
909 val = phy_read(phydev, AT803X_SMART_SPEED);
913 if (val & AT803X_SMART_SPEED_ENABLE)
914 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
916 *d = DOWNSHIFT_DEV_DISABLE;
921 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
927 case DOWNSHIFT_DEV_DEFAULT_COUNT:
928 cnt = AT803X_DEFAULT_DOWNSHIFT;
930 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
931 set = AT803X_SMART_SPEED_ENABLE |
932 AT803X_SMART_SPEED_BYPASS_TIMER |
933 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
934 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
936 case DOWNSHIFT_DEV_DISABLE:
938 mask = AT803X_SMART_SPEED_ENABLE |
939 AT803X_SMART_SPEED_BYPASS_TIMER;
945 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
947 /* After changing the smart speed settings, we need to perform a
948 * software reset, use phy_init_hw() to make sure we set the
949 * reapply any values which might got lost during software reset.
952 ret = phy_init_hw(phydev);
957 static int at803x_get_tunable(struct phy_device *phydev,
958 struct ethtool_tunable *tuna, void *data)
961 case ETHTOOL_PHY_DOWNSHIFT:
962 return at803x_get_downshift(phydev, data);
968 static int at803x_set_tunable(struct phy_device *phydev,
969 struct ethtool_tunable *tuna, const void *data)
972 case ETHTOOL_PHY_DOWNSHIFT:
973 return at803x_set_downshift(phydev, *(const u8 *)data);
979 static int at803x_cable_test_result_trans(u16 status)
981 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
982 case AT803X_CDT_STATUS_STAT_NORMAL:
983 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
984 case AT803X_CDT_STATUS_STAT_SHORT:
985 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
986 case AT803X_CDT_STATUS_STAT_OPEN:
987 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
988 case AT803X_CDT_STATUS_STAT_FAIL:
990 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
994 static bool at803x_cdt_test_failed(u16 status)
996 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
997 AT803X_CDT_STATUS_STAT_FAIL;
1000 static bool at803x_cdt_fault_length_valid(u16 status)
1002 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1003 case AT803X_CDT_STATUS_STAT_OPEN:
1004 case AT803X_CDT_STATUS_STAT_SHORT:
1010 static int at803x_cdt_fault_length(u16 status)
1014 /* According to the datasheet the distance to the fault is
1015 * DELTA_TIME * 0.824 meters.
1017 * The author suspect the correct formula is:
1019 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1021 * where c is the speed of light, VF is the velocity factor of
1022 * the twisted pair cable, 125MHz the counter frequency and
1023 * we need to divide by 2 because the hardware will measure the
1024 * round trip time to the fault and back to the PHY.
1026 * With a VF of 0.69 we get the factor 0.824 mentioned in the
1029 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1031 return (dt * 824) / 10;
1034 static int at803x_cdt_start(struct phy_device *phydev, int pair)
1038 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1039 AT803X_CDT_ENABLE_TEST;
1041 return phy_write(phydev, AT803X_CDT, cdt);
1044 static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1048 /* One test run takes about 25ms */
1049 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1050 !(val & AT803X_CDT_ENABLE_TEST),
1051 30000, 100000, true);
1053 return ret < 0 ? ret : 0;
1056 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1058 static const int ethtool_pair[] = {
1059 ETHTOOL_A_CABLE_PAIR_A,
1060 ETHTOOL_A_CABLE_PAIR_B,
1061 ETHTOOL_A_CABLE_PAIR_C,
1062 ETHTOOL_A_CABLE_PAIR_D,
1066 ret = at803x_cdt_start(phydev, pair);
1070 ret = at803x_cdt_wait_for_completion(phydev);
1074 val = phy_read(phydev, AT803X_CDT_STATUS);
1078 if (at803x_cdt_test_failed(val))
1081 ethnl_cable_test_result(phydev, ethtool_pair[pair],
1082 at803x_cable_test_result_trans(val));
1084 if (at803x_cdt_fault_length_valid(val))
1085 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1086 at803x_cdt_fault_length(val));
1091 static int at803x_cable_test_get_status(struct phy_device *phydev,
1094 unsigned long pair_mask;
1098 if (phydev->phy_id == ATH9331_PHY_ID ||
1099 phydev->phy_id == ATH8032_PHY_ID)
1106 /* According to the datasheet the CDT can be performed when
1107 * there is no link partner or when the link partner is
1108 * auto-negotiating. Starting the test will restart the AN
1109 * automatically. It seems that doing this repeatedly we will
1110 * get a slot where our link partner won't disturb our
1113 while (pair_mask && retries--) {
1114 for_each_set_bit(pair, &pair_mask, 4) {
1115 ret = at803x_cable_test_one_pair(phydev, pair);
1119 clear_bit(pair, &pair_mask);
1130 static int at803x_cable_test_start(struct phy_device *phydev)
1132 /* Enable auto-negotiation, but advertise no capabilities, no link
1133 * will be established. A restart of the auto-negotiation is not
1134 * required, because the cable test will automatically break the link.
1136 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1137 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1138 if (phydev->phy_id != ATH9331_PHY_ID &&
1139 phydev->phy_id != ATH8032_PHY_ID)
1140 phy_write(phydev, MII_CTRL1000, 0);
1142 /* we do all the (time consuming) work later */
1146 static struct phy_driver at803x_driver[] = {
1148 /* Qualcomm Atheros AR8035 */
1149 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1150 .name = "Qualcomm Atheros AR8035",
1151 .flags = PHY_POLL_CABLE_TEST,
1152 .probe = at803x_probe,
1153 .remove = at803x_remove,
1154 .config_aneg = at803x_config_aneg,
1155 .config_init = at803x_config_init,
1156 .soft_reset = genphy_soft_reset,
1157 .set_wol = at803x_set_wol,
1158 .get_wol = at803x_get_wol,
1159 .suspend = at803x_suspend,
1160 .resume = at803x_resume,
1161 /* PHY_GBIT_FEATURES */
1162 .read_status = at803x_read_status,
1163 .config_intr = at803x_config_intr,
1164 .handle_interrupt = at803x_handle_interrupt,
1165 .get_tunable = at803x_get_tunable,
1166 .set_tunable = at803x_set_tunable,
1167 .cable_test_start = at803x_cable_test_start,
1168 .cable_test_get_status = at803x_cable_test_get_status,
1170 /* Qualcomm Atheros AR8030 */
1171 .phy_id = ATH8030_PHY_ID,
1172 .name = "Qualcomm Atheros AR8030",
1173 .phy_id_mask = AT8030_PHY_ID_MASK,
1174 .probe = at803x_probe,
1175 .remove = at803x_remove,
1176 .config_init = at803x_config_init,
1177 .link_change_notify = at803x_link_change_notify,
1178 .set_wol = at803x_set_wol,
1179 .get_wol = at803x_get_wol,
1180 .suspend = at803x_suspend,
1181 .resume = at803x_resume,
1182 /* PHY_BASIC_FEATURES */
1183 .config_intr = at803x_config_intr,
1184 .handle_interrupt = at803x_handle_interrupt,
1186 /* Qualcomm Atheros AR8031/AR8033 */
1187 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1188 .name = "Qualcomm Atheros AR8031/AR8033",
1189 .flags = PHY_POLL_CABLE_TEST,
1190 .probe = at803x_probe,
1191 .remove = at803x_remove,
1192 .config_init = at803x_config_init,
1193 .config_aneg = at803x_config_aneg,
1194 .soft_reset = genphy_soft_reset,
1195 .set_wol = at803x_set_wol,
1196 .get_wol = at803x_get_wol,
1197 .suspend = at803x_suspend,
1198 .resume = at803x_resume,
1199 /* PHY_GBIT_FEATURES */
1200 .read_status = at803x_read_status,
1201 .aneg_done = at803x_aneg_done,
1202 .config_intr = &at803x_config_intr,
1203 .handle_interrupt = at803x_handle_interrupt,
1204 .get_tunable = at803x_get_tunable,
1205 .set_tunable = at803x_set_tunable,
1206 .cable_test_start = at803x_cable_test_start,
1207 .cable_test_get_status = at803x_cable_test_get_status,
1209 /* Qualcomm Atheros AR8032 */
1210 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1211 .name = "Qualcomm Atheros AR8032",
1212 .probe = at803x_probe,
1213 .remove = at803x_remove,
1214 .flags = PHY_POLL_CABLE_TEST,
1215 .config_init = at803x_config_init,
1216 .link_change_notify = at803x_link_change_notify,
1217 .set_wol = at803x_set_wol,
1218 .get_wol = at803x_get_wol,
1219 .suspend = at803x_suspend,
1220 .resume = at803x_resume,
1221 /* PHY_BASIC_FEATURES */
1222 .config_intr = at803x_config_intr,
1223 .handle_interrupt = at803x_handle_interrupt,
1224 .cable_test_start = at803x_cable_test_start,
1225 .cable_test_get_status = at803x_cable_test_get_status,
1227 /* ATHEROS AR9331 */
1228 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1229 .name = "Qualcomm Atheros AR9331 built-in PHY",
1230 .suspend = at803x_suspend,
1231 .resume = at803x_resume,
1232 .flags = PHY_POLL_CABLE_TEST,
1233 /* PHY_BASIC_FEATURES */
1234 .config_intr = &at803x_config_intr,
1235 .handle_interrupt = at803x_handle_interrupt,
1236 .cable_test_start = at803x_cable_test_start,
1237 .cable_test_get_status = at803x_cable_test_get_status,
1238 .read_status = at803x_read_status,
1239 .soft_reset = genphy_soft_reset,
1240 .config_aneg = at803x_config_aneg,
1243 module_phy_driver(at803x_driver);
1245 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
1246 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1247 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1248 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1249 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1250 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1254 MODULE_DEVICE_TABLE(mdio, atheros_tbl);