drivers/net/phy/at803x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/at803x.c
   4  *
   5  * Driver for Qualcomm Atheros AR803x PHY
   6  *
   7  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
   8  */
   9
  10 #include <linux/phy.h>
  11 #include <linux/module.h>
  12 #include <linux/string.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/ethtool_netlink.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/bitfield.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/regulator/of_regulator.h>
  20 #include <linux/regulator/driver.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/phylink.h>
  23 #include <linux/sfp.h>
  24 #include <dt-bindings/net/qca-ar803x.h>
  25
  26 #define AT803X_SPECIFIC_FUNCTION_CONTROL        0x10
  27 #define AT803X_SFC_ASSERT_CRS                   BIT(11)
  28 #define AT803X_SFC_FORCE_LINK                   BIT(10)
  29 #define AT803X_SFC_MDI_CROSSOVER_MODE_M         GENMASK(6, 5)
  30 #define AT803X_SFC_AUTOMATIC_CROSSOVER          0x3
  31 #define AT803X_SFC_MANUAL_MDIX                  0x1
  32 #define AT803X_SFC_MANUAL_MDI                   0x0
  33 #define AT803X_SFC_SQE_TEST                     BIT(2)
  34 #define AT803X_SFC_POLARITY_REVERSAL            BIT(1)
  35 #define AT803X_SFC_DISABLE_JABBER               BIT(0)
  36
  37 #define AT803X_SPECIFIC_STATUS                  0x11
  38 #define AT803X_SS_SPEED_MASK                    GENMASK(15, 14)
  39 #define AT803X_SS_SPEED_1000                    2
  40 #define AT803X_SS_SPEED_100                     1
  41 #define AT803X_SS_SPEED_10                      0
  42 #define AT803X_SS_DUPLEX                        BIT(13)
  43 #define AT803X_SS_SPEED_DUPLEX_RESOLVED         BIT(11)
  44 #define AT803X_SS_MDIX                          BIT(6)
  45
  46 #define QCA808X_SS_SPEED_MASK                   GENMASK(9, 7)
  47 #define QCA808X_SS_SPEED_2500                   4
  48
  49 #define AT803X_INTR_ENABLE                      0x12
  50 #define AT803X_INTR_ENABLE_AUTONEG_ERR          BIT(15)
  51 #define AT803X_INTR_ENABLE_SPEED_CHANGED        BIT(14)
  52 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED       BIT(13)
  53 #define AT803X_INTR_ENABLE_PAGE_RECEIVED        BIT(12)
  54 #define AT803X_INTR_ENABLE_LINK_FAIL            BIT(11)
  55 #define AT803X_INTR_ENABLE_LINK_SUCCESS         BIT(10)
  56 #define AT803X_INTR_ENABLE_LINK_FAIL_BX         BIT(8)
  57 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX      BIT(7)
  58 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE  BIT(5)
  59 #define AT803X_INTR_ENABLE_POLARITY_CHANGED     BIT(1)
  60 #define AT803X_INTR_ENABLE_WOL                  BIT(0)
  61
  62 #define AT803X_INTR_STATUS                      0x13
  63
  64 #define AT803X_SMART_SPEED                      0x14
  65 #define AT803X_SMART_SPEED_ENABLE               BIT(5)
  66 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK     GENMASK(4, 2)
  67 #define AT803X_SMART_SPEED_BYPASS_TIMER         BIT(1)
  68 #define AT803X_CDT                              0x16
  69 #define AT803X_CDT_MDI_PAIR_MASK                GENMASK(9, 8)
  70 #define AT803X_CDT_ENABLE_TEST                  BIT(0)
  71 #define AT803X_CDT_STATUS                       0x1c
  72 #define AT803X_CDT_STATUS_STAT_NORMAL           0
  73 #define AT803X_CDT_STATUS_STAT_SHORT            1
  74 #define AT803X_CDT_STATUS_STAT_OPEN             2
  75 #define AT803X_CDT_STATUS_STAT_FAIL             3
  76 #define AT803X_CDT_STATUS_STAT_MASK             GENMASK(9, 8)
  77 #define AT803X_CDT_STATUS_DELTA_TIME_MASK       GENMASK(7, 0)
  78 #define AT803X_LED_CONTROL                      0x18
  79
  80 #define AT803X_PHY_MMD3_WOL_CTRL                0x8012
  81 #define AT803X_WOL_EN                           BIT(5)
  82 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET         0x804C
  83 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET        0x804B
  84 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET        0x804A
  85 #define AT803X_REG_CHIP_CONFIG                  0x1f
  86 #define AT803X_BT_BX_REG_SEL                    0x8000
  87
  88 #define AT803X_DEBUG_ADDR                       0x1D
  89 #define AT803X_DEBUG_DATA                       0x1E
  90
  91 #define AT803X_MODE_CFG_MASK                    0x0F
  92 #define AT803X_MODE_CFG_BASET_RGMII             0x00
  93 #define AT803X_MODE_CFG_BASET_SGMII             0x01
  94 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM      0x02
  95 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM      0x03
  96 #define AT803X_MODE_CFG_BX1000_CONV_50OHM       0x04
  97 #define AT803X_MODE_CFG_BX1000_CONV_75OHM       0x05
  98 #define AT803X_MODE_CFG_FX100_RGMII_50OHM       0x06
  99 #define AT803X_MODE_CFG_FX100_CONV_50OHM        0x07
 100 #define AT803X_MODE_CFG_RGMII_AUTO_MDET         0x0B
 101 #define AT803X_MODE_CFG_FX100_RGMII_75OHM       0x0E
 102 #define AT803X_MODE_CFG_FX100_CONV_75OHM        0x0F
 103
 104 #define AT803X_PSSR                             0x11    /*PHY-Specific Status Register*/
 105 #define AT803X_PSSR_MR_AN_COMPLETE              0x0200
 106
 107 #define AT803X_DEBUG_ANALOG_TEST_CTRL           0x00
 108 #define QCA8327_DEBUG_MANU_CTRL_EN              BIT(2)
 109 #define QCA8337_DEBUG_MANU_CTRL_EN              GENMASK(3, 2)
 110 #define AT803X_DEBUG_RX_CLK_DLY_EN              BIT(15)
 111
 112 #define AT803X_DEBUG_SYSTEM_CTRL_MODE           0x05
 113 #define AT803X_DEBUG_TX_CLK_DLY_EN              BIT(8)
 114
 115 #define AT803X_DEBUG_REG_HIB_CTRL               0x0b
 116 #define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U     BIT(10)
 117 #define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE   BIT(13)
 118
 119 #define AT803X_DEBUG_REG_3C                     0x3C
 120
 121 #define AT803X_DEBUG_REG_GREEN                  0x3D
 122 #define   AT803X_DEBUG_GATE_CLK_IN1000          BIT(6)
 123
 124 #define AT803X_DEBUG_REG_1F                     0x1F
 125 #define AT803X_DEBUG_PLL_ON                     BIT(2)
 126 #define AT803X_DEBUG_RGMII_1V8                  BIT(3)
 127
 128 #define MDIO_AZ_DEBUG                           0x800D
 129
 130 /* AT803x supports either the XTAL input pad, an internal PLL or the
 131  * DSP as clock reference for the clock output pad. The XTAL reference
 132  * is only used for 25 MHz output, all other frequencies need the PLL.
 133  * The DSP as a clock reference is used in synchronous ethernet
 134  * applications.
 135  *
 136  * By default the PLL is only enabled if there is a link. Otherwise
 137  * the PHY will go into low power state and disabled the PLL. You can
 138  * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
 139  * enabled.
 140  */
 141 #define AT803X_MMD7_CLK25M                      0x8016
 142 #define AT803X_CLK_OUT_MASK                     GENMASK(4, 2)
 143 #define AT803X_CLK_OUT_25MHZ_XTAL               0
 144 #define AT803X_CLK_OUT_25MHZ_DSP                1
 145 #define AT803X_CLK_OUT_50MHZ_PLL                2
 146 #define AT803X_CLK_OUT_50MHZ_DSP                3
 147 #define AT803X_CLK_OUT_62_5MHZ_PLL              4
 148 #define AT803X_CLK_OUT_62_5MHZ_DSP              5
 149 #define AT803X_CLK_OUT_125MHZ_PLL               6
 150 #define AT803X_CLK_OUT_125MHZ_DSP               7
 151
 152 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
 153  * but doesn't support choosing between XTAL/PLL and DSP.
 154  */
 155 #define AT8035_CLK_OUT_MASK                     GENMASK(4, 3)
 156
 157 #define AT803X_CLK_OUT_STRENGTH_MASK            GENMASK(8, 7)
 158 #define AT803X_CLK_OUT_STRENGTH_FULL            0
 159 #define AT803X_CLK_OUT_STRENGTH_HALF            1
 160 #define AT803X_CLK_OUT_STRENGTH_QUARTER         2
 161
 162 #define AT803X_DEFAULT_DOWNSHIFT                5
 163 #define AT803X_MIN_DOWNSHIFT                    2
 164 #define AT803X_MAX_DOWNSHIFT                    9
 165
 166 #define AT803X_MMD3_SMARTEEE_CTL1               0x805b
 167 #define AT803X_MMD3_SMARTEEE_CTL2               0x805c
 168 #define AT803X_MMD3_SMARTEEE_CTL3               0x805d
 169 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN        BIT(8)
 170
 171 #define ATH9331_PHY_ID                          0x004dd041
 172 #define ATH8030_PHY_ID                          0x004dd076
 173 #define ATH8031_PHY_ID                          0x004dd074
 174 #define ATH8032_PHY_ID                          0x004dd023
 175 #define ATH8035_PHY_ID                          0x004dd072
 176 #define AT8030_PHY_ID_MASK                      0xffffffef
 177
 178 #define QCA8081_PHY_ID                          0x004dd101
 179
 180 #define QCA8327_A_PHY_ID                        0x004dd033
 181 #define QCA8327_B_PHY_ID                        0x004dd034
 182 #define QCA8337_PHY_ID                          0x004dd036
 183 #define QCA9561_PHY_ID                          0x004dd042
 184 #define QCA8K_PHY_ID_MASK                       0xffffffff
 185
 186 #define QCA8K_DEVFLAGS_REVISION_MASK            GENMASK(2, 0)
 187
 188 #define AT803X_PAGE_FIBER                       0
 189 #define AT803X_PAGE_COPPER                      1
 190
 191 /* don't turn off internal PLL */
 192 #define AT803X_KEEP_PLL_ENABLED                 BIT(0)
 193 #define AT803X_DISABLE_SMARTEEE                 BIT(1)
 194
 195 /* ADC threshold */
 196 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD         0x2c80
 197 #define QCA808X_ADC_THRESHOLD_MASK              GENMASK(7, 0)
 198 #define QCA808X_ADC_THRESHOLD_80MV              0
 199 #define QCA808X_ADC_THRESHOLD_100MV             0xf0
 200 #define QCA808X_ADC_THRESHOLD_200MV             0x0f
 201 #define QCA808X_ADC_THRESHOLD_300MV             0xff
 202
 203 /* CLD control */
 204 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7         0x8007
 205 #define QCA808X_8023AZ_AFE_CTRL_MASK            GENMASK(8, 4)
 206 #define QCA808X_8023AZ_AFE_EN                   0x90
 207
 208 /* AZ control */
 209 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL       0x8008
 210 #define QCA808X_MMD3_AZ_TRAINING_VAL            0x1c32
 211
 212 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB     0x8014
 213 #define QCA808X_MSE_THRESHOLD_20DB_VALUE        0x529
 214
 215 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB     0x800E
 216 #define QCA808X_MSE_THRESHOLD_17DB_VALUE        0x341
 217
 218 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB     0x801E
 219 #define QCA808X_MSE_THRESHOLD_27DB_VALUE        0x419
 220
 221 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB     0x8020
 222 #define QCA808X_MSE_THRESHOLD_28DB_VALUE        0x341
 223
 224 #define QCA808X_PHY_MMD7_TOP_OPTION1            0x901c
 225 #define QCA808X_TOP_OPTION1_DATA                0x0
 226
 227 #define QCA808X_PHY_MMD3_DEBUG_1                0xa100
 228 #define QCA808X_MMD3_DEBUG_1_VALUE              0x9203
 229 #define QCA808X_PHY_MMD3_DEBUG_2                0xa101
 230 #define QCA808X_MMD3_DEBUG_2_VALUE              0x48ad
 231 #define QCA808X_PHY_MMD3_DEBUG_3                0xa103
 232 #define QCA808X_MMD3_DEBUG_3_VALUE              0x1698
 233 #define QCA808X_PHY_MMD3_DEBUG_4                0xa105
 234 #define QCA808X_MMD3_DEBUG_4_VALUE              0x8001
 235 #define QCA808X_PHY_MMD3_DEBUG_5                0xa106
 236 #define QCA808X_MMD3_DEBUG_5_VALUE              0x1111
 237 #define QCA808X_PHY_MMD3_DEBUG_6                0xa011
 238 #define QCA808X_MMD3_DEBUG_6_VALUE              0x5f85
 239
 240 /* master/slave seed config */
 241 #define QCA808X_PHY_DEBUG_LOCAL_SEED            9
 242 #define QCA808X_MASTER_SLAVE_SEED_ENABLE        BIT(1)
 243 #define QCA808X_MASTER_SLAVE_SEED_CFG           GENMASK(12, 2)
 244 #define QCA808X_MASTER_SLAVE_SEED_RANGE         0x32
 245
 246 /* Hibernation yields lower power consumpiton in contrast with normal operation mode.
 247  * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
 248  */
 249 #define QCA808X_DBG_AN_TEST                     0xb
 250 #define QCA808X_HIBERNATION_EN                  BIT(15)
 251
 252 #define QCA808X_CDT_ENABLE_TEST                 BIT(15)
 253 #define QCA808X_CDT_INTER_CHECK_DIS             BIT(13)
 254 #define QCA808X_CDT_LENGTH_UNIT                 BIT(10)
 255
 256 #define QCA808X_MMD3_CDT_STATUS                 0x8064
 257 #define QCA808X_MMD3_CDT_DIAG_PAIR_A            0x8065
 258 #define QCA808X_MMD3_CDT_DIAG_PAIR_B            0x8066
 259 #define QCA808X_MMD3_CDT_DIAG_PAIR_C            0x8067
 260 #define QCA808X_MMD3_CDT_DIAG_PAIR_D            0x8068
 261 #define QCA808X_CDT_DIAG_LENGTH                 GENMASK(7, 0)
 262
 263 #define QCA808X_CDT_CODE_PAIR_A                 GENMASK(15, 12)
 264 #define QCA808X_CDT_CODE_PAIR_B                 GENMASK(11, 8)
 265 #define QCA808X_CDT_CODE_PAIR_C                 GENMASK(7, 4)
 266 #define QCA808X_CDT_CODE_PAIR_D                 GENMASK(3, 0)
 267 #define QCA808X_CDT_STATUS_STAT_FAIL            0
 268 #define QCA808X_CDT_STATUS_STAT_NORMAL          1
 269 #define QCA808X_CDT_STATUS_STAT_OPEN            2
 270 #define QCA808X_CDT_STATUS_STAT_SHORT           3
 271
 272 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
 273 MODULE_AUTHOR("Matus Ujhelyi");
 274 MODULE_LICENSE("GPL");
 275
 276 enum stat_access_type {
 277         PHY,
 278         MMD
 279 };
 280
 281 struct at803x_hw_stat {
 282         const char *string;
 283         u8 reg;
 284         u32 mask;
 285         enum stat_access_type access_type;
 286 };
 287
 288 static struct at803x_hw_stat at803x_hw_stats[] = {
 289         { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
 290         { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
 291         { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
 292 };
 293
 294 struct at803x_priv {
 295         int flags;
 296         u16 clk_25m_reg;
 297         u16 clk_25m_mask;
 298         u8 smarteee_lpi_tw_1g;
 299         u8 smarteee_lpi_tw_100m;
 300         bool is_fiber;
 301         bool is_1000basex;
 302         struct regulator_dev *vddio_rdev;
 303         struct regulator_dev *vddh_rdev;
 304         struct regulator *vddio;
 305         u64 stats[ARRAY_SIZE(at803x_hw_stats)];
 306 };
 307
 308 struct at803x_context {
 309         u16 bmcr;
 310         u16 advertise;
 311         u16 control1000;
 312         u16 int_enable;
 313         u16 smart_speed;
 314         u16 led_control;
 315 };
 316
 317 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
 318 {
 319         int ret;
 320
 321         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 322         if (ret < 0)
 323                 return ret;
 324
 325         return phy_write(phydev, AT803X_DEBUG_DATA, data);
 326 }
 327
 328 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 329 {
 330         int ret;
 331
 332         ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
 333         if (ret < 0)
 334                 return ret;
 335
 336         return phy_read(phydev, AT803X_DEBUG_DATA);
 337 }
 338
 339 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
 340                                  u16 clear, u16 set)
 341 {
 342         u16 val;
 343         int ret;
 344
 345         ret = at803x_debug_reg_read(phydev, reg);
 346         if (ret < 0)
 347                 return ret;
 348
 349         val = ret & 0xffff;
 350         val &= ~clear;
 351         val |= set;
 352
 353         return phy_write(phydev, AT803X_DEBUG_DATA, val);
 354 }
 355
 356 static int at803x_write_page(struct phy_device *phydev, int page)
 357 {
 358         int mask;
 359         int set;
 360
 361         if (page == AT803X_PAGE_COPPER) {
 362                 set = AT803X_BT_BX_REG_SEL;
 363                 mask = 0;
 364         } else {
 365                 set = 0;
 366                 mask = AT803X_BT_BX_REG_SEL;
 367         }
 368
 369         return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
 370 }
 371
 372 static int at803x_read_page(struct phy_device *phydev)
 373 {
 374         int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 375
 376         if (ccr < 0)
 377                 return ccr;
 378
 379         if (ccr & AT803X_BT_BX_REG_SEL)
 380                 return AT803X_PAGE_COPPER;
 381
 382         return AT803X_PAGE_FIBER;
 383 }
 384
 385 static int at803x_enable_rx_delay(struct phy_device *phydev)
 386 {
 387         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
 388                                      AT803X_DEBUG_RX_CLK_DLY_EN);
 389 }
 390
 391 static int at803x_enable_tx_delay(struct phy_device *phydev)
 392 {
 393         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
 394                                      AT803X_DEBUG_TX_CLK_DLY_EN);
 395 }
 396
 397 static int at803x_disable_rx_delay(struct phy_device *phydev)
 398 {
 399         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 400                                      AT803X_DEBUG_RX_CLK_DLY_EN, 0);
 401 }
 402
 403 static int at803x_disable_tx_delay(struct phy_device *phydev)
 404 {
 405         return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
 406                                      AT803X_DEBUG_TX_CLK_DLY_EN, 0);
 407 }
 408
 409 /* save relevant PHY registers to private copy */
 410 static void at803x_context_save(struct phy_device *phydev,
 411                                 struct at803x_context *context)
 412 {
 413         context->bmcr = phy_read(phydev, MII_BMCR);
 414         context->advertise = phy_read(phydev, MII_ADVERTISE);
 415         context->control1000 = phy_read(phydev, MII_CTRL1000);
 416         context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
 417         context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
 418         context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
 419 }
 420
 421 /* restore relevant PHY registers from private copy */
 422 static void at803x_context_restore(struct phy_device *phydev,
 423                                    const struct at803x_context *context)
 424 {
 425         phy_write(phydev, MII_BMCR, context->bmcr);
 426         phy_write(phydev, MII_ADVERTISE, context->advertise);
 427         phy_write(phydev, MII_CTRL1000, context->control1000);
 428         phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
 429         phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
 430         phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
 431 }
 432
 433 static int at803x_set_wol(struct phy_device *phydev,
 434                           struct ethtool_wolinfo *wol)
 435 {
 436         int ret, irq_enabled;
 437
 438         if (wol->wolopts & WAKE_MAGIC) {
 439                 struct net_device *ndev = phydev->attached_dev;
 440                 const u8 *mac;
 441                 unsigned int i;
 442                 static const unsigned int offsets[] = {
 443                         AT803X_LOC_MAC_ADDR_32_47_OFFSET,
 444                         AT803X_LOC_MAC_ADDR_16_31_OFFSET,
 445                         AT803X_LOC_MAC_ADDR_0_15_OFFSET,
 446                 };
 447
 448                 if (!ndev)
 449                         return -ENODEV;
 450
 451                 mac = (const u8 *) ndev->dev_addr;
 452
 453                 if (!is_valid_ether_addr(mac))
 454                         return -EINVAL;
 455
 456                 for (i = 0; i < 3; i++)
 457                         phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
 458                                       mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
 459
 460                 /* Enable WOL function */
 461                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
 462                                 0, AT803X_WOL_EN);
 463                 if (ret)
 464                         return ret;
 465                 /* Enable WOL interrupt */
 466                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
 467                 if (ret)
 468                         return ret;
 469         } else {
 470                 /* Disable WoL function */
 471                 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL,
 472                                 AT803X_WOL_EN, 0);
 473                 if (ret)
 474                         return ret;
 475                 /* Disable WOL interrupt */
 476                 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
 477                 if (ret)
 478                         return ret;
 479         }
 480
 481         /* Clear WOL status */
 482         ret = phy_read(phydev, AT803X_INTR_STATUS);
 483         if (ret < 0)
 484                 return ret;
 485
 486         /* Check if there are other interrupts except for WOL triggered when PHY is
 487          * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
 488          * be passed up to the interrupt PIN.
 489          */
 490         irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
 491         if (irq_enabled < 0)
 492                 return irq_enabled;
 493
 494         irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
 495         if (ret & irq_enabled && !phy_polling_mode(phydev))
 496                 phy_trigger_machine(phydev);
 497
 498         return 0;
 499 }
 500
 501 static void at803x_get_wol(struct phy_device *phydev,
 502                            struct ethtool_wolinfo *wol)
 503 {
 504         int value;
 505
 506         wol->supported = WAKE_MAGIC;
 507         wol->wolopts = 0;
 508
 509         value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL);
 510         if (value < 0)
 511                 return;
 512
 513         if (value & AT803X_WOL_EN)
 514                 wol->wolopts |= WAKE_MAGIC;
 515 }
 516
 517 static int at803x_get_sset_count(struct phy_device *phydev)
 518 {
 519         return ARRAY_SIZE(at803x_hw_stats);
 520 }
 521
 522 static void at803x_get_strings(struct phy_device *phydev, u8 *data)
 523 {
 524         int i;
 525
 526         for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
 527                 strscpy(data + i * ETH_GSTRING_LEN,
 528                         at803x_hw_stats[i].string, ETH_GSTRING_LEN);
 529         }
 530 }
 531
 532 static u64 at803x_get_stat(struct phy_device *phydev, int i)
 533 {
 534         struct at803x_hw_stat stat = at803x_hw_stats[i];
 535         struct at803x_priv *priv = phydev->priv;
 536         int val;
 537         u64 ret;
 538
 539         if (stat.access_type == MMD)
 540                 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
 541         else
 542                 val = phy_read(phydev, stat.reg);
 543
 544         if (val < 0) {
 545                 ret = U64_MAX;
 546         } else {
 547                 val = val & stat.mask;
 548                 priv->stats[i] += val;
 549                 ret = priv->stats[i];
 550         }
 551
 552         return ret;
 553 }
 554
 555 static void at803x_get_stats(struct phy_device *phydev,
 556                              struct ethtool_stats *stats, u64 *data)
 557 {
 558         int i;
 559
 560         for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
 561                 data[i] = at803x_get_stat(phydev, i);
 562 }
 563
 564 static int at803x_suspend(struct phy_device *phydev)
 565 {
 566         int value;
 567         int wol_enabled;
 568
 569         value = phy_read(phydev, AT803X_INTR_ENABLE);
 570         wol_enabled = value & AT803X_INTR_ENABLE_WOL;
 571
 572         if (wol_enabled)
 573                 value = BMCR_ISOLATE;
 574         else
 575                 value = BMCR_PDOWN;
 576
 577         phy_modify(phydev, MII_BMCR, 0, value);
 578
 579         return 0;
 580 }
 581
 582 static int at803x_resume(struct phy_device *phydev)
 583 {
 584         return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
 585 }
 586
 587 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
 588                                             unsigned int selector)
 589 {
 590         struct phy_device *phydev = rdev_get_drvdata(rdev);
 591
 592         if (selector)
 593                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 594                                              0, AT803X_DEBUG_RGMII_1V8);
 595         else
 596                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 597                                              AT803X_DEBUG_RGMII_1V8, 0);
 598 }
 599
 600 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
 601 {
 602         struct phy_device *phydev = rdev_get_drvdata(rdev);
 603         int val;
 604
 605         val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
 606         if (val < 0)
 607                 return val;
 608
 609         return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
 610 }
 611
 612 static const struct regulator_ops vddio_regulator_ops = {
 613         .list_voltage = regulator_list_voltage_table,
 614         .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
 615         .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
 616 };
 617
 618 static const unsigned int vddio_voltage_table[] = {
 619         1500000,
 620         1800000,
 621 };
 622
 623 static const struct regulator_desc vddio_desc = {
 624         .name = "vddio",
 625         .of_match = of_match_ptr("vddio-regulator"),
 626         .n_voltages = ARRAY_SIZE(vddio_voltage_table),
 627         .volt_table = vddio_voltage_table,
 628         .ops = &vddio_regulator_ops,
 629         .type = REGULATOR_VOLTAGE,
 630         .owner = THIS_MODULE,
 631 };
 632
 633 static const struct regulator_ops vddh_regulator_ops = {
 634 };
 635
 636 static const struct regulator_desc vddh_desc = {
 637         .name = "vddh",
 638         .of_match = of_match_ptr("vddh-regulator"),
 639         .n_voltages = 1,
 640         .fixed_uV = 2500000,
 641         .ops = &vddh_regulator_ops,
 642         .type = REGULATOR_VOLTAGE,
 643         .owner = THIS_MODULE,
 644 };
 645
 646 static int at8031_register_regulators(struct phy_device *phydev)
 647 {
 648         struct at803x_priv *priv = phydev->priv;
 649         struct device *dev = &phydev->mdio.dev;
 650         struct regulator_config config = { };
 651
 652         config.dev = dev;
 653         config.driver_data = phydev;
 654
 655         priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
 656         if (IS_ERR(priv->vddio_rdev)) {
 657                 phydev_err(phydev, "failed to register VDDIO regulator\n");
 658                 return PTR_ERR(priv->vddio_rdev);
 659         }
 660
 661         priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
 662         if (IS_ERR(priv->vddh_rdev)) {
 663                 phydev_err(phydev, "failed to register VDDH regulator\n");
 664                 return PTR_ERR(priv->vddh_rdev);
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
 671 {
 672         struct phy_device *phydev = upstream;
 673         __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
 674         __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
 675         phy_interface_t iface;
 676
 677         linkmode_zero(phy_support);
 678         phylink_set(phy_support, 1000baseX_Full);
 679         phylink_set(phy_support, 1000baseT_Full);
 680         phylink_set(phy_support, Autoneg);
 681         phylink_set(phy_support, Pause);
 682         phylink_set(phy_support, Asym_Pause);
 683
 684         linkmode_zero(sfp_support);
 685         sfp_parse_support(phydev->sfp_bus, id, sfp_support);
 686         /* Some modules support 10G modes as well as others we support.
 687          * Mask out non-supported modes so the correct interface is picked.
 688          */
 689         linkmode_and(sfp_support, phy_support, sfp_support);
 690
 691         if (linkmode_empty(sfp_support)) {
 692                 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
 693                 return -EINVAL;
 694         }
 695
 696         iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
 697
 698         /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
 699          * interface for use with SFP modules.
 700          * However, some copper modules detected as having a preferred SGMII
 701          * interface do default to and function in 1000Base-X mode, so just
 702          * print a warning and allow such modules, as they may have some chance
 703          * of working.
 704          */
 705         if (iface == PHY_INTERFACE_MODE_SGMII)
 706                 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
 707         else if (iface != PHY_INTERFACE_MODE_1000BASEX)
 708                 return -EINVAL;
 709
 710         return 0;
 711 }
 712
 713 static const struct sfp_upstream_ops at803x_sfp_ops = {
 714         .attach = phy_sfp_attach,
 715         .detach = phy_sfp_detach,
 716         .module_insert = at803x_sfp_insert,
 717 };
 718
 719 static int at803x_parse_dt(struct phy_device *phydev)
 720 {
 721         struct device_node *node = phydev->mdio.dev.of_node;
 722         struct at803x_priv *priv = phydev->priv;
 723         u32 freq, strength, tw;
 724         unsigned int sel;
 725         int ret;
 726
 727         if (!IS_ENABLED(CONFIG_OF_MDIO))
 728                 return 0;
 729
 730         if (of_property_read_bool(node, "qca,disable-smarteee"))
 731                 priv->flags |= AT803X_DISABLE_SMARTEEE;
 732
 733         if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
 734                 if (!tw || tw > 255) {
 735                         phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
 736                         return -EINVAL;
 737                 }
 738                 priv->smarteee_lpi_tw_1g = tw;
 739         }
 740
 741         if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
 742                 if (!tw || tw > 255) {
 743                         phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
 744                         return -EINVAL;
 745                 }
 746                 priv->smarteee_lpi_tw_100m = tw;
 747         }
 748
 749         ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
 750         if (!ret) {
 751                 switch (freq) {
 752                 case 25000000:
 753                         sel = AT803X_CLK_OUT_25MHZ_XTAL;
 754                         break;
 755                 case 50000000:
 756                         sel = AT803X_CLK_OUT_50MHZ_PLL;
 757                         break;
 758                 case 62500000:
 759                         sel = AT803X_CLK_OUT_62_5MHZ_PLL;
 760                         break;
 761                 case 125000000:
 762                         sel = AT803X_CLK_OUT_125MHZ_PLL;
 763                         break;
 764                 default:
 765                         phydev_err(phydev, "invalid qca,clk-out-frequency\n");
 766                         return -EINVAL;
 767                 }
 768
 769                 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
 770                 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
 771
 772                 /* Fixup for the AR8030/AR8035. This chip has another mask and
 773                  * doesn't support the DSP reference. Eg. the lowest bit of the
 774                  * mask. The upper two bits select the same frequencies. Mask
 775                  * the lowest bit here.
 776                  *
 777                  * Warning:
 778                  *   There was no datasheet for the AR8030 available so this is
 779                  *   just a guess. But the AR8035 is listed as pin compatible
 780                  *   to the AR8030 so there might be a good chance it works on
 781                  *   the AR8030 too.
 782                  */
 783                 if (phydev->drv->phy_id == ATH8030_PHY_ID ||
 784                     phydev->drv->phy_id == ATH8035_PHY_ID) {
 785                         priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
 786                         priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
 787                 }
 788         }
 789
 790         ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
 791         if (!ret) {
 792                 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
 793                 switch (strength) {
 794                 case AR803X_STRENGTH_FULL:
 795                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
 796                         break;
 797                 case AR803X_STRENGTH_HALF:
 798                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
 799                         break;
 800                 case AR803X_STRENGTH_QUARTER:
 801                         priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
 802                         break;
 803                 default:
 804                         phydev_err(phydev, "invalid qca,clk-out-strength\n");
 805                         return -EINVAL;
 806                 }
 807         }
 808
 809         /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
 810          * options.
 811          */
 812         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
 813                 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
 814                         priv->flags |= AT803X_KEEP_PLL_ENABLED;
 815
 816                 ret = at8031_register_regulators(phydev);
 817                 if (ret < 0)
 818                         return ret;
 819
 820                 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
 821                                                           "vddio");
 822                 if (IS_ERR(priv->vddio)) {
 823                         phydev_err(phydev, "failed to get VDDIO regulator\n");
 824                         return PTR_ERR(priv->vddio);
 825                 }
 826
 827                 /* Only AR8031/8033 support 1000Base-X for SFP modules */
 828                 ret = phy_sfp_probe(phydev, &at803x_sfp_ops);
 829                 if (ret < 0)
 830                         return ret;
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int at803x_probe(struct phy_device *phydev)
 837 {
 838         struct device *dev = &phydev->mdio.dev;
 839         struct at803x_priv *priv;
 840         int ret;
 841
 842         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 843         if (!priv)
 844                 return -ENOMEM;
 845
 846         phydev->priv = priv;
 847
 848         ret = at803x_parse_dt(phydev);
 849         if (ret)
 850                 return ret;
 851
 852         if (priv->vddio) {
 853                 ret = regulator_enable(priv->vddio);
 854                 if (ret < 0)
 855                         return ret;
 856         }
 857
 858         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
 859                 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 860                 int mode_cfg;
 861                 struct ethtool_wolinfo wol = {
 862                         .wolopts = 0,
 863                 };
 864
 865                 if (ccr < 0)
 866                         goto err;
 867                 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
 868
 869                 switch (mode_cfg) {
 870                 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
 871                 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
 872                         priv->is_1000basex = true;
 873                         fallthrough;
 874                 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
 875                 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
 876                         priv->is_fiber = true;
 877                         break;
 878                 }
 879
 880                 /* Disable WOL by default */
 881                 ret = at803x_set_wol(phydev, &wol);
 882                 if (ret < 0) {
 883                         phydev_err(phydev, "failed to disable WOL on probe: %d\n", ret);
 884                         goto err;
 885                 }
 886         }
 887
 888         return 0;
 889
 890 err:
 891         if (priv->vddio)
 892                 regulator_disable(priv->vddio);
 893
 894         return ret;
 895 }
 896
 897 static void at803x_remove(struct phy_device *phydev)
 898 {
 899         struct at803x_priv *priv = phydev->priv;
 900
 901         if (priv->vddio)
 902                 regulator_disable(priv->vddio);
 903 }
 904
 905 static int at803x_get_features(struct phy_device *phydev)
 906 {
 907         struct at803x_priv *priv = phydev->priv;
 908         int err;
 909
 910         err = genphy_read_abilities(phydev);
 911         if (err)
 912                 return err;
 913
 914         if (phydev->drv->phy_id == QCA8081_PHY_ID) {
 915                 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE);
 916                 if (err < 0)
 917                         return err;
 918
 919                 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported,
 920                                 err & MDIO_PMA_NG_EXTABLE_2_5GBT);
 921         }
 922
 923         if (phydev->drv->phy_id != ATH8031_PHY_ID)
 924                 return 0;
 925
 926         /* AR8031/AR8033 have different status registers
 927          * for copper and fiber operation. However, the
 928          * extended status register is the same for both
 929          * operation modes.
 930          *
 931          * As a result of that, ESTATUS_1000_XFULL is set
 932          * to 1 even when operating in copper TP mode.
 933          *
 934          * Remove this mode from the supported link modes
 935          * when not operating in 1000BaseX mode.
 936          */
 937         if (!priv->is_1000basex)
 938                 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 939                                    phydev->supported);
 940
 941         return 0;
 942 }
 943
 944 static int at803x_smarteee_config(struct phy_device *phydev)
 945 {
 946         struct at803x_priv *priv = phydev->priv;
 947         u16 mask = 0, val = 0;
 948         int ret;
 949
 950         if (priv->flags & AT803X_DISABLE_SMARTEEE)
 951                 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
 952                                       AT803X_MMD3_SMARTEEE_CTL3,
 953                                       AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
 954
 955         if (priv->smarteee_lpi_tw_1g) {
 956                 mask |= 0xff00;
 957                 val |= priv->smarteee_lpi_tw_1g << 8;
 958         }
 959         if (priv->smarteee_lpi_tw_100m) {
 960                 mask |= 0x00ff;
 961                 val |= priv->smarteee_lpi_tw_100m;
 962         }
 963         if (!mask)
 964                 return 0;
 965
 966         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
 967                              mask, val);
 968         if (ret)
 969                 return ret;
 970
 971         return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
 972                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
 973                               AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
 974 }
 975
 976 static int at803x_clk_out_config(struct phy_device *phydev)
 977 {
 978         struct at803x_priv *priv = phydev->priv;
 979
 980         if (!priv->clk_25m_mask)
 981                 return 0;
 982
 983         return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
 984                               priv->clk_25m_mask, priv->clk_25m_reg);
 985 }
 986
 987 static int at8031_pll_config(struct phy_device *phydev)
 988 {
 989         struct at803x_priv *priv = phydev->priv;
 990
 991         /* The default after hardware reset is PLL OFF. After a soft reset, the
 992          * values are retained.
 993          */
 994         if (priv->flags & AT803X_KEEP_PLL_ENABLED)
 995                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 996                                              0, AT803X_DEBUG_PLL_ON);
 997         else
 998                 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 999                                              AT803X_DEBUG_PLL_ON, 0);
1000 }
1001
1002 static int at803x_config_init(struct phy_device *phydev)
1003 {
1004         struct at803x_priv *priv = phydev->priv;
1005         int ret;
1006
1007         if (phydev->drv->phy_id == ATH8031_PHY_ID) {
1008                 /* Some bootloaders leave the fiber page selected.
1009                  * Switch to the appropriate page (fiber or copper), as otherwise we
1010                  * read the PHY capabilities from the wrong page.
1011                  */
1012                 phy_lock_mdio_bus(phydev);
1013                 ret = at803x_write_page(phydev,
1014                                         priv->is_fiber ? AT803X_PAGE_FIBER :
1015                                                          AT803X_PAGE_COPPER);
1016                 phy_unlock_mdio_bus(phydev);
1017                 if (ret)
1018                         return ret;
1019
1020                 ret = at8031_pll_config(phydev);
1021                 if (ret < 0)
1022                         return ret;
1023         }
1024
1025         /* The RX and TX delay default is:
1026          *   after HW reset: RX delay enabled and TX delay disabled
1027          *   after SW reset: RX delay enabled, while TX delay retains the
1028          *   value before reset.
1029          */
1030         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1031             phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1032                 ret = at803x_enable_rx_delay(phydev);
1033         else
1034                 ret = at803x_disable_rx_delay(phydev);
1035         if (ret < 0)
1036                 return ret;
1037
1038         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1039             phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1040                 ret = at803x_enable_tx_delay(phydev);
1041         else
1042                 ret = at803x_disable_tx_delay(phydev);
1043         if (ret < 0)
1044                 return ret;
1045
1046         ret = at803x_smarteee_config(phydev);
1047         if (ret < 0)
1048                 return ret;
1049
1050         ret = at803x_clk_out_config(phydev);
1051         if (ret < 0)
1052                 return ret;
1053
1054         /* Ar803x extended next page bit is enabled by default. Cisco
1055          * multigig switches read this bit and attempt to negotiate 10Gbps
1056          * rates even if the next page bit is disabled. This is incorrect
1057          * behaviour but we still need to accommodate it. XNP is only needed
1058          * for 10Gbps support, so disable XNP.
1059          */
1060         return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
1061 }
1062
1063 static int at803x_ack_interrupt(struct phy_device *phydev)
1064 {
1065         int err;
1066
1067         err = phy_read(phydev, AT803X_INTR_STATUS);
1068
1069         return (err < 0) ? err : 0;
1070 }
1071
1072 static int at803x_config_intr(struct phy_device *phydev)
1073 {
1074         struct at803x_priv *priv = phydev->priv;
1075         int err;
1076         int value;
1077
1078         value = phy_read(phydev, AT803X_INTR_ENABLE);
1079
1080         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1081                 /* Clear any pending interrupts */
1082                 err = at803x_ack_interrupt(phydev);
1083                 if (err)
1084                         return err;
1085
1086                 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
1087                 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
1088                 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
1089                 value |= AT803X_INTR_ENABLE_LINK_FAIL;
1090                 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
1091                 if (priv->is_fiber) {
1092                         value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
1093                         value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
1094                 }
1095
1096                 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
1097         } else {
1098                 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
1099                 if (err)
1100                         return err;
1101
1102                 /* Clear any pending interrupts */
1103                 err = at803x_ack_interrupt(phydev);
1104         }
1105
1106         return err;
1107 }
1108
1109 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
1110 {
1111         int irq_status, int_enabled;
1112
1113         irq_status = phy_read(phydev, AT803X_INTR_STATUS);
1114         if (irq_status < 0) {
1115                 phy_error(phydev);
1116                 return IRQ_NONE;
1117         }
1118
1119         /* Read the current enabled interrupts */
1120         int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
1121         if (int_enabled < 0) {
1122                 phy_error(phydev);
1123                 return IRQ_NONE;
1124         }
1125
1126         /* See if this was one of our enabled interrupts */
1127         if (!(irq_status & int_enabled))
1128                 return IRQ_NONE;
1129
1130         phy_trigger_machine(phydev);
1131
1132         return IRQ_HANDLED;
1133 }
1134
1135 static void at803x_link_change_notify(struct phy_device *phydev)
1136 {
1137         /*
1138          * Conduct a hardware reset for AT8030 every time a link loss is
1139          * signalled. This is necessary to circumvent a hardware bug that
1140          * occurs when the cable is unplugged while TX packets are pending
1141          * in the FIFO. In such cases, the FIFO enters an error mode it
1142          * cannot recover from by software.
1143          */
1144         if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
1145                 struct at803x_context context;
1146
1147                 at803x_context_save(phydev, &context);
1148
1149                 phy_device_reset(phydev, 1);
1150                 msleep(1);
1151                 phy_device_reset(phydev, 0);
1152                 msleep(1);
1153
1154                 at803x_context_restore(phydev, &context);
1155
1156                 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
1157         }
1158 }
1159
1160 static int at803x_read_specific_status(struct phy_device *phydev)
1161 {
1162         int ss;
1163
1164         /* Read the AT8035 PHY-Specific Status register, which indicates the
1165          * speed and duplex that the PHY is actually using, irrespective of
1166          * whether we are in autoneg mode or not.
1167          */
1168         ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
1169         if (ss < 0)
1170                 return ss;
1171
1172         if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
1173                 int sfc, speed;
1174
1175                 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
1176                 if (sfc < 0)
1177                         return sfc;
1178
1179                 /* qca8081 takes the different bits for speed value from at803x */
1180                 if (phydev->drv->phy_id == QCA8081_PHY_ID)
1181                         speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss);
1182                 else
1183                         speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss);
1184
1185                 switch (speed) {
1186                 case AT803X_SS_SPEED_10:
1187                         phydev->speed = SPEED_10;
1188                         break;
1189                 case AT803X_SS_SPEED_100:
1190                         phydev->speed = SPEED_100;
1191                         break;
1192                 case AT803X_SS_SPEED_1000:
1193                         phydev->speed = SPEED_1000;
1194                         break;
1195                 case QCA808X_SS_SPEED_2500:
1196                         phydev->speed = SPEED_2500;
1197                         break;
1198                 }
1199                 if (ss & AT803X_SS_DUPLEX)
1200                         phydev->duplex = DUPLEX_FULL;
1201                 else
1202                         phydev->duplex = DUPLEX_HALF;
1203
1204                 if (ss & AT803X_SS_MDIX)
1205                         phydev->mdix = ETH_TP_MDI_X;
1206                 else
1207                         phydev->mdix = ETH_TP_MDI;
1208
1209                 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
1210                 case AT803X_SFC_MANUAL_MDI:
1211                         phydev->mdix_ctrl = ETH_TP_MDI;
1212                         break;
1213                 case AT803X_SFC_MANUAL_MDIX:
1214                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1215                         break;
1216                 case AT803X_SFC_AUTOMATIC_CROSSOVER:
1217                         phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1218                         break;
1219                 }
1220         }
1221
1222         return 0;
1223 }
1224
1225 static int at803x_read_status(struct phy_device *phydev)
1226 {
1227         struct at803x_priv *priv = phydev->priv;
1228         int err, old_link = phydev->link;
1229
1230         if (priv->is_1000basex)
1231                 return genphy_c37_read_status(phydev);
1232
1233         /* Update the link, but return if there was an error */
1234         err = genphy_update_link(phydev);
1235         if (err)
1236                 return err;
1237
1238         /* why bother the PHY if nothing can have changed */
1239         if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
1240                 return 0;
1241
1242         phydev->speed = SPEED_UNKNOWN;
1243         phydev->duplex = DUPLEX_UNKNOWN;
1244         phydev->pause = 0;
1245         phydev->asym_pause = 0;
1246
1247         err = genphy_read_lpa(phydev);
1248         if (err < 0)
1249                 return err;
1250
1251         err = at803x_read_specific_status(phydev);
1252         if (err < 0)
1253                 return err;
1254
1255         if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1256                 phy_resolve_aneg_pause(phydev);
1257
1258         return 0;
1259 }
1260
1261 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1262 {
1263         u16 val;
1264
1265         switch (ctrl) {
1266         case ETH_TP_MDI:
1267                 val = AT803X_SFC_MANUAL_MDI;
1268                 break;
1269         case ETH_TP_MDI_X:
1270                 val = AT803X_SFC_MANUAL_MDIX;
1271                 break;
1272         case ETH_TP_MDI_AUTO:
1273                 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1274                 break;
1275         default:
1276                 return 0;
1277         }
1278
1279         return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1280                           AT803X_SFC_MDI_CROSSOVER_MODE_M,
1281                           FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1282 }
1283
1284 static int at803x_config_aneg(struct phy_device *phydev)
1285 {
1286         struct at803x_priv *priv = phydev->priv;
1287         int ret;
1288
1289         ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1290         if (ret < 0)
1291                 return ret;
1292
1293         /* Changes of the midx bits are disruptive to the normal operation;
1294          * therefore any changes to these registers must be followed by a
1295          * software reset to take effect.
1296          */
1297         if (ret == 1) {
1298                 ret = genphy_soft_reset(phydev);
1299                 if (ret < 0)
1300                         return ret;
1301         }
1302
1303         if (priv->is_1000basex)
1304                 return genphy_c37_config_aneg(phydev);
1305
1306         /* Do not restart auto-negotiation by setting ret to 0 defautly,
1307          * when calling __genphy_config_aneg later.
1308          */
1309         ret = 0;
1310
1311         if (phydev->drv->phy_id == QCA8081_PHY_ID) {
1312                 int phy_ctrl = 0;
1313
1314                 /* The reg MII_BMCR also needs to be configured for force mode, the
1315                  * genphy_config_aneg is also needed.
1316                  */
1317                 if (phydev->autoneg == AUTONEG_DISABLE)
1318                         genphy_c45_pma_setup_forced(phydev);
1319
1320                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
1321                         phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
1322
1323                 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1324                                 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
1325                 if (ret < 0)
1326                         return ret;
1327         }
1328
1329         return __genphy_config_aneg(phydev, ret);
1330 }
1331
1332 static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1333 {
1334         int val;
1335
1336         val = phy_read(phydev, AT803X_SMART_SPEED);
1337         if (val < 0)
1338                 return val;
1339
1340         if (val & AT803X_SMART_SPEED_ENABLE)
1341                 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1342         else
1343                 *d = DOWNSHIFT_DEV_DISABLE;
1344
1345         return 0;
1346 }
1347
1348 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1349 {
1350         u16 mask, set;
1351         int ret;
1352
1353         switch (cnt) {
1354         case DOWNSHIFT_DEV_DEFAULT_COUNT:
1355                 cnt = AT803X_DEFAULT_DOWNSHIFT;
1356                 fallthrough;
1357         case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1358                 set = AT803X_SMART_SPEED_ENABLE |
1359                       AT803X_SMART_SPEED_BYPASS_TIMER |
1360                       FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1361                 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1362                 break;
1363         case DOWNSHIFT_DEV_DISABLE:
1364                 set = 0;
1365                 mask = AT803X_SMART_SPEED_ENABLE |
1366                        AT803X_SMART_SPEED_BYPASS_TIMER;
1367                 break;
1368         default:
1369                 return -EINVAL;
1370         }
1371
1372         ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1373
1374         /* After changing the smart speed settings, we need to perform a
1375          * software reset, use phy_init_hw() to make sure we set the
1376          * reapply any values which might got lost during software reset.
1377          */
1378         if (ret == 1)
1379                 ret = phy_init_hw(phydev);
1380
1381         return ret;
1382 }
1383
1384 static int at803x_get_tunable(struct phy_device *phydev,
1385                               struct ethtool_tunable *tuna, void *data)
1386 {
1387         switch (tuna->id) {
1388         case ETHTOOL_PHY_DOWNSHIFT:
1389                 return at803x_get_downshift(phydev, data);
1390         default:
1391                 return -EOPNOTSUPP;
1392         }
1393 }
1394
1395 static int at803x_set_tunable(struct phy_device *phydev,
1396                               struct ethtool_tunable *tuna, const void *data)
1397 {
1398         switch (tuna->id) {
1399         case ETHTOOL_PHY_DOWNSHIFT:
1400                 return at803x_set_downshift(phydev, *(const u8 *)data);
1401         default:
1402                 return -EOPNOTSUPP;
1403         }
1404 }
1405
1406 static int at803x_cable_test_result_trans(u16 status)
1407 {
1408         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1409         case AT803X_CDT_STATUS_STAT_NORMAL:
1410                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1411         case AT803X_CDT_STATUS_STAT_SHORT:
1412                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1413         case AT803X_CDT_STATUS_STAT_OPEN:
1414                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1415         case AT803X_CDT_STATUS_STAT_FAIL:
1416         default:
1417                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1418         }
1419 }
1420
1421 static bool at803x_cdt_test_failed(u16 status)
1422 {
1423         return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1424                 AT803X_CDT_STATUS_STAT_FAIL;
1425 }
1426
1427 static bool at803x_cdt_fault_length_valid(u16 status)
1428 {
1429         switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1430         case AT803X_CDT_STATUS_STAT_OPEN:
1431         case AT803X_CDT_STATUS_STAT_SHORT:
1432                 return true;
1433         }
1434         return false;
1435 }
1436
1437 static int at803x_cdt_fault_length(u16 status)
1438 {
1439         int dt;
1440
1441         /* According to the datasheet the distance to the fault is
1442          * DELTA_TIME * 0.824 meters.
1443          *
1444          * The author suspect the correct formula is:
1445          *
1446          *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1447          *
1448          * where c is the speed of light, VF is the velocity factor of
1449          * the twisted pair cable, 125MHz the counter frequency and
1450          * we need to divide by 2 because the hardware will measure the
1451          * round trip time to the fault and back to the PHY.
1452          *
1453          * With a VF of 0.69 we get the factor 0.824 mentioned in the
1454          * datasheet.
1455          */
1456         dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1457
1458         return (dt * 824) / 10;
1459 }
1460
1461 static int at803x_cdt_start(struct phy_device *phydev, int pair)
1462 {
1463         u16 cdt;
1464
1465         /* qca8081 takes the different bit 15 to enable CDT test */
1466         if (phydev->drv->phy_id == QCA8081_PHY_ID)
1467                 cdt = QCA808X_CDT_ENABLE_TEST |
1468                         QCA808X_CDT_LENGTH_UNIT |
1469                         QCA808X_CDT_INTER_CHECK_DIS;
1470         else
1471                 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1472                         AT803X_CDT_ENABLE_TEST;
1473
1474         return phy_write(phydev, AT803X_CDT, cdt);
1475 }
1476
1477 static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1478 {
1479         int val, ret;
1480         u16 cdt_en;
1481
1482         if (phydev->drv->phy_id == QCA8081_PHY_ID)
1483                 cdt_en = QCA808X_CDT_ENABLE_TEST;
1484         else
1485                 cdt_en = AT803X_CDT_ENABLE_TEST;
1486
1487         /* One test run takes about 25ms */
1488         ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1489                                     !(val & cdt_en),
1490                                     30000, 100000, true);
1491
1492         return ret < 0 ? ret : 0;
1493 }
1494
1495 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1496 {
1497         static const int ethtool_pair[] = {
1498                 ETHTOOL_A_CABLE_PAIR_A,
1499                 ETHTOOL_A_CABLE_PAIR_B,
1500                 ETHTOOL_A_CABLE_PAIR_C,
1501                 ETHTOOL_A_CABLE_PAIR_D,
1502         };
1503         int ret, val;
1504
1505         ret = at803x_cdt_start(phydev, pair);
1506         if (ret)
1507                 return ret;
1508
1509         ret = at803x_cdt_wait_for_completion(phydev);
1510         if (ret)
1511                 return ret;
1512
1513         val = phy_read(phydev, AT803X_CDT_STATUS);
1514         if (val < 0)
1515                 return val;
1516
1517         if (at803x_cdt_test_failed(val))
1518                 return 0;
1519
1520         ethnl_cable_test_result(phydev, ethtool_pair[pair],
1521                                 at803x_cable_test_result_trans(val));
1522
1523         if (at803x_cdt_fault_length_valid(val))
1524                 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1525                                               at803x_cdt_fault_length(val));
1526
1527         return 1;
1528 }
1529
1530 static int at803x_cable_test_get_status(struct phy_device *phydev,
1531                                         bool *finished)
1532 {
1533         unsigned long pair_mask;
1534         int retries = 20;
1535         int pair, ret;
1536
1537         if (phydev->phy_id == ATH9331_PHY_ID ||
1538             phydev->phy_id == ATH8032_PHY_ID ||
1539             phydev->phy_id == QCA9561_PHY_ID)
1540                 pair_mask = 0x3;
1541         else
1542                 pair_mask = 0xf;
1543
1544         *finished = false;
1545
1546         /* According to the datasheet the CDT can be performed when
1547          * there is no link partner or when the link partner is
1548          * auto-negotiating. Starting the test will restart the AN
1549          * automatically. It seems that doing this repeatedly we will
1550          * get a slot where our link partner won't disturb our
1551          * measurement.
1552          */
1553         while (pair_mask && retries--) {
1554                 for_each_set_bit(pair, &pair_mask, 4) {
1555                         ret = at803x_cable_test_one_pair(phydev, pair);
1556                         if (ret < 0)
1557                                 return ret;
1558                         if (ret)
1559                                 clear_bit(pair, &pair_mask);
1560                 }
1561                 if (pair_mask)
1562                         msleep(250);
1563         }
1564
1565         *finished = true;
1566
1567         return 0;
1568 }
1569
1570 static int at803x_cable_test_start(struct phy_device *phydev)
1571 {
1572         /* Enable auto-negotiation, but advertise no capabilities, no link
1573          * will be established. A restart of the auto-negotiation is not
1574          * required, because the cable test will automatically break the link.
1575          */
1576         phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1577         phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1578         if (phydev->phy_id != ATH9331_PHY_ID &&
1579             phydev->phy_id != ATH8032_PHY_ID &&
1580             phydev->phy_id != QCA9561_PHY_ID)
1581                 phy_write(phydev, MII_CTRL1000, 0);
1582
1583         /* we do all the (time consuming) work later */
1584         return 0;
1585 }
1586
1587 static int qca83xx_config_init(struct phy_device *phydev)
1588 {
1589         u8 switch_revision;
1590
1591         switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1592
1593         switch (switch_revision) {
1594         case 1:
1595                 /* For 100M waveform */
1596                 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
1597                 /* Turn on Gigabit clock */
1598                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
1599                 break;
1600
1601         case 2:
1602                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1603                 fallthrough;
1604         case 4:
1605                 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1606                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
1607                 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
1608                 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1609                 break;
1610         }
1611
1612         /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1613          * Disable on init and enable only with 100m speed following
1614          * qca original source code.
1615          */
1616         if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
1617             phydev->drv->phy_id == QCA8327_B_PHY_ID)
1618                 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1619                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
1620
1621         /* Following original QCA sourcecode set port to prefer master */
1622         phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1623
1624         return 0;
1625 }
1626
1627 static void qca83xx_link_change_notify(struct phy_device *phydev)
1628 {
1629         /* QCA8337 doesn't require DAC Amplitude adjustement */
1630         if (phydev->drv->phy_id == QCA8337_PHY_ID)
1631                 return;
1632
1633         /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1634         if (phydev->state == PHY_RUNNING) {
1635                 if (phydev->speed == SPEED_100)
1636                         at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1637                                               QCA8327_DEBUG_MANU_CTRL_EN,
1638                                               QCA8327_DEBUG_MANU_CTRL_EN);
1639         } else {
1640                 /* Reset DAC Amplitude adjustment */
1641                 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1642                                       QCA8327_DEBUG_MANU_CTRL_EN, 0);
1643         }
1644 }
1645
1646 static int qca83xx_resume(struct phy_device *phydev)
1647 {
1648         int ret, val;
1649
1650         /* Skip reset if not suspended */
1651         if (!phydev->suspended)
1652                 return 0;
1653
1654         /* Reinit the port, reset values set by suspend */
1655         qca83xx_config_init(phydev);
1656
1657         /* Reset the port on port resume */
1658         phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1659
1660         /* On resume from suspend the switch execute a reset and
1661          * restart auto-negotiation. Wait for reset to complete.
1662          */
1663         ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1664                                     50000, 600000, true);
1665         if (ret)
1666                 return ret;
1667
1668         msleep(1);
1669
1670         return 0;
1671 }
1672
1673 static int qca83xx_suspend(struct phy_device *phydev)
1674 {
1675         u16 mask = 0;
1676
1677         /* Only QCA8337 support actual suspend.
1678          * QCA8327 cause port unreliability when phy suspend
1679          * is set.
1680          */
1681         if (phydev->drv->phy_id == QCA8337_PHY_ID) {
1682                 genphy_suspend(phydev);
1683         } else {
1684                 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1685                 phy_modify(phydev, MII_BMCR, mask, 0);
1686         }
1687
1688         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1689                               AT803X_DEBUG_GATE_CLK_IN1000, 0);
1690
1691         at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1692                               AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1693                               AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
1694
1695         return 0;
1696 }
1697
1698 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1699 {
1700         int ret;
1701
1702         /* Enable fast retrain */
1703         ret = genphy_c45_fast_retrain(phydev, true);
1704         if (ret)
1705                 return ret;
1706
1707         phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1708                         QCA808X_TOP_OPTION1_DATA);
1709         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1710                         QCA808X_MSE_THRESHOLD_20DB_VALUE);
1711         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1712                         QCA808X_MSE_THRESHOLD_17DB_VALUE);
1713         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1714                         QCA808X_MSE_THRESHOLD_27DB_VALUE);
1715         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1716                         QCA808X_MSE_THRESHOLD_28DB_VALUE);
1717         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1718                         QCA808X_MMD3_DEBUG_1_VALUE);
1719         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1720                         QCA808X_MMD3_DEBUG_4_VALUE);
1721         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1722                         QCA808X_MMD3_DEBUG_5_VALUE);
1723         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1724                         QCA808X_MMD3_DEBUG_3_VALUE);
1725         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1726                         QCA808X_MMD3_DEBUG_6_VALUE);
1727         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
1728                         QCA808X_MMD3_DEBUG_2_VALUE);
1729
1730         return 0;
1731 }
1732
1733 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev)
1734 {
1735         u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE);
1736
1737         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1738                         QCA808X_MASTER_SLAVE_SEED_CFG,
1739                         FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value));
1740 }
1741
1742 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
1743 {
1744         u16 seed_enable = 0;
1745
1746         if (enable)
1747                 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE;
1748
1749         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
1750                         QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable);
1751 }
1752
1753 static int qca808x_config_init(struct phy_device *phydev)
1754 {
1755         int ret;
1756
1757         /* Active adc&vga on 802.3az for the link 1000M and 100M */
1758         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
1759                         QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
1760         if (ret)
1761                 return ret;
1762
1763         /* Adjust the threshold on 802.3az for the link 1000M */
1764         ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
1765                         QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);
1766         if (ret)
1767                 return ret;
1768
1769         /* Config the fast retrain for the link 2500M */
1770         ret = qca808x_phy_fast_retrain_config(phydev);
1771         if (ret)
1772                 return ret;
1773
1774         /* Configure lower ramdom seed to make phy linked as slave mode */
1775         ret = qca808x_phy_ms_random_seed_set(phydev);
1776         if (ret)
1777                 return ret;
1778
1779         /* Enable seed */
1780         ret = qca808x_phy_ms_seed_enable(phydev, true);
1781         if (ret)
1782                 return ret;
1783
1784         /* Configure adc threshold as 100mv for the link 10M */
1785         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
1786                         QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
1787 }
1788
1789 static int qca808x_read_status(struct phy_device *phydev)
1790 {
1791         int ret;
1792
1793         ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
1794         if (ret < 0)
1795                 return ret;
1796
1797         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
1798                         ret & MDIO_AN_10GBT_STAT_LP2_5G);
1799
1800         ret = genphy_read_status(phydev);
1801         if (ret)
1802                 return ret;
1803
1804         ret = at803x_read_specific_status(phydev);
1805         if (ret < 0)
1806                 return ret;
1807
1808         if (phydev->link) {
1809                 if (phydev->speed == SPEED_2500)
1810                         phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1811                 else
1812                         phydev->interface = PHY_INTERFACE_MODE_SGMII;
1813         } else {
1814                 /* generate seed as a lower random value to make PHY linked as SLAVE easily,
1815                  * except for master/slave configuration fault detected.
1816                  * the reason for not putting this code into the function link_change_notify is
1817                  * the corner case where the link partner is also the qca8081 PHY and the seed
1818                  * value is configured as the same value, the link can't be up and no link change
1819                  * occurs.
1820                  */
1821                 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) {
1822                         qca808x_phy_ms_seed_enable(phydev, false);
1823                 } else {
1824                         qca808x_phy_ms_random_seed_set(phydev);
1825                         qca808x_phy_ms_seed_enable(phydev, true);
1826                 }
1827         }
1828
1829         return 0;
1830 }
1831
1832 static int qca808x_soft_reset(struct phy_device *phydev)
1833 {
1834         int ret;
1835
1836         ret = genphy_soft_reset(phydev);
1837         if (ret < 0)
1838                 return ret;
1839
1840         return qca808x_phy_ms_seed_enable(phydev, true);
1841 }
1842
1843 static bool qca808x_cdt_fault_length_valid(int cdt_code)
1844 {
1845         switch (cdt_code) {
1846         case QCA808X_CDT_STATUS_STAT_SHORT:
1847         case QCA808X_CDT_STATUS_STAT_OPEN:
1848                 return true;
1849         default:
1850                 return false;
1851         }
1852 }
1853
1854 static int qca808x_cable_test_result_trans(int cdt_code)
1855 {
1856         switch (cdt_code) {
1857         case QCA808X_CDT_STATUS_STAT_NORMAL:
1858                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1859         case QCA808X_CDT_STATUS_STAT_SHORT:
1860                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1861         case QCA808X_CDT_STATUS_STAT_OPEN:
1862                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1863         case QCA808X_CDT_STATUS_STAT_FAIL:
1864         default:
1865                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1866         }
1867 }
1868
1869 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair)
1870 {
1871         int val;
1872         u32 cdt_length_reg = 0;
1873
1874         switch (pair) {
1875         case ETHTOOL_A_CABLE_PAIR_A:
1876                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
1877                 break;
1878         case ETHTOOL_A_CABLE_PAIR_B:
1879                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
1880                 break;
1881         case ETHTOOL_A_CABLE_PAIR_C:
1882                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
1883                 break;
1884         case ETHTOOL_A_CABLE_PAIR_D:
1885                 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
1886                 break;
1887         default:
1888                 return -EINVAL;
1889         }
1890
1891         val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
1892         if (val < 0)
1893                 return val;
1894
1895         return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10;
1896 }
1897
1898 static int qca808x_cable_test_start(struct phy_device *phydev)
1899 {
1900         int ret;
1901
1902         /* perform CDT with the following configs:
1903          * 1. disable hibernation.
1904          * 2. force PHY working in MDI mode.
1905          * 3. for PHY working in 1000BaseT.
1906          * 4. configure the threshold.
1907          */
1908
1909         ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
1910         if (ret < 0)
1911                 return ret;
1912
1913         ret = at803x_config_mdix(phydev, ETH_TP_MDI);
1914         if (ret < 0)
1915                 return ret;
1916
1917         /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
1918         phydev->duplex = DUPLEX_FULL;
1919         phydev->speed = SPEED_1000;
1920         ret = genphy_c45_pma_setup_forced(phydev);
1921         if (ret < 0)
1922                 return ret;
1923
1924         ret = genphy_setup_forced(phydev);
1925         if (ret < 0)
1926                 return ret;
1927
1928         /* configure the thresholds for open, short, pair ok test */
1929         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
1930         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
1931         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
1932         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
1933         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
1934         phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
1935
1936         return 0;
1937 }
1938
1939 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
1940 {
1941         int ret, val;
1942         int pair_a, pair_b, pair_c, pair_d;
1943
1944         *finished = false;
1945
1946         ret = at803x_cdt_start(phydev, 0);
1947         if (ret)
1948                 return ret;
1949
1950         ret = at803x_cdt_wait_for_completion(phydev);
1951         if (ret)
1952                 return ret;
1953
1954         val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
1955         if (val < 0)
1956                 return val;
1957
1958         pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val);
1959         pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val);
1960         pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val);
1961         pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val);
1962
1963         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1964                                 qca808x_cable_test_result_trans(pair_a));
1965         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
1966                                 qca808x_cable_test_result_trans(pair_b));
1967         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
1968                                 qca808x_cable_test_result_trans(pair_c));
1969         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
1970                                 qca808x_cable_test_result_trans(pair_d));
1971
1972         if (qca808x_cdt_fault_length_valid(pair_a))
1973                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
1974                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));
1975         if (qca808x_cdt_fault_length_valid(pair_b))
1976                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,
1977                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));
1978         if (qca808x_cdt_fault_length_valid(pair_c))
1979                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,
1980                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));
1981         if (qca808x_cdt_fault_length_valid(pair_d))
1982                 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,
1983                                 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));
1984
1985         *finished = true;
1986
1987         return 0;
1988 }
1989
1990 static struct phy_driver at803x_driver[] = {
1991 {
1992         /* Qualcomm Atheros AR8035 */
1993         PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1994         .name                   = "Qualcomm Atheros AR8035",
1995         .flags                  = PHY_POLL_CABLE_TEST,
1996         .probe                  = at803x_probe,
1997         .remove                 = at803x_remove,
1998         .config_aneg            = at803x_config_aneg,
1999         .config_init            = at803x_config_init,
2000         .soft_reset             = genphy_soft_reset,
2001         .set_wol                = at803x_set_wol,
2002         .get_wol                = at803x_get_wol,
2003         .suspend                = at803x_suspend,
2004         .resume                 = at803x_resume,
2005         /* PHY_GBIT_FEATURES */
2006         .read_status            = at803x_read_status,
2007         .config_intr            = at803x_config_intr,
2008         .handle_interrupt       = at803x_handle_interrupt,
2009         .get_tunable            = at803x_get_tunable,
2010         .set_tunable            = at803x_set_tunable,
2011         .cable_test_start       = at803x_cable_test_start,
2012         .cable_test_get_status  = at803x_cable_test_get_status,
2013 }, {
2014         /* Qualcomm Atheros AR8030 */
2015         .phy_id                 = ATH8030_PHY_ID,
2016         .name                   = "Qualcomm Atheros AR8030",
2017         .phy_id_mask            = AT8030_PHY_ID_MASK,
2018         .probe                  = at803x_probe,
2019         .remove                 = at803x_remove,
2020         .config_init            = at803x_config_init,
2021         .link_change_notify     = at803x_link_change_notify,
2022         .set_wol                = at803x_set_wol,
2023         .get_wol                = at803x_get_wol,
2024         .suspend                = at803x_suspend,
2025         .resume                 = at803x_resume,
2026         /* PHY_BASIC_FEATURES */
2027         .config_intr            = at803x_config_intr,
2028         .handle_interrupt       = at803x_handle_interrupt,
2029 }, {
2030         /* Qualcomm Atheros AR8031/AR8033 */
2031         PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
2032         .name                   = "Qualcomm Atheros AR8031/AR8033",
2033         .flags                  = PHY_POLL_CABLE_TEST,
2034         .probe                  = at803x_probe,
2035         .remove                 = at803x_remove,
2036         .config_init            = at803x_config_init,
2037         .config_aneg            = at803x_config_aneg,
2038         .soft_reset             = genphy_soft_reset,
2039         .set_wol                = at803x_set_wol,
2040         .get_wol                = at803x_get_wol,
2041         .suspend                = at803x_suspend,
2042         .resume                 = at803x_resume,
2043         .read_page              = at803x_read_page,
2044         .write_page             = at803x_write_page,
2045         .get_features           = at803x_get_features,
2046         .read_status            = at803x_read_status,
2047         .config_intr            = &at803x_config_intr,
2048         .handle_interrupt       = at803x_handle_interrupt,
2049         .get_tunable            = at803x_get_tunable,
2050         .set_tunable            = at803x_set_tunable,
2051         .cable_test_start       = at803x_cable_test_start,
2052         .cable_test_get_status  = at803x_cable_test_get_status,
2053 }, {
2054         /* Qualcomm Atheros AR8032 */
2055         PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
2056         .name                   = "Qualcomm Atheros AR8032",
2057         .probe                  = at803x_probe,
2058         .remove                 = at803x_remove,
2059         .flags                  = PHY_POLL_CABLE_TEST,
2060         .config_init            = at803x_config_init,
2061         .link_change_notify     = at803x_link_change_notify,
2062         .set_wol                = at803x_set_wol,
2063         .get_wol                = at803x_get_wol,
2064         .suspend                = at803x_suspend,
2065         .resume                 = at803x_resume,
2066         /* PHY_BASIC_FEATURES */
2067         .config_intr            = at803x_config_intr,
2068         .handle_interrupt       = at803x_handle_interrupt,
2069         .cable_test_start       = at803x_cable_test_start,
2070         .cable_test_get_status  = at803x_cable_test_get_status,
2071 }, {
2072         /* ATHEROS AR9331 */
2073         PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
2074         .name                   = "Qualcomm Atheros AR9331 built-in PHY",
2075         .suspend                = at803x_suspend,
2076         .resume                 = at803x_resume,
2077         .flags                  = PHY_POLL_CABLE_TEST,
2078         /* PHY_BASIC_FEATURES */
2079         .config_intr            = &at803x_config_intr,
2080         .handle_interrupt       = at803x_handle_interrupt,
2081         .cable_test_start       = at803x_cable_test_start,
2082         .cable_test_get_status  = at803x_cable_test_get_status,
2083         .read_status            = at803x_read_status,
2084         .soft_reset             = genphy_soft_reset,
2085         .config_aneg            = at803x_config_aneg,
2086 }, {
2087         /* Qualcomm Atheros QCA9561 */
2088         PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
2089         .name                   = "Qualcomm Atheros QCA9561 built-in PHY",
2090         .suspend                = at803x_suspend,
2091         .resume                 = at803x_resume,
2092         .flags                  = PHY_POLL_CABLE_TEST,
2093         /* PHY_BASIC_FEATURES */
2094         .config_intr            = &at803x_config_intr,
2095         .handle_interrupt       = at803x_handle_interrupt,
2096         .cable_test_start       = at803x_cable_test_start,
2097         .cable_test_get_status  = at803x_cable_test_get_status,
2098         .read_status            = at803x_read_status,
2099         .soft_reset             = genphy_soft_reset,
2100         .config_aneg            = at803x_config_aneg,
2101 }, {
2102         /* QCA8337 */
2103         .phy_id                 = QCA8337_PHY_ID,
2104         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2105         .name                   = "Qualcomm Atheros 8337 internal PHY",
2106         /* PHY_GBIT_FEATURES */
2107         .link_change_notify     = qca83xx_link_change_notify,
2108         .probe                  = at803x_probe,
2109         .flags                  = PHY_IS_INTERNAL,
2110         .config_init            = qca83xx_config_init,
2111         .soft_reset             = genphy_soft_reset,
2112         .get_sset_count         = at803x_get_sset_count,
2113         .get_strings            = at803x_get_strings,
2114         .get_stats              = at803x_get_stats,
2115         .suspend                = qca83xx_suspend,
2116         .resume                 = qca83xx_resume,
2117 }, {
2118         /* QCA8327-A from switch QCA8327-AL1A */
2119         .phy_id                 = QCA8327_A_PHY_ID,
2120         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2121         .name                   = "Qualcomm Atheros 8327-A internal PHY",
2122         /* PHY_GBIT_FEATURES */
2123         .link_change_notify     = qca83xx_link_change_notify,
2124         .probe                  = at803x_probe,
2125         .flags                  = PHY_IS_INTERNAL,
2126         .config_init            = qca83xx_config_init,
2127         .soft_reset             = genphy_soft_reset,
2128         .get_sset_count         = at803x_get_sset_count,
2129         .get_strings            = at803x_get_strings,
2130         .get_stats              = at803x_get_stats,
2131         .suspend                = qca83xx_suspend,
2132         .resume                 = qca83xx_resume,
2133 }, {
2134         /* QCA8327-B from switch QCA8327-BL1A */
2135         .phy_id                 = QCA8327_B_PHY_ID,
2136         .phy_id_mask            = QCA8K_PHY_ID_MASK,
2137         .name                   = "Qualcomm Atheros 8327-B internal PHY",
2138         /* PHY_GBIT_FEATURES */
2139         .link_change_notify     = qca83xx_link_change_notify,
2140         .probe                  = at803x_probe,
2141         .flags                  = PHY_IS_INTERNAL,
2142         .config_init            = qca83xx_config_init,
2143         .soft_reset             = genphy_soft_reset,
2144         .get_sset_count         = at803x_get_sset_count,
2145         .get_strings            = at803x_get_strings,
2146         .get_stats              = at803x_get_stats,
2147         .suspend                = qca83xx_suspend,
2148         .resume                 = qca83xx_resume,
2149 }, {
2150         /* Qualcomm QCA8081 */
2151         PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
2152         .name                   = "Qualcomm QCA8081",
2153         .flags                  = PHY_POLL_CABLE_TEST,
2154         .config_intr            = at803x_config_intr,
2155         .handle_interrupt       = at803x_handle_interrupt,
2156         .get_tunable            = at803x_get_tunable,
2157         .set_tunable            = at803x_set_tunable,
2158         .set_wol                = at803x_set_wol,
2159         .get_wol                = at803x_get_wol,
2160         .get_features           = at803x_get_features,
2161         .config_aneg            = at803x_config_aneg,
2162         .suspend                = genphy_suspend,
2163         .resume                 = genphy_resume,
2164         .read_status            = qca808x_read_status,
2165         .config_init            = qca808x_config_init,
2166         .soft_reset             = qca808x_soft_reset,
2167         .cable_test_start       = qca808x_cable_test_start,
2168         .cable_test_get_status  = qca808x_cable_test_get_status,
2169 }, };
2170
2171 module_phy_driver(at803x_driver);
2172
2173 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
2174         { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
2175         { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
2176         { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
2177         { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
2178         { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
2179         { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
2180         { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
2181         { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
2182         { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
2183         { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
2184         { }
2185 };
2186
2187 MODULE_DEVICE_TABLE(mdio, atheros_tbl);