1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
9 #include <linux/delay.h>
10 #include <linux/pcs/pcs-xpcs.h>
11 #include <linux/mdio.h>
12 #include <linux/phylink.h>
13 #include <linux/workqueue.h>
16 #define phylink_pcs_to_xpcs(pl_pcs) \
17 container_of((pl_pcs), struct dw_xpcs, pcs)
19 static const int xpcs_usxgmii_features[] = {
20 ETHTOOL_LINK_MODE_Pause_BIT,
21 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 ETHTOOL_LINK_MODE_Autoneg_BIT,
23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 __ETHTOOL_LINK_MODE_MASK_NBITS,
30 static const int xpcs_10gkr_features[] = {
31 ETHTOOL_LINK_MODE_Pause_BIT,
32 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 __ETHTOOL_LINK_MODE_MASK_NBITS,
37 static const int xpcs_xlgmii_features[] = {
38 ETHTOOL_LINK_MODE_Pause_BIT,
39 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 __ETHTOOL_LINK_MODE_MASK_NBITS,
67 static const int xpcs_sgmii_features[] = {
68 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
69 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
70 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
71 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
72 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
73 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
74 __ETHTOOL_LINK_MODE_MASK_NBITS,
77 static const int xpcs_2500basex_features[] = {
78 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
79 ETHTOOL_LINK_MODE_Autoneg_BIT,
80 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
81 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
82 __ETHTOOL_LINK_MODE_MASK_NBITS,
85 static const phy_interface_t xpcs_usxgmii_interfaces[] = {
86 PHY_INTERFACE_MODE_USXGMII,
89 static const phy_interface_t xpcs_10gkr_interfaces[] = {
90 PHY_INTERFACE_MODE_10GKR,
93 static const phy_interface_t xpcs_xlgmii_interfaces[] = {
94 PHY_INTERFACE_MODE_XLGMII,
97 static const phy_interface_t xpcs_sgmii_interfaces[] = {
98 PHY_INTERFACE_MODE_SGMII,
101 static const phy_interface_t xpcs_2500basex_interfaces[] = {
102 PHY_INTERFACE_MODE_2500BASEX,
103 PHY_INTERFACE_MODE_MAX,
112 DW_XPCS_INTERFACE_MAX,
116 const int *supported;
117 const phy_interface_t *interface;
120 int (*pma_config)(struct dw_xpcs *xpcs);
126 const struct xpcs_compat *compat;
129 static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
130 phy_interface_t interface)
134 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
135 const struct xpcs_compat *compat = &id->compat[i];
137 for (j = 0; j < compat->num_interfaces; j++)
138 if (compat->interface[j] == interface)
145 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
147 const struct xpcs_compat *compat;
149 compat = xpcs_find_compat(xpcs->id, interface);
153 return compat->an_mode;
155 EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
157 static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
158 enum ethtool_link_mode_bit_indices linkmode)
162 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
163 if (compat->supported[i] == linkmode)
169 #define xpcs_linkmode_supported(compat, mode) \
170 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
172 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
174 u32 reg_addr = mdiobus_c45_addr(dev, reg);
175 struct mii_bus *bus = xpcs->mdiodev->bus;
176 int addr = xpcs->mdiodev->addr;
178 return mdiobus_read(bus, addr, reg_addr);
181 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
183 u32 reg_addr = mdiobus_c45_addr(dev, reg);
184 struct mii_bus *bus = xpcs->mdiodev->bus;
185 int addr = xpcs->mdiodev->addr;
187 return mdiobus_write(bus, addr, reg_addr, val);
190 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
192 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
195 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
198 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
201 static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
203 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
206 static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
208 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
211 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
213 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
214 unsigned int retries = 12;
219 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
222 } while (ret & MDIO_CTRL1_RESET && --retries);
224 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
227 static int xpcs_soft_reset(struct dw_xpcs *xpcs,
228 const struct xpcs_compat *compat)
232 switch (compat->an_mode) {
236 case DW_AN_C37_SGMII:
238 dev = MDIO_MMD_VEND2;
244 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
248 return xpcs_poll_reset(xpcs, dev);
251 #define xpcs_warn(__xpcs, __state, __args...) \
253 if ((__state)->link) \
254 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
257 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
258 struct phylink_link_state *state)
262 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
266 if (ret & MDIO_STAT1_FAULT) {
267 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
271 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
275 if (ret & MDIO_STAT2_RXFAULT)
276 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
277 if (ret & MDIO_STAT2_TXFAULT)
278 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
280 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
284 if (ret & DW_RXFIFO_ERR) {
285 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
289 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
293 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
294 xpcs_warn(xpcs, state, "Link is not locked!\n");
296 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
300 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
301 xpcs_warn(xpcs, state, "Link has errors!\n");
308 static int xpcs_read_link_c73(struct dw_xpcs *xpcs, bool an)
313 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
317 if (!(ret & MDIO_STAT1_LSTATUS))
321 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
325 if (!(ret & MDIO_STAT1_LSTATUS))
332 static int xpcs_get_max_usxgmii_speed(const unsigned long *supported)
334 int max = SPEED_UNKNOWN;
336 if (phylink_test(supported, 1000baseKX_Full))
338 if (phylink_test(supported, 2500baseX_Full))
340 if (phylink_test(supported, 10000baseKX4_Full))
342 if (phylink_test(supported, 10000baseKR_Full))
348 static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
354 speed_sel = DW_USXGMII_10;
357 speed_sel = DW_USXGMII_100;
360 speed_sel = DW_USXGMII_1000;
363 speed_sel = DW_USXGMII_2500;
366 speed_sel = DW_USXGMII_5000;
369 speed_sel = DW_USXGMII_10000;
372 /* Nothing to do here */
376 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
380 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
384 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
388 ret &= ~DW_USXGMII_SS_MASK;
389 ret |= speed_sel | DW_USXGMII_FULL;
391 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
395 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
399 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
406 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
409 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
410 const struct xpcs_compat *compat)
414 /* By default, in USXGMII mode XPCS operates at 10G baud and
415 * replicates data to achieve lower speeds. Hereby, in this
416 * default configuration we need to advertise all supported
417 * modes and not only the ones we want to use.
422 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
423 adv |= DW_C73_2500KX;
425 /* TODO: 5000baseKR */
427 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
433 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
434 adv |= DW_C73_1000KX;
435 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
436 adv |= DW_C73_10000KX4;
437 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
438 adv |= DW_C73_10000KR;
440 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
445 adv = DW_C73_AN_ADV_SF;
446 if (xpcs_linkmode_supported(compat, Pause))
448 if (xpcs_linkmode_supported(compat, Asym_Pause))
449 adv |= DW_C73_ASYM_PAUSE;
451 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
454 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
455 const struct xpcs_compat *compat)
459 ret = _xpcs_config_aneg_c73(xpcs, compat);
463 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
467 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
469 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
472 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
473 struct phylink_link_state *state,
474 const struct xpcs_compat *compat)
478 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
482 if (ret & MDIO_AN_STAT1_COMPLETE) {
483 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
487 /* Check if Aneg outcome is valid */
488 if (!(ret & DW_C73_AN_ADV_SF)) {
489 xpcs_config_aneg_c73(xpcs, compat);
499 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
500 struct phylink_link_state *state)
504 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
508 if (!(ret & MDIO_AN_STAT1_LPABLE)) {
509 phylink_clear(state->lp_advertising, Autoneg);
513 phylink_set(state->lp_advertising, Autoneg);
515 /* Clause 73 outcome */
516 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3);
520 if (ret & DW_C73_2500KX)
521 phylink_set(state->lp_advertising, 2500baseX_Full);
523 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2);
527 if (ret & DW_C73_1000KX)
528 phylink_set(state->lp_advertising, 1000baseKX_Full);
529 if (ret & DW_C73_10000KX4)
530 phylink_set(state->lp_advertising, 10000baseKX4_Full);
531 if (ret & DW_C73_10000KR)
532 phylink_set(state->lp_advertising, 10000baseKR_Full);
534 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
538 if (ret & DW_C73_PAUSE)
539 phylink_set(state->lp_advertising, Pause);
540 if (ret & DW_C73_ASYM_PAUSE)
541 phylink_set(state->lp_advertising, Asym_Pause);
543 linkmode_and(state->lp_advertising, state->lp_advertising,
548 static void xpcs_resolve_lpa_c73(struct dw_xpcs *xpcs,
549 struct phylink_link_state *state)
551 int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising);
553 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
554 state->speed = max_speed;
555 state->duplex = DUPLEX_FULL;
558 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
559 struct phylink_link_state *state)
561 unsigned long *adv = state->advertising;
562 int speed = SPEED_UNKNOWN;
565 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
566 int new_speed = SPEED_UNKNOWN;
569 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
570 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
571 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
572 new_speed = SPEED_25000;
574 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
575 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
576 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
577 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
578 new_speed = SPEED_40000;
580 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
581 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
582 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
583 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
584 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
585 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
586 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
587 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
588 new_speed = SPEED_50000;
590 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
591 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
592 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
593 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
594 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
595 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
596 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
597 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
598 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
599 new_speed = SPEED_100000;
605 if (new_speed > speed)
612 static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
613 struct phylink_link_state *state)
615 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
616 state->duplex = DUPLEX_FULL;
618 switch (state->interface) {
619 case PHY_INTERFACE_MODE_10GKR:
620 state->speed = SPEED_10000;
622 case PHY_INTERFACE_MODE_XLGMII:
623 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
626 state->speed = SPEED_UNKNOWN;
631 void xpcs_validate(struct dw_xpcs *xpcs, unsigned long *supported,
632 struct phylink_link_state *state)
634 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported);
635 const struct xpcs_compat *compat;
638 /* phylink expects us to report all supported modes with
639 * PHY_INTERFACE_MODE_NA, just don't limit the supported and
640 * advertising masks and exit.
642 if (state->interface == PHY_INTERFACE_MODE_NA)
645 bitmap_zero(xpcs_supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
647 compat = xpcs_find_compat(xpcs->id, state->interface);
649 /* Populate the supported link modes for this
653 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
654 set_bit(compat->supported[i], xpcs_supported);
656 linkmode_and(supported, supported, xpcs_supported);
657 linkmode_and(state->advertising, state->advertising, xpcs_supported);
659 EXPORT_SYMBOL_GPL(xpcs_validate);
661 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
667 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
668 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
669 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
670 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
672 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
675 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
676 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
677 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
678 DW_VR_MII_EEE_MULT_FACT_100NS);
681 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
685 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
689 ret |= DW_VR_MII_EEE_TRN_LPI;
690 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
692 EXPORT_SYMBOL_GPL(xpcs_config_eee);
694 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode)
698 /* For AN for C37 SGMII mode, the settings are :-
699 * 1) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
700 * 2) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
701 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
702 * 3) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
703 * speed/duplex mode change by HW after SGMII AN complete)
705 * Note: Since it is MAC side SGMII, there is no need to set
706 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
707 * PHY about the link state change after C28 AN is completed
708 * between PHY and Link Partner. There is also no need to
709 * trigger AN restart for MAC-side SGMII.
711 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
715 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
716 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
717 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
718 DW_VR_MII_PCS_MODE_MASK);
719 ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII <<
720 DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
721 DW_VR_MII_TX_CONFIG_MASK);
722 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
726 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
730 if (phylink_autoneg_inband(mode))
731 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
733 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
735 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
738 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
742 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
745 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
746 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
747 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
751 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
755 ret |= SGMII_SPEED_SS6;
756 ret &= ~SGMII_SPEED_SS13;
757 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
760 int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
763 const struct xpcs_compat *compat;
766 compat = xpcs_find_compat(xpcs->id, interface);
770 switch (compat->an_mode) {
772 if (phylink_autoneg_inband(mode)) {
773 ret = xpcs_config_aneg_c73(xpcs, compat);
778 case DW_AN_C37_SGMII:
779 ret = xpcs_config_aneg_c37_sgmii(xpcs, mode);
784 ret = xpcs_config_2500basex(xpcs);
792 if (compat->pma_config) {
793 ret = compat->pma_config(xpcs);
800 EXPORT_SYMBOL_GPL(xpcs_do_config);
802 static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode,
803 phy_interface_t interface,
804 const unsigned long *advertising,
805 bool permit_pause_to_mac)
807 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
809 return xpcs_do_config(xpcs, interface, mode);
812 static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
813 struct phylink_link_state *state,
814 const struct xpcs_compat *compat)
818 /* Link needs to be read first ... */
819 state->link = xpcs_read_link_c73(xpcs, state->an_enabled) > 0 ? 1 : 0;
821 /* ... and then we check the faults. */
822 ret = xpcs_read_fault_c73(xpcs, state);
824 ret = xpcs_soft_reset(xpcs, compat);
830 return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND);
833 if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
834 state->an_complete = true;
835 xpcs_read_lpa_c73(xpcs, state);
836 xpcs_resolve_lpa_c73(xpcs, state);
837 } else if (state->an_enabled) {
839 } else if (state->link) {
840 xpcs_resolve_pma(xpcs, state);
846 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
847 struct phylink_link_state *state)
851 /* Reset link_state */
853 state->speed = SPEED_UNKNOWN;
854 state->duplex = DUPLEX_UNKNOWN;
857 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
858 * status, speed and duplex.
860 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
864 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
869 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
870 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
871 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
872 state->speed = SPEED_1000;
873 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
874 state->speed = SPEED_100;
876 state->speed = SPEED_10;
878 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
879 state->duplex = DUPLEX_FULL;
881 state->duplex = DUPLEX_HALF;
887 static void xpcs_get_state(struct phylink_pcs *pcs,
888 struct phylink_link_state *state)
890 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
891 const struct xpcs_compat *compat;
894 compat = xpcs_find_compat(xpcs->id, state->interface);
898 switch (compat->an_mode) {
900 ret = xpcs_get_state_c73(xpcs, state, compat);
902 pr_err("xpcs_get_state_c73 returned %pe\n",
907 case DW_AN_C37_SGMII:
908 ret = xpcs_get_state_c37_sgmii(xpcs, state);
910 pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
919 static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode,
920 int speed, int duplex)
924 if (phylink_autoneg_inband(mode))
929 val = BMCR_SPEED1000;
941 if (duplex == DUPLEX_FULL)
942 val |= BMCR_FULLDPLX;
944 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
946 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
949 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
950 phy_interface_t interface, int speed, int duplex)
952 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
954 if (interface == PHY_INTERFACE_MODE_USXGMII)
955 return xpcs_config_usxgmii(xpcs, speed);
956 if (interface == PHY_INTERFACE_MODE_SGMII)
957 return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);
959 EXPORT_SYMBOL_GPL(xpcs_link_up);
961 static u32 xpcs_get_id(struct dw_xpcs *xpcs)
966 /* First, search C73 PCS using PCS MMD */
967 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
973 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
977 /* If Device IDs are not all zeros or all ones,
978 * we found C73 AN-type device
980 if ((id | ret) && (id | ret) != 0xffffffff)
983 /* Next, search C37 PCS using Vendor-Specific MII MMD */
984 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
990 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
994 /* If Device IDs are not all zeros, we found C37 AN-type device */
1001 static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1002 [DW_XPCS_USXGMII] = {
1003 .supported = xpcs_usxgmii_features,
1004 .interface = xpcs_usxgmii_interfaces,
1005 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1006 .an_mode = DW_AN_C73,
1009 .supported = xpcs_10gkr_features,
1010 .interface = xpcs_10gkr_interfaces,
1011 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1012 .an_mode = DW_AN_C73,
1014 [DW_XPCS_XLGMII] = {
1015 .supported = xpcs_xlgmii_features,
1016 .interface = xpcs_xlgmii_interfaces,
1017 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1018 .an_mode = DW_AN_C73,
1021 .supported = xpcs_sgmii_features,
1022 .interface = xpcs_sgmii_interfaces,
1023 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1024 .an_mode = DW_AN_C37_SGMII,
1026 [DW_XPCS_2500BASEX] = {
1027 .supported = xpcs_2500basex_features,
1028 .interface = xpcs_2500basex_interfaces,
1029 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
1030 .an_mode = DW_2500BASEX,
1034 static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1036 .supported = xpcs_sgmii_features,
1037 .interface = xpcs_sgmii_interfaces,
1038 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1039 .an_mode = DW_AN_C37_SGMII,
1040 .pma_config = nxp_sja1105_sgmii_pma_config,
1044 static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1046 .supported = xpcs_sgmii_features,
1047 .interface = xpcs_sgmii_interfaces,
1048 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1049 .an_mode = DW_AN_C37_SGMII,
1050 .pma_config = nxp_sja1110_sgmii_pma_config,
1052 [DW_XPCS_2500BASEX] = {
1053 .supported = xpcs_2500basex_features,
1054 .interface = xpcs_2500basex_interfaces,
1055 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1056 .an_mode = DW_2500BASEX,
1057 .pma_config = nxp_sja1110_2500basex_pma_config,
1061 static const struct xpcs_id xpcs_id_list[] = {
1063 .id = SYNOPSYS_XPCS_ID,
1064 .mask = SYNOPSYS_XPCS_MASK,
1065 .compat = synopsys_xpcs_compat,
1067 .id = NXP_SJA1105_XPCS_ID,
1068 .mask = SYNOPSYS_XPCS_MASK,
1069 .compat = nxp_sja1105_xpcs_compat,
1071 .id = NXP_SJA1110_XPCS_ID,
1072 .mask = SYNOPSYS_XPCS_MASK,
1073 .compat = nxp_sja1110_xpcs_compat,
1077 static const struct phylink_pcs_ops xpcs_phylink_ops = {
1078 .pcs_config = xpcs_config,
1079 .pcs_get_state = xpcs_get_state,
1080 .pcs_link_up = xpcs_link_up,
1083 struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1084 phy_interface_t interface)
1086 struct dw_xpcs *xpcs;
1090 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1094 xpcs->mdiodev = mdiodev;
1096 xpcs_id = xpcs_get_id(xpcs);
1098 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1099 const struct xpcs_id *entry = &xpcs_id_list[i];
1100 const struct xpcs_compat *compat;
1102 if ((xpcs_id & entry->mask) != entry->id)
1107 compat = xpcs_find_compat(entry, interface);
1113 xpcs->pcs.ops = &xpcs_phylink_ops;
1114 xpcs->pcs.poll = true;
1116 ret = xpcs_soft_reset(xpcs, compat);
1128 return ERR_PTR(ret);
1130 EXPORT_SYMBOL_GPL(xpcs_create);
1132 void xpcs_destroy(struct dw_xpcs *xpcs)
1136 EXPORT_SYMBOL_GPL(xpcs_destroy);
1138 MODULE_LICENSE("GPL v2");