2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
46 #include <linux/module.h>
47 #include <linux/kernel.h>
48 #include <linux/spinlock.h>
49 #include <linux/workqueue.h>
50 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
55 #include <asm/types.h>
56 #include <asm/pgtable.h>
57 #include <asm/system.h>
58 #include <asm/delay.h>
59 #include <asm/dma-mapping.h>
61 /* Checksum offload for Tx works for most packets, but
62 * fails if previous packet sent did not use hw csum
64 #define MV643XX_CHECKSUM_OFFLOAD_TX
66 #define MV643XX_TX_FAST_REFILL
70 * Number of RX / TX descriptors on RX / TX rings.
71 * Note that allocating RX descriptors is done by allocating the RX
72 * ring AND a preallocated RX buffers (skb's) for each descriptor.
73 * The TX descriptors only allocates the TX descriptors ring,
74 * with no pre allocated TX buffers (skb's are allocated by higher layers.
77 /* Default TX ring size is 1000 descriptors */
78 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
80 /* Default RX ring size is 400 descriptors */
81 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
83 #define MV643XX_TX_COAL 100
85 #define MV643XX_RX_COAL 100
88 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
89 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
91 #define MAX_DESCS_PER_SKB 1
94 #define ETH_VLAN_HLEN 4
96 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
97 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
98 ETH_VLAN_HLEN + ETH_FCS_LEN)
99 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
100 dma_get_cache_alignment())
103 * Registers shared between all ports.
105 #define PHY_ADDR_REG 0x0000
106 #define SMI_REG 0x0004
109 * Per-port registers.
111 #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
112 #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
113 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
114 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
115 #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
116 #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
117 #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
118 #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
119 #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
120 #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
121 #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
122 #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
123 #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
124 #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
125 #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
126 #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
127 #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
128 #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
129 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
130 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
131 #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
133 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
134 #define UNICAST_NORMAL_MODE (0 << 0)
135 #define UNICAST_PROMISCUOUS_MODE (1 << 0)
136 #define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
137 #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
138 #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
139 #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
140 #define RECEIVE_BC_IF_IP (0 << 8)
141 #define REJECT_BC_IF_IP (1 << 8)
142 #define RECEIVE_BC_IF_ARP (0 << 9)
143 #define REJECT_BC_IF_ARP (1 << 9)
144 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
145 #define CAPTURE_TCP_FRAMES_DIS (0 << 14)
146 #define CAPTURE_TCP_FRAMES_EN (1 << 14)
147 #define CAPTURE_UDP_FRAMES_DIS (0 << 15)
148 #define CAPTURE_UDP_FRAMES_EN (1 << 15)
149 #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
150 #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
151 #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
153 #define PORT_CONFIG_DEFAULT_VALUE \
154 UNICAST_NORMAL_MODE | \
155 DEFAULT_RX_QUEUE(0) | \
156 DEFAULT_RX_ARP_QUEUE(0) | \
157 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
159 RECEIVE_BC_IF_ARP | \
160 CAPTURE_TCP_FRAMES_DIS | \
161 CAPTURE_UDP_FRAMES_DIS | \
162 DEFAULT_RX_TCP_QUEUE(0) | \
163 DEFAULT_RX_UDP_QUEUE(0) | \
164 DEFAULT_RX_BPDU_QUEUE(0)
166 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
167 #define CLASSIFY_EN (1 << 0)
168 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
169 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
170 #define PARTITION_DISABLE (0 << 2)
171 #define PARTITION_ENABLE (1 << 2)
173 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
174 SPAN_BPDU_PACKETS_AS_NORMAL | \
177 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
178 #define RIFB (1 << 0)
179 #define RX_BURST_SIZE_1_64BIT (0 << 1)
180 #define RX_BURST_SIZE_2_64BIT (1 << 1)
181 #define RX_BURST_SIZE_4_64BIT (2 << 1)
182 #define RX_BURST_SIZE_8_64BIT (3 << 1)
183 #define RX_BURST_SIZE_16_64BIT (4 << 1)
184 #define BLM_RX_NO_SWAP (1 << 4)
185 #define BLM_RX_BYTE_SWAP (0 << 4)
186 #define BLM_TX_NO_SWAP (1 << 5)
187 #define BLM_TX_BYTE_SWAP (0 << 5)
188 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
189 #define DESCRIPTORS_NO_SWAP (0 << 6)
190 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
191 #define TX_BURST_SIZE_1_64BIT (0 << 22)
192 #define TX_BURST_SIZE_2_64BIT (1 << 22)
193 #define TX_BURST_SIZE_4_64BIT (2 << 22)
194 #define TX_BURST_SIZE_8_64BIT (3 << 22)
195 #define TX_BURST_SIZE_16_64BIT (4 << 22)
197 #if defined(__BIG_ENDIAN)
198 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
199 RX_BURST_SIZE_4_64BIT | \
201 TX_BURST_SIZE_4_64BIT
202 #elif defined(__LITTLE_ENDIAN)
203 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
204 RX_BURST_SIZE_4_64BIT | \
208 TX_BURST_SIZE_4_64BIT
210 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
213 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
214 #define SERIAL_PORT_DISABLE (0 << 0)
215 #define SERIAL_PORT_ENABLE (1 << 0)
216 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
217 #define FORCE_LINK_PASS (1 << 1)
218 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
219 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
220 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
221 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
222 #define ADV_NO_FLOW_CTRL (0 << 4)
223 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
224 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
225 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
226 #define FORCE_BP_MODE_NO_JAM (0 << 7)
227 #define FORCE_BP_MODE_JAM_TX (1 << 7)
228 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
229 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
230 #define FORCE_LINK_FAIL (0 << 10)
231 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
232 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
233 #define RETRANSMIT_FOREVER (1 << 11)
234 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
235 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
236 #define DTE_ADV_0 (0 << 14)
237 #define DTE_ADV_1 (1 << 14)
238 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
239 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
240 #define AUTO_NEG_NO_CHANGE (0 << 16)
241 #define RESTART_AUTO_NEG (1 << 16)
242 #define MAX_RX_PACKET_1518BYTE (0 << 17)
243 #define MAX_RX_PACKET_1522BYTE (1 << 17)
244 #define MAX_RX_PACKET_1552BYTE (2 << 17)
245 #define MAX_RX_PACKET_9022BYTE (3 << 17)
246 #define MAX_RX_PACKET_9192BYTE (4 << 17)
247 #define MAX_RX_PACKET_9700BYTE (5 << 17)
248 #define MAX_RX_PACKET_MASK (7 << 17)
249 #define CLR_EXT_LOOPBACK (0 << 20)
250 #define SET_EXT_LOOPBACK (1 << 20)
251 #define SET_HALF_DUPLEX_MODE (0 << 21)
252 #define SET_FULL_DUPLEX_MODE (1 << 21)
253 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
254 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
255 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
256 #define SET_GMII_SPEED_TO_1000 (1 << 23)
257 #define SET_MII_SPEED_TO_10 (0 << 24)
258 #define SET_MII_SPEED_TO_100 (1 << 24)
260 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
261 DO_NOT_FORCE_LINK_PASS | \
262 ENABLE_AUTO_NEG_FOR_DUPLX | \
263 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
264 ADV_SYMMETRIC_FLOW_CTRL | \
265 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
266 FORCE_BP_MODE_NO_JAM | \
267 (1 << 9) /* reserved */ | \
268 DO_NOT_FORCE_LINK_FAIL | \
269 RETRANSMIT_16_ATTEMPTS | \
270 ENABLE_AUTO_NEG_SPEED_GMII | \
272 DISABLE_AUTO_NEG_BYPASS | \
273 AUTO_NEG_NO_CHANGE | \
274 MAX_RX_PACKET_9700BYTE | \
276 SET_FULL_DUPLEX_MODE | \
277 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
279 /* These macros describe Ethernet Serial Status reg (PSR) bits */
280 #define PORT_STATUS_MODE_10_BIT (1 << 0)
281 #define PORT_STATUS_LINK_UP (1 << 1)
282 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
283 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
284 #define PORT_STATUS_GMII_1000 (1 << 4)
285 #define PORT_STATUS_MII_100 (1 << 5)
286 /* PSR bit 6 is undocumented */
287 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
288 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
289 #define PORT_STATUS_PARTITION (1 << 9)
290 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
291 /* PSR bits 11-31 are reserved */
293 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
294 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
298 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
299 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
301 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
302 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
303 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
304 #define ETH_INT_CAUSE_EXT 0x00000002
305 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
307 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
308 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
309 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
310 #define ETH_INT_CAUSE_PHY 0x00010000
311 #define ETH_INT_CAUSE_STATE 0x00100000
312 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
315 #define ETH_INT_MASK_ALL 0x00000000
316 #define ETH_INT_MASK_ALL_EXT 0x00000000
318 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
319 #define PHY_WAIT_MICRO_SECONDS 10
321 /* Buffer offset from buffer pointer */
322 #define RX_BUF_OFFSET 0x2
324 /* Gigabit Ethernet Unit Global Registers */
326 /* MIB Counters register definitions */
327 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
328 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
329 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
330 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
331 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
332 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
333 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
334 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
335 #define ETH_MIB_FRAMES_64_OCTETS 0x20
336 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
337 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
338 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
339 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
340 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
341 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
342 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
343 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
344 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
345 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
346 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
347 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
348 #define ETH_MIB_FC_SENT 0x54
349 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
350 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
351 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
352 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
353 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
354 #define ETH_MIB_JABBER_RECEIVED 0x6c
355 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
356 #define ETH_MIB_BAD_CRC_EVENT 0x74
357 #define ETH_MIB_COLLISION 0x78
358 #define ETH_MIB_LATE_COLLISION 0x7c
360 /* Port serial status reg (PSR) */
361 #define ETH_INTERFACE_PCM 0x00000001
362 #define ETH_LINK_IS_UP 0x00000002
363 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
364 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
365 #define ETH_GMII_SPEED_1000 0x00000010
366 #define ETH_MII_SPEED_100 0x00000020
367 #define ETH_TX_IN_PROGRESS 0x00000080
368 #define ETH_BYPASS_ACTIVE 0x00000100
369 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
370 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
373 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
374 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
375 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
376 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
378 /* Interrupt Cause Register Bit Definitions */
380 /* SDMA command status fields macros */
382 /* Tx & Rx descriptors status */
383 #define ETH_ERROR_SUMMARY 0x00000001
385 /* Tx & Rx descriptors command */
386 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
388 /* Tx descriptors status */
389 #define ETH_LC_ERROR 0
390 #define ETH_UR_ERROR 0x00000002
391 #define ETH_RL_ERROR 0x00000004
392 #define ETH_LLC_SNAP_FORMAT 0x00000200
394 /* Rx descriptors status */
395 #define ETH_OVERRUN_ERROR 0x00000002
396 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
397 #define ETH_RESOURCE_ERROR 0x00000006
398 #define ETH_VLAN_TAGGED 0x00080000
399 #define ETH_BPDU_FRAME 0x00100000
400 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
401 #define ETH_OTHER_FRAME_TYPE 0x00400000
402 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
403 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
404 #define ETH_FRAME_HEADER_OK 0x02000000
405 #define ETH_RX_LAST_DESC 0x04000000
406 #define ETH_RX_FIRST_DESC 0x08000000
407 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
408 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
409 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
411 /* Rx descriptors byte count */
412 #define ETH_FRAME_FRAGMENTED 0x00000004
414 /* Tx descriptors command */
415 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
416 #define ETH_FRAME_SET_TO_VLAN 0x00008000
417 #define ETH_UDP_FRAME 0x00010000
418 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
419 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
420 #define ETH_ZERO_PADDING 0x00080000
421 #define ETH_TX_LAST_DESC 0x00100000
422 #define ETH_TX_FIRST_DESC 0x00200000
423 #define ETH_GEN_CRC 0x00400000
424 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
425 #define ETH_AUTO_MODE 0x40000000
427 #define ETH_TX_IHL_SHIFT 11
431 typedef enum _eth_func_ret_status {
432 ETH_OK, /* Returned as expected. */
433 ETH_ERROR, /* Fundamental error. */
434 ETH_RETRY, /* Could not process request. Try later.*/
435 ETH_END_OF_JOB, /* Ring has nothing to process. */
436 ETH_QUEUE_FULL, /* Ring resource error. */
437 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
438 } ETH_FUNC_RET_STATUS;
440 typedef enum _eth_target {
448 /* These are for big-endian machines. Little endian needs different
451 #if defined(__BIG_ENDIAN)
453 u16 byte_cnt; /* Descriptor buffer byte count */
454 u16 buf_size; /* Buffer size */
455 u32 cmd_sts; /* Descriptor command status */
456 u32 next_desc_ptr; /* Next descriptor pointer */
457 u32 buf_ptr; /* Descriptor buffer pointer */
461 u16 byte_cnt; /* buffer byte count */
462 u16 l4i_chk; /* CPU provided TCP checksum */
463 u32 cmd_sts; /* Command/status field */
464 u32 next_desc_ptr; /* Pointer to next descriptor */
465 u32 buf_ptr; /* pointer to buffer for this descriptor*/
467 #elif defined(__LITTLE_ENDIAN)
469 u32 cmd_sts; /* Descriptor command status */
470 u16 buf_size; /* Buffer size */
471 u16 byte_cnt; /* Descriptor buffer byte count */
472 u32 buf_ptr; /* Descriptor buffer pointer */
473 u32 next_desc_ptr; /* Next descriptor pointer */
477 u32 cmd_sts; /* Command/status field */
478 u16 l4i_chk; /* CPU provided TCP checksum */
479 u16 byte_cnt; /* buffer byte count */
480 u32 buf_ptr; /* pointer to buffer for this descriptor*/
481 u32 next_desc_ptr; /* Pointer to next descriptor */
484 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
487 /* Unified struct for Rx and Tx operations. The user is not required to */
488 /* be familier with neither Tx nor Rx descriptors. */
490 unsigned short byte_cnt; /* Descriptor buffer byte count */
491 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
492 unsigned int cmd_sts; /* Descriptor command status */
493 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
494 struct sk_buff *return_info; /* User resource return information */
497 /* Ethernet port specific information */
498 struct mv643xx_mib_counters {
499 u64 good_octets_received;
500 u32 bad_octets_received;
501 u32 internal_mac_transmit_err;
502 u32 good_frames_received;
503 u32 bad_frames_received;
504 u32 broadcast_frames_received;
505 u32 multicast_frames_received;
506 u32 frames_64_octets;
507 u32 frames_65_to_127_octets;
508 u32 frames_128_to_255_octets;
509 u32 frames_256_to_511_octets;
510 u32 frames_512_to_1023_octets;
511 u32 frames_1024_to_max_octets;
512 u64 good_octets_sent;
513 u32 good_frames_sent;
514 u32 excessive_collision;
515 u32 multicast_frames_sent;
516 u32 broadcast_frames_sent;
517 u32 unrec_mac_control_received;
519 u32 good_fc_received;
521 u32 undersize_received;
522 u32 fragments_received;
523 u32 oversize_received;
525 u32 mac_receive_error;
531 struct mv643xx_private {
532 int port_num; /* User Ethernet port number */
534 u32 rx_sram_addr; /* Base address of rx sram area */
535 u32 rx_sram_size; /* Size of rx sram area */
536 u32 tx_sram_addr; /* Base address of tx sram area */
537 u32 tx_sram_size; /* Size of tx sram area */
539 int rx_resource_err; /* Rx ring resource error flag */
541 /* Tx/Rx rings managment indexes fields. For driver use */
543 /* Next available and first returning Rx resource */
544 int rx_curr_desc_q, rx_used_desc_q;
546 /* Next available and first returning Tx resource */
547 int tx_curr_desc_q, tx_used_desc_q;
549 #ifdef MV643XX_TX_FAST_REFILL
550 u32 tx_clean_threshold;
553 struct eth_rx_desc *p_rx_desc_area;
554 dma_addr_t rx_desc_dma;
555 int rx_desc_area_size;
556 struct sk_buff **rx_skb;
558 struct eth_tx_desc *p_tx_desc_area;
559 dma_addr_t tx_desc_dma;
560 int tx_desc_area_size;
561 struct sk_buff **tx_skb;
563 struct work_struct tx_timeout_task;
565 struct net_device *dev;
566 struct napi_struct napi;
567 struct net_device_stats stats;
568 struct mv643xx_mib_counters mib_counters;
570 /* Size of Tx Ring per queue */
572 /* Number of tx descriptors in use */
574 /* Size of Rx Ring per queue */
576 /* Number of rx descriptors in use */
580 * Used in case RX Ring is empty, which can be caused when
581 * system does not have resources (skb's)
583 struct timer_list timeout;
587 struct mii_if_info mii;
590 /* Static function declarations */
591 static void eth_port_init(struct mv643xx_private *mp);
592 static void eth_port_reset(unsigned int eth_port_num);
593 static void eth_port_start(struct net_device *dev);
595 static void ethernet_phy_reset(unsigned int eth_port_num);
597 static void eth_port_write_smi_reg(unsigned int eth_port_num,
598 unsigned int phy_reg, unsigned int value);
600 static void eth_port_read_smi_reg(unsigned int eth_port_num,
601 unsigned int phy_reg, unsigned int *value);
603 static void eth_clear_mib_counters(unsigned int eth_port_num);
605 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
606 struct pkt_info *p_pkt_info);
607 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
608 struct pkt_info *p_pkt_info);
610 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr);
611 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr);
612 static void eth_port_set_multicast_list(struct net_device *);
613 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
614 unsigned int queues);
615 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
616 unsigned int queues);
617 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
618 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
619 static int mv643xx_eth_open(struct net_device *);
620 static int mv643xx_eth_stop(struct net_device *);
621 static int mv643xx_eth_change_mtu(struct net_device *, int);
622 static void eth_port_init_mac_tables(unsigned int eth_port_num);
624 static int mv643xx_poll(struct napi_struct *napi, int budget);
626 static int ethernet_phy_get(unsigned int eth_port_num);
627 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
628 static int ethernet_phy_detect(unsigned int eth_port_num);
629 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
630 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
631 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
632 static const struct ethtool_ops mv643xx_ethtool_ops;
634 static char mv643xx_driver_name[] = "mv643xx_eth";
635 static char mv643xx_driver_version[] = "1.0";
637 static void __iomem *mv643xx_eth_base;
639 /* used to protect SMI_REG, which is shared across ports */
640 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
642 static inline u32 mv_read(int offset)
644 return readl(mv643xx_eth_base + offset);
647 static inline void mv_write(int offset, u32 data)
649 writel(data, mv643xx_eth_base + offset);
653 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
655 * Input : pointer to ethernet interface network device structure
657 * Output : 0 upon success, -EINVAL upon failure
659 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
661 if ((new_mtu > 9500) || (new_mtu < 64))
666 * Stop then re-open the interface. This will allocate RX skb's with
668 * There is a possible danger that the open will not successed, due
669 * to memory is full, which might fail the open function.
671 if (netif_running(dev)) {
672 mv643xx_eth_stop(dev);
673 if (mv643xx_eth_open(dev))
675 "%s: Fatal error on opening device\n",
683 * mv643xx_eth_rx_refill_descs
685 * Fills / refills RX queue on a certain gigabit ethernet port
687 * Input : pointer to ethernet interface network device structure
690 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
692 struct mv643xx_private *mp = netdev_priv(dev);
693 struct pkt_info pkt_info;
697 while (mp->rx_desc_count < mp->rx_ring_size) {
698 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
702 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
704 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
705 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
706 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
707 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
708 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
709 pkt_info.return_info = skb;
710 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
712 "%s: Error allocating RX Ring\n", dev->name);
715 skb_reserve(skb, ETH_HW_IP_ALIGN);
718 * If RX ring is empty of SKB, set a timer to try allocating
719 * again at a later time.
721 if (mp->rx_desc_count == 0) {
722 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
723 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
724 add_timer(&mp->timeout);
729 * mv643xx_eth_rx_refill_descs_timer_wrapper
731 * Timer routine to wake up RX queue filling task. This function is
732 * used only in case the RX queue is empty, and all alloc_skb has
733 * failed (due to out of memory event).
735 * Input : pointer to ethernet interface network device structure
738 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
740 mv643xx_eth_rx_refill_descs((struct net_device *)data);
744 * mv643xx_eth_update_mac_address
746 * Update the MAC address of the port in the address table
748 * Input : pointer to ethernet interface network device structure
751 static void mv643xx_eth_update_mac_address(struct net_device *dev)
753 struct mv643xx_private *mp = netdev_priv(dev);
754 unsigned int port_num = mp->port_num;
756 eth_port_init_mac_tables(port_num);
757 eth_port_uc_addr_set(port_num, dev->dev_addr);
761 * mv643xx_eth_set_rx_mode
763 * Change from promiscuos to regular rx mode
765 * Input : pointer to ethernet interface network device structure
768 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
770 struct mv643xx_private *mp = netdev_priv(dev);
773 config_reg = mv_read(PORT_CONFIG_REG(mp->port_num));
774 if (dev->flags & IFF_PROMISC)
775 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
777 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
778 mv_write(PORT_CONFIG_REG(mp->port_num), config_reg);
780 eth_port_set_multicast_list(dev);
784 * mv643xx_eth_set_mac_address
786 * Change the interface's mac address.
787 * No special hardware thing should be done because interface is always
788 * put in promiscuous mode.
790 * Input : pointer to ethernet interface network device structure and
791 * a pointer to the designated entry to be added to the cache.
792 * Output : zero upon success, negative upon failure
794 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
798 for (i = 0; i < 6; i++)
799 /* +2 is for the offset of the HW addr type */
800 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
801 mv643xx_eth_update_mac_address(dev);
806 * mv643xx_eth_tx_timeout
808 * Called upon a timeout on transmitting a packet
810 * Input : pointer to ethernet interface network device structure.
813 static void mv643xx_eth_tx_timeout(struct net_device *dev)
815 struct mv643xx_private *mp = netdev_priv(dev);
817 printk(KERN_INFO "%s: TX timeout ", dev->name);
819 /* Do the reset outside of interrupt context */
820 schedule_work(&mp->tx_timeout_task);
824 * mv643xx_eth_tx_timeout_task
826 * Actual routine to reset the adapter when a timeout on Tx has occurred
828 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
830 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
832 struct net_device *dev = mp->mii.dev; /* yuck */
834 if (!netif_running(dev))
837 netif_stop_queue(dev);
839 eth_port_reset(mp->port_num);
842 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
843 netif_wake_queue(dev);
847 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
849 * If force is non-zero, frees uncompleted descriptors as well
851 int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
853 struct mv643xx_private *mp = netdev_priv(dev);
854 struct eth_tx_desc *desc;
863 while (mp->tx_desc_count > 0) {
864 spin_lock_irqsave(&mp->lock, flags);
866 /* tx_desc_count might have changed before acquiring the lock */
867 if (mp->tx_desc_count <= 0) {
868 spin_unlock_irqrestore(&mp->lock, flags);
872 tx_index = mp->tx_used_desc_q;
873 desc = &mp->p_tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
876 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
877 spin_unlock_irqrestore(&mp->lock, flags);
881 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
884 addr = desc->buf_ptr;
885 count = desc->byte_cnt;
886 skb = mp->tx_skb[tx_index];
888 mp->tx_skb[tx_index] = NULL;
890 if (cmd_sts & ETH_ERROR_SUMMARY) {
891 printk("%s: Error in TX\n", dev->name);
892 dev->stats.tx_errors++;
895 spin_unlock_irqrestore(&mp->lock, flags);
897 if (cmd_sts & ETH_TX_FIRST_DESC)
898 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
900 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
903 dev_kfree_skb_irq(skb);
911 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
913 struct mv643xx_private *mp = netdev_priv(dev);
915 if (mv643xx_eth_free_tx_descs(dev, 0) &&
916 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
917 netif_wake_queue(dev);
920 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
922 mv643xx_eth_free_tx_descs(dev, 1);
926 * mv643xx_eth_receive
928 * This function is forward packets that are received from the port's
929 * queues toward kernel core or FastRoute them to another interface.
931 * Input : dev - a pointer to the required interface
932 * max - maximum number to receive (0 means unlimted)
934 * Output : number of served packets
936 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
938 struct mv643xx_private *mp = netdev_priv(dev);
939 struct net_device_stats *stats = &dev->stats;
940 unsigned int received_packets = 0;
942 struct pkt_info pkt_info;
944 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
945 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
952 * Note byte count includes 4 byte CRC count
955 stats->rx_bytes += pkt_info.byte_cnt;
956 skb = pkt_info.return_info;
958 * In case received a packet without first / last bits on OR
959 * the error summary bit is on, the packets needs to be dropeed.
961 if (((pkt_info.cmd_sts
962 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
963 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
964 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
966 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
967 ETH_RX_LAST_DESC)) !=
968 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
971 "%s: Received packet spread "
972 "on multiple descriptors\n",
975 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
978 dev_kfree_skb_irq(skb);
981 * The -4 is for the CRC in the trailer of the
984 skb_put(skb, pkt_info.byte_cnt - 4);
986 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
987 skb->ip_summed = CHECKSUM_UNNECESSARY;
989 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
991 skb->protocol = eth_type_trans(skb, dev);
993 netif_receive_skb(skb);
998 dev->last_rx = jiffies;
1000 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1002 return received_packets;
1005 /* Set the mv643xx port configuration register for the speed/duplex mode. */
1006 static void mv643xx_eth_update_pscr(struct net_device *dev,
1007 struct ethtool_cmd *ecmd)
1009 struct mv643xx_private *mp = netdev_priv(dev);
1010 int port_num = mp->port_num;
1012 unsigned int queues;
1014 o_pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
1017 /* clear speed, duplex and rx buffer size fields */
1018 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1019 SET_GMII_SPEED_TO_1000 |
1020 SET_FULL_DUPLEX_MODE |
1021 MAX_RX_PACKET_MASK);
1023 if (ecmd->duplex == DUPLEX_FULL)
1024 n_pscr |= SET_FULL_DUPLEX_MODE;
1026 if (ecmd->speed == SPEED_1000)
1027 n_pscr |= SET_GMII_SPEED_TO_1000 |
1028 MAX_RX_PACKET_9700BYTE;
1030 if (ecmd->speed == SPEED_100)
1031 n_pscr |= SET_MII_SPEED_TO_100;
1032 n_pscr |= MAX_RX_PACKET_1522BYTE;
1035 if (n_pscr != o_pscr) {
1036 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1037 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1039 queues = mv643xx_eth_port_disable_tx(port_num);
1041 o_pscr &= ~SERIAL_PORT_ENABLE;
1042 mv_write(PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
1043 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1044 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1046 mv643xx_eth_port_enable_tx(port_num, queues);
1052 * mv643xx_eth_int_handler
1054 * Main interrupt handler for the gigbit ethernet ports
1056 * Input : irq - irq number (not used)
1057 * dev_id - a pointer to the required interface's data structure
1062 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1064 struct net_device *dev = (struct net_device *)dev_id;
1065 struct mv643xx_private *mp = netdev_priv(dev);
1066 u32 eth_int_cause, eth_int_cause_ext = 0;
1067 unsigned int port_num = mp->port_num;
1069 /* Read interrupt cause registers */
1070 eth_int_cause = mv_read(INTERRUPT_CAUSE_REG(port_num)) &
1072 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1073 eth_int_cause_ext = mv_read(
1074 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
1075 ETH_INT_UNMASK_ALL_EXT;
1076 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num),
1077 ~eth_int_cause_ext);
1080 /* PHY status changed */
1081 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
1082 struct ethtool_cmd cmd;
1084 if (mii_link_ok(&mp->mii)) {
1085 mii_ethtool_gset(&mp->mii, &cmd);
1086 mv643xx_eth_update_pscr(dev, &cmd);
1087 mv643xx_eth_port_enable_tx(port_num,
1088 ETH_TX_QUEUES_ENABLED);
1089 if (!netif_carrier_ok(dev)) {
1090 netif_carrier_on(dev);
1091 if (mp->tx_ring_size - mp->tx_desc_count >=
1093 netif_wake_queue(dev);
1095 } else if (netif_carrier_ok(dev)) {
1096 netif_stop_queue(dev);
1097 netif_carrier_off(dev);
1102 if (eth_int_cause & ETH_INT_CAUSE_RX) {
1103 /* schedule the NAPI poll routine to maintain port */
1104 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1106 /* wait for previous write to complete */
1107 mv_read(INTERRUPT_MASK_REG(port_num));
1109 netif_rx_schedule(dev, &mp->napi);
1112 if (eth_int_cause & ETH_INT_CAUSE_RX)
1113 mv643xx_eth_receive_queue(dev, INT_MAX);
1115 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
1116 mv643xx_eth_free_completed_tx_descs(dev);
1119 * If no real interrupt occured, exit.
1120 * This can happen when using gigE interrupt coalescing mechanism.
1122 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
1131 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1134 * This routine sets the RX coalescing interrupt mechanism parameter.
1135 * This parameter is a timeout counter, that counts in 64 t_clk
1136 * chunks ; that when timeout event occurs a maskable interrupt
1138 * The parameter is calculated using the tClk of the MV-643xx chip
1139 * , and the required delay of the interrupt in usec.
1142 * unsigned int eth_port_num Ethernet port number
1143 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1144 * unsigned int delay Delay in usec
1147 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1150 * The interrupt coalescing value set in the gigE port.
1153 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
1154 unsigned int t_clk, unsigned int delay)
1156 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
1158 /* Set RX Coalescing mechanism */
1159 mv_write(SDMA_CONFIG_REG(eth_port_num),
1160 ((coal & 0x3fff) << 8) |
1161 (mv_read(SDMA_CONFIG_REG(eth_port_num))
1169 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
1172 * This routine sets the TX coalescing interrupt mechanism parameter.
1173 * This parameter is a timeout counter, that counts in 64 t_clk
1174 * chunks ; that when timeout event occurs a maskable interrupt
1176 * The parameter is calculated using the t_cLK frequency of the
1177 * MV-643xx chip and the required delay in the interrupt in uSec
1180 * unsigned int eth_port_num Ethernet port number
1181 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1182 * unsigned int delay Delay in uSeconds
1185 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1188 * The interrupt coalescing value set in the gigE port.
1191 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
1192 unsigned int t_clk, unsigned int delay)
1195 coal = ((t_clk / 1000000) * delay) / 64;
1196 /* Set TX Coalescing mechanism */
1197 mv_write(TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), coal << 4);
1202 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1205 * This function prepares a Rx chained list of descriptors and packet
1206 * buffers in a form of a ring. The routine must be called after port
1207 * initialization routine and before port start routine.
1208 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1209 * devices in the system (i.e. DRAM). This function uses the ethernet
1210 * struct 'virtual to physical' routine (set by the user) to set the ring
1211 * with physical addresses.
1214 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1217 * The routine updates the Ethernet port control struct with information
1218 * regarding the Rx descriptors and buffers.
1223 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1225 volatile struct eth_rx_desc *p_rx_desc;
1226 int rx_desc_num = mp->rx_ring_size;
1229 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1230 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
1231 for (i = 0; i < rx_desc_num; i++) {
1232 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1233 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
1236 /* Save Rx desc pointer to driver struct. */
1237 mp->rx_curr_desc_q = 0;
1238 mp->rx_used_desc_q = 0;
1240 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1244 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1247 * This function prepares a Tx chained list of descriptors and packet
1248 * buffers in a form of a ring. The routine must be called after port
1249 * initialization routine and before port start routine.
1250 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1251 * devices in the system (i.e. DRAM). This function uses the ethernet
1252 * struct 'virtual to physical' routine (set by the user) to set the ring
1253 * with physical addresses.
1256 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1259 * The routine updates the Ethernet port control struct with information
1260 * regarding the Tx descriptors and buffers.
1265 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1267 int tx_desc_num = mp->tx_ring_size;
1268 struct eth_tx_desc *p_tx_desc;
1271 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1272 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
1273 for (i = 0; i < tx_desc_num; i++) {
1274 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1275 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
1278 mp->tx_curr_desc_q = 0;
1279 mp->tx_used_desc_q = 0;
1281 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1284 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1286 struct mv643xx_private *mp = netdev_priv(dev);
1289 spin_lock_irq(&mp->lock);
1290 err = mii_ethtool_sset(&mp->mii, cmd);
1291 spin_unlock_irq(&mp->lock);
1296 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1298 struct mv643xx_private *mp = netdev_priv(dev);
1301 spin_lock_irq(&mp->lock);
1302 err = mii_ethtool_gset(&mp->mii, cmd);
1303 spin_unlock_irq(&mp->lock);
1305 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1306 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1307 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1315 * This function is called when openning the network device. The function
1316 * should initialize all the hardware, initialize cyclic Rx/Tx
1317 * descriptors chain and buffers and allocate an IRQ to the network
1320 * Input : a pointer to the network device structure
1322 * Output : zero of success , nonzero if fails.
1325 static int mv643xx_eth_open(struct net_device *dev)
1327 struct mv643xx_private *mp = netdev_priv(dev);
1328 unsigned int port_num = mp->port_num;
1332 /* Clear any pending ethernet port interrupts */
1333 mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
1334 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1335 /* wait for previous write to complete */
1336 mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num));
1338 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1339 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1341 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
1348 memset(&mp->timeout, 0, sizeof(struct timer_list));
1349 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1350 mp->timeout.data = (unsigned long)dev;
1352 /* Allocate RX and TX skb rings */
1353 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1356 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1360 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1363 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1365 goto out_free_rx_skb;
1368 /* Allocate TX ring */
1369 mp->tx_desc_count = 0;
1370 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
1371 mp->tx_desc_area_size = size;
1373 if (mp->tx_sram_size) {
1374 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
1376 mp->tx_desc_dma = mp->tx_sram_addr;
1378 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
1382 if (!mp->p_tx_desc_area) {
1383 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1386 goto out_free_tx_skb;
1388 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
1389 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
1391 ether_init_tx_desc_ring(mp);
1393 /* Allocate RX ring */
1394 mp->rx_desc_count = 0;
1395 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
1396 mp->rx_desc_area_size = size;
1398 if (mp->rx_sram_size) {
1399 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
1401 mp->rx_desc_dma = mp->rx_sram_addr;
1403 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
1407 if (!mp->p_rx_desc_area) {
1408 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1410 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1412 if (mp->rx_sram_size)
1413 iounmap(mp->p_tx_desc_area);
1415 dma_free_coherent(NULL, mp->tx_desc_area_size,
1416 mp->p_tx_desc_area, mp->tx_desc_dma);
1418 goto out_free_tx_skb;
1420 memset((void *)mp->p_rx_desc_area, 0, size);
1422 ether_init_rx_desc_ring(mp);
1424 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1427 napi_enable(&mp->napi);
1430 eth_port_start(dev);
1432 /* Interrupt Coalescing */
1436 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
1440 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
1442 /* Unmask phy and link status changes interrupts */
1443 mv_write(INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
1445 /* Unmask RX buffer and TX end interrupt */
1446 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1455 free_irq(dev->irq, dev);
1460 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1462 struct mv643xx_private *mp = netdev_priv(dev);
1464 /* Stop Tx Queues */
1465 mv643xx_eth_port_disable_tx(mp->port_num);
1467 /* Free outstanding skb's on TX ring */
1468 mv643xx_eth_free_all_tx_descs(dev);
1470 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1473 if (mp->tx_sram_size)
1474 iounmap(mp->p_tx_desc_area);
1476 dma_free_coherent(NULL, mp->tx_desc_area_size,
1477 mp->p_tx_desc_area, mp->tx_desc_dma);
1480 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1482 struct mv643xx_private *mp = netdev_priv(dev);
1483 unsigned int port_num = mp->port_num;
1486 /* Stop RX Queues */
1487 mv643xx_eth_port_disable_rx(port_num);
1489 /* Free preallocated skb's on RX rings */
1490 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1491 if (mp->rx_skb[curr]) {
1492 dev_kfree_skb(mp->rx_skb[curr]);
1493 mp->rx_desc_count--;
1497 if (mp->rx_desc_count)
1499 "%s: Error in freeing Rx Ring. %d skb's still"
1500 " stuck in RX Ring - ignoring them\n", dev->name,
1503 if (mp->rx_sram_size)
1504 iounmap(mp->p_rx_desc_area);
1506 dma_free_coherent(NULL, mp->rx_desc_area_size,
1507 mp->p_rx_desc_area, mp->rx_desc_dma);
1513 * This function is used when closing the network device.
1514 * It updates the hardware,
1515 * release all memory that holds buffers and descriptors and release the IRQ.
1516 * Input : a pointer to the device structure
1517 * Output : zero if success , nonzero if fails
1520 static int mv643xx_eth_stop(struct net_device *dev)
1522 struct mv643xx_private *mp = netdev_priv(dev);
1523 unsigned int port_num = mp->port_num;
1525 /* Mask all interrupts on ethernet port */
1526 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1527 /* wait for previous write to complete */
1528 mv_read(INTERRUPT_MASK_REG(port_num));
1531 napi_disable(&mp->napi);
1533 netif_carrier_off(dev);
1534 netif_stop_queue(dev);
1536 eth_port_reset(mp->port_num);
1538 mv643xx_eth_free_tx_rings(dev);
1539 mv643xx_eth_free_rx_rings(dev);
1541 free_irq(dev->irq, dev);
1550 * This function is used in case of NAPI
1552 static int mv643xx_poll(struct napi_struct *napi, int budget)
1554 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
1555 struct net_device *dev = mp->dev;
1556 unsigned int port_num = mp->port_num;
1559 #ifdef MV643XX_TX_FAST_REFILL
1560 if (++mp->tx_clean_threshold > 5) {
1561 mv643xx_eth_free_completed_tx_descs(dev);
1562 mp->tx_clean_threshold = 0;
1567 if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1568 != (u32) mp->rx_used_desc_q)
1569 work_done = mv643xx_eth_receive_queue(dev, budget);
1571 if (work_done < budget) {
1572 netif_rx_complete(dev, napi);
1573 mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
1574 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1575 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1583 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1585 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1586 * This helper function detects that case.
1589 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1594 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1595 fragp = &skb_shinfo(skb)->frags[frag];
1596 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1603 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1605 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1609 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1611 tx_desc_curr = mp->tx_curr_desc_q;
1612 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1614 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1616 return tx_desc_curr;
1620 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1622 * Ensure the data for each fragment to be transmitted is mapped properly,
1623 * then fill in descriptors in the tx hw queue.
1625 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1626 struct sk_buff *skb)
1630 struct eth_tx_desc *desc;
1632 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1633 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1635 tx_index = eth_alloc_tx_desc_index(mp);
1636 desc = &mp->p_tx_desc_area[tx_index];
1638 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1639 /* Last Frag enables interrupt and frees the skb */
1640 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1641 desc->cmd_sts |= ETH_ZERO_PADDING |
1643 ETH_TX_ENABLE_INTERRUPT;
1644 mp->tx_skb[tx_index] = skb;
1646 mp->tx_skb[tx_index] = NULL;
1648 desc = &mp->p_tx_desc_area[tx_index];
1650 desc->byte_cnt = this_frag->size;
1651 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1652 this_frag->page_offset,
1659 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1661 * Ensure the data for an skb to be transmitted is mapped properly,
1662 * then fill in descriptors in the tx hw queue and start the hardware.
1664 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1665 struct sk_buff *skb)
1668 struct eth_tx_desc *desc;
1671 int nr_frags = skb_shinfo(skb)->nr_frags;
1673 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1675 tx_index = eth_alloc_tx_desc_index(mp);
1676 desc = &mp->p_tx_desc_area[tx_index];
1679 eth_tx_fill_frag_descs(mp, skb);
1681 length = skb_headlen(skb);
1682 mp->tx_skb[tx_index] = NULL;
1684 cmd_sts |= ETH_ZERO_PADDING |
1686 ETH_TX_ENABLE_INTERRUPT;
1688 mp->tx_skb[tx_index] = skb;
1691 desc->byte_cnt = length;
1692 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1694 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1695 BUG_ON(skb->protocol != ETH_P_IP);
1697 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1698 ETH_GEN_IP_V_4_CHECKSUM |
1699 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
1701 switch (ip_hdr(skb)->protocol) {
1703 cmd_sts |= ETH_UDP_FRAME;
1704 desc->l4i_chk = udp_hdr(skb)->check;
1707 desc->l4i_chk = tcp_hdr(skb)->check;
1713 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1714 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1718 /* ensure all other descriptors are written before first cmd_sts */
1720 desc->cmd_sts = cmd_sts;
1722 /* ensure all descriptors are written before poking hardware */
1724 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1726 mp->tx_desc_count += nr_frags + 1;
1730 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1733 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1735 struct mv643xx_private *mp = netdev_priv(dev);
1736 struct net_device_stats *stats = &dev->stats;
1737 unsigned long flags;
1739 BUG_ON(netif_queue_stopped(dev));
1740 BUG_ON(skb == NULL);
1742 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1743 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1744 netif_stop_queue(dev);
1748 if (has_tiny_unaligned_frags(skb)) {
1749 if (__skb_linearize(skb)) {
1750 stats->tx_dropped++;
1751 printk(KERN_DEBUG "%s: failed to linearize tiny "
1752 "unaligned fragment\n", dev->name);
1757 spin_lock_irqsave(&mp->lock, flags);
1759 eth_tx_submit_descs_for_skb(mp, skb);
1760 stats->tx_bytes += skb->len;
1761 stats->tx_packets++;
1762 dev->trans_start = jiffies;
1764 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1765 netif_stop_queue(dev);
1767 spin_unlock_irqrestore(&mp->lock, flags);
1769 return 0; /* success */
1772 #ifdef CONFIG_NET_POLL_CONTROLLER
1773 static void mv643xx_netpoll(struct net_device *netdev)
1775 struct mv643xx_private *mp = netdev_priv(netdev);
1776 int port_num = mp->port_num;
1778 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1779 /* wait for previous write to complete */
1780 mv_read(INTERRUPT_MASK_REG(port_num));
1782 mv643xx_eth_int_handler(netdev->irq, netdev);
1784 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1788 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1789 int speed, int duplex,
1790 struct ethtool_cmd *cmd)
1792 struct mv643xx_private *mp = netdev_priv(dev);
1794 memset(cmd, 0, sizeof(*cmd));
1796 cmd->port = PORT_MII;
1797 cmd->transceiver = XCVR_INTERNAL;
1798 cmd->phy_address = phy_address;
1801 cmd->autoneg = AUTONEG_ENABLE;
1802 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1803 cmd->speed = SPEED_100;
1804 cmd->advertising = ADVERTISED_10baseT_Half |
1805 ADVERTISED_10baseT_Full |
1806 ADVERTISED_100baseT_Half |
1807 ADVERTISED_100baseT_Full;
1808 if (mp->mii.supports_gmii)
1809 cmd->advertising |= ADVERTISED_1000baseT_Full;
1811 cmd->autoneg = AUTONEG_DISABLE;
1813 cmd->duplex = duplex;
1820 * First function called after registering the network device.
1821 * It's purpose is to initialize the device as an ethernet device,
1822 * fill the ethernet device structure with pointers * to functions,
1823 * and set the MAC address of the interface
1825 * Input : struct device *
1826 * Output : -ENOMEM if failed , 0 if success
1828 static int mv643xx_eth_probe(struct platform_device *pdev)
1830 struct mv643xx_eth_platform_data *pd;
1832 struct mv643xx_private *mp;
1833 struct net_device *dev;
1835 struct resource *res;
1837 struct ethtool_cmd cmd;
1838 int duplex = DUPLEX_HALF;
1839 int speed = 0; /* default to auto-negotiation */
1840 DECLARE_MAC_BUF(mac);
1842 pd = pdev->dev.platform_data;
1844 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
1848 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1852 platform_set_drvdata(pdev, dev);
1854 mp = netdev_priv(dev);
1857 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
1860 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1862 dev->irq = res->start;
1864 dev->open = mv643xx_eth_open;
1865 dev->stop = mv643xx_eth_stop;
1866 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1867 dev->set_mac_address = mv643xx_eth_set_mac_address;
1868 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1870 /* No need to Tx Timeout */
1871 dev->tx_timeout = mv643xx_eth_tx_timeout;
1873 #ifdef CONFIG_NET_POLL_CONTROLLER
1874 dev->poll_controller = mv643xx_netpoll;
1877 dev->watchdog_timeo = 2 * HZ;
1879 dev->change_mtu = mv643xx_eth_change_mtu;
1880 dev->do_ioctl = mv643xx_eth_do_ioctl;
1881 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1883 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1884 #ifdef MAX_SKB_FRAGS
1886 * Zero copy can only work if we use Discovery II memory. Else, we will
1887 * have to map the buffers to ISA memory which is only 16 MB
1889 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1893 /* Configure the timeout task */
1894 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1896 spin_lock_init(&mp->lock);
1898 port_num = mp->port_num = pd->port_number;
1900 /* set default config values */
1901 eth_port_uc_addr_get(port_num, dev->dev_addr);
1902 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1903 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1905 if (is_valid_ether_addr(pd->mac_addr))
1906 memcpy(dev->dev_addr, pd->mac_addr, 6);
1908 if (pd->phy_addr || pd->force_phy_addr)
1909 ethernet_phy_set(port_num, pd->phy_addr);
1911 if (pd->rx_queue_size)
1912 mp->rx_ring_size = pd->rx_queue_size;
1914 if (pd->tx_queue_size)
1915 mp->tx_ring_size = pd->tx_queue_size;
1917 if (pd->tx_sram_size) {
1918 mp->tx_sram_size = pd->tx_sram_size;
1919 mp->tx_sram_addr = pd->tx_sram_addr;
1922 if (pd->rx_sram_size) {
1923 mp->rx_sram_size = pd->rx_sram_size;
1924 mp->rx_sram_addr = pd->rx_sram_addr;
1927 duplex = pd->duplex;
1930 /* Hook up MII support for ethtool */
1932 mp->mii.mdio_read = mv643xx_mdio_read;
1933 mp->mii.mdio_write = mv643xx_mdio_write;
1934 mp->mii.phy_id = ethernet_phy_get(port_num);
1935 mp->mii.phy_id_mask = 0x3f;
1936 mp->mii.reg_num_mask = 0x1f;
1938 err = ethernet_phy_detect(port_num);
1940 pr_debug("MV643xx ethernet port %d: "
1941 "No PHY detected at addr %d\n",
1942 port_num, ethernet_phy_get(port_num));
1946 ethernet_phy_reset(port_num);
1947 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
1948 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1949 mv643xx_eth_update_pscr(dev, &cmd);
1950 mv643xx_set_settings(dev, &cmd);
1952 SET_NETDEV_DEV(dev, &pdev->dev);
1953 err = register_netdev(dev);
1959 "%s: port %d with MAC address %s\n",
1960 dev->name, port_num, print_mac(mac, p));
1962 if (dev->features & NETIF_F_SG)
1963 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1965 if (dev->features & NETIF_F_IP_CSUM)
1966 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1969 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1970 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1974 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1979 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1982 if (mp->tx_sram_size > 0)
1983 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1993 static int mv643xx_eth_remove(struct platform_device *pdev)
1995 struct net_device *dev = platform_get_drvdata(pdev);
1997 unregister_netdev(dev);
1998 flush_scheduled_work();
2001 platform_set_drvdata(pdev, NULL);
2005 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2007 struct resource *res;
2009 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2011 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2015 mv643xx_eth_base = ioremap(res->start, res->end - res->start + 1);
2016 if (mv643xx_eth_base == NULL)
2023 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2025 iounmap(mv643xx_eth_base);
2026 mv643xx_eth_base = NULL;
2031 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2033 struct net_device *dev = platform_get_drvdata(pdev);
2034 struct mv643xx_private *mp = netdev_priv(dev);
2035 unsigned int port_num = mp->port_num;
2037 /* Mask all interrupts on ethernet port */
2038 mv_write(INTERRUPT_MASK_REG(port_num), 0);
2039 mv_read (INTERRUPT_MASK_REG(port_num));
2041 eth_port_reset(port_num);
2044 static struct platform_driver mv643xx_eth_driver = {
2045 .probe = mv643xx_eth_probe,
2046 .remove = mv643xx_eth_remove,
2047 .shutdown = mv643xx_eth_shutdown,
2049 .name = MV643XX_ETH_NAME,
2053 static struct platform_driver mv643xx_eth_shared_driver = {
2054 .probe = mv643xx_eth_shared_probe,
2055 .remove = mv643xx_eth_shared_remove,
2057 .name = MV643XX_ETH_SHARED_NAME,
2062 * mv643xx_init_module
2064 * Registers the network drivers into the Linux kernel
2070 static int __init mv643xx_init_module(void)
2074 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2076 rc = platform_driver_register(&mv643xx_eth_driver);
2078 platform_driver_unregister(&mv643xx_eth_shared_driver);
2084 * mv643xx_cleanup_module
2086 * Registers the network drivers into the Linux kernel
2092 static void __exit mv643xx_cleanup_module(void)
2094 platform_driver_unregister(&mv643xx_eth_driver);
2095 platform_driver_unregister(&mv643xx_eth_shared_driver);
2098 module_init(mv643xx_init_module);
2099 module_exit(mv643xx_cleanup_module);
2101 MODULE_LICENSE("GPL");
2102 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2103 " and Dale Farnsworth");
2104 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2107 * The second part is the low level driver of the gigE ethernet ports.
2111 * Marvell's Gigabit Ethernet controller low level driver
2114 * This file introduce low level API to Marvell's Gigabit Ethernet
2115 * controller. This Gigabit Ethernet Controller driver API controls
2116 * 1) Operations (i.e. port init, start, reset etc').
2117 * 2) Data flow (i.e. port send, receive etc').
2118 * Each Gigabit Ethernet port is controlled via
2119 * struct mv643xx_private.
2120 * This struct includes user configuration information as well as
2121 * driver internal data needed for its operations.
2123 * Supported Features:
2124 * - This low level driver is OS independent. Allocating memory for
2125 * the descriptor rings and buffers are not within the scope of
2127 * - The user is free from Rx/Tx queue managing.
2128 * - This low level driver introduce functionality API that enable
2129 * the to operate Marvell's Gigabit Ethernet Controller in a
2131 * - Simple Gigabit Ethernet port operation API.
2132 * - Simple Gigabit Ethernet port data flow API.
2133 * - Data flow and operation API support per queue functionality.
2134 * - Support cached descriptors for better performance.
2135 * - Enable access to all four DRAM banks and internal SRAM memory
2137 * - PHY access and control API.
2138 * - Port control register configuration API.
2139 * - Full control over Unicast and Multicast MAC configurations.
2143 * Initialization phase
2144 * This phase complete the initialization of the the
2145 * mv643xx_private struct.
2146 * User information regarding port configuration has to be set
2147 * prior to calling the port initialization routine.
2149 * In this phase any port Tx/Rx activity is halted, MIB counters
2150 * are cleared, PHY address is set according to user parameter and
2151 * access to DRAM and internal SRAM memory spaces.
2153 * Driver ring initialization
2154 * Allocating memory for the descriptor rings and buffers is not
2155 * within the scope of this driver. Thus, the user is required to
2156 * allocate memory for the descriptors ring and buffers. Those
2157 * memory parameters are used by the Rx and Tx ring initialization
2158 * routines in order to curve the descriptor linked list in a form
2160 * Note: Pay special attention to alignment issues when using
2161 * cached descriptors/buffers. In this phase the driver store
2162 * information in the mv643xx_private struct regarding each queue
2166 * This phase prepares the Ethernet port for Rx and Tx activity.
2167 * It uses the information stored in the mv643xx_private struct to
2168 * initialize the various port registers.
2171 * All packet references to/from the driver are done using
2173 * This struct is a unified struct used with Rx and Tx operations.
2174 * This way the user is not required to be familiar with neither
2175 * Tx nor Rx descriptors structures.
2176 * The driver's descriptors rings are management by indexes.
2177 * Those indexes controls the ring resources and used to indicate
2178 * a SW resource error:
2180 * This index points to the current available resource for use. For
2181 * example in Rx process this index will point to the descriptor
2182 * that will be passed to the user upon calling the receive
2183 * routine. In Tx process, this index will point to the descriptor
2184 * that will be assigned with the user packet info and transmitted.
2186 * This index points to the descriptor that need to restore its
2187 * resources. For example in Rx process, using the Rx buffer return
2188 * API will attach the buffer returned in packet info to the
2189 * descriptor pointed by 'used'. In Tx process, using the Tx
2190 * descriptor return will merely return the user packet info with
2191 * the command status of the transmitted buffer pointed by the
2192 * 'used' index. Nevertheless, it is essential to use this routine
2193 * to update the 'used' index.
2195 * This index supports Tx Scatter-Gather. It points to the first
2196 * descriptor of a packet assembled of multiple buffers. For
2197 * example when in middle of Such packet we have a Tx resource
2198 * error the 'curr' index get the value of 'first' to indicate
2199 * that the ring returned to its state before trying to transmit
2202 * Receive operation:
2203 * The eth_port_receive API set the packet information struct,
2204 * passed by the caller, with received information from the
2205 * 'current' SDMA descriptor.
2206 * It is the user responsibility to return this resource back
2207 * to the Rx descriptor ring to enable the reuse of this source.
2208 * Return Rx resource is done using the eth_rx_return_buff API.
2210 * Prior to calling the initialization routine eth_port_init() the user
2211 * must set the following fields under mv643xx_private struct:
2212 * port_num User Ethernet port number.
2213 * port_config User port configuration value.
2214 * port_config_extend User port config extend value.
2215 * port_sdma_config User port SDMA config value.
2216 * port_serial_control User port serial control value.
2218 * This driver data flow is done using the struct pkt_info which
2219 * is a unified struct for Rx and Tx operations:
2221 * byte_cnt Tx/Rx descriptor buffer byte count.
2222 * l4i_chk CPU provided TCP Checksum. For Tx operation
2224 * cmd_sts Tx/Rx descriptor command status.
2225 * buf_ptr Tx/Rx descriptor buffer pointer.
2226 * return_info Tx/Rx user resource return information.
2230 static int ethernet_phy_get(unsigned int eth_port_num);
2231 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
2233 /* Ethernet Port routines */
2234 static void eth_port_set_filter_table_entry(int table, unsigned char entry);
2237 * eth_port_init - Initialize the Ethernet port driver
2240 * This function prepares the ethernet port to start its activity:
2241 * 1) Completes the ethernet port driver struct initialization toward port
2243 * 2) Resets the device to a quiescent state in case of warm reboot.
2244 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2245 * 4) Clean MAC tables. The reset status of those tables is unknown.
2246 * 5) Set PHY address.
2247 * Note: Call this routine prior to eth_port_start routine and after
2248 * setting user values in the user fields of Ethernet port control
2252 * struct mv643xx_private *mp Ethernet port control struct
2260 static void eth_port_init(struct mv643xx_private *mp)
2262 mp->rx_resource_err = 0;
2264 eth_port_reset(mp->port_num);
2266 eth_port_init_mac_tables(mp->port_num);
2270 * eth_port_start - Start the Ethernet port activity.
2273 * This routine prepares the Ethernet port for Rx and Tx activity:
2274 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2275 * has been initialized a descriptor's ring (using
2276 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2277 * 2. Initialize and enable the Ethernet configuration port by writing to
2278 * the port's configuration and command registers.
2279 * 3. Initialize and enable the SDMA by writing to the SDMA's
2280 * configuration and command registers. After completing these steps,
2281 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2283 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2284 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2285 * and ether_init_rx_desc_ring for Rx queues).
2288 * dev - a pointer to the required interface
2291 * Ethernet port is ready to receive and transmit.
2296 static void eth_port_start(struct net_device *dev)
2298 struct mv643xx_private *mp = netdev_priv(dev);
2299 unsigned int port_num = mp->port_num;
2300 int tx_curr_desc, rx_curr_desc;
2302 struct ethtool_cmd ethtool_cmd;
2304 /* Assignment of Tx CTRP of given queue */
2305 tx_curr_desc = mp->tx_curr_desc_q;
2306 mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2307 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2309 /* Assignment of Rx CRDP of given queue */
2310 rx_curr_desc = mp->rx_curr_desc_q;
2311 mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2312 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2314 /* Add the assigned Ethernet address to the port's address table */
2315 eth_port_uc_addr_set(port_num, dev->dev_addr);
2317 /* Assign port configuration and command. */
2318 mv_write(PORT_CONFIG_REG(port_num),
2319 PORT_CONFIG_DEFAULT_VALUE);
2321 mv_write(PORT_CONFIG_EXTEND_REG(port_num),
2322 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2324 pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
2326 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2327 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
2329 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2330 DISABLE_AUTO_NEG_SPEED_GMII |
2331 DISABLE_AUTO_NEG_FOR_DUPLX |
2332 DO_NOT_FORCE_LINK_FAIL |
2333 SERIAL_PORT_CONTROL_RESERVED;
2335 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
2337 pscr |= SERIAL_PORT_ENABLE;
2338 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
2340 /* Assign port SDMA configuration */
2341 mv_write(SDMA_CONFIG_REG(port_num),
2342 PORT_SDMA_CONFIG_DEFAULT_VALUE);
2344 /* Enable port Rx. */
2345 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
2347 /* Disable port bandwidth limits by clearing MTU register */
2348 mv_write(MAXIMUM_TRANSMIT_UNIT(port_num), 0);
2350 /* save phy settings across reset */
2351 mv643xx_get_settings(dev, ðtool_cmd);
2352 ethernet_phy_reset(mp->port_num);
2353 mv643xx_set_settings(dev, ðtool_cmd);
2357 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
2359 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
2365 mac_l = (p_addr[4] << 8) | (p_addr[5]);
2366 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
2369 mv_write(MAC_ADDR_LOW(port_num), mac_l);
2370 mv_write(MAC_ADDR_HIGH(port_num), mac_h);
2372 /* Accept frames with this address */
2373 table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
2374 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
2378 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
2380 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
2385 mac_h = mv_read(MAC_ADDR_HIGH(port_num));
2386 mac_l = mv_read(MAC_ADDR_LOW(port_num));
2388 p_addr[0] = (mac_h >> 24) & 0xff;
2389 p_addr[1] = (mac_h >> 16) & 0xff;
2390 p_addr[2] = (mac_h >> 8) & 0xff;
2391 p_addr[3] = mac_h & 0xff;
2392 p_addr[4] = (mac_l >> 8) & 0xff;
2393 p_addr[5] = mac_l & 0xff;
2397 * The entries in each table are indexed by a hash of a packet's MAC
2398 * address. One bit in each entry determines whether the packet is
2399 * accepted. There are 4 entries (each 8 bits wide) in each register
2400 * of the table. The bits in each entry are defined as follows:
2401 * 0 Accept=1, Drop=0
2402 * 3-1 Queue (ETH_Q0=0)
2405 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2407 unsigned int table_reg;
2408 unsigned int tbl_offset;
2409 unsigned int reg_offset;
2411 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2412 reg_offset = entry % 4; /* Entry offset within the register */
2414 /* Set "accepts frame bit" at specified table entry */
2415 table_reg = mv_read(table + tbl_offset);
2416 table_reg |= 0x01 << (8 * reg_offset);
2417 mv_write(table + tbl_offset, table_reg);
2421 * eth_port_mc_addr - Multicast address settings.
2423 * The MV device supports multicast using two tables:
2424 * 1) Special Multicast Table for MAC addresses of the form
2425 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2426 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2427 * Table entries in the DA-Filter table.
2428 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2429 * is used as an index to the Other Multicast Table entries in the
2430 * DA-Filter table. This function calculates the CRC-8bit value.
2431 * In either case, eth_port_set_filter_table_entry() is then called
2432 * to set to set the actual table entry.
2434 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2438 unsigned char crc_result = 0;
2444 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2445 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2446 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2448 eth_port_set_filter_table_entry(table, p_addr[5]);
2452 /* Calculate CRC-8 out of the given address */
2453 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2454 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2455 (p_addr[4] << 8) | (p_addr[5] << 0);
2457 for (i = 0; i < 32; i++)
2458 mac_array[i] = (mac_l >> i) & 0x1;
2459 for (i = 32; i < 48; i++)
2460 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2462 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2463 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2464 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2465 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2466 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2468 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2469 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2470 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2471 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2472 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2473 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2474 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2476 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2477 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2478 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2479 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2480 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2481 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2483 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2484 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2485 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2486 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2487 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2488 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2490 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2491 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2492 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2493 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2494 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2495 mac_array[3] ^ mac_array[2];
2497 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2498 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2499 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2500 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2501 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2502 mac_array[4] ^ mac_array[3];
2504 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2505 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2506 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2507 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2508 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2511 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2512 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2513 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2514 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2515 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2517 for (i = 0; i < 8; i++)
2518 crc_result = crc_result | (crc[i] << i);
2520 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2521 eth_port_set_filter_table_entry(table, crc_result);
2525 * Set the entire multicast list based on dev->mc_list.
2527 static void eth_port_set_multicast_list(struct net_device *dev)
2530 struct dev_mc_list *mc_list;
2533 struct mv643xx_private *mp = netdev_priv(dev);
2534 unsigned int eth_port_num = mp->port_num;
2536 /* If the device is in promiscuous mode or in all multicast mode,
2537 * we will fully populate both multicast tables with accept.
2538 * This is guaranteed to yield a match on all multicast addresses...
2540 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2541 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2542 /* Set all entries in DA filter special multicast
2544 * Set for ETH_Q0 for now
2546 * 0 Accept=1, Drop=0
2547 * 3-1 Queue ETH_Q0=0
2550 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2552 /* Set all entries in DA filter other multicast
2554 * Set for ETH_Q0 for now
2556 * 0 Accept=1, Drop=0
2557 * 3-1 Queue ETH_Q0=0
2560 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2565 /* We will clear out multicast tables every time we get the list.
2566 * Then add the entire new list...
2568 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2569 /* Clear DA filter special multicast table (Ex_dFSMT) */
2570 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2571 (eth_port_num) + table_index, 0);
2573 /* Clear DA filter other multicast table (Ex_dFOMT) */
2574 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2575 (eth_port_num) + table_index, 0);
2578 /* Get pointer to net_device multicast list and add each one... */
2579 for (i = 0, mc_list = dev->mc_list;
2580 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2581 i++, mc_list = mc_list->next)
2582 if (mc_list->dmi_addrlen == 6)
2583 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2587 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2590 * Go through all the DA filter tables (Unicast, Special Multicast &
2591 * Other Multicast) and set each entry to 0.
2594 * unsigned int eth_port_num Ethernet Port number.
2597 * Multicast and Unicast packets are rejected.
2602 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2606 /* Clear DA filter unicast table (Ex_dFUT) */
2607 for (table_index = 0; table_index <= 0xC; table_index += 4)
2608 mv_write(DA_FILTER_UNICAST_TABLE_BASE
2609 (eth_port_num) + table_index, 0);
2611 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2612 /* Clear DA filter special multicast table (Ex_dFSMT) */
2613 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2614 (eth_port_num) + table_index, 0);
2615 /* Clear DA filter other multicast table (Ex_dFOMT) */
2616 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2617 (eth_port_num) + table_index, 0);
2622 * eth_clear_mib_counters - Clear all MIB counters
2625 * This function clears all MIB counters of a specific ethernet port.
2626 * A read from the MIB counter will reset the counter.
2629 * unsigned int eth_port_num Ethernet Port number.
2632 * After reading all MIB counters, the counters resets.
2635 * MIB counter value.
2638 static void eth_clear_mib_counters(unsigned int eth_port_num)
2642 /* Perform dummy reads from MIB counters */
2643 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2645 mv_read(MIB_COUNTERS_BASE(eth_port_num) + i);
2648 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2650 return mv_read(MIB_COUNTERS_BASE(mp->port_num) + offset);
2653 static void eth_update_mib_counters(struct mv643xx_private *mp)
2655 struct mv643xx_mib_counters *p = &mp->mib_counters;
2658 p->good_octets_received +=
2659 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2660 p->good_octets_received +=
2661 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2663 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2664 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2666 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2668 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2669 p->good_octets_sent +=
2670 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2672 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2673 offset <= ETH_MIB_LATE_COLLISION;
2675 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2679 * ethernet_phy_detect - Detect whether a phy is present
2682 * This function tests whether there is a PHY present on
2683 * the specified port.
2686 * unsigned int eth_port_num Ethernet Port number.
2693 * -ENODEV on failure
2696 static int ethernet_phy_detect(unsigned int port_num)
2698 unsigned int phy_reg_data0;
2701 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2702 auto_neg = phy_reg_data0 & 0x1000;
2703 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2704 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2706 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2707 if ((phy_reg_data0 & 0x1000) == auto_neg)
2708 return -ENODEV; /* change didn't take */
2710 phy_reg_data0 ^= 0x1000;
2711 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2716 * ethernet_phy_get - Get the ethernet port PHY address.
2719 * This routine returns the given ethernet port PHY address.
2722 * unsigned int eth_port_num Ethernet Port number.
2731 static int ethernet_phy_get(unsigned int eth_port_num)
2733 unsigned int reg_data;
2735 reg_data = mv_read(PHY_ADDR_REG);
2737 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2741 * ethernet_phy_set - Set the ethernet port PHY address.
2744 * This routine sets the given ethernet port PHY address.
2747 * unsigned int eth_port_num Ethernet Port number.
2748 * int phy_addr PHY address.
2757 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2760 int addr_shift = 5 * eth_port_num;
2762 reg_data = mv_read(PHY_ADDR_REG);
2763 reg_data &= ~(0x1f << addr_shift);
2764 reg_data |= (phy_addr & 0x1f) << addr_shift;
2765 mv_write(PHY_ADDR_REG, reg_data);
2769 * ethernet_phy_reset - Reset Ethernet port PHY.
2772 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2775 * unsigned int eth_port_num Ethernet Port number.
2784 static void ethernet_phy_reset(unsigned int eth_port_num)
2786 unsigned int phy_reg_data;
2789 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2790 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2791 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2793 /* wait for PHY to come out of reset */
2796 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2797 } while (phy_reg_data & 0x8000);
2800 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
2801 unsigned int queues)
2803 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
2806 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2807 unsigned int queues)
2809 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
2812 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2816 /* Stop Tx port activity. Check port Tx activity. */
2817 queues = mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2819 /* Issue stop command for active queues only */
2820 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
2822 /* Wait for all Tx activity to terminate. */
2823 /* Check port cause register that all Tx queues are stopped */
2824 while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2825 udelay(PHY_WAIT_MICRO_SECONDS);
2827 /* Wait for Tx FIFO to empty */
2828 while (mv_read(PORT_STATUS_REG(port_num)) &
2829 ETH_PORT_TX_FIFO_EMPTY)
2830 udelay(PHY_WAIT_MICRO_SECONDS);
2836 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2840 /* Stop Rx port activity. Check port Rx activity. */
2841 queues = mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2843 /* Issue stop command for active queues only */
2844 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
2846 /* Wait for all Rx activity to terminate. */
2847 /* Check port cause register that all Rx queues are stopped */
2848 while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2849 udelay(PHY_WAIT_MICRO_SECONDS);
2856 * eth_port_reset - Reset Ethernet port
2859 * This routine resets the chip by aborting any SDMA engine activity and
2860 * clearing the MIB counters. The Receiver and the Transmit unit are in
2861 * idle state after this command is performed and the port is disabled.
2864 * unsigned int eth_port_num Ethernet Port number.
2867 * Channel activity is halted.
2873 static void eth_port_reset(unsigned int port_num)
2875 unsigned int reg_data;
2877 mv643xx_eth_port_disable_tx(port_num);
2878 mv643xx_eth_port_disable_rx(port_num);
2880 /* Clear all MIB counters */
2881 eth_clear_mib_counters(port_num);
2883 /* Reset the Enable bit in the Configuration Register */
2884 reg_data = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
2885 reg_data &= ~(SERIAL_PORT_ENABLE |
2886 DO_NOT_FORCE_LINK_FAIL |
2888 mv_write(PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2893 * eth_port_read_smi_reg - Read PHY registers
2896 * This routine utilize the SMI interface to interact with the PHY in
2897 * order to perform PHY register read.
2900 * unsigned int port_num Ethernet Port number.
2901 * unsigned int phy_reg PHY register address offset.
2902 * unsigned int *value Register value buffer.
2905 * Write the value of a specified PHY register into given buffer.
2908 * false if the PHY is busy or read data is not in valid state.
2912 static void eth_port_read_smi_reg(unsigned int port_num,
2913 unsigned int phy_reg, unsigned int *value)
2915 int phy_addr = ethernet_phy_get(port_num);
2916 unsigned long flags;
2919 /* the SMI register is a shared resource */
2920 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2922 /* wait for the SMI register to become available */
2923 for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
2924 if (i == PHY_WAIT_ITERATIONS) {
2925 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2928 udelay(PHY_WAIT_MICRO_SECONDS);
2932 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2934 /* now wait for the data to be valid */
2935 for (i = 0; !(mv_read(SMI_REG) & ETH_SMI_READ_VALID); i++) {
2936 if (i == PHY_WAIT_ITERATIONS) {
2937 printk("mv643xx PHY read timeout, port %d\n", port_num);
2940 udelay(PHY_WAIT_MICRO_SECONDS);
2943 *value = mv_read(SMI_REG) & 0xffff;
2945 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2949 * eth_port_write_smi_reg - Write to PHY registers
2952 * This routine utilize the SMI interface to interact with the PHY in
2953 * order to perform writes to PHY registers.
2956 * unsigned int eth_port_num Ethernet Port number.
2957 * unsigned int phy_reg PHY register address offset.
2958 * unsigned int value Register value.
2961 * Write the given value to the specified PHY register.
2964 * false if the PHY is busy.
2968 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2969 unsigned int phy_reg, unsigned int value)
2973 unsigned long flags;
2975 phy_addr = ethernet_phy_get(eth_port_num);
2977 /* the SMI register is a shared resource */
2978 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2980 /* wait for the SMI register to become available */
2981 for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
2982 if (i == PHY_WAIT_ITERATIONS) {
2983 printk("mv643xx PHY busy timeout, port %d\n",
2987 udelay(PHY_WAIT_MICRO_SECONDS);
2990 mv_write(SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2991 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2993 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2997 * Wrappers for MII support library.
2999 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
3002 struct mv643xx_private *mp = netdev_priv(dev);
3004 eth_port_read_smi_reg(mp->port_num, location, &val);
3008 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
3010 struct mv643xx_private *mp = netdev_priv(dev);
3011 eth_port_write_smi_reg(mp->port_num, location, val);
3015 * eth_port_receive - Get received information from Rx ring.
3018 * This routine returns the received data to the caller. There is no
3019 * data copying during routine operation. All information is returned
3020 * using pointer to packet information struct passed from the caller.
3021 * If the routine exhausts Rx ring resources then the resource error flag
3025 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3026 * struct pkt_info *p_pkt_info User packet buffer.
3029 * Rx ring current and used indexes are updated.
3032 * ETH_ERROR in case the routine can not access Rx desc ring.
3033 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3034 * ETH_END_OF_JOB if there is no received data.
3037 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
3038 struct pkt_info *p_pkt_info)
3040 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
3041 volatile struct eth_rx_desc *p_rx_desc;
3042 unsigned int command_status;
3043 unsigned long flags;
3045 /* Do not process Rx ring in case of Rx ring resource error */
3046 if (mp->rx_resource_err)
3047 return ETH_QUEUE_FULL;
3049 spin_lock_irqsave(&mp->lock, flags);
3051 /* Get the Rx Desc ring 'curr and 'used' indexes */
3052 rx_curr_desc = mp->rx_curr_desc_q;
3053 rx_used_desc = mp->rx_used_desc_q;
3055 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
3057 /* The following parameters are used to save readings from memory */
3058 command_status = p_rx_desc->cmd_sts;
3061 /* Nothing to receive... */
3062 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
3063 spin_unlock_irqrestore(&mp->lock, flags);
3064 return ETH_END_OF_JOB;
3067 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
3068 p_pkt_info->cmd_sts = command_status;
3069 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
3070 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
3071 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
3074 * Clean the return info field to indicate that the
3075 * packet has been moved to the upper layers
3077 mp->rx_skb[rx_curr_desc] = NULL;
3079 /* Update current index in data structure */
3080 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
3081 mp->rx_curr_desc_q = rx_next_curr_desc;
3083 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
3084 if (rx_next_curr_desc == rx_used_desc)
3085 mp->rx_resource_err = 1;
3087 spin_unlock_irqrestore(&mp->lock, flags);
3093 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3096 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3097 * next 'used' descriptor and attached the returned buffer to it.
3098 * In case the Rx ring was in "resource error" condition, where there are
3099 * no available Rx resources, the function resets the resource error flag.
3102 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3103 * struct pkt_info *p_pkt_info Information on returned buffer.
3106 * New available Rx resource in Rx descriptor ring.
3109 * ETH_ERROR in case the routine can not access Rx desc ring.
3112 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
3113 struct pkt_info *p_pkt_info)
3115 int used_rx_desc; /* Where to return Rx resource */
3116 volatile struct eth_rx_desc *p_used_rx_desc;
3117 unsigned long flags;
3119 spin_lock_irqsave(&mp->lock, flags);
3121 /* Get 'used' Rx descriptor */
3122 used_rx_desc = mp->rx_used_desc_q;
3123 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
3125 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3126 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
3127 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
3129 /* Flush the write pipe */
3131 /* Return the descriptor to DMA ownership */
3133 p_used_rx_desc->cmd_sts =
3134 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3137 /* Move the used descriptor pointer to the next descriptor */
3138 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
3140 /* Any Rx return cancels the Rx resource error status */
3141 mp->rx_resource_err = 0;
3143 spin_unlock_irqrestore(&mp->lock, flags);
3148 /************* Begin ethtool support *************************/
3150 struct mv643xx_stats {
3151 char stat_string[ETH_GSTRING_LEN];
3156 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
3157 offsetof(struct mv643xx_private, m)
3159 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3160 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3161 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3162 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3163 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3164 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3165 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3166 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3167 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3168 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3169 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3170 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3171 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3172 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3173 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3174 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3175 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3176 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3177 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3178 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3179 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3180 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3181 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3182 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3183 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3184 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3185 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3186 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3187 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3188 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3189 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3190 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3191 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3192 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3193 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3194 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3195 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3196 { "collision", MV643XX_STAT(mib_counters.collision) },
3197 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3200 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
3202 static void mv643xx_get_drvinfo(struct net_device *netdev,
3203 struct ethtool_drvinfo *drvinfo)
3205 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3206 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3207 strncpy(drvinfo->fw_version, "N/A", 32);
3208 strncpy(drvinfo->bus_info, "mv643xx", 32);
3209 drvinfo->n_stats = MV643XX_STATS_LEN;
3212 static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
3216 return MV643XX_STATS_LEN;
3222 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
3223 struct ethtool_stats *stats, uint64_t *data)
3225 struct mv643xx_private *mp = netdev->priv;
3228 eth_update_mib_counters(mp);
3230 for (i = 0; i < MV643XX_STATS_LEN; i++) {
3231 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3232 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3233 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3237 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3244 for (i=0; i < MV643XX_STATS_LEN; i++) {
3245 memcpy(data + i * ETH_GSTRING_LEN,
3246 mv643xx_gstrings_stats[i].stat_string,
3253 static u32 mv643xx_eth_get_link(struct net_device *dev)
3255 struct mv643xx_private *mp = netdev_priv(dev);
3257 return mii_link_ok(&mp->mii);
3260 static int mv643xx_eth_nway_restart(struct net_device *dev)
3262 struct mv643xx_private *mp = netdev_priv(dev);
3264 return mii_nway_restart(&mp->mii);
3267 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3269 struct mv643xx_private *mp = netdev_priv(dev);
3271 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
3274 static const struct ethtool_ops mv643xx_ethtool_ops = {
3275 .get_settings = mv643xx_get_settings,
3276 .set_settings = mv643xx_set_settings,
3277 .get_drvinfo = mv643xx_get_drvinfo,
3278 .get_link = mv643xx_eth_get_link,
3279 .set_sg = ethtool_op_set_sg,
3280 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3281 .get_strings = mv643xx_get_strings,
3282 .nway_reset = mv643xx_eth_nway_restart,
3285 /************* End ethtool support *************************/