1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Driver for the MDIO interface of Microsemi network switches.
5 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
6 * Copyright (c) 2017 Microsemi Corporation
9 #include <linux/bitops.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mdio/mdio-mscc-miim.h>
14 #include <linux/module.h>
15 #include <linux/of_mdio.h>
16 #include <linux/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
21 #define MSCC_MIIM_REG_STATUS 0x0
22 #define MSCC_MIIM_STATUS_STAT_PENDING BIT(2)
23 #define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
24 #define MSCC_MIIM_REG_CMD 0x8
25 #define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
26 #define MSCC_MIIM_CMD_OPR_READ BIT(2)
27 #define MSCC_MIIM_CMD_WRDATA_SHIFT 4
28 #define MSCC_MIIM_CMD_REGAD_SHIFT 20
29 #define MSCC_MIIM_CMD_PHYAD_SHIFT 25
30 #define MSCC_MIIM_CMD_VLD BIT(31)
31 #define MSCC_MIIM_REG_DATA 0xC
32 #define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
34 #define MSCC_PHY_REG_PHY_CFG 0x0
35 #define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3))
36 #define PHY_CFG_PHY_COMMON_RESET BIT(4)
37 #define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
38 #define MSCC_PHY_REG_PHY_STATUS 0x4
40 #define LAN966X_CUPHY_COMMON_CFG 0x0
41 #define CUPHY_COMMON_CFG_RESET_N BIT(0)
43 struct mscc_miim_info {
44 unsigned int phy_reset_offset;
45 unsigned int phy_reset_bits;
48 struct mscc_miim_dev {
50 int mii_status_offset;
51 struct regmap *phy_regs;
52 const struct mscc_miim_info *info;
55 /* When high resolution timers aren't built-in: we can't use usleep_range() as
56 * we would sleep way too long. Use udelay() instead.
58 #define mscc_readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us)\
60 if (!IS_ENABLED(CONFIG_HIGH_RES_TIMERS)) \
61 readx_poll_timeout_atomic(op, addr, val, cond, delay_us, \
63 readx_poll_timeout(op, addr, val, cond, delay_us, timeout_us); \
66 static int mscc_miim_status(struct mii_bus *bus)
68 struct mscc_miim_dev *miim = bus->priv;
71 ret = regmap_read(miim->regs,
72 MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val);
74 WARN_ONCE(1, "mscc miim status read error %d\n", ret);
81 static int mscc_miim_wait_ready(struct mii_bus *bus)
85 return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
86 !(val & MSCC_MIIM_STATUS_STAT_BUSY), 50,
90 static int mscc_miim_wait_pending(struct mii_bus *bus)
94 return mscc_readx_poll_timeout(mscc_miim_status, bus, val,
95 !(val & MSCC_MIIM_STATUS_STAT_PENDING),
99 static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
101 struct mscc_miim_dev *miim = bus->priv;
105 if (regnum & MII_ADDR_C45)
108 ret = mscc_miim_wait_pending(bus);
112 ret = regmap_write(miim->regs,
113 MSCC_MIIM_REG_CMD + miim->mii_status_offset,
115 (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
116 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
117 MSCC_MIIM_CMD_OPR_READ);
120 WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret);
124 ret = mscc_miim_wait_ready(bus);
128 ret = regmap_read(miim->regs,
129 MSCC_MIIM_REG_DATA + miim->mii_status_offset, &val);
131 WARN_ONCE(1, "mscc miim read data reg error %d\n", ret);
135 if (val & MSCC_MIIM_DATA_ERROR) {
145 static int mscc_miim_write(struct mii_bus *bus, int mii_id,
146 int regnum, u16 value)
148 struct mscc_miim_dev *miim = bus->priv;
151 if (regnum & MII_ADDR_C45)
154 ret = mscc_miim_wait_pending(bus);
158 ret = regmap_write(miim->regs,
159 MSCC_MIIM_REG_CMD + miim->mii_status_offset,
161 (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
162 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
163 (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
164 MSCC_MIIM_CMD_OPR_WRITE);
167 WARN_ONCE(1, "mscc miim write error %d\n", ret);
172 static int mscc_miim_reset(struct mii_bus *bus)
174 struct mscc_miim_dev *miim = bus->priv;
175 unsigned int offset, bits;
181 offset = miim->info->phy_reset_offset;
182 bits = miim->info->phy_reset_bits;
184 ret = regmap_update_bits(miim->phy_regs, offset, bits, 0);
186 WARN_ONCE(1, "mscc reset set error %d\n", ret);
190 ret = regmap_update_bits(miim->phy_regs, offset, bits, bits);
192 WARN_ONCE(1, "mscc reset clear error %d\n", ret);
201 static const struct regmap_config mscc_miim_regmap_config = {
207 static const struct regmap_config mscc_miim_phy_regmap_config = {
214 int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name,
215 struct regmap *mii_regmap, int status_offset)
217 struct mscc_miim_dev *miim;
220 bus = devm_mdiobus_alloc_size(dev, sizeof(*miim));
225 bus->read = mscc_miim_read;
226 bus->write = mscc_miim_write;
227 bus->reset = mscc_miim_reset;
228 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(dev));
235 miim->regs = mii_regmap;
236 miim->mii_status_offset = status_offset;
242 EXPORT_SYMBOL(mscc_miim_setup);
244 static int mscc_miim_probe(struct platform_device *pdev)
246 struct regmap *mii_regmap, *phy_regmap = NULL;
247 void __iomem *regs, *phy_regs;
248 struct mscc_miim_dev *miim;
249 struct resource *res;
253 regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
255 dev_err(&pdev->dev, "Unable to map MIIM registers\n");
256 return PTR_ERR(regs);
259 mii_regmap = devm_regmap_init_mmio(&pdev->dev, regs,
260 &mscc_miim_regmap_config);
262 if (IS_ERR(mii_regmap)) {
263 dev_err(&pdev->dev, "Unable to create MIIM regmap\n");
264 return PTR_ERR(mii_regmap);
267 /* This resource is optional */
268 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
270 phy_regs = devm_ioremap_resource(&pdev->dev, res);
271 if (IS_ERR(phy_regs)) {
272 dev_err(&pdev->dev, "Unable to map internal phy registers\n");
273 return PTR_ERR(phy_regs);
276 phy_regmap = devm_regmap_init_mmio(&pdev->dev, phy_regs,
277 &mscc_miim_phy_regmap_config);
278 if (IS_ERR(phy_regmap)) {
279 dev_err(&pdev->dev, "Unable to create phy register regmap\n");
280 return PTR_ERR(phy_regmap);
284 ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0);
286 dev_err(&pdev->dev, "Unable to setup the MDIO bus\n");
291 miim->phy_regs = phy_regmap;
293 miim->info = device_get_match_data(&pdev->dev);
297 ret = of_mdiobus_register(bus, pdev->dev.of_node);
299 dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
303 platform_set_drvdata(pdev, bus);
308 static int mscc_miim_remove(struct platform_device *pdev)
310 struct mii_bus *bus = platform_get_drvdata(pdev);
312 mdiobus_unregister(bus);
317 static const struct mscc_miim_info mscc_ocelot_miim_info = {
318 .phy_reset_offset = MSCC_PHY_REG_PHY_CFG,
319 .phy_reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET |
323 static const struct mscc_miim_info microchip_lan966x_miim_info = {
324 .phy_reset_offset = LAN966X_CUPHY_COMMON_CFG,
325 .phy_reset_bits = CUPHY_COMMON_CFG_RESET_N,
328 static const struct of_device_id mscc_miim_match[] = {
330 .compatible = "mscc,ocelot-miim",
331 .data = &mscc_ocelot_miim_info
333 .compatible = "microchip,lan966x-miim",
334 .data = µchip_lan966x_miim_info
338 MODULE_DEVICE_TABLE(of, mscc_miim_match);
340 static struct platform_driver mscc_miim_driver = {
341 .probe = mscc_miim_probe,
342 .remove = mscc_miim_remove,
345 .of_match_table = mscc_miim_match,
349 module_platform_driver(mscc_miim_driver);
351 MODULE_DESCRIPTION("Microsemi MIIM driver");
352 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
353 MODULE_LICENSE("Dual MIT/GPL");