1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2021 Linaro Ltd.
9 #include <linux/bitfield.h>
11 #include "ipa_version.h"
18 * IPA registers are located within the "ipa-reg" address space defined by
19 * Device Tree. The offset of each register within that space is specified
20 * by symbols defined below. The address space is mapped to virtual memory
21 * space in ipa_mem_init(). All IPA registers are 32 bits wide.
23 * Certain register types are duplicated for a number of instances of
24 * something. For example, each IPA endpoint has an set of registers
25 * defining its configuration. The offset to an endpoint's set of registers
26 * is computed based on an "base" offset, plus an endpoint's ID multiplied
27 * and a "stride" value for the register. For such registers, the offset is
28 * computed by a function-like macro that takes a parameter used in the
31 * Some register offsets depend on execution environment. For these an "ee"
32 * parameter is supplied to the offset macro. The "ee" value is a member of
33 * the gsi_ee enumerated type.
35 * The offset of a register dependent on endpoint ID is computed by a macro
36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an
37 * "ep" parameter is valid for any endpoint; a register with a "txep" or
38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The
39 * "*ep" value is assumed to be less than the maximum valid endpoint ID
40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX.
42 * The offset of registers related to filter and route tables is computed
43 * by a macro that is supplied a parameter "er". The "er" represents an
44 * endpoint ID for filters, or a route ID for routes. For filters, the
45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted
46 * because not all endpoints support filtering. For routes, the route ID
47 * must be less than IPA_ROUTE_MAX.
49 * The offset of registers related to resource types is computed by a macro
50 * that is supplied a parameter "rt". The "rt" represents a resource type,
51 * which is is a member of the ipa_resource_type_src enumerated type for
52 * source endpoint resources or the ipa_resource_type_dst enumerated type
53 * for destination endpoint resources.
55 * Some registers encode multiple fields within them. For these, each field
56 * has a symbol below defining a field mask that encodes both the position
57 * and width of the field within its register.
59 * In some cases, different versions of IPA hardware use different offset or
60 * field mask values. In such cases an inline_function(ipa) is used rather
61 * than a MACRO to define the offset or field mask to use.
63 * Finally, some registers hold bitmasks representing endpoints. In such
64 * cases the @available field in the @ipa structure defines the "full" set
65 * of valid bits for the register.
68 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c
69 /* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */
70 #define ENABLE_FMASK GENMASK(0, 0)
71 /* The next field is present for IPA v4.7+ */
72 #define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0)
73 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1)
74 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2)
75 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3)
76 /* The next field is not present for IPA v4.5+ */
77 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4)
78 /* The next twelve fields are present for IPA v4.0+ */
79 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5)
80 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6)
81 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7)
82 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8)
83 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9)
84 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10)
85 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11)
86 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12)
87 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13)
88 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14)
89 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15)
90 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16)
91 /* The next five fields are present for IPA v4.9+ */
92 #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19)
93 #define GENQMB_AOOOWR_FMASK GENMASK(20, 20)
94 #define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21)
95 #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30)
96 #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31)
98 /* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */
99 static inline u32 arbitration_lock_disable_encoded(enum ipa_version version,
102 /* assert(version >= IPA_VERSION_4_0); */
104 if (version < IPA_VERSION_4_9)
105 return u32_encode_bits(mask, GENMASK(20, 17));
107 if (version == IPA_VERSION_4_9)
108 return u32_encode_bits(mask, GENMASK(24, 22));
110 return u32_encode_bits(mask, GENMASK(23, 22));
113 /* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */
114 static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version,
117 u32 val = enable ? 1 : 0;
119 /* assert(version >= IPA_VERSION_4_5); */
121 if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7)
122 return u32_encode_bits(val, GENMASK(21, 21));
124 return u32_encode_bits(val, GENMASK(17, 17));
127 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044
128 #define RX_FMASK GENMASK(0, 0)
129 #define PROC_FMASK GENMASK(1, 1)
130 #define TX_WRAPPER_FMASK GENMASK(2, 2)
131 #define MISC_FMASK GENMASK(3, 3)
132 #define RAM_ARB_FMASK GENMASK(4, 4)
133 #define FTCH_HPS_FMASK GENMASK(5, 5)
134 #define FTCH_DPS_FMASK GENMASK(6, 6)
135 #define HPS_FMASK GENMASK(7, 7)
136 #define DPS_FMASK GENMASK(8, 8)
137 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9)
138 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10)
139 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11)
140 #define RSRC_MNGR_FMASK GENMASK(12, 12)
141 #define CTX_HANDLER_FMASK GENMASK(13, 13)
142 #define ACK_MNGR_FMASK GENMASK(14, 14)
143 #define D_DCPH_FMASK GENMASK(15, 15)
144 #define H_DCPH_FMASK GENMASK(16, 16)
145 /* The next field is not present for IPA v4.5+ */
146 #define DCMP_FMASK GENMASK(17, 17)
147 /* The next three fields are present for IPA v3.5+ */
148 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18)
149 #define TX_0_FMASK GENMASK(19, 19)
150 #define TX_1_FMASK GENMASK(20, 20)
151 /* The next field is present for IPA v3.5.1+ */
152 #define FNR_FMASK GENMASK(21, 21)
153 /* The next eight fields are present for IPA v4.0+ */
154 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22)
155 #define AGGR_WRAPPER_FMASK GENMASK(23, 23)
156 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24)
157 #define QMB_FMASK GENMASK(25, 25)
158 #define WEIGHT_ARB_FMASK GENMASK(26, 26)
159 #define GSI_IF_FMASK GENMASK(27, 27)
160 #define GLOBAL_FMASK GENMASK(28, 28)
161 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29)
162 /* The next field is present for IPA v4.5+ */
163 #define DPL_FIFO_FMASK GENMASK(30, 30)
164 /* The next field is present for IPA v4.7+ */
165 #define DRBIP_FMASK GENMASK(31, 31)
167 #define IPA_REG_ROUTE_OFFSET 0x00000048
168 #define ROUTE_DIS_FMASK GENMASK(0, 0)
169 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1)
170 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6)
171 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7)
172 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17)
173 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24)
175 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054
176 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0)
177 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16)
179 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074
180 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0)
181 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4)
183 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078
184 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0)
185 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4)
186 /* The next two fields are present for IPA v4.0+ */
187 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16)
188 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24)
190 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version)
192 if (version < IPA_VERSION_4_0)
198 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version)
200 if (version < IPA_VERSION_4_0)
206 /* The next four fields are used for the hash enable and flush registers */
207 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0)
208 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4)
209 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8)
210 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12)
212 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */
213 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version)
215 if (version < IPA_VERSION_4_0)
221 /* The next register is not present for IPA v4.5+ */
222 #define IPA_REG_BCR_OFFSET 0x000001d0
223 /* The next two fields are not present for IPA v4.2+ */
224 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0)
225 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1)
226 /* The next field is invalid for IPA v4.0+ */
227 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2)
228 /* The next two fields are not present for IPA v4.2+ */
229 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3)
230 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4)
231 /* The next five fields are present for IPA v3.5+ */
232 #define BCR_DUAL_TX_FMASK GENMASK(5, 5)
233 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6)
234 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7)
235 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8)
236 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9)
238 /* Backward compatibility register value to use for each version */
239 static inline u32 ipa_reg_bcr_val(enum ipa_version version)
241 if (version == IPA_VERSION_3_5_1)
242 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK |
243 BCR_TX_NOT_USING_BRESP_FMASK |
244 BCR_SUSPEND_L2_IRQ_FMASK |
245 BCR_HOLB_DROP_L2_IRQ_FMASK |
248 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1)
249 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK |
250 BCR_SUSPEND_L2_IRQ_FMASK |
251 BCR_HOLB_DROP_L2_IRQ_FMASK |
254 /* assert(version != IPA_VERSION_4_5); */
259 /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */
260 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8
262 /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */
263 static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version,
266 if (version < IPA_VERSION_4_5)
267 return u32_encode_bits(addr, GENMASK(16, 0));
269 return u32_encode_bits(addr, GENMASK(17, 0));
272 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */
273 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec
275 /* The next register is not present for IPA v4.5+ */
276 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0
277 /* The next field is not present for IPA v3.5+ */
278 #define EOT_COAL_GRANULARITY GENMASK(3, 0)
279 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4)
281 /* The next register is present for IPA v3.5+ */
282 #define IPA_REG_TX_CFG_OFFSET 0x000001fc
283 /* The next three fields are not present for IPA v4.0+ */
284 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0)
285 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1)
286 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2)
287 /* The next six fields are present for IPA v4.0+ */
288 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2)
289 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6)
290 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10)
291 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11)
292 #define PA_MASK_EN_FMASK GENMASK(12, 12)
293 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13)
294 /* The next field is present for IPA v4.5+ */
295 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17)
296 /* The next field is present for IPA v4.2+, but not IPA v4.5 */
297 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18)
298 /* The next field is present for IPA v4.2 only */
299 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19)
301 /* The next register is present for IPA v3.5+ */
302 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210
303 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0)
304 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8)
305 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16)
306 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24)
308 /* The next register is present for IPA v3.5+ */
309 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version)
311 if (version >= IPA_VERSION_4_2)
317 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0)
318 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16)
320 /* The next register is present for IPA v4.5+ */
321 #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c
322 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0)
323 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7)
324 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8)
325 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16)
327 /* The next register is present for IPA v4.5+ */
328 #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250
329 #define DIV_VALUE_FMASK GENMASK(8, 0)
330 #define DIV_ENABLE_FMASK GENMASK(31, 31)
332 /* The next register is present for IPA v4.5+ */
333 #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254
334 #define GRAN_0_FMASK GENMASK(2, 0)
335 #define GRAN_1_FMASK GENMASK(5, 3)
336 #define GRAN_2_FMASK GENMASK(8, 6)
337 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */
338 enum ipa_pulse_gran {
339 IPA_GRAN_10_US = 0x0,
340 IPA_GRAN_20_US = 0x1,
341 IPA_GRAN_50_US = 0x2,
342 IPA_GRAN_100_US = 0x3,
344 IPA_GRAN_10_MS = 0x5,
345 IPA_GRAN_100_MS = 0x6,
346 IPA_GRAN_655350_US = 0x7,
349 /* Not all of the following are present (depends on IPA version) */
350 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \
351 (0x00000400 + 0x0020 * (rt))
352 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \
353 (0x00000404 + 0x0020 * (rt))
354 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \
355 (0x00000408 + 0x0020 * (rt))
356 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \
357 (0x00000500 + 0x0020 * (rt))
358 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \
359 (0x00000504 + 0x0020 * (rt))
360 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \
361 (0x00000508 + 0x0020 * (rt))
362 /* The next four fields are used for all resource group registers */
363 #define X_MIN_LIM_FMASK GENMASK(5, 0)
364 #define X_MAX_LIM_FMASK GENMASK(13, 8)
365 /* The next two fields are not always present (if resource count is odd) */
366 #define Y_MIN_LIM_FMASK GENMASK(21, 16)
367 #define Y_MAX_LIM_FMASK GENMASK(29, 24)
369 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \
370 (0x00000800 + 0x0070 * (ep))
371 /* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */
372 #define ENDP_SUSPEND_FMASK GENMASK(0, 0)
373 /* Valid only for TX (IPA consumer) endpoints */
374 #define ENDP_DELAY_FMASK GENMASK(1, 1)
376 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \
377 (0x00000808 + 0x0070 * (ep))
378 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0)
379 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1)
380 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3)
381 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8)
383 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */
384 enum ipa_cs_offload_en {
385 IPA_CS_OFFLOAD_NONE = 0x0,
386 IPA_CS_OFFLOAD_UL = 0x1, /* Before IPA v4.5 (TX) */
387 IPA_CS_OFFLOAD_DL = 0x2, /* Before IPA v4.5 (RX) */
390 /* Valid only for TX (IPA consumer) endpoints */
391 #define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \
392 (0x0000080c + 0x0070 * (ep))
393 #define NAT_EN_FMASK GENMASK(1, 0)
395 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */
397 IPA_NAT_BYPASS = 0x0,
402 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \
403 (0x00000810 + 0x0070 * (ep))
404 #define HDR_LEN_FMASK GENMASK(5, 0)
405 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6)
406 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7)
407 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13)
408 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19)
409 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20)
410 /* The next field is not present for IPA v4.9+ */
411 #define HDR_A5_MUX_FMASK GENMASK(26, 26)
412 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27)
413 /* The next field is not present for IPA v4.5+ */
414 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28)
415 /* The next two fields are present for IPA v4.5+ */
416 #define HDR_LEN_MSB_FMASK GENMASK(29, 28)
417 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30)
419 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */
420 static inline u32 ipa_header_size_encoded(enum ipa_version version,
423 u32 size = header_size & field_mask(HDR_LEN_FMASK);
426 val = u32_encode_bits(size, HDR_LEN_FMASK);
427 if (version < IPA_VERSION_4_5) {
428 /* ipa_assert(header_size == size); */
432 /* IPA v4.5 adds a few more most-significant bits */
433 size = header_size >> hweight32(HDR_LEN_FMASK);
434 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK);
439 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */
440 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version,
443 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK);
446 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK);
447 if (version < IPA_VERSION_4_5) {
448 /* ipa_assert(offset == off); */
452 /* IPA v4.5 adds a few more most-significant bits */
453 off = offset >> hweight32(HDR_OFST_METADATA_FMASK);
454 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK);
459 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \
460 (0x00000814 + 0x0070 * (ep))
461 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0)
462 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1)
463 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2)
464 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3)
465 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4)
466 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10)
467 /* The next three fields are present for IPA v4.5+ */
468 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16)
469 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18)
470 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20)
472 /* Valid only for RX (IPA producer) endpoints */
473 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \
474 (0x00000818 + 0x0070 * (rxep))
476 /* Valid only for TX (IPA consumer) endpoints */
477 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \
478 (0x00000820 + 0x0070 * (txep))
479 #define MODE_FMASK GENMASK(2, 0)
480 /* The next field is present for IPA v4.5+ */
481 #define DCPH_ENABLE_FMASK GENMASK(3, 3)
482 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4)
483 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12)
484 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28)
485 #define PAD_EN_FMASK GENMASK(29, 29)
486 /* The next field is not present for IPA v4.5+ */
487 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30)
488 /* The next field is present for IPA v4.9+ */
489 #define DRBIP_ACL_ENABLE GENMASK(30, 30)
491 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */
494 IPA_ENABLE_FRAMING_HDLC = 0x1,
495 IPA_ENABLE_DEFRAMING_HDLC = 0x2,
499 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \
500 (0x00000824 + 0x0070 * (ep))
501 #define AGGR_EN_FMASK GENMASK(1, 0)
502 #define AGGR_TYPE_FMASK GENMASK(4, 2)
504 /* The legacy value is used for IPA hardware before IPA v4.5 */
505 static inline u32 aggr_byte_limit_fmask(bool legacy)
507 return legacy ? GENMASK(9, 5) : GENMASK(10, 5);
510 /* The legacy value is used for IPA hardware before IPA v4.5 */
511 static inline u32 aggr_time_limit_fmask(bool legacy)
513 return legacy ? GENMASK(14, 10) : GENMASK(16, 12);
516 /* The legacy value is used for IPA hardware before IPA v4.5 */
517 static inline u32 aggr_pkt_limit_fmask(bool legacy)
519 return legacy ? GENMASK(20, 15) : GENMASK(22, 17);
522 /* The legacy value is used for IPA hardware before IPA v4.5 */
523 static inline u32 aggr_sw_eof_active_fmask(bool legacy)
525 return legacy ? GENMASK(21, 21) : GENMASK(23, 23);
528 /* The legacy value is used for IPA hardware before IPA v4.5 */
529 static inline u32 aggr_force_close_fmask(bool legacy)
531 return legacy ? GENMASK(22, 22) : GENMASK(24, 24);
534 /* The legacy value is used for IPA hardware before IPA v4.5 */
535 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy)
537 return legacy ? GENMASK(24, 24) : GENMASK(26, 26);
540 /* The next field is present for IPA v4.5+ */
541 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27)
543 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */
545 IPA_BYPASS_AGGR = 0x0, /* (TX, RX) */
546 IPA_ENABLE_AGGR = 0x1, /* (RX) */
547 IPA_ENABLE_DEAGGR = 0x2, /* (TX) */
550 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */
561 /* Valid only for RX (IPA producer) endpoints */
562 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \
563 (0x0000082c + 0x0070 * (rxep))
564 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0)
566 /* Valid only for RX (IPA producer) endpoints */
567 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \
568 (0x00000830 + 0x0070 * (rxep))
569 /* The next two fields are present for IPA v4.2 only */
570 #define BASE_VALUE_FMASK GENMASK(4, 0)
571 #define SCALE_FMASK GENMASK(12, 8)
572 /* The next two fields are present for IPA v4.5 */
573 #define TIME_LIMIT_FMASK GENMASK(4, 0)
574 #define GRAN_SEL_FMASK GENMASK(8, 8)
576 /* Valid only for TX (IPA consumer) endpoints */
577 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \
578 (0x00000834 + 0x0070 * (txep))
579 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0)
580 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6)
581 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7)
582 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8)
583 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14)
584 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16)
586 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \
587 (0x00000838 + 0x0070 * (ep))
588 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */
589 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp)
591 if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5)
592 return u32_encode_bits(rsrc_grp, GENMASK(2, 0));
594 if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7)
595 return u32_encode_bits(rsrc_grp, GENMASK(0, 0));
597 return u32_encode_bits(rsrc_grp, GENMASK(1, 0));
600 /* Valid only for TX (IPA consumer) endpoints */
601 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \
602 (0x0000083c + 0x0070 * (txep))
603 #define SEQ_TYPE_FMASK GENMASK(7, 0)
604 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8)
607 * enum ipa_seq_type - HPS and DPS sequencer type
608 * @IPA_SEQ_DMA: Perform DMA only
609 * @IPA_SEQ_1_PASS: One pass through the pipeline
610 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor
611 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor
612 * @IPA_SEQ_2_PASS: Two passes through the pipeline
613 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor
614 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined)
616 * The low-order byte of the sequencer type register defines the number of
617 * passes a packet takes through the IPA pipeline. The last pass through can
618 * optionally skip the microprocessor. Deciphering is optional for all types;
619 * if enabled, an additional mask (two bits) is added to the type value.
621 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
622 * supported (or meaningful).
626 IPA_SEQ_1_PASS = 0x02,
627 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04,
628 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06,
629 IPA_SEQ_2_PASS = 0x0a,
630 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c,
631 /* The next value can be ORed with the above */
632 IPA_SEQ_DECIPHER = 0x11,
636 * enum ipa_seq_rep_type - replicated packet sequencer type
637 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets
639 * This goes in the second byte of the endpoint sequencer type register.
641 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
642 * supported (or meaningful).
644 enum ipa_seq_rep_type {
645 IPA_SEQ_REP_DMA_PARSER = 0x08,
648 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \
649 (0x00000840 + 0x0070 * (ep))
650 #define STATUS_EN_FMASK GENMASK(0, 0)
651 #define STATUS_ENDP_FMASK GENMASK(5, 1)
652 /* The next field is not present for IPA v4.5+ */
653 #define STATUS_LOCATION_FMASK GENMASK(8, 8)
654 /* The next field is present for IPA v4.0+ */
655 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9)
657 /* The next register is not present for IPA v4.2 (which no hashing support) */
658 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \
659 (0x0000085c + 0x0070 * (er))
660 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0)
661 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1)
662 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2)
663 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3)
664 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4)
665 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5)
666 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6)
667 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0)
669 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16)
670 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17)
671 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18)
672 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19)
673 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20)
674 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21)
675 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22)
676 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16)
678 static inline u32 ipa_reg_irq_stts_ee_n_offset(enum ipa_version version,
681 if (version < IPA_VERSION_4_9)
682 return 0x00003008 + 0x1000 * ee;
684 return 0x00004008 + 0x1000 * ee;
687 static inline u32 ipa_reg_irq_stts_offset(enum ipa_version version)
689 return ipa_reg_irq_stts_ee_n_offset(version, GSI_EE_AP);
692 static inline u32 ipa_reg_irq_en_ee_n_offset(enum ipa_version version, u32 ee)
694 if (version < IPA_VERSION_4_9)
695 return 0x0000300c + 0x1000 * ee;
697 return 0x0000400c + 0x1000 * ee;
700 static inline u32 ipa_reg_irq_en_offset(enum ipa_version version)
702 return ipa_reg_irq_en_ee_n_offset(version, GSI_EE_AP);
705 static inline u32 ipa_reg_irq_clr_ee_n_offset(enum ipa_version version, u32 ee)
707 if (version < IPA_VERSION_4_9)
708 return 0x00003010 + 0x1000 * ee;
710 return 0x00004010 + 0x1000 * ee;
713 static inline u32 ipa_reg_irq_clr_offset(enum ipa_version version)
715 return ipa_reg_irq_clr_ee_n_offset(version, GSI_EE_AP);
719 * enum ipa_irq_id - Bit positions representing type of IPA IRQ
720 * @IPA_IRQ_UC_0: Microcontroller event interrupt
721 * @IPA_IRQ_UC_1: Microcontroller response interrupt
722 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt
723 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last)
725 * IRQ types not described above are not currently used.
727 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used)
728 * @IPA_IRQ_EOT_COAL: (Not currently used)
729 * @IPA_IRQ_UC_2: (Not currently used)
730 * @IPA_IRQ_UC_3: (Not currently used)
731 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used)
732 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used)
733 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used)
734 * @IPA_IRQ_RX_ERR: (Not currently used)
735 * @IPA_IRQ_DEAGGR_ERR: (Not currently used)
736 * @IPA_IRQ_TX_ERR: (Not currently used)
737 * @IPA_IRQ_STEP_MODE: (Not currently used)
738 * @IPA_IRQ_PROC_ERR: (Not currently used)
739 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used)
740 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used)
741 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used)
742 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used)
743 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used)
744 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used)
745 * @IPA_IRQ_UCP: (Not currently used)
746 * @IPA_IRQ_DCMP: (Not currently used)
747 * @IPA_IRQ_GSI_EE: (Not currently used)
748 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used)
749 * @IPA_IRQ_GSI_UC: (Not currently used)
750 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used)
751 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used)
752 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used)
753 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used)
756 IPA_IRQ_BAD_SNOC_ACCESS = 0x0,
757 /* The next bit is not present for IPA v3.5+ */
758 IPA_IRQ_EOT_COAL = 0x1,
763 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6,
764 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7,
765 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8,
766 IPA_IRQ_RX_ERR = 0x9,
767 IPA_IRQ_DEAGGR_ERR = 0xa,
768 IPA_IRQ_TX_ERR = 0xb,
769 IPA_IRQ_STEP_MODE = 0xc,
770 IPA_IRQ_PROC_ERR = 0xd,
771 IPA_IRQ_TX_SUSPEND = 0xe,
772 IPA_IRQ_TX_HOLB_DROP = 0xf,
773 IPA_IRQ_BAM_GSI_IDLE = 0x10,
774 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11,
775 IPA_IRQ_PIPE_RED_BELOW = 0x12,
776 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13,
777 IPA_IRQ_PIPE_RED_ABOVE = 0x14,
779 /* The next bit is not present for IPA v4.5+ */
781 IPA_IRQ_GSI_EE = 0x17,
782 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18,
783 IPA_IRQ_GSI_UC = 0x19,
784 /* The next bit is present for IPA v4.5+ */
785 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a,
786 /* The next three bits are present for IPA v4.9+ */
787 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b,
788 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c,
789 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d,
790 IPA_IRQ_COUNT, /* Last; not an id */
793 static inline u32 ipa_reg_irq_uc_ee_n_offset(enum ipa_version version, u32 ee)
795 if (version < IPA_VERSION_4_9)
796 return 0x0000301c + 0x1000 * ee;
798 return 0x0000401c + 0x1000 * ee;
801 static inline u32 ipa_reg_irq_uc_offset(enum ipa_version version)
803 return ipa_reg_irq_uc_ee_n_offset(version, GSI_EE_AP);
806 #define UC_INTR_FMASK GENMASK(0, 0)
808 /* ipa->available defines the valid bits in the SUSPEND_INFO register */
810 ipa_reg_irq_suspend_info_ee_n_offset(enum ipa_version version, u32 ee)
812 if (version == IPA_VERSION_3_0)
813 return 0x00003098 + 0x1000 * ee;
815 if (version < IPA_VERSION_4_9)
816 return 0x00003030 + 0x1000 * ee;
818 return 0x00004030 + 0x1000 * ee;
822 ipa_reg_irq_suspend_info_offset(enum ipa_version version)
824 return ipa_reg_irq_suspend_info_ee_n_offset(version, GSI_EE_AP);
827 /* ipa->available defines the valid bits in the SUSPEND_EN register */
829 ipa_reg_irq_suspend_en_ee_n_offset(enum ipa_version version, u32 ee)
831 /* assert(version != IPA_VERSION_3_0); */
833 if (version < IPA_VERSION_4_9)
834 return 0x00003034 + 0x1000 * ee;
836 return 0x00004034 + 0x1000 * ee;
840 ipa_reg_irq_suspend_en_offset(enum ipa_version version)
842 return ipa_reg_irq_suspend_en_ee_n_offset(version, GSI_EE_AP);
845 /* ipa->available defines the valid bits in the SUSPEND_CLR register */
847 ipa_reg_irq_suspend_clr_ee_n_offset(enum ipa_version version, u32 ee)
849 /* assert(version != IPA_VERSION_3_0); */
851 if (version < IPA_VERSION_4_9)
852 return 0x00003038 + 0x1000 * ee;
854 return 0x00004038 + 0x1000 * ee;
858 ipa_reg_irq_suspend_clr_offset(enum ipa_version version)
860 return ipa_reg_irq_suspend_clr_ee_n_offset(version, GSI_EE_AP);
863 int ipa_reg_init(struct ipa *ipa);
864 void ipa_reg_exit(struct ipa *ipa);
866 #endif /* _IPA_REG_H_ */