1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2020 Linaro Ltd.
7 #include <linux/types.h>
8 #include <linux/device.h>
9 #include <linux/slab.h>
10 #include <linux/bitfield.h>
11 #include <linux/if_rmnet.h>
12 #include <linux/dma-direction.h>
15 #include "gsi_trans.h"
18 #include "ipa_endpoint.h"
21 #include "ipa_modem.h"
22 #include "ipa_table.h"
24 #include "ipa_clock.h"
26 #define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0)
28 #define IPA_REPLENISH_BATCH 16
30 /* RX buffer is 1 page (or a power-of-2 contiguous pages) */
31 #define IPA_RX_BUFFER_SIZE 8192 /* PAGE_SIZE > 4096 wastes a LOT */
33 /* The amount of RX buffer space consumed by standard skb overhead */
34 #define IPA_RX_BUFFER_OVERHEAD (PAGE_SIZE - SKB_MAX_ORDER(NET_SKB_PAD, 0))
36 /* Where to find the QMAP mux_id for a packet within modem-supplied metadata */
37 #define IPA_ENDPOINT_QMAP_METADATA_MASK 0x000000ff /* host byte order */
39 #define IPA_ENDPOINT_RESET_AGGR_RETRY_MAX 3
40 #define IPA_AGGR_TIME_LIMIT 500 /* microseconds */
42 /** enum ipa_status_opcode - status element opcode hardware values */
43 enum ipa_status_opcode {
44 IPA_STATUS_OPCODE_PACKET = 0x01,
45 IPA_STATUS_OPCODE_DROPPED_PACKET = 0x04,
46 IPA_STATUS_OPCODE_SUSPENDED_PACKET = 0x08,
47 IPA_STATUS_OPCODE_PACKET_2ND_PASS = 0x40,
50 /** enum ipa_status_exception - status element exception type */
51 enum ipa_status_exception {
52 /* 0 means no exception */
53 IPA_STATUS_EXCEPTION_DEAGGR = 0x01,
56 /* Status element provided by hardware */
58 u8 opcode; /* enum ipa_status_opcode */
59 u8 exception; /* enum ipa_status_exception */
71 /* Field masks for struct ipa_status structure fields */
72 #define IPA_STATUS_DST_IDX_FMASK GENMASK(4, 0)
73 #define IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK GENMASK(31, 22)
77 static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count,
78 const struct ipa_gsi_endpoint_data *all_data,
79 const struct ipa_gsi_endpoint_data *data)
81 const struct ipa_gsi_endpoint_data *other_data;
82 struct device *dev = &ipa->pdev->dev;
83 enum ipa_endpoint_name other_name;
85 if (ipa_gsi_endpoint_data_empty(data))
88 if (!data->toward_ipa) {
89 if (data->endpoint.filter_support) {
90 dev_err(dev, "filtering not supported for "
96 return true; /* Nothing more to check for RX */
99 if (data->endpoint.config.status_enable) {
100 other_name = data->endpoint.config.tx.status_endpoint;
101 if (other_name >= count) {
102 dev_err(dev, "status endpoint name %u out of range "
104 other_name, data->endpoint_id);
108 /* Status endpoint must be defined... */
109 other_data = &all_data[other_name];
110 if (ipa_gsi_endpoint_data_empty(other_data)) {
111 dev_err(dev, "DMA endpoint name %u undefined "
113 other_name, data->endpoint_id);
117 /* ...and has to be an RX endpoint... */
118 if (other_data->toward_ipa) {
120 "status endpoint for endpoint %u not RX\n",
125 /* ...and if it's to be an AP endpoint... */
126 if (other_data->ee_id == GSI_EE_AP) {
127 /* ...make sure it has status enabled. */
128 if (!other_data->endpoint.config.status_enable) {
130 "status not enabled for endpoint %u\n",
131 other_data->endpoint_id);
137 if (data->endpoint.config.dma_mode) {
138 other_name = data->endpoint.config.dma_endpoint;
139 if (other_name >= count) {
140 dev_err(dev, "DMA endpoint name %u out of range "
142 other_name, data->endpoint_id);
146 other_data = &all_data[other_name];
147 if (ipa_gsi_endpoint_data_empty(other_data)) {
148 dev_err(dev, "DMA endpoint name %u undefined "
150 other_name, data->endpoint_id);
158 static u32 aggr_byte_limit_max(enum ipa_version version)
160 if (version < IPA_VERSION_4_5)
161 return field_max(aggr_byte_limit_fmask(true));
163 return field_max(aggr_byte_limit_fmask(false));
166 static bool ipa_endpoint_data_valid(struct ipa *ipa, u32 count,
167 const struct ipa_gsi_endpoint_data *data)
169 const struct ipa_gsi_endpoint_data *dp = data;
170 struct device *dev = &ipa->pdev->dev;
171 enum ipa_endpoint_name name;
174 /* Not sure where this constraint come from... */
175 BUILD_BUG_ON(sizeof(struct ipa_status) % 4);
177 if (count > IPA_ENDPOINT_COUNT) {
178 dev_err(dev, "too many endpoints specified (%u > %u)\n",
179 count, IPA_ENDPOINT_COUNT);
183 /* The aggregation byte limit defines the point at which an
184 * aggregation window will close. It is programmed into the
185 * IPA hardware as a number of KB. We don't use "hard byte
186 * limit" aggregation, which means that we need to supply
187 * enough space in a receive buffer to hold a complete MTU
188 * plus normal skb overhead *after* that aggregation byte
189 * limit has been crossed.
191 * This check ensures we don't define a receive buffer size
192 * that would exceed what we can represent in the field that
193 * is used to program its size.
195 limit = aggr_byte_limit_max(ipa->version) * SZ_1K;
196 limit += IPA_MTU + IPA_RX_BUFFER_OVERHEAD;
197 if (limit < IPA_RX_BUFFER_SIZE) {
198 dev_err(dev, "buffer size too big for aggregation (%u > %u)\n",
199 IPA_RX_BUFFER_SIZE, limit);
203 /* Make sure needed endpoints have defined data */
204 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_COMMAND_TX])) {
205 dev_err(dev, "command TX endpoint not defined\n");
208 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_LAN_RX])) {
209 dev_err(dev, "LAN RX endpoint not defined\n");
212 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_TX])) {
213 dev_err(dev, "AP->modem TX endpoint not defined\n");
216 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_RX])) {
217 dev_err(dev, "AP<-modem RX endpoint not defined\n");
221 for (name = 0; name < count; name++, dp++)
222 if (!ipa_endpoint_data_valid_one(ipa, count, data, dp))
228 #else /* !IPA_VALIDATE */
230 static bool ipa_endpoint_data_valid(struct ipa *ipa, u32 count,
231 const struct ipa_gsi_endpoint_data *data)
236 #endif /* !IPA_VALIDATE */
238 /* Allocate a transaction to use on a non-command endpoint */
239 static struct gsi_trans *ipa_endpoint_trans_alloc(struct ipa_endpoint *endpoint,
242 struct gsi *gsi = &endpoint->ipa->gsi;
243 u32 channel_id = endpoint->channel_id;
244 enum dma_data_direction direction;
246 direction = endpoint->toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
248 return gsi_channel_trans_alloc(gsi, channel_id, tre_count, direction);
251 /* suspend_delay represents suspend for RX, delay for TX endpoints.
252 * Note that suspend is not supported starting with IPA v4.0.
255 ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
257 u32 offset = IPA_REG_ENDP_INIT_CTRL_N_OFFSET(endpoint->endpoint_id);
258 struct ipa *ipa = endpoint->ipa;
263 /* Suspend is not supported for IPA v4.0+. Delay doesn't work
264 * correctly on IPA v4.2.
266 * if (endpoint->toward_ipa)
267 * assert(ipa->version != IPA_VERSION_4.2);
269 * assert(ipa->version == IPA_VERSION_3_5_1);
271 mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK;
273 val = ioread32(ipa->reg_virt + offset);
274 /* Don't bother if it's already in the requested state */
275 state = !!(val & mask);
276 if (suspend_delay != state) {
278 iowrite32(val, ipa->reg_virt + offset);
284 /* We currently don't care what the previous state was for delay mode */
286 ipa_endpoint_program_delay(struct ipa_endpoint *endpoint, bool enable)
288 /* assert(endpoint->toward_ipa); */
290 /* Delay mode doesn't work properly for IPA v4.2 */
291 if (endpoint->ipa->version != IPA_VERSION_4_2)
292 (void)ipa_endpoint_init_ctrl(endpoint, enable);
295 static bool ipa_endpoint_aggr_active(struct ipa_endpoint *endpoint)
297 u32 mask = BIT(endpoint->endpoint_id);
298 struct ipa *ipa = endpoint->ipa;
302 /* assert(mask & ipa->available); */
303 offset = ipa_reg_state_aggr_active_offset(ipa->version);
304 val = ioread32(ipa->reg_virt + offset);
306 return !!(val & mask);
309 static void ipa_endpoint_force_close(struct ipa_endpoint *endpoint)
311 u32 mask = BIT(endpoint->endpoint_id);
312 struct ipa *ipa = endpoint->ipa;
314 /* assert(mask & ipa->available); */
315 iowrite32(mask, ipa->reg_virt + IPA_REG_AGGR_FORCE_CLOSE_OFFSET);
319 * ipa_endpoint_suspend_aggr() - Emulate suspend interrupt
320 * @endpoint: Endpoint on which to emulate a suspend
322 * Emulate suspend IPA interrupt to unsuspend an endpoint suspended
323 * with an open aggregation frame. This is to work around a hardware
324 * issue in IPA version 3.5.1 where the suspend interrupt will not be
325 * generated when it should be.
327 static void ipa_endpoint_suspend_aggr(struct ipa_endpoint *endpoint)
329 struct ipa *ipa = endpoint->ipa;
331 if (!endpoint->data->aggregation)
334 /* Nothing to do if the endpoint doesn't have aggregation open */
335 if (!ipa_endpoint_aggr_active(endpoint))
338 /* Force close aggregation */
339 ipa_endpoint_force_close(endpoint);
341 ipa_interrupt_simulate_suspend(ipa->interrupt);
344 /* Returns previous suspend state (true means suspend was enabled) */
346 ipa_endpoint_program_suspend(struct ipa_endpoint *endpoint, bool enable)
350 if (endpoint->ipa->version != IPA_VERSION_3_5_1)
351 return enable; /* For IPA v4.0+, no change made */
353 /* assert(!endpoint->toward_ipa); */
355 suspended = ipa_endpoint_init_ctrl(endpoint, enable);
357 /* A client suspended with an open aggregation frame will not
358 * generate a SUSPEND IPA interrupt. If enabling suspend, have
359 * ipa_endpoint_suspend_aggr() handle this.
361 if (enable && !suspended)
362 ipa_endpoint_suspend_aggr(endpoint);
367 /* Enable or disable delay or suspend mode on all modem endpoints */
368 void ipa_endpoint_modem_pause_all(struct ipa *ipa, bool enable)
372 /* DELAY mode doesn't work correctly on IPA v4.2 */
373 if (ipa->version == IPA_VERSION_4_2)
376 for (endpoint_id = 0; endpoint_id < IPA_ENDPOINT_MAX; endpoint_id++) {
377 struct ipa_endpoint *endpoint = &ipa->endpoint[endpoint_id];
379 if (endpoint->ee_id != GSI_EE_MODEM)
382 /* Set TX delay mode or RX suspend mode */
383 if (endpoint->toward_ipa)
384 ipa_endpoint_program_delay(endpoint, enable);
386 (void)ipa_endpoint_program_suspend(endpoint, enable);
390 /* Reset all modem endpoints to use the default exception endpoint */
391 int ipa_endpoint_modem_exception_reset_all(struct ipa *ipa)
393 u32 initialized = ipa->initialized;
394 struct gsi_trans *trans;
397 /* We need one command per modem TX endpoint. We can get an upper
398 * bound on that by assuming all initialized endpoints are modem->IPA.
399 * That won't happen, and we could be more precise, but this is fine
400 * for now. We need to end the transaction with a "tag process."
402 count = hweight32(initialized) + ipa_cmd_tag_process_count();
403 trans = ipa_cmd_trans_alloc(ipa, count);
405 dev_err(&ipa->pdev->dev,
406 "no transaction to reset modem exception endpoints\n");
410 while (initialized) {
411 u32 endpoint_id = __ffs(initialized);
412 struct ipa_endpoint *endpoint;
415 initialized ^= BIT(endpoint_id);
417 /* We only reset modem TX endpoints */
418 endpoint = &ipa->endpoint[endpoint_id];
419 if (!(endpoint->ee_id == GSI_EE_MODEM && endpoint->toward_ipa))
422 offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id);
424 /* Value written is 0, and all bits are updated. That
425 * means status is disabled on the endpoint, and as a
426 * result all other fields in the register are ignored.
428 ipa_cmd_register_write_add(trans, offset, 0, ~0, false);
431 ipa_cmd_tag_process_add(trans);
433 /* XXX This should have a 1 second timeout */
434 gsi_trans_commit_wait(trans);
439 static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
441 u32 offset = IPA_REG_ENDP_INIT_CFG_N_OFFSET(endpoint->endpoint_id);
444 /* FRAG_OFFLOAD_EN is 0 */
445 if (endpoint->data->checksum) {
446 if (endpoint->toward_ipa) {
449 val |= u32_encode_bits(IPA_CS_OFFLOAD_UL,
450 CS_OFFLOAD_EN_FMASK);
451 /* Checksum header offset is in 4-byte units */
452 checksum_offset = sizeof(struct rmnet_map_header);
453 checksum_offset /= sizeof(u32);
454 val |= u32_encode_bits(checksum_offset,
455 CS_METADATA_HDR_OFFSET_FMASK);
457 val |= u32_encode_bits(IPA_CS_OFFLOAD_DL,
458 CS_OFFLOAD_EN_FMASK);
461 val |= u32_encode_bits(IPA_CS_OFFLOAD_NONE,
462 CS_OFFLOAD_EN_FMASK);
464 /* CS_GEN_QMB_MASTER_SEL is 0 */
466 iowrite32(val, endpoint->ipa->reg_virt + offset);
470 * ipa_endpoint_init_hdr() - Initialize HDR endpoint configuration register
471 * @endpoint: Endpoint pointer
473 * We program QMAP endpoints so each packet received is preceded by a QMAP
474 * header structure. The QMAP header contains a 1-byte mux_id and 2-byte
475 * packet size field, and we have the IPA hardware populate both for each
476 * received packet. The header is configured (in the HDR_EXT register)
477 * to use big endian format.
479 * The packet size is written into the QMAP header's pkt_len field. That
480 * location is defined here using the HDR_OFST_PKT_SIZE field.
482 * The mux_id comes from a 4-byte metadata value supplied with each packet
483 * by the modem. It is *not* a QMAP header, but it does contain the mux_id
484 * value that we want, in its low-order byte. A bitmask defined in the
485 * endpoint's METADATA_MASK register defines which byte within the modem
486 * metadata contains the mux_id. And the OFST_METADATA field programmed
487 * here indicates where the extracted byte should be placed within the QMAP
490 static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
492 u32 offset = IPA_REG_ENDP_INIT_HDR_N_OFFSET(endpoint->endpoint_id);
493 struct ipa *ipa = endpoint->ipa;
496 if (endpoint->data->qmap) {
497 size_t header_size = sizeof(struct rmnet_map_header);
498 enum ipa_version version = ipa->version;
500 /* We might supply a checksum header after the QMAP header */
501 if (endpoint->toward_ipa && endpoint->data->checksum)
502 header_size += sizeof(struct rmnet_map_ul_csum_header);
503 val |= ipa_header_size_encoded(version, header_size);
505 /* Define how to fill fields in a received QMAP header */
506 if (!endpoint->toward_ipa) {
507 u32 offset; /* Field offset within header */
509 /* Where IPA will write the metadata value */
510 offset = offsetof(struct rmnet_map_header, mux_id);
511 val |= ipa_metadata_offset_encoded(version, offset);
513 /* Where IPA will write the length */
514 offset = offsetof(struct rmnet_map_header, pkt_len);
515 /* Upper bits are stored in HDR_EXT with IPA v4.5 */
516 if (version == IPA_VERSION_4_5)
517 offset &= field_mask(HDR_OFST_PKT_SIZE_FMASK);
519 val |= HDR_OFST_PKT_SIZE_VALID_FMASK;
520 val |= u32_encode_bits(offset, HDR_OFST_PKT_SIZE_FMASK);
522 /* For QMAP TX, metadata offset is 0 (modem assumes this) */
523 val |= HDR_OFST_METADATA_VALID_FMASK;
525 /* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */
526 /* HDR_A5_MUX is 0 */
527 /* HDR_LEN_INC_DEAGG_HDR is 0 */
528 /* HDR_METADATA_REG_VALID is 0 (TX only, version < v4.5) */
531 iowrite32(val, ipa->reg_virt + offset);
534 static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
536 u32 offset = IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(endpoint->endpoint_id);
537 u32 pad_align = endpoint->data->rx.pad_align;
538 struct ipa *ipa = endpoint->ipa;
541 val |= HDR_ENDIANNESS_FMASK; /* big endian */
543 /* A QMAP header contains a 6 bit pad field at offset 0. The RMNet
544 * driver assumes this field is meaningful in packets it receives,
545 * and assumes the header's payload length includes that padding.
546 * The RMNet driver does *not* pad packets it sends, however, so
547 * the pad field (although 0) should be ignored.
549 if (endpoint->data->qmap && !endpoint->toward_ipa) {
550 val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK;
551 /* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */
552 val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK;
553 /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */
556 /* HDR_PAYLOAD_LEN_INC_PADDING is 0 */
557 if (!endpoint->toward_ipa)
558 val |= u32_encode_bits(pad_align, HDR_PAD_TO_ALIGNMENT_FMASK);
560 /* IPA v4.5 adds some most-significant bits to a few fields,
561 * two of which are defined in the HDR (not HDR_EXT) register.
563 if (ipa->version == IPA_VERSION_4_5) {
564 /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */
565 if (endpoint->data->qmap && !endpoint->toward_ipa) {
568 offset = offsetof(struct rmnet_map_header, pkt_len);
569 offset >>= hweight32(HDR_OFST_PKT_SIZE_FMASK);
570 val |= u32_encode_bits(offset,
571 HDR_OFST_PKT_SIZE_MSB_FMASK);
572 /* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */
575 iowrite32(val, ipa->reg_virt + offset);
578 static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
580 u32 endpoint_id = endpoint->endpoint_id;
584 if (endpoint->toward_ipa)
585 return; /* Register not valid for TX endpoints */
587 offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id);
589 /* Note that HDR_ENDIANNESS indicates big endian header fields */
590 if (endpoint->data->qmap)
591 val = cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK);
593 iowrite32(val, endpoint->ipa->reg_virt + offset);
596 static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
598 u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id);
601 if (!endpoint->toward_ipa)
602 return; /* Register not valid for RX endpoints */
604 if (endpoint->data->dma_mode) {
605 enum ipa_endpoint_name name = endpoint->data->dma_endpoint;
608 dma_endpoint_id = endpoint->ipa->name_map[name]->endpoint_id;
610 val = u32_encode_bits(IPA_DMA, MODE_FMASK);
611 val |= u32_encode_bits(dma_endpoint_id, DEST_PIPE_INDEX_FMASK);
613 val = u32_encode_bits(IPA_BASIC, MODE_FMASK);
615 /* All other bits unspecified (and 0) */
617 iowrite32(val, endpoint->ipa->reg_virt + offset);
620 /* Compute the aggregation size value to use for a given buffer size */
621 static u32 ipa_aggr_size_kb(u32 rx_buffer_size)
623 /* We don't use "hard byte limit" aggregation, so we define the
624 * aggregation limit such that our buffer has enough space *after*
625 * that limit to receive a full MTU of data, plus overhead.
627 rx_buffer_size -= IPA_MTU + IPA_RX_BUFFER_OVERHEAD;
629 return rx_buffer_size / SZ_1K;
632 /* Encoded values for AGGR endpoint register fields */
633 static u32 aggr_byte_limit_encoded(enum ipa_version version, u32 limit)
635 if (version < IPA_VERSION_4_5)
636 return u32_encode_bits(limit, aggr_byte_limit_fmask(true));
638 return u32_encode_bits(limit, aggr_byte_limit_fmask(false));
641 /* Encode the aggregation timer limit (microseconds) based on IPA version */
642 static u32 aggr_time_limit_encoded(enum ipa_version version, u32 limit)
648 if (version < IPA_VERSION_4_5) {
649 /* We set aggregation granularity in ipa_hardware_config() */
650 limit = DIV_ROUND_CLOSEST(limit, IPA_AGGR_GRANULARITY);
652 return u32_encode_bits(limit, aggr_time_limit_fmask(true));
655 /* IPA v4.5 expresses the time limit using Qtime. The AP has
656 * pulse generators 0 and 1 available, which were configured
657 * in ipa_qtime_config() to have granularity 100 usec and
658 * 1 msec, respectively. Use pulse generator 0 if possible,
659 * otherwise fall back to pulse generator 1.
661 fmask = aggr_time_limit_fmask(false);
662 val = DIV_ROUND_CLOSEST(limit, 100);
663 if (val > field_max(fmask)) {
664 /* Have to use pulse generator 1 (millisecond granularity) */
665 gran_sel = AGGR_GRAN_SEL_FMASK;
666 val = DIV_ROUND_CLOSEST(limit, 1000);
668 /* We can use pulse generator 0 (100 usec granularity) */
672 return gran_sel | u32_encode_bits(val, fmask);
675 static u32 aggr_sw_eof_active_encoded(enum ipa_version version, bool enabled)
677 u32 val = enabled ? 1 : 0;
679 if (version < IPA_VERSION_4_5)
680 return u32_encode_bits(val, aggr_sw_eof_active_fmask(true));
682 return u32_encode_bits(val, aggr_sw_eof_active_fmask(false));
685 static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
687 u32 offset = IPA_REG_ENDP_INIT_AGGR_N_OFFSET(endpoint->endpoint_id);
688 enum ipa_version version = endpoint->ipa->version;
691 if (endpoint->data->aggregation) {
692 if (!endpoint->toward_ipa) {
696 val |= u32_encode_bits(IPA_ENABLE_AGGR, AGGR_EN_FMASK);
697 val |= u32_encode_bits(IPA_GENERIC, AGGR_TYPE_FMASK);
699 limit = ipa_aggr_size_kb(IPA_RX_BUFFER_SIZE);
700 val |= aggr_byte_limit_encoded(version, limit);
702 limit = IPA_AGGR_TIME_LIMIT;
703 val |= aggr_time_limit_encoded(version, limit);
705 /* AGGR_PKT_LIMIT is 0 (unlimited) */
707 close_eof = endpoint->data->rx.aggr_close_eof;
708 val |= aggr_sw_eof_active_encoded(version, close_eof);
710 /* AGGR_HARD_BYTE_LIMIT_ENABLE is 0 */
712 val |= u32_encode_bits(IPA_ENABLE_DEAGGR,
714 val |= u32_encode_bits(IPA_QCMAP, AGGR_TYPE_FMASK);
715 /* other fields ignored */
717 /* AGGR_FORCE_CLOSE is 0 */
718 /* AGGR_GRAN_SEL is 0 for IPA v4.5 */
720 val |= u32_encode_bits(IPA_BYPASS_AGGR, AGGR_EN_FMASK);
721 /* other fields ignored */
724 iowrite32(val, endpoint->ipa->reg_virt + offset);
727 /* Return the Qtime-based head-of-line blocking timer value that
728 * represents the given number of microseconds. The result
729 * includes both the timer value and the selected timer granularity.
731 static u32 hol_block_timer_qtime_val(struct ipa *ipa, u32 microseconds)
736 /* IPA v4.5 expresses time limits using Qtime. The AP has
737 * pulse generators 0 and 1 available, which were configured
738 * in ipa_qtime_config() to have granularity 100 usec and
739 * 1 msec, respectively. Use pulse generator 0 if possible,
740 * otherwise fall back to pulse generator 1.
742 val = DIV_ROUND_CLOSEST(microseconds, 100);
743 if (val > field_max(TIME_LIMIT_FMASK)) {
744 /* Have to use pulse generator 1 (millisecond granularity) */
745 gran_sel = GRAN_SEL_FMASK;
746 val = DIV_ROUND_CLOSEST(microseconds, 1000);
748 /* We can use pulse generator 0 (100 usec granularity) */
752 return gran_sel | u32_encode_bits(val, TIME_LIMIT_FMASK);
755 /* The head-of-line blocking timer is defined as a tick count. For
756 * IPA version 4.5 the tick count is based on the Qtimer, which is
757 * derived from the 19.2 MHz SoC XO clock. For older IPA versions
758 * each tick represents 128 cycles of the IPA core clock.
760 * Return the encoded value that should be written to that register
761 * that represents the timeout period provided. For IPA v4.2 this
762 * encodes a base and scale value, while for earlier versions the
763 * value is a simple tick count.
765 static u32 hol_block_timer_val(struct ipa *ipa, u32 microseconds)
775 return 0; /* Nothing to compute if timer period is 0 */
777 if (ipa->version == IPA_VERSION_4_5)
778 return hol_block_timer_qtime_val(ipa, microseconds);
780 /* Use 64 bit arithmetic to avoid overflow... */
781 rate = ipa_clock_rate(ipa);
782 ticks = DIV_ROUND_CLOSEST(microseconds * rate, 128 * USEC_PER_SEC);
783 /* ...but we still need to fit into a 32-bit register */
784 WARN_ON(ticks > U32_MAX);
786 /* IPA v3.5.1 through v4.1 just record the tick count */
787 if (ipa->version < IPA_VERSION_4_2)
790 /* For IPA v4.2, the tick count is represented by base and
791 * scale fields within the 32-bit timer register, where:
792 * ticks = base << scale;
793 * The best precision is achieved when the base value is as
794 * large as possible. Find the highest set bit in the tick
795 * count, and extract the number of bits in the base field
796 * such that that high bit is included.
798 high = fls(ticks); /* 1..32 */
799 width = HWEIGHT32(BASE_VALUE_FMASK);
800 scale = high > width ? high - width : 0;
802 /* If we're scaling, round up to get a closer result */
803 ticks += 1 << (scale - 1);
804 /* High bit was set, so rounding might have affected it */
805 if (fls(ticks) != high)
809 val = u32_encode_bits(scale, SCALE_FMASK);
810 val |= u32_encode_bits(ticks >> scale, BASE_VALUE_FMASK);
815 /* If microseconds is 0, timeout is immediate */
816 static void ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint,
819 u32 endpoint_id = endpoint->endpoint_id;
820 struct ipa *ipa = endpoint->ipa;
824 offset = IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(endpoint_id);
825 val = hol_block_timer_val(ipa, microseconds);
826 iowrite32(val, ipa->reg_virt + offset);
830 ipa_endpoint_init_hol_block_enable(struct ipa_endpoint *endpoint, bool enable)
832 u32 endpoint_id = endpoint->endpoint_id;
836 val = enable ? HOL_BLOCK_EN_FMASK : 0;
837 offset = IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(endpoint_id);
838 iowrite32(val, endpoint->ipa->reg_virt + offset);
841 void ipa_endpoint_modem_hol_block_clear_all(struct ipa *ipa)
845 for (i = 0; i < IPA_ENDPOINT_MAX; i++) {
846 struct ipa_endpoint *endpoint = &ipa->endpoint[i];
848 if (endpoint->toward_ipa || endpoint->ee_id != GSI_EE_MODEM)
851 ipa_endpoint_init_hol_block_timer(endpoint, 0);
852 ipa_endpoint_init_hol_block_enable(endpoint, true);
856 static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint)
858 u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id);
861 if (!endpoint->toward_ipa)
862 return; /* Register not valid for RX endpoints */
864 /* DEAGGR_HDR_LEN is 0 */
865 /* PACKET_OFFSET_VALID is 0 */
866 /* PACKET_OFFSET_LOCATION is ignored (not valid) */
867 /* MAX_PACKET_LEN is 0 (not enforced) */
869 iowrite32(val, endpoint->ipa->reg_virt + offset);
872 static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint)
874 u32 offset = IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(endpoint->endpoint_id);
875 struct ipa *ipa = endpoint->ipa;
878 val = rsrc_grp_encoded(ipa->version, endpoint->data->resource_group);
879 iowrite32(val, ipa->reg_virt + offset);
882 static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
884 u32 offset = IPA_REG_ENDP_INIT_SEQ_N_OFFSET(endpoint->endpoint_id);
885 u32 seq_type = endpoint->seq_type;
888 if (!endpoint->toward_ipa)
889 return; /* Register not valid for RX endpoints */
891 /* Sequencer type is made up of four nibbles */
892 val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK);
893 val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK);
894 /* The second two apply to replicated packets */
895 val |= u32_encode_bits((seq_type >> 8) & 0xf, HPS_REP_SEQ_TYPE_FMASK);
896 val |= u32_encode_bits((seq_type >> 12) & 0xf, DPS_REP_SEQ_TYPE_FMASK);
898 iowrite32(val, endpoint->ipa->reg_virt + offset);
902 * ipa_endpoint_skb_tx() - Transmit a socket buffer
903 * @endpoint: Endpoint pointer
904 * @skb: Socket buffer to send
906 * Returns: 0 if successful, or a negative error code
908 int ipa_endpoint_skb_tx(struct ipa_endpoint *endpoint, struct sk_buff *skb)
910 struct gsi_trans *trans;
914 /* Make sure source endpoint's TLV FIFO has enough entries to
915 * hold the linear portion of the skb and all its fragments.
916 * If not, see if we can linearize it before giving up.
918 nr_frags = skb_shinfo(skb)->nr_frags;
919 if (1 + nr_frags > endpoint->trans_tre_max) {
920 if (skb_linearize(skb))
925 trans = ipa_endpoint_trans_alloc(endpoint, 1 + nr_frags);
929 ret = gsi_trans_skb_add(trans, skb);
932 trans->data = skb; /* transaction owns skb now */
934 gsi_trans_commit(trans, !netdev_xmit_more());
939 gsi_trans_free(trans);
944 static void ipa_endpoint_status(struct ipa_endpoint *endpoint)
946 u32 endpoint_id = endpoint->endpoint_id;
947 struct ipa *ipa = endpoint->ipa;
951 offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id);
953 if (endpoint->data->status_enable) {
954 val |= STATUS_EN_FMASK;
955 if (endpoint->toward_ipa) {
956 enum ipa_endpoint_name name;
957 u32 status_endpoint_id;
959 name = endpoint->data->tx.status_endpoint;
960 status_endpoint_id = ipa->name_map[name]->endpoint_id;
962 val |= u32_encode_bits(status_endpoint_id,
965 /* STATUS_LOCATION is 0, meaning status element precedes
966 * packet (not present for IPA v4.5)
968 /* STATUS_PKT_SUPPRESS_FMASK is 0 (not present for v3.5.1) */
971 iowrite32(val, ipa->reg_virt + offset);
974 static int ipa_endpoint_replenish_one(struct ipa_endpoint *endpoint)
976 struct gsi_trans *trans;
977 bool doorbell = false;
983 page = dev_alloc_pages(get_order(IPA_RX_BUFFER_SIZE));
987 trans = ipa_endpoint_trans_alloc(endpoint, 1);
991 /* Offset the buffer to make space for skb headroom */
992 offset = NET_SKB_PAD;
993 len = IPA_RX_BUFFER_SIZE - offset;
995 ret = gsi_trans_page_add(trans, page, len, offset);
998 trans->data = page; /* transaction owns page now */
1000 if (++endpoint->replenish_ready == IPA_REPLENISH_BATCH) {
1002 endpoint->replenish_ready = 0;
1005 gsi_trans_commit(trans, doorbell);
1010 gsi_trans_free(trans);
1012 __free_pages(page, get_order(IPA_RX_BUFFER_SIZE));
1018 * ipa_endpoint_replenish() - Replenish the Rx packets cache.
1019 * @endpoint: Endpoint to be replenished
1020 * @count: Number of buffers to send to hardware
1022 * Allocate RX packet wrapper structures with maximal socket buffers
1023 * for an endpoint. These are supplied to the hardware, which fills
1024 * them with incoming data.
1026 static void ipa_endpoint_replenish(struct ipa_endpoint *endpoint, u32 count)
1031 if (!endpoint->replenish_enabled) {
1033 atomic_add(count, &endpoint->replenish_saved);
1038 while (atomic_dec_not_zero(&endpoint->replenish_backlog))
1039 if (ipa_endpoint_replenish_one(endpoint))
1040 goto try_again_later;
1042 atomic_add(count, &endpoint->replenish_backlog);
1047 /* The last one didn't succeed, so fix the backlog */
1048 backlog = atomic_inc_return(&endpoint->replenish_backlog);
1051 atomic_add(count, &endpoint->replenish_backlog);
1053 /* Whenever a receive buffer transaction completes we'll try to
1054 * replenish again. It's unlikely, but if we fail to supply even
1055 * one buffer, nothing will trigger another replenish attempt.
1056 * Receive buffer transactions use one TRE, so schedule work to
1057 * try replenishing again if our backlog is *all* available TREs.
1059 gsi = &endpoint->ipa->gsi;
1060 if (backlog == gsi_channel_tre_max(gsi, endpoint->channel_id))
1061 schedule_delayed_work(&endpoint->replenish_work,
1062 msecs_to_jiffies(1));
1065 static void ipa_endpoint_replenish_enable(struct ipa_endpoint *endpoint)
1067 struct gsi *gsi = &endpoint->ipa->gsi;
1071 endpoint->replenish_enabled = true;
1072 while ((saved = atomic_xchg(&endpoint->replenish_saved, 0)))
1073 atomic_add(saved, &endpoint->replenish_backlog);
1075 /* Start replenishing if hardware currently has no buffers */
1076 max_backlog = gsi_channel_tre_max(gsi, endpoint->channel_id);
1077 if (atomic_read(&endpoint->replenish_backlog) == max_backlog)
1078 ipa_endpoint_replenish(endpoint, 0);
1081 static void ipa_endpoint_replenish_disable(struct ipa_endpoint *endpoint)
1085 endpoint->replenish_enabled = false;
1086 while ((backlog = atomic_xchg(&endpoint->replenish_backlog, 0)))
1087 atomic_add(backlog, &endpoint->replenish_saved);
1090 static void ipa_endpoint_replenish_work(struct work_struct *work)
1092 struct delayed_work *dwork = to_delayed_work(work);
1093 struct ipa_endpoint *endpoint;
1095 endpoint = container_of(dwork, struct ipa_endpoint, replenish_work);
1097 ipa_endpoint_replenish(endpoint, 0);
1100 static void ipa_endpoint_skb_copy(struct ipa_endpoint *endpoint,
1101 void *data, u32 len, u32 extra)
1103 struct sk_buff *skb;
1105 skb = __dev_alloc_skb(len, GFP_ATOMIC);
1108 memcpy(skb->data, data, len);
1109 skb->truesize += extra;
1112 /* Now receive it, or drop it if there's no netdev */
1113 if (endpoint->netdev)
1114 ipa_modem_skb_rx(endpoint->netdev, skb);
1116 dev_kfree_skb_any(skb);
1119 static bool ipa_endpoint_skb_build(struct ipa_endpoint *endpoint,
1120 struct page *page, u32 len)
1122 struct sk_buff *skb;
1124 /* Nothing to do if there's no netdev */
1125 if (!endpoint->netdev)
1128 /* assert(len <= SKB_WITH_OVERHEAD(IPA_RX_BUFFER_SIZE-NET_SKB_PAD)); */
1129 skb = build_skb(page_address(page), IPA_RX_BUFFER_SIZE);
1131 /* Reserve the headroom and account for the data */
1132 skb_reserve(skb, NET_SKB_PAD);
1136 /* Receive the buffer (or record drop if unable to build it) */
1137 ipa_modem_skb_rx(endpoint->netdev, skb);
1142 /* The format of a packet status element is the same for several status
1143 * types (opcodes). Other types aren't currently supported.
1145 static bool ipa_status_format_packet(enum ipa_status_opcode opcode)
1148 case IPA_STATUS_OPCODE_PACKET:
1149 case IPA_STATUS_OPCODE_DROPPED_PACKET:
1150 case IPA_STATUS_OPCODE_SUSPENDED_PACKET:
1151 case IPA_STATUS_OPCODE_PACKET_2ND_PASS:
1158 static bool ipa_endpoint_status_skip(struct ipa_endpoint *endpoint,
1159 const struct ipa_status *status)
1163 if (!ipa_status_format_packet(status->opcode))
1165 if (!status->pkt_len)
1167 endpoint_id = u32_get_bits(status->endp_dst_idx,
1168 IPA_STATUS_DST_IDX_FMASK);
1169 if (endpoint_id != endpoint->endpoint_id)
1172 return false; /* Don't skip this packet, process it */
1175 /* Return whether the status indicates the packet should be dropped */
1176 static bool ipa_status_drop_packet(const struct ipa_status *status)
1180 /* Deaggregation exceptions we drop; all other types we consume */
1181 if (status->exception)
1182 return status->exception == IPA_STATUS_EXCEPTION_DEAGGR;
1184 /* Drop the packet if it fails to match a routing rule; otherwise no */
1185 val = le32_get_bits(status->flags1, IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK);
1187 return val == field_max(IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK);
1190 static void ipa_endpoint_status_parse(struct ipa_endpoint *endpoint,
1191 struct page *page, u32 total_len)
1193 void *data = page_address(page) + NET_SKB_PAD;
1194 u32 unused = IPA_RX_BUFFER_SIZE - total_len;
1195 u32 resid = total_len;
1198 const struct ipa_status *status = data;
1202 if (resid < sizeof(*status)) {
1203 dev_err(&endpoint->ipa->pdev->dev,
1204 "short message (%u bytes < %zu byte status)\n",
1205 resid, sizeof(*status));
1209 /* Skip over status packets that lack packet data */
1210 if (ipa_endpoint_status_skip(endpoint, status)) {
1211 data += sizeof(*status);
1212 resid -= sizeof(*status);
1216 /* Compute the amount of buffer space consumed by the
1217 * packet, including the status element. If the hardware
1218 * is configured to pad packet data to an aligned boundary,
1219 * account for that. And if checksum offload is is enabled
1220 * a trailer containing computed checksum information will
1223 align = endpoint->data->rx.pad_align ? : 1;
1224 len = le16_to_cpu(status->pkt_len);
1225 len = sizeof(*status) + ALIGN(len, align);
1226 if (endpoint->data->checksum)
1227 len += sizeof(struct rmnet_map_dl_csum_trailer);
1229 /* Charge the new packet with a proportional fraction of
1230 * the unused space in the original receive buffer.
1231 * XXX Charge a proportion of the *whole* receive buffer?
1233 if (!ipa_status_drop_packet(status)) {
1234 u32 extra = unused * len / total_len;
1235 void *data2 = data + sizeof(*status);
1236 u32 len2 = le16_to_cpu(status->pkt_len);
1238 /* Client receives only packet data (no status) */
1239 ipa_endpoint_skb_copy(endpoint, data2, len2, extra);
1242 /* Consume status and the full packet it describes */
1248 /* Complete a TX transaction, command or from ipa_endpoint_skb_tx() */
1249 static void ipa_endpoint_tx_complete(struct ipa_endpoint *endpoint,
1250 struct gsi_trans *trans)
1254 /* Complete transaction initiated in ipa_endpoint_replenish_one() */
1255 static void ipa_endpoint_rx_complete(struct ipa_endpoint *endpoint,
1256 struct gsi_trans *trans)
1260 ipa_endpoint_replenish(endpoint, 1);
1262 if (trans->cancelled)
1265 /* Parse or build a socket buffer using the actual received length */
1267 if (endpoint->data->status_enable)
1268 ipa_endpoint_status_parse(endpoint, page, trans->len);
1269 else if (ipa_endpoint_skb_build(endpoint, page, trans->len))
1270 trans->data = NULL; /* Pages have been consumed */
1273 void ipa_endpoint_trans_complete(struct ipa_endpoint *endpoint,
1274 struct gsi_trans *trans)
1276 if (endpoint->toward_ipa)
1277 ipa_endpoint_tx_complete(endpoint, trans);
1279 ipa_endpoint_rx_complete(endpoint, trans);
1282 void ipa_endpoint_trans_release(struct ipa_endpoint *endpoint,
1283 struct gsi_trans *trans)
1285 if (endpoint->toward_ipa) {
1286 struct ipa *ipa = endpoint->ipa;
1288 /* Nothing to do for command transactions */
1289 if (endpoint != ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]) {
1290 struct sk_buff *skb = trans->data;
1293 dev_kfree_skb_any(skb);
1296 struct page *page = trans->data;
1299 __free_pages(page, get_order(IPA_RX_BUFFER_SIZE));
1303 void ipa_endpoint_default_route_set(struct ipa *ipa, u32 endpoint_id)
1307 /* ROUTE_DIS is 0 */
1308 val = u32_encode_bits(endpoint_id, ROUTE_DEF_PIPE_FMASK);
1309 val |= ROUTE_DEF_HDR_TABLE_FMASK;
1310 val |= u32_encode_bits(0, ROUTE_DEF_HDR_OFST_FMASK);
1311 val |= u32_encode_bits(endpoint_id, ROUTE_FRAG_DEF_PIPE_FMASK);
1312 val |= ROUTE_DEF_RETAIN_HDR_FMASK;
1314 iowrite32(val, ipa->reg_virt + IPA_REG_ROUTE_OFFSET);
1317 void ipa_endpoint_default_route_clear(struct ipa *ipa)
1319 ipa_endpoint_default_route_set(ipa, 0);
1323 * ipa_endpoint_reset_rx_aggr() - Reset RX endpoint with aggregation active
1324 * @endpoint: Endpoint to be reset
1326 * If aggregation is active on an RX endpoint when a reset is performed
1327 * on its underlying GSI channel, a special sequence of actions must be
1328 * taken to ensure the IPA pipeline is properly cleared.
1330 * Return: 0 if successful, or a negative error code
1332 static int ipa_endpoint_reset_rx_aggr(struct ipa_endpoint *endpoint)
1334 struct device *dev = &endpoint->ipa->pdev->dev;
1335 struct ipa *ipa = endpoint->ipa;
1336 struct gsi *gsi = &ipa->gsi;
1337 bool suspended = false;
1344 virt = kzalloc(len, GFP_KERNEL);
1348 addr = dma_map_single(dev, virt, len, DMA_FROM_DEVICE);
1349 if (dma_mapping_error(dev, addr)) {
1354 /* Force close aggregation before issuing the reset */
1355 ipa_endpoint_force_close(endpoint);
1357 /* Reset and reconfigure the channel with the doorbell engine
1358 * disabled. Then poll until we know aggregation is no longer
1359 * active. We'll re-enable the doorbell (if appropriate) when
1360 * we reset again below.
1362 gsi_channel_reset(gsi, endpoint->channel_id, false);
1364 /* Make sure the channel isn't suspended */
1365 suspended = ipa_endpoint_program_suspend(endpoint, false);
1367 /* Start channel and do a 1 byte read */
1368 ret = gsi_channel_start(gsi, endpoint->channel_id);
1370 goto out_suspend_again;
1372 ret = gsi_trans_read_byte(gsi, endpoint->channel_id, addr);
1374 goto err_endpoint_stop;
1376 /* Wait for aggregation to be closed on the channel */
1377 retries = IPA_ENDPOINT_RESET_AGGR_RETRY_MAX;
1379 if (!ipa_endpoint_aggr_active(endpoint))
1382 } while (retries--);
1384 /* Check one last time */
1385 if (ipa_endpoint_aggr_active(endpoint))
1386 dev_err(dev, "endpoint %u still active during reset\n",
1387 endpoint->endpoint_id);
1389 gsi_trans_read_byte_done(gsi, endpoint->channel_id);
1391 ret = gsi_channel_stop(gsi, endpoint->channel_id);
1393 goto out_suspend_again;
1395 /* Finally, reset and reconfigure the channel again (re-enabling the
1396 * the doorbell engine if appropriate). Sleep for 1 millisecond to
1397 * complete the channel reset sequence. Finish by suspending the
1398 * channel again (if necessary).
1400 gsi_channel_reset(gsi, endpoint->channel_id, true);
1404 goto out_suspend_again;
1407 (void)gsi_channel_stop(gsi, endpoint->channel_id);
1410 (void)ipa_endpoint_program_suspend(endpoint, true);
1411 dma_unmap_single(dev, addr, len, DMA_FROM_DEVICE);
1418 static void ipa_endpoint_reset(struct ipa_endpoint *endpoint)
1420 u32 channel_id = endpoint->channel_id;
1421 struct ipa *ipa = endpoint->ipa;
1425 /* On IPA v3.5.1, if an RX endpoint is reset while aggregation
1426 * is active, we need to handle things specially to recover.
1427 * All other cases just need to reset the underlying GSI channel.
1429 special = ipa->version == IPA_VERSION_3_5_1 &&
1430 !endpoint->toward_ipa &&
1431 endpoint->data->aggregation;
1432 if (special && ipa_endpoint_aggr_active(endpoint))
1433 ret = ipa_endpoint_reset_rx_aggr(endpoint);
1435 gsi_channel_reset(&ipa->gsi, channel_id, true);
1438 dev_err(&ipa->pdev->dev,
1439 "error %d resetting channel %u for endpoint %u\n",
1440 ret, endpoint->channel_id, endpoint->endpoint_id);
1443 static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
1445 if (endpoint->toward_ipa)
1446 ipa_endpoint_program_delay(endpoint, false);
1448 (void)ipa_endpoint_program_suspend(endpoint, false);
1449 ipa_endpoint_init_cfg(endpoint);
1450 ipa_endpoint_init_hdr(endpoint);
1451 ipa_endpoint_init_hdr_ext(endpoint);
1452 ipa_endpoint_init_hdr_metadata_mask(endpoint);
1453 ipa_endpoint_init_mode(endpoint);
1454 ipa_endpoint_init_aggr(endpoint);
1455 ipa_endpoint_init_deaggr(endpoint);
1456 ipa_endpoint_init_rsrc_grp(endpoint);
1457 ipa_endpoint_init_seq(endpoint);
1458 ipa_endpoint_status(endpoint);
1461 int ipa_endpoint_enable_one(struct ipa_endpoint *endpoint)
1463 struct ipa *ipa = endpoint->ipa;
1464 struct gsi *gsi = &ipa->gsi;
1467 ret = gsi_channel_start(gsi, endpoint->channel_id);
1469 dev_err(&ipa->pdev->dev,
1470 "error %d starting %cX channel %u for endpoint %u\n",
1471 ret, endpoint->toward_ipa ? 'T' : 'R',
1472 endpoint->channel_id, endpoint->endpoint_id);
1476 if (!endpoint->toward_ipa) {
1477 ipa_interrupt_suspend_enable(ipa->interrupt,
1478 endpoint->endpoint_id);
1479 ipa_endpoint_replenish_enable(endpoint);
1482 ipa->enabled |= BIT(endpoint->endpoint_id);
1487 void ipa_endpoint_disable_one(struct ipa_endpoint *endpoint)
1489 u32 mask = BIT(endpoint->endpoint_id);
1490 struct ipa *ipa = endpoint->ipa;
1491 struct gsi *gsi = &ipa->gsi;
1494 if (!(ipa->enabled & mask))
1497 ipa->enabled ^= mask;
1499 if (!endpoint->toward_ipa) {
1500 ipa_endpoint_replenish_disable(endpoint);
1501 ipa_interrupt_suspend_disable(ipa->interrupt,
1502 endpoint->endpoint_id);
1505 /* Note that if stop fails, the channel's state is not well-defined */
1506 ret = gsi_channel_stop(gsi, endpoint->channel_id);
1508 dev_err(&ipa->pdev->dev,
1509 "error %d attempting to stop endpoint %u\n", ret,
1510 endpoint->endpoint_id);
1513 void ipa_endpoint_suspend_one(struct ipa_endpoint *endpoint)
1515 struct device *dev = &endpoint->ipa->pdev->dev;
1516 struct gsi *gsi = &endpoint->ipa->gsi;
1520 if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id)))
1523 if (!endpoint->toward_ipa) {
1524 ipa_endpoint_replenish_disable(endpoint);
1525 (void)ipa_endpoint_program_suspend(endpoint, true);
1528 /* IPA v3.5.1 doesn't use channel stop for suspend */
1529 stop_channel = endpoint->ipa->version != IPA_VERSION_3_5_1;
1530 ret = gsi_channel_suspend(gsi, endpoint->channel_id, stop_channel);
1532 dev_err(dev, "error %d suspending channel %u\n", ret,
1533 endpoint->channel_id);
1536 void ipa_endpoint_resume_one(struct ipa_endpoint *endpoint)
1538 struct device *dev = &endpoint->ipa->pdev->dev;
1539 struct gsi *gsi = &endpoint->ipa->gsi;
1543 if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id)))
1546 if (!endpoint->toward_ipa)
1547 (void)ipa_endpoint_program_suspend(endpoint, false);
1549 /* IPA v3.5.1 doesn't use channel start for resume */
1550 start_channel = endpoint->ipa->version != IPA_VERSION_3_5_1;
1551 ret = gsi_channel_resume(gsi, endpoint->channel_id, start_channel);
1553 dev_err(dev, "error %d resuming channel %u\n", ret,
1554 endpoint->channel_id);
1555 else if (!endpoint->toward_ipa)
1556 ipa_endpoint_replenish_enable(endpoint);
1559 void ipa_endpoint_suspend(struct ipa *ipa)
1561 if (!ipa->setup_complete)
1564 if (ipa->modem_netdev)
1565 ipa_modem_suspend(ipa->modem_netdev);
1567 ipa_cmd_tag_process(ipa);
1569 ipa_endpoint_suspend_one(ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]);
1570 ipa_endpoint_suspend_one(ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]);
1573 void ipa_endpoint_resume(struct ipa *ipa)
1575 if (!ipa->setup_complete)
1578 ipa_endpoint_resume_one(ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]);
1579 ipa_endpoint_resume_one(ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]);
1581 if (ipa->modem_netdev)
1582 ipa_modem_resume(ipa->modem_netdev);
1585 static void ipa_endpoint_setup_one(struct ipa_endpoint *endpoint)
1587 struct gsi *gsi = &endpoint->ipa->gsi;
1588 u32 channel_id = endpoint->channel_id;
1590 /* Only AP endpoints get set up */
1591 if (endpoint->ee_id != GSI_EE_AP)
1594 endpoint->trans_tre_max = gsi_channel_trans_tre_max(gsi, channel_id);
1595 if (!endpoint->toward_ipa) {
1596 /* RX transactions require a single TRE, so the maximum
1597 * backlog is the same as the maximum outstanding TREs.
1599 endpoint->replenish_enabled = false;
1600 atomic_set(&endpoint->replenish_saved,
1601 gsi_channel_tre_max(gsi, endpoint->channel_id));
1602 atomic_set(&endpoint->replenish_backlog, 0);
1603 INIT_DELAYED_WORK(&endpoint->replenish_work,
1604 ipa_endpoint_replenish_work);
1607 ipa_endpoint_program(endpoint);
1609 endpoint->ipa->set_up |= BIT(endpoint->endpoint_id);
1612 static void ipa_endpoint_teardown_one(struct ipa_endpoint *endpoint)
1614 endpoint->ipa->set_up &= ~BIT(endpoint->endpoint_id);
1616 if (!endpoint->toward_ipa)
1617 cancel_delayed_work_sync(&endpoint->replenish_work);
1619 ipa_endpoint_reset(endpoint);
1622 void ipa_endpoint_setup(struct ipa *ipa)
1624 u32 initialized = ipa->initialized;
1627 while (initialized) {
1628 u32 endpoint_id = __ffs(initialized);
1630 initialized ^= BIT(endpoint_id);
1632 ipa_endpoint_setup_one(&ipa->endpoint[endpoint_id]);
1636 void ipa_endpoint_teardown(struct ipa *ipa)
1638 u32 set_up = ipa->set_up;
1641 u32 endpoint_id = __fls(set_up);
1643 set_up ^= BIT(endpoint_id);
1645 ipa_endpoint_teardown_one(&ipa->endpoint[endpoint_id]);
1650 int ipa_endpoint_config(struct ipa *ipa)
1652 struct device *dev = &ipa->pdev->dev;
1661 /* Find out about the endpoints supplied by the hardware, and ensure
1662 * the highest one doesn't exceed the number we support.
1664 val = ioread32(ipa->reg_virt + IPA_REG_FLAVOR_0_OFFSET);
1666 /* Our RX is an IPA producer */
1667 rx_base = u32_get_bits(val, IPA_PROD_LOWEST_FMASK);
1668 max = rx_base + u32_get_bits(val, IPA_MAX_PROD_PIPES_FMASK);
1669 if (max > IPA_ENDPOINT_MAX) {
1670 dev_err(dev, "too many endpoints (%u > %u)\n",
1671 max, IPA_ENDPOINT_MAX);
1674 rx_mask = GENMASK(max - 1, rx_base);
1676 /* Our TX is an IPA consumer */
1677 max = u32_get_bits(val, IPA_MAX_CONS_PIPES_FMASK);
1678 tx_mask = GENMASK(max - 1, 0);
1680 ipa->available = rx_mask | tx_mask;
1682 /* Check for initialized endpoints not supported by the hardware */
1683 if (ipa->initialized & ~ipa->available) {
1684 dev_err(dev, "unavailable endpoint id(s) 0x%08x\n",
1685 ipa->initialized & ~ipa->available);
1686 ret = -EINVAL; /* Report other errors too */
1689 initialized = ipa->initialized;
1690 while (initialized) {
1691 u32 endpoint_id = __ffs(initialized);
1692 struct ipa_endpoint *endpoint;
1694 initialized ^= BIT(endpoint_id);
1696 /* Make sure it's pointing in the right direction */
1697 endpoint = &ipa->endpoint[endpoint_id];
1698 if ((endpoint_id < rx_base) != !!endpoint->toward_ipa) {
1699 dev_err(dev, "endpoint id %u wrong direction\n",
1708 void ipa_endpoint_deconfig(struct ipa *ipa)
1710 ipa->available = 0; /* Nothing more to do */
1713 static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name,
1714 const struct ipa_gsi_endpoint_data *data)
1716 struct ipa_endpoint *endpoint;
1718 endpoint = &ipa->endpoint[data->endpoint_id];
1720 if (data->ee_id == GSI_EE_AP)
1721 ipa->channel_map[data->channel_id] = endpoint;
1722 ipa->name_map[name] = endpoint;
1724 endpoint->ipa = ipa;
1725 endpoint->ee_id = data->ee_id;
1726 endpoint->seq_type = data->endpoint.seq_type;
1727 endpoint->channel_id = data->channel_id;
1728 endpoint->endpoint_id = data->endpoint_id;
1729 endpoint->toward_ipa = data->toward_ipa;
1730 endpoint->data = &data->endpoint.config;
1732 ipa->initialized |= BIT(endpoint->endpoint_id);
1735 void ipa_endpoint_exit_one(struct ipa_endpoint *endpoint)
1737 endpoint->ipa->initialized &= ~BIT(endpoint->endpoint_id);
1739 memset(endpoint, 0, sizeof(*endpoint));
1742 void ipa_endpoint_exit(struct ipa *ipa)
1744 u32 initialized = ipa->initialized;
1746 while (initialized) {
1747 u32 endpoint_id = __fls(initialized);
1749 initialized ^= BIT(endpoint_id);
1751 ipa_endpoint_exit_one(&ipa->endpoint[endpoint_id]);
1753 memset(ipa->name_map, 0, sizeof(ipa->name_map));
1754 memset(ipa->channel_map, 0, sizeof(ipa->channel_map));
1757 /* Returns a bitmask of endpoints that support filtering, or 0 on error */
1758 u32 ipa_endpoint_init(struct ipa *ipa, u32 count,
1759 const struct ipa_gsi_endpoint_data *data)
1761 enum ipa_endpoint_name name;
1764 if (!ipa_endpoint_data_valid(ipa, count, data))
1765 return 0; /* Error */
1767 ipa->initialized = 0;
1770 for (name = 0; name < count; name++, data++) {
1771 if (ipa_gsi_endpoint_data_empty(data))
1772 continue; /* Skip over empty slots */
1774 ipa_endpoint_init_one(ipa, name, data);
1776 if (data->endpoint.filter_support)
1777 filter_map |= BIT(data->endpoint_id);
1780 if (!ipa_filter_map_valid(ipa, filter_map))
1781 goto err_endpoint_exit;
1783 return filter_map; /* Non-zero bitmask */
1786 ipa_endpoint_exit(ipa);
1788 return 0; /* Error */