1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2020 Linaro Ltd.
7 #include <linux/types.h>
8 #include <linux/device.h>
9 #include <linux/slab.h>
10 #include <linux/bitfield.h>
11 #include <linux/if_rmnet.h>
12 #include <linux/dma-direction.h>
15 #include "gsi_trans.h"
18 #include "ipa_endpoint.h"
21 #include "ipa_modem.h"
22 #include "ipa_table.h"
24 #include "ipa_clock.h"
26 #define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0)
28 #define IPA_REPLENISH_BATCH 16
30 /* RX buffer is 1 page (or a power-of-2 contiguous pages) */
31 #define IPA_RX_BUFFER_SIZE 8192 /* PAGE_SIZE > 4096 wastes a LOT */
33 /* The amount of RX buffer space consumed by standard skb overhead */
34 #define IPA_RX_BUFFER_OVERHEAD (PAGE_SIZE - SKB_MAX_ORDER(NET_SKB_PAD, 0))
36 /* Where to find the QMAP mux_id for a packet within modem-supplied metadata */
37 #define IPA_ENDPOINT_QMAP_METADATA_MASK 0x000000ff /* host byte order */
39 #define IPA_ENDPOINT_RESET_AGGR_RETRY_MAX 3
40 #define IPA_AGGR_TIME_LIMIT_DEFAULT 500 /* microseconds */
42 /** enum ipa_status_opcode - status element opcode hardware values */
43 enum ipa_status_opcode {
44 IPA_STATUS_OPCODE_PACKET = 0x01,
45 IPA_STATUS_OPCODE_DROPPED_PACKET = 0x04,
46 IPA_STATUS_OPCODE_SUSPENDED_PACKET = 0x08,
47 IPA_STATUS_OPCODE_PACKET_2ND_PASS = 0x40,
50 /** enum ipa_status_exception - status element exception type */
51 enum ipa_status_exception {
52 /* 0 means no exception */
53 IPA_STATUS_EXCEPTION_DEAGGR = 0x01,
56 /* Status element provided by hardware */
58 u8 opcode; /* enum ipa_status_opcode */
59 u8 exception; /* enum ipa_status_exception */
71 /* Field masks for struct ipa_status structure fields */
72 #define IPA_STATUS_DST_IDX_FMASK GENMASK(4, 0)
73 #define IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK GENMASK(31, 22)
77 static void ipa_endpoint_validate_build(void)
79 /* The aggregation byte limit defines the point at which an
80 * aggregation window will close. It is programmed into the
81 * IPA hardware as a number of KB. We don't use "hard byte
82 * limit" aggregation, which means that we need to supply
83 * enough space in a receive buffer to hold a complete MTU
84 * plus normal skb overhead *after* that aggregation byte
85 * limit has been crossed.
87 * This check just ensures we don't define a receive buffer
88 * size that would exceed what we can represent in the field
89 * that is used to program its size.
91 BUILD_BUG_ON(IPA_RX_BUFFER_SIZE >
92 field_max(AGGR_BYTE_LIMIT_FMASK) * SZ_1K +
93 IPA_MTU + IPA_RX_BUFFER_OVERHEAD);
95 /* I honestly don't know where this requirement comes from. But
96 * it holds, and if we someday need to loosen the constraint we
97 * can try to track it down.
99 BUILD_BUG_ON(sizeof(struct ipa_status) % 4);
102 static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count,
103 const struct ipa_gsi_endpoint_data *all_data,
104 const struct ipa_gsi_endpoint_data *data)
106 const struct ipa_gsi_endpoint_data *other_data;
107 struct device *dev = &ipa->pdev->dev;
108 enum ipa_endpoint_name other_name;
110 if (ipa_gsi_endpoint_data_empty(data))
113 if (!data->toward_ipa) {
114 if (data->endpoint.filter_support) {
115 dev_err(dev, "filtering not supported for "
121 return true; /* Nothing more to check for RX */
124 if (data->endpoint.config.status_enable) {
125 other_name = data->endpoint.config.tx.status_endpoint;
126 if (other_name >= count) {
127 dev_err(dev, "status endpoint name %u out of range "
129 other_name, data->endpoint_id);
133 /* Status endpoint must be defined... */
134 other_data = &all_data[other_name];
135 if (ipa_gsi_endpoint_data_empty(other_data)) {
136 dev_err(dev, "DMA endpoint name %u undefined "
138 other_name, data->endpoint_id);
142 /* ...and has to be an RX endpoint... */
143 if (other_data->toward_ipa) {
145 "status endpoint for endpoint %u not RX\n",
150 /* ...and if it's to be an AP endpoint... */
151 if (other_data->ee_id == GSI_EE_AP) {
152 /* ...make sure it has status enabled. */
153 if (!other_data->endpoint.config.status_enable) {
155 "status not enabled for endpoint %u\n",
156 other_data->endpoint_id);
162 if (data->endpoint.config.dma_mode) {
163 other_name = data->endpoint.config.dma_endpoint;
164 if (other_name >= count) {
165 dev_err(dev, "DMA endpoint name %u out of range "
167 other_name, data->endpoint_id);
171 other_data = &all_data[other_name];
172 if (ipa_gsi_endpoint_data_empty(other_data)) {
173 dev_err(dev, "DMA endpoint name %u undefined "
175 other_name, data->endpoint_id);
183 static bool ipa_endpoint_data_valid(struct ipa *ipa, u32 count,
184 const struct ipa_gsi_endpoint_data *data)
186 const struct ipa_gsi_endpoint_data *dp = data;
187 struct device *dev = &ipa->pdev->dev;
188 enum ipa_endpoint_name name;
190 ipa_endpoint_validate_build();
192 if (count > IPA_ENDPOINT_COUNT) {
193 dev_err(dev, "too many endpoints specified (%u > %u)\n",
194 count, IPA_ENDPOINT_COUNT);
198 /* Make sure needed endpoints have defined data */
199 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_COMMAND_TX])) {
200 dev_err(dev, "command TX endpoint not defined\n");
203 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_LAN_RX])) {
204 dev_err(dev, "LAN RX endpoint not defined\n");
207 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_TX])) {
208 dev_err(dev, "AP->modem TX endpoint not defined\n");
211 if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_RX])) {
212 dev_err(dev, "AP<-modem RX endpoint not defined\n");
216 for (name = 0; name < count; name++, dp++)
217 if (!ipa_endpoint_data_valid_one(ipa, count, data, dp))
223 #else /* !IPA_VALIDATE */
225 static bool ipa_endpoint_data_valid(struct ipa *ipa, u32 count,
226 const struct ipa_gsi_endpoint_data *data)
231 #endif /* !IPA_VALIDATE */
233 /* Allocate a transaction to use on a non-command endpoint */
234 static struct gsi_trans *ipa_endpoint_trans_alloc(struct ipa_endpoint *endpoint,
237 struct gsi *gsi = &endpoint->ipa->gsi;
238 u32 channel_id = endpoint->channel_id;
239 enum dma_data_direction direction;
241 direction = endpoint->toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
243 return gsi_channel_trans_alloc(gsi, channel_id, tre_count, direction);
246 /* suspend_delay represents suspend for RX, delay for TX endpoints.
247 * Note that suspend is not supported starting with IPA v4.0.
250 ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
252 u32 offset = IPA_REG_ENDP_INIT_CTRL_N_OFFSET(endpoint->endpoint_id);
253 struct ipa *ipa = endpoint->ipa;
258 /* Suspend is not supported for IPA v4.0+. Delay doesn't work
259 * correctly on IPA v4.2.
261 * if (endpoint->toward_ipa)
262 * assert(ipa->version != IPA_VERSION_4.2);
264 * assert(ipa->version == IPA_VERSION_3_5_1);
266 mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK;
268 val = ioread32(ipa->reg_virt + offset);
269 /* Don't bother if it's already in the requested state */
270 state = !!(val & mask);
271 if (suspend_delay != state) {
273 iowrite32(val, ipa->reg_virt + offset);
279 /* We currently don't care what the previous state was for delay mode */
281 ipa_endpoint_program_delay(struct ipa_endpoint *endpoint, bool enable)
283 /* assert(endpoint->toward_ipa); */
285 /* Delay mode doesn't work properly for IPA v4.2 */
286 if (endpoint->ipa->version != IPA_VERSION_4_2)
287 (void)ipa_endpoint_init_ctrl(endpoint, enable);
290 static bool ipa_endpoint_aggr_active(struct ipa_endpoint *endpoint)
292 u32 mask = BIT(endpoint->endpoint_id);
293 struct ipa *ipa = endpoint->ipa;
297 /* assert(mask & ipa->available); */
298 offset = ipa_reg_state_aggr_active_offset(ipa->version);
299 val = ioread32(ipa->reg_virt + offset);
301 return !!(val & mask);
304 static void ipa_endpoint_force_close(struct ipa_endpoint *endpoint)
306 u32 mask = BIT(endpoint->endpoint_id);
307 struct ipa *ipa = endpoint->ipa;
309 /* assert(mask & ipa->available); */
310 iowrite32(mask, ipa->reg_virt + IPA_REG_AGGR_FORCE_CLOSE_OFFSET);
314 * ipa_endpoint_suspend_aggr() - Emulate suspend interrupt
315 * @endpoint: Endpoint on which to emulate a suspend
317 * Emulate suspend IPA interrupt to unsuspend an endpoint suspended
318 * with an open aggregation frame. This is to work around a hardware
319 * issue in IPA version 3.5.1 where the suspend interrupt will not be
320 * generated when it should be.
322 static void ipa_endpoint_suspend_aggr(struct ipa_endpoint *endpoint)
324 struct ipa *ipa = endpoint->ipa;
326 if (!endpoint->data->aggregation)
329 /* Nothing to do if the endpoint doesn't have aggregation open */
330 if (!ipa_endpoint_aggr_active(endpoint))
333 /* Force close aggregation */
334 ipa_endpoint_force_close(endpoint);
336 ipa_interrupt_simulate_suspend(ipa->interrupt);
339 /* Returns previous suspend state (true means suspend was enabled) */
341 ipa_endpoint_program_suspend(struct ipa_endpoint *endpoint, bool enable)
345 if (endpoint->ipa->version != IPA_VERSION_3_5_1)
346 return enable; /* For IPA v4.0+, no change made */
348 /* assert(!endpoint->toward_ipa); */
350 suspended = ipa_endpoint_init_ctrl(endpoint, enable);
352 /* A client suspended with an open aggregation frame will not
353 * generate a SUSPEND IPA interrupt. If enabling suspend, have
354 * ipa_endpoint_suspend_aggr() handle this.
356 if (enable && !suspended)
357 ipa_endpoint_suspend_aggr(endpoint);
362 /* Enable or disable delay or suspend mode on all modem endpoints */
363 void ipa_endpoint_modem_pause_all(struct ipa *ipa, bool enable)
367 /* DELAY mode doesn't work correctly on IPA v4.2 */
368 if (ipa->version == IPA_VERSION_4_2)
371 for (endpoint_id = 0; endpoint_id < IPA_ENDPOINT_MAX; endpoint_id++) {
372 struct ipa_endpoint *endpoint = &ipa->endpoint[endpoint_id];
374 if (endpoint->ee_id != GSI_EE_MODEM)
377 /* Set TX delay mode or RX suspend mode */
378 if (endpoint->toward_ipa)
379 ipa_endpoint_program_delay(endpoint, enable);
381 (void)ipa_endpoint_program_suspend(endpoint, enable);
385 /* Reset all modem endpoints to use the default exception endpoint */
386 int ipa_endpoint_modem_exception_reset_all(struct ipa *ipa)
388 u32 initialized = ipa->initialized;
389 struct gsi_trans *trans;
392 /* We need one command per modem TX endpoint. We can get an upper
393 * bound on that by assuming all initialized endpoints are modem->IPA.
394 * That won't happen, and we could be more precise, but this is fine
395 * for now. We need to end the transaction with a "tag process."
397 count = hweight32(initialized) + ipa_cmd_tag_process_count();
398 trans = ipa_cmd_trans_alloc(ipa, count);
400 dev_err(&ipa->pdev->dev,
401 "no transaction to reset modem exception endpoints\n");
405 while (initialized) {
406 u32 endpoint_id = __ffs(initialized);
407 struct ipa_endpoint *endpoint;
410 initialized ^= BIT(endpoint_id);
412 /* We only reset modem TX endpoints */
413 endpoint = &ipa->endpoint[endpoint_id];
414 if (!(endpoint->ee_id == GSI_EE_MODEM && endpoint->toward_ipa))
417 offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id);
419 /* Value written is 0, and all bits are updated. That
420 * means status is disabled on the endpoint, and as a
421 * result all other fields in the register are ignored.
423 ipa_cmd_register_write_add(trans, offset, 0, ~0, false);
426 ipa_cmd_tag_process_add(trans);
428 /* XXX This should have a 1 second timeout */
429 gsi_trans_commit_wait(trans);
434 static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
436 u32 offset = IPA_REG_ENDP_INIT_CFG_N_OFFSET(endpoint->endpoint_id);
439 /* FRAG_OFFLOAD_EN is 0 */
440 if (endpoint->data->checksum) {
441 if (endpoint->toward_ipa) {
444 val |= u32_encode_bits(IPA_CS_OFFLOAD_UL,
445 CS_OFFLOAD_EN_FMASK);
446 /* Checksum header offset is in 4-byte units */
447 checksum_offset = sizeof(struct rmnet_map_header);
448 checksum_offset /= sizeof(u32);
449 val |= u32_encode_bits(checksum_offset,
450 CS_METADATA_HDR_OFFSET_FMASK);
452 val |= u32_encode_bits(IPA_CS_OFFLOAD_DL,
453 CS_OFFLOAD_EN_FMASK);
456 val |= u32_encode_bits(IPA_CS_OFFLOAD_NONE,
457 CS_OFFLOAD_EN_FMASK);
459 /* CS_GEN_QMB_MASTER_SEL is 0 */
461 iowrite32(val, endpoint->ipa->reg_virt + offset);
465 * ipa_endpoint_init_hdr() - Initialize HDR endpoint configuration register
466 * @endpoint: Endpoint pointer
468 * We program QMAP endpoints so each packet received is preceded by a QMAP
469 * header structure. The QMAP header contains a 1-byte mux_id and 2-byte
470 * packet size field, and we have the IPA hardware populate both for each
471 * received packet. The header is configured (in the HDR_EXT register)
472 * to use big endian format.
474 * The packet size is written into the QMAP header's pkt_len field. That
475 * location is defined here using the HDR_OFST_PKT_SIZE field.
477 * The mux_id comes from a 4-byte metadata value supplied with each packet
478 * by the modem. It is *not* a QMAP header, but it does contain the mux_id
479 * value that we want, in its low-order byte. A bitmask defined in the
480 * endpoint's METADATA_MASK register defines which byte within the modem
481 * metadata contains the mux_id. And the OFST_METADATA field programmed
482 * here indicates where the extracted byte should be placed within the QMAP
485 static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
487 u32 offset = IPA_REG_ENDP_INIT_HDR_N_OFFSET(endpoint->endpoint_id);
488 struct ipa *ipa = endpoint->ipa;
491 if (endpoint->data->qmap) {
492 size_t header_size = sizeof(struct rmnet_map_header);
493 enum ipa_version version = ipa->version;
495 /* We might supply a checksum header after the QMAP header */
496 if (endpoint->toward_ipa && endpoint->data->checksum)
497 header_size += sizeof(struct rmnet_map_ul_csum_header);
498 val |= ipa_header_size_encoded(version, header_size);
500 /* Define how to fill fields in a received QMAP header */
501 if (!endpoint->toward_ipa) {
502 u32 offset; /* Field offset within header */
504 /* Where IPA will write the metadata value */
505 offset = offsetof(struct rmnet_map_header, mux_id);
506 val |= ipa_metadata_offset_encoded(version, offset);
508 /* Where IPA will write the length */
509 offset = offsetof(struct rmnet_map_header, pkt_len);
510 /* Upper bits are stored in HDR_EXT with IPA v4.5 */
511 if (version == IPA_VERSION_4_5)
512 offset &= field_mask(HDR_OFST_PKT_SIZE_FMASK);
514 val |= HDR_OFST_PKT_SIZE_VALID_FMASK;
515 val |= u32_encode_bits(offset, HDR_OFST_PKT_SIZE_FMASK);
517 /* For QMAP TX, metadata offset is 0 (modem assumes this) */
518 val |= HDR_OFST_METADATA_VALID_FMASK;
520 /* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */
521 /* HDR_A5_MUX is 0 */
522 /* HDR_LEN_INC_DEAGG_HDR is 0 */
523 /* HDR_METADATA_REG_VALID is 0 (TX only) */
526 iowrite32(val, ipa->reg_virt + offset);
529 static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
531 u32 offset = IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(endpoint->endpoint_id);
532 u32 pad_align = endpoint->data->rx.pad_align;
533 struct ipa *ipa = endpoint->ipa;
536 val |= HDR_ENDIANNESS_FMASK; /* big endian */
538 /* A QMAP header contains a 6 bit pad field at offset 0. The RMNet
539 * driver assumes this field is meaningful in packets it receives,
540 * and assumes the header's payload length includes that padding.
541 * The RMNet driver does *not* pad packets it sends, however, so
542 * the pad field (although 0) should be ignored.
544 if (endpoint->data->qmap && !endpoint->toward_ipa) {
545 val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK;
546 /* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */
547 val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK;
548 /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */
551 /* HDR_PAYLOAD_LEN_INC_PADDING is 0 */
552 if (!endpoint->toward_ipa)
553 val |= u32_encode_bits(pad_align, HDR_PAD_TO_ALIGNMENT_FMASK);
555 /* IPA v4.5 adds some most-significant bits to a few fields,
556 * two of which are defined in the HDR (not HDR_EXT) register.
558 if (ipa->version == IPA_VERSION_4_5) {
559 /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */
560 if (endpoint->data->qmap && !endpoint->toward_ipa) {
563 offset = offsetof(struct rmnet_map_header, pkt_len);
564 offset >>= hweight32(HDR_OFST_PKT_SIZE_FMASK);
565 val |= u32_encode_bits(offset,
566 HDR_OFST_PKT_SIZE_MSB_FMASK);
567 /* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */
570 iowrite32(val, ipa->reg_virt + offset);
573 static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
575 u32 endpoint_id = endpoint->endpoint_id;
579 if (endpoint->toward_ipa)
580 return; /* Register not valid for TX endpoints */
582 offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id);
584 /* Note that HDR_ENDIANNESS indicates big endian header fields */
585 if (endpoint->data->qmap)
586 val = cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK);
588 iowrite32(val, endpoint->ipa->reg_virt + offset);
591 static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
593 u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id);
596 if (!endpoint->toward_ipa)
597 return; /* Register not valid for RX endpoints */
599 if (endpoint->data->dma_mode) {
600 enum ipa_endpoint_name name = endpoint->data->dma_endpoint;
603 dma_endpoint_id = endpoint->ipa->name_map[name]->endpoint_id;
605 val = u32_encode_bits(IPA_DMA, MODE_FMASK);
606 val |= u32_encode_bits(dma_endpoint_id, DEST_PIPE_INDEX_FMASK);
608 val = u32_encode_bits(IPA_BASIC, MODE_FMASK);
610 /* All other bits unspecified (and 0) */
612 iowrite32(val, endpoint->ipa->reg_virt + offset);
615 /* Compute the aggregation size value to use for a given buffer size */
616 static u32 ipa_aggr_size_kb(u32 rx_buffer_size)
618 /* We don't use "hard byte limit" aggregation, so we define the
619 * aggregation limit such that our buffer has enough space *after*
620 * that limit to receive a full MTU of data, plus overhead.
622 rx_buffer_size -= IPA_MTU + IPA_RX_BUFFER_OVERHEAD;
624 return rx_buffer_size / SZ_1K;
627 static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
629 u32 offset = IPA_REG_ENDP_INIT_AGGR_N_OFFSET(endpoint->endpoint_id);
632 if (endpoint->data->aggregation) {
633 if (!endpoint->toward_ipa) {
636 val |= u32_encode_bits(IPA_ENABLE_AGGR, AGGR_EN_FMASK);
637 val |= u32_encode_bits(IPA_GENERIC, AGGR_TYPE_FMASK);
639 limit = ipa_aggr_size_kb(IPA_RX_BUFFER_SIZE);
640 val |= u32_encode_bits(limit, AGGR_BYTE_LIMIT_FMASK);
642 limit = IPA_AGGR_TIME_LIMIT_DEFAULT;
643 limit = DIV_ROUND_CLOSEST(limit, IPA_AGGR_GRANULARITY);
644 val |= u32_encode_bits(limit, AGGR_TIME_LIMIT_FMASK);
646 /* AGGR_PKT_LIMIT is 0 (unlimited) */
648 if (endpoint->data->rx.aggr_close_eof)
649 val |= AGGR_SW_EOF_ACTIVE_FMASK;
650 /* AGGR_HARD_BYTE_LIMIT_ENABLE is 0 */
652 val |= u32_encode_bits(IPA_ENABLE_DEAGGR,
654 val |= u32_encode_bits(IPA_QCMAP, AGGR_TYPE_FMASK);
655 /* other fields ignored */
657 /* AGGR_FORCE_CLOSE is 0 */
659 val |= u32_encode_bits(IPA_BYPASS_AGGR, AGGR_EN_FMASK);
660 /* other fields ignored */
663 iowrite32(val, endpoint->ipa->reg_virt + offset);
666 /* The head-of-line blocking timer is defined as a tick count, where each
667 * tick represents 128 cycles of the IPA core clock. Return the value
668 * that should be written to that register that represents the timeout
671 static u32 ipa_reg_init_hol_block_timer_val(struct ipa *ipa, u32 microseconds)
681 return 0; /* Nothing to compute if timer period is 0 */
683 /* Use 64 bit arithmetic to avoid overflow... */
684 rate = ipa_clock_rate(ipa);
685 ticks = DIV_ROUND_CLOSEST(microseconds * rate, 128 * USEC_PER_SEC);
686 /* ...but we still need to fit into a 32-bit register */
687 WARN_ON(ticks > U32_MAX);
689 /* IPA v3.5.1 through v4.1 just record the tick count */
690 if (ipa->version < IPA_VERSION_4_2)
693 /* For IPA v4.2, the tick count is represented by base and
694 * scale fields within the 32-bit timer register, where:
695 * ticks = base << scale;
696 * The best precision is achieved when the base value is as
697 * large as possible. Find the highest set bit in the tick
698 * count, and extract the number of bits in the base field
699 * such that that high bit is included.
701 high = fls(ticks); /* 1..32 */
702 width = HWEIGHT32(BASE_VALUE_FMASK);
703 scale = high > width ? high - width : 0;
705 /* If we're scaling, round up to get a closer result */
706 ticks += 1 << (scale - 1);
707 /* High bit was set, so rounding might have affected it */
708 if (fls(ticks) != high)
712 val = u32_encode_bits(scale, SCALE_FMASK);
713 val |= u32_encode_bits(ticks >> scale, BASE_VALUE_FMASK);
718 /* If microseconds is 0, timeout is immediate */
719 static void ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint,
722 u32 endpoint_id = endpoint->endpoint_id;
723 struct ipa *ipa = endpoint->ipa;
727 offset = IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(endpoint_id);
728 val = ipa_reg_init_hol_block_timer_val(ipa, microseconds);
729 iowrite32(val, ipa->reg_virt + offset);
733 ipa_endpoint_init_hol_block_enable(struct ipa_endpoint *endpoint, bool enable)
735 u32 endpoint_id = endpoint->endpoint_id;
739 val = enable ? HOL_BLOCK_EN_FMASK : 0;
740 offset = IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(endpoint_id);
741 iowrite32(val, endpoint->ipa->reg_virt + offset);
744 void ipa_endpoint_modem_hol_block_clear_all(struct ipa *ipa)
748 for (i = 0; i < IPA_ENDPOINT_MAX; i++) {
749 struct ipa_endpoint *endpoint = &ipa->endpoint[i];
751 if (endpoint->toward_ipa || endpoint->ee_id != GSI_EE_MODEM)
754 ipa_endpoint_init_hol_block_timer(endpoint, 0);
755 ipa_endpoint_init_hol_block_enable(endpoint, true);
759 static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint)
761 u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id);
764 if (!endpoint->toward_ipa)
765 return; /* Register not valid for RX endpoints */
767 /* DEAGGR_HDR_LEN is 0 */
768 /* PACKET_OFFSET_VALID is 0 */
769 /* PACKET_OFFSET_LOCATION is ignored (not valid) */
770 /* MAX_PACKET_LEN is 0 (not enforced) */
772 iowrite32(val, endpoint->ipa->reg_virt + offset);
775 static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint)
777 u32 offset = IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(endpoint->endpoint_id);
778 struct ipa *ipa = endpoint->ipa;
781 val = rsrc_grp_encoded(ipa->version, endpoint->data->resource_group);
782 iowrite32(val, ipa->reg_virt + offset);
785 static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
787 u32 offset = IPA_REG_ENDP_INIT_SEQ_N_OFFSET(endpoint->endpoint_id);
788 u32 seq_type = endpoint->seq_type;
791 if (!endpoint->toward_ipa)
792 return; /* Register not valid for RX endpoints */
794 /* Sequencer type is made up of four nibbles */
795 val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK);
796 val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK);
797 /* The second two apply to replicated packets */
798 val |= u32_encode_bits((seq_type >> 8) & 0xf, HPS_REP_SEQ_TYPE_FMASK);
799 val |= u32_encode_bits((seq_type >> 12) & 0xf, DPS_REP_SEQ_TYPE_FMASK);
801 iowrite32(val, endpoint->ipa->reg_virt + offset);
805 * ipa_endpoint_skb_tx() - Transmit a socket buffer
806 * @endpoint: Endpoint pointer
807 * @skb: Socket buffer to send
809 * Returns: 0 if successful, or a negative error code
811 int ipa_endpoint_skb_tx(struct ipa_endpoint *endpoint, struct sk_buff *skb)
813 struct gsi_trans *trans;
817 /* Make sure source endpoint's TLV FIFO has enough entries to
818 * hold the linear portion of the skb and all its fragments.
819 * If not, see if we can linearize it before giving up.
821 nr_frags = skb_shinfo(skb)->nr_frags;
822 if (1 + nr_frags > endpoint->trans_tre_max) {
823 if (skb_linearize(skb))
828 trans = ipa_endpoint_trans_alloc(endpoint, 1 + nr_frags);
832 ret = gsi_trans_skb_add(trans, skb);
835 trans->data = skb; /* transaction owns skb now */
837 gsi_trans_commit(trans, !netdev_xmit_more());
842 gsi_trans_free(trans);
847 static void ipa_endpoint_status(struct ipa_endpoint *endpoint)
849 u32 endpoint_id = endpoint->endpoint_id;
850 struct ipa *ipa = endpoint->ipa;
854 offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id);
856 if (endpoint->data->status_enable) {
857 val |= STATUS_EN_FMASK;
858 if (endpoint->toward_ipa) {
859 enum ipa_endpoint_name name;
860 u32 status_endpoint_id;
862 name = endpoint->data->tx.status_endpoint;
863 status_endpoint_id = ipa->name_map[name]->endpoint_id;
865 val |= u32_encode_bits(status_endpoint_id,
868 /* STATUS_LOCATION is 0 (status element precedes packet) */
869 /* The next field is present for IPA v4.0 and above */
870 /* STATUS_PKT_SUPPRESS_FMASK is 0 */
873 iowrite32(val, ipa->reg_virt + offset);
876 static int ipa_endpoint_replenish_one(struct ipa_endpoint *endpoint)
878 struct gsi_trans *trans;
879 bool doorbell = false;
885 page = dev_alloc_pages(get_order(IPA_RX_BUFFER_SIZE));
889 trans = ipa_endpoint_trans_alloc(endpoint, 1);
893 /* Offset the buffer to make space for skb headroom */
894 offset = NET_SKB_PAD;
895 len = IPA_RX_BUFFER_SIZE - offset;
897 ret = gsi_trans_page_add(trans, page, len, offset);
900 trans->data = page; /* transaction owns page now */
902 if (++endpoint->replenish_ready == IPA_REPLENISH_BATCH) {
904 endpoint->replenish_ready = 0;
907 gsi_trans_commit(trans, doorbell);
912 gsi_trans_free(trans);
914 __free_pages(page, get_order(IPA_RX_BUFFER_SIZE));
920 * ipa_endpoint_replenish() - Replenish the Rx packets cache.
921 * @endpoint: Endpoint to be replenished
922 * @count: Number of buffers to send to hardware
924 * Allocate RX packet wrapper structures with maximal socket buffers
925 * for an endpoint. These are supplied to the hardware, which fills
926 * them with incoming data.
928 static void ipa_endpoint_replenish(struct ipa_endpoint *endpoint, u32 count)
933 if (!endpoint->replenish_enabled) {
935 atomic_add(count, &endpoint->replenish_saved);
940 while (atomic_dec_not_zero(&endpoint->replenish_backlog))
941 if (ipa_endpoint_replenish_one(endpoint))
942 goto try_again_later;
944 atomic_add(count, &endpoint->replenish_backlog);
949 /* The last one didn't succeed, so fix the backlog */
950 backlog = atomic_inc_return(&endpoint->replenish_backlog);
953 atomic_add(count, &endpoint->replenish_backlog);
955 /* Whenever a receive buffer transaction completes we'll try to
956 * replenish again. It's unlikely, but if we fail to supply even
957 * one buffer, nothing will trigger another replenish attempt.
958 * Receive buffer transactions use one TRE, so schedule work to
959 * try replenishing again if our backlog is *all* available TREs.
961 gsi = &endpoint->ipa->gsi;
962 if (backlog == gsi_channel_tre_max(gsi, endpoint->channel_id))
963 schedule_delayed_work(&endpoint->replenish_work,
964 msecs_to_jiffies(1));
967 static void ipa_endpoint_replenish_enable(struct ipa_endpoint *endpoint)
969 struct gsi *gsi = &endpoint->ipa->gsi;
973 endpoint->replenish_enabled = true;
974 while ((saved = atomic_xchg(&endpoint->replenish_saved, 0)))
975 atomic_add(saved, &endpoint->replenish_backlog);
977 /* Start replenishing if hardware currently has no buffers */
978 max_backlog = gsi_channel_tre_max(gsi, endpoint->channel_id);
979 if (atomic_read(&endpoint->replenish_backlog) == max_backlog)
980 ipa_endpoint_replenish(endpoint, 0);
983 static void ipa_endpoint_replenish_disable(struct ipa_endpoint *endpoint)
987 endpoint->replenish_enabled = false;
988 while ((backlog = atomic_xchg(&endpoint->replenish_backlog, 0)))
989 atomic_add(backlog, &endpoint->replenish_saved);
992 static void ipa_endpoint_replenish_work(struct work_struct *work)
994 struct delayed_work *dwork = to_delayed_work(work);
995 struct ipa_endpoint *endpoint;
997 endpoint = container_of(dwork, struct ipa_endpoint, replenish_work);
999 ipa_endpoint_replenish(endpoint, 0);
1002 static void ipa_endpoint_skb_copy(struct ipa_endpoint *endpoint,
1003 void *data, u32 len, u32 extra)
1005 struct sk_buff *skb;
1007 skb = __dev_alloc_skb(len, GFP_ATOMIC);
1010 memcpy(skb->data, data, len);
1011 skb->truesize += extra;
1014 /* Now receive it, or drop it if there's no netdev */
1015 if (endpoint->netdev)
1016 ipa_modem_skb_rx(endpoint->netdev, skb);
1018 dev_kfree_skb_any(skb);
1021 static bool ipa_endpoint_skb_build(struct ipa_endpoint *endpoint,
1022 struct page *page, u32 len)
1024 struct sk_buff *skb;
1026 /* Nothing to do if there's no netdev */
1027 if (!endpoint->netdev)
1030 /* assert(len <= SKB_WITH_OVERHEAD(IPA_RX_BUFFER_SIZE-NET_SKB_PAD)); */
1031 skb = build_skb(page_address(page), IPA_RX_BUFFER_SIZE);
1033 /* Reserve the headroom and account for the data */
1034 skb_reserve(skb, NET_SKB_PAD);
1038 /* Receive the buffer (or record drop if unable to build it) */
1039 ipa_modem_skb_rx(endpoint->netdev, skb);
1044 /* The format of a packet status element is the same for several status
1045 * types (opcodes). Other types aren't currently supported.
1047 static bool ipa_status_format_packet(enum ipa_status_opcode opcode)
1050 case IPA_STATUS_OPCODE_PACKET:
1051 case IPA_STATUS_OPCODE_DROPPED_PACKET:
1052 case IPA_STATUS_OPCODE_SUSPENDED_PACKET:
1053 case IPA_STATUS_OPCODE_PACKET_2ND_PASS:
1060 static bool ipa_endpoint_status_skip(struct ipa_endpoint *endpoint,
1061 const struct ipa_status *status)
1065 if (!ipa_status_format_packet(status->opcode))
1067 if (!status->pkt_len)
1069 endpoint_id = u32_get_bits(status->endp_dst_idx,
1070 IPA_STATUS_DST_IDX_FMASK);
1071 if (endpoint_id != endpoint->endpoint_id)
1074 return false; /* Don't skip this packet, process it */
1077 /* Return whether the status indicates the packet should be dropped */
1078 static bool ipa_status_drop_packet(const struct ipa_status *status)
1082 /* Deaggregation exceptions we drop; all other types we consume */
1083 if (status->exception)
1084 return status->exception == IPA_STATUS_EXCEPTION_DEAGGR;
1086 /* Drop the packet if it fails to match a routing rule; otherwise no */
1087 val = le32_get_bits(status->flags1, IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK);
1089 return val == field_max(IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK);
1092 static void ipa_endpoint_status_parse(struct ipa_endpoint *endpoint,
1093 struct page *page, u32 total_len)
1095 void *data = page_address(page) + NET_SKB_PAD;
1096 u32 unused = IPA_RX_BUFFER_SIZE - total_len;
1097 u32 resid = total_len;
1100 const struct ipa_status *status = data;
1104 if (resid < sizeof(*status)) {
1105 dev_err(&endpoint->ipa->pdev->dev,
1106 "short message (%u bytes < %zu byte status)\n",
1107 resid, sizeof(*status));
1111 /* Skip over status packets that lack packet data */
1112 if (ipa_endpoint_status_skip(endpoint, status)) {
1113 data += sizeof(*status);
1114 resid -= sizeof(*status);
1118 /* Compute the amount of buffer space consumed by the
1119 * packet, including the status element. If the hardware
1120 * is configured to pad packet data to an aligned boundary,
1121 * account for that. And if checksum offload is is enabled
1122 * a trailer containing computed checksum information will
1125 align = endpoint->data->rx.pad_align ? : 1;
1126 len = le16_to_cpu(status->pkt_len);
1127 len = sizeof(*status) + ALIGN(len, align);
1128 if (endpoint->data->checksum)
1129 len += sizeof(struct rmnet_map_dl_csum_trailer);
1131 /* Charge the new packet with a proportional fraction of
1132 * the unused space in the original receive buffer.
1133 * XXX Charge a proportion of the *whole* receive buffer?
1135 if (!ipa_status_drop_packet(status)) {
1136 u32 extra = unused * len / total_len;
1137 void *data2 = data + sizeof(*status);
1138 u32 len2 = le16_to_cpu(status->pkt_len);
1140 /* Client receives only packet data (no status) */
1141 ipa_endpoint_skb_copy(endpoint, data2, len2, extra);
1144 /* Consume status and the full packet it describes */
1150 /* Complete a TX transaction, command or from ipa_endpoint_skb_tx() */
1151 static void ipa_endpoint_tx_complete(struct ipa_endpoint *endpoint,
1152 struct gsi_trans *trans)
1156 /* Complete transaction initiated in ipa_endpoint_replenish_one() */
1157 static void ipa_endpoint_rx_complete(struct ipa_endpoint *endpoint,
1158 struct gsi_trans *trans)
1162 ipa_endpoint_replenish(endpoint, 1);
1164 if (trans->cancelled)
1167 /* Parse or build a socket buffer using the actual received length */
1169 if (endpoint->data->status_enable)
1170 ipa_endpoint_status_parse(endpoint, page, trans->len);
1171 else if (ipa_endpoint_skb_build(endpoint, page, trans->len))
1172 trans->data = NULL; /* Pages have been consumed */
1175 void ipa_endpoint_trans_complete(struct ipa_endpoint *endpoint,
1176 struct gsi_trans *trans)
1178 if (endpoint->toward_ipa)
1179 ipa_endpoint_tx_complete(endpoint, trans);
1181 ipa_endpoint_rx_complete(endpoint, trans);
1184 void ipa_endpoint_trans_release(struct ipa_endpoint *endpoint,
1185 struct gsi_trans *trans)
1187 if (endpoint->toward_ipa) {
1188 struct ipa *ipa = endpoint->ipa;
1190 /* Nothing to do for command transactions */
1191 if (endpoint != ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]) {
1192 struct sk_buff *skb = trans->data;
1195 dev_kfree_skb_any(skb);
1198 struct page *page = trans->data;
1201 __free_pages(page, get_order(IPA_RX_BUFFER_SIZE));
1205 void ipa_endpoint_default_route_set(struct ipa *ipa, u32 endpoint_id)
1209 /* ROUTE_DIS is 0 */
1210 val = u32_encode_bits(endpoint_id, ROUTE_DEF_PIPE_FMASK);
1211 val |= ROUTE_DEF_HDR_TABLE_FMASK;
1212 val |= u32_encode_bits(0, ROUTE_DEF_HDR_OFST_FMASK);
1213 val |= u32_encode_bits(endpoint_id, ROUTE_FRAG_DEF_PIPE_FMASK);
1214 val |= ROUTE_DEF_RETAIN_HDR_FMASK;
1216 iowrite32(val, ipa->reg_virt + IPA_REG_ROUTE_OFFSET);
1219 void ipa_endpoint_default_route_clear(struct ipa *ipa)
1221 ipa_endpoint_default_route_set(ipa, 0);
1225 * ipa_endpoint_reset_rx_aggr() - Reset RX endpoint with aggregation active
1226 * @endpoint: Endpoint to be reset
1228 * If aggregation is active on an RX endpoint when a reset is performed
1229 * on its underlying GSI channel, a special sequence of actions must be
1230 * taken to ensure the IPA pipeline is properly cleared.
1232 * Return: 0 if successful, or a negative error code
1234 static int ipa_endpoint_reset_rx_aggr(struct ipa_endpoint *endpoint)
1236 struct device *dev = &endpoint->ipa->pdev->dev;
1237 struct ipa *ipa = endpoint->ipa;
1238 struct gsi *gsi = &ipa->gsi;
1239 bool suspended = false;
1246 virt = kzalloc(len, GFP_KERNEL);
1250 addr = dma_map_single(dev, virt, len, DMA_FROM_DEVICE);
1251 if (dma_mapping_error(dev, addr)) {
1256 /* Force close aggregation before issuing the reset */
1257 ipa_endpoint_force_close(endpoint);
1259 /* Reset and reconfigure the channel with the doorbell engine
1260 * disabled. Then poll until we know aggregation is no longer
1261 * active. We'll re-enable the doorbell (if appropriate) when
1262 * we reset again below.
1264 gsi_channel_reset(gsi, endpoint->channel_id, false);
1266 /* Make sure the channel isn't suspended */
1267 suspended = ipa_endpoint_program_suspend(endpoint, false);
1269 /* Start channel and do a 1 byte read */
1270 ret = gsi_channel_start(gsi, endpoint->channel_id);
1272 goto out_suspend_again;
1274 ret = gsi_trans_read_byte(gsi, endpoint->channel_id, addr);
1276 goto err_endpoint_stop;
1278 /* Wait for aggregation to be closed on the channel */
1279 retries = IPA_ENDPOINT_RESET_AGGR_RETRY_MAX;
1281 if (!ipa_endpoint_aggr_active(endpoint))
1284 } while (retries--);
1286 /* Check one last time */
1287 if (ipa_endpoint_aggr_active(endpoint))
1288 dev_err(dev, "endpoint %u still active during reset\n",
1289 endpoint->endpoint_id);
1291 gsi_trans_read_byte_done(gsi, endpoint->channel_id);
1293 ret = gsi_channel_stop(gsi, endpoint->channel_id);
1295 goto out_suspend_again;
1297 /* Finally, reset and reconfigure the channel again (re-enabling the
1298 * the doorbell engine if appropriate). Sleep for 1 millisecond to
1299 * complete the channel reset sequence. Finish by suspending the
1300 * channel again (if necessary).
1302 gsi_channel_reset(gsi, endpoint->channel_id, true);
1306 goto out_suspend_again;
1309 (void)gsi_channel_stop(gsi, endpoint->channel_id);
1312 (void)ipa_endpoint_program_suspend(endpoint, true);
1313 dma_unmap_single(dev, addr, len, DMA_FROM_DEVICE);
1320 static void ipa_endpoint_reset(struct ipa_endpoint *endpoint)
1322 u32 channel_id = endpoint->channel_id;
1323 struct ipa *ipa = endpoint->ipa;
1327 /* On IPA v3.5.1, if an RX endpoint is reset while aggregation
1328 * is active, we need to handle things specially to recover.
1329 * All other cases just need to reset the underlying GSI channel.
1331 special = ipa->version == IPA_VERSION_3_5_1 &&
1332 !endpoint->toward_ipa &&
1333 endpoint->data->aggregation;
1334 if (special && ipa_endpoint_aggr_active(endpoint))
1335 ret = ipa_endpoint_reset_rx_aggr(endpoint);
1337 gsi_channel_reset(&ipa->gsi, channel_id, true);
1340 dev_err(&ipa->pdev->dev,
1341 "error %d resetting channel %u for endpoint %u\n",
1342 ret, endpoint->channel_id, endpoint->endpoint_id);
1345 static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
1347 if (endpoint->toward_ipa)
1348 ipa_endpoint_program_delay(endpoint, false);
1350 (void)ipa_endpoint_program_suspend(endpoint, false);
1351 ipa_endpoint_init_cfg(endpoint);
1352 ipa_endpoint_init_hdr(endpoint);
1353 ipa_endpoint_init_hdr_ext(endpoint);
1354 ipa_endpoint_init_hdr_metadata_mask(endpoint);
1355 ipa_endpoint_init_mode(endpoint);
1356 ipa_endpoint_init_aggr(endpoint);
1357 ipa_endpoint_init_deaggr(endpoint);
1358 ipa_endpoint_init_rsrc_grp(endpoint);
1359 ipa_endpoint_init_seq(endpoint);
1360 ipa_endpoint_status(endpoint);
1363 int ipa_endpoint_enable_one(struct ipa_endpoint *endpoint)
1365 struct ipa *ipa = endpoint->ipa;
1366 struct gsi *gsi = &ipa->gsi;
1369 ret = gsi_channel_start(gsi, endpoint->channel_id);
1371 dev_err(&ipa->pdev->dev,
1372 "error %d starting %cX channel %u for endpoint %u\n",
1373 ret, endpoint->toward_ipa ? 'T' : 'R',
1374 endpoint->channel_id, endpoint->endpoint_id);
1378 if (!endpoint->toward_ipa) {
1379 ipa_interrupt_suspend_enable(ipa->interrupt,
1380 endpoint->endpoint_id);
1381 ipa_endpoint_replenish_enable(endpoint);
1384 ipa->enabled |= BIT(endpoint->endpoint_id);
1389 void ipa_endpoint_disable_one(struct ipa_endpoint *endpoint)
1391 u32 mask = BIT(endpoint->endpoint_id);
1392 struct ipa *ipa = endpoint->ipa;
1393 struct gsi *gsi = &ipa->gsi;
1396 if (!(ipa->enabled & mask))
1399 ipa->enabled ^= mask;
1401 if (!endpoint->toward_ipa) {
1402 ipa_endpoint_replenish_disable(endpoint);
1403 ipa_interrupt_suspend_disable(ipa->interrupt,
1404 endpoint->endpoint_id);
1407 /* Note that if stop fails, the channel's state is not well-defined */
1408 ret = gsi_channel_stop(gsi, endpoint->channel_id);
1410 dev_err(&ipa->pdev->dev,
1411 "error %d attempting to stop endpoint %u\n", ret,
1412 endpoint->endpoint_id);
1415 void ipa_endpoint_suspend_one(struct ipa_endpoint *endpoint)
1417 struct device *dev = &endpoint->ipa->pdev->dev;
1418 struct gsi *gsi = &endpoint->ipa->gsi;
1422 if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id)))
1425 if (!endpoint->toward_ipa) {
1426 ipa_endpoint_replenish_disable(endpoint);
1427 (void)ipa_endpoint_program_suspend(endpoint, true);
1430 /* IPA v3.5.1 doesn't use channel stop for suspend */
1431 stop_channel = endpoint->ipa->version != IPA_VERSION_3_5_1;
1432 ret = gsi_channel_suspend(gsi, endpoint->channel_id, stop_channel);
1434 dev_err(dev, "error %d suspending channel %u\n", ret,
1435 endpoint->channel_id);
1438 void ipa_endpoint_resume_one(struct ipa_endpoint *endpoint)
1440 struct device *dev = &endpoint->ipa->pdev->dev;
1441 struct gsi *gsi = &endpoint->ipa->gsi;
1445 if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id)))
1448 if (!endpoint->toward_ipa)
1449 (void)ipa_endpoint_program_suspend(endpoint, false);
1451 /* IPA v3.5.1 doesn't use channel start for resume */
1452 start_channel = endpoint->ipa->version != IPA_VERSION_3_5_1;
1453 ret = gsi_channel_resume(gsi, endpoint->channel_id, start_channel);
1455 dev_err(dev, "error %d resuming channel %u\n", ret,
1456 endpoint->channel_id);
1457 else if (!endpoint->toward_ipa)
1458 ipa_endpoint_replenish_enable(endpoint);
1461 void ipa_endpoint_suspend(struct ipa *ipa)
1463 if (!ipa->setup_complete)
1466 if (ipa->modem_netdev)
1467 ipa_modem_suspend(ipa->modem_netdev);
1469 ipa_cmd_tag_process(ipa);
1471 ipa_endpoint_suspend_one(ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]);
1472 ipa_endpoint_suspend_one(ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]);
1475 void ipa_endpoint_resume(struct ipa *ipa)
1477 if (!ipa->setup_complete)
1480 ipa_endpoint_resume_one(ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]);
1481 ipa_endpoint_resume_one(ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]);
1483 if (ipa->modem_netdev)
1484 ipa_modem_resume(ipa->modem_netdev);
1487 static void ipa_endpoint_setup_one(struct ipa_endpoint *endpoint)
1489 struct gsi *gsi = &endpoint->ipa->gsi;
1490 u32 channel_id = endpoint->channel_id;
1492 /* Only AP endpoints get set up */
1493 if (endpoint->ee_id != GSI_EE_AP)
1496 endpoint->trans_tre_max = gsi_channel_trans_tre_max(gsi, channel_id);
1497 if (!endpoint->toward_ipa) {
1498 /* RX transactions require a single TRE, so the maximum
1499 * backlog is the same as the maximum outstanding TREs.
1501 endpoint->replenish_enabled = false;
1502 atomic_set(&endpoint->replenish_saved,
1503 gsi_channel_tre_max(gsi, endpoint->channel_id));
1504 atomic_set(&endpoint->replenish_backlog, 0);
1505 INIT_DELAYED_WORK(&endpoint->replenish_work,
1506 ipa_endpoint_replenish_work);
1509 ipa_endpoint_program(endpoint);
1511 endpoint->ipa->set_up |= BIT(endpoint->endpoint_id);
1514 static void ipa_endpoint_teardown_one(struct ipa_endpoint *endpoint)
1516 endpoint->ipa->set_up &= ~BIT(endpoint->endpoint_id);
1518 if (!endpoint->toward_ipa)
1519 cancel_delayed_work_sync(&endpoint->replenish_work);
1521 ipa_endpoint_reset(endpoint);
1524 void ipa_endpoint_setup(struct ipa *ipa)
1526 u32 initialized = ipa->initialized;
1529 while (initialized) {
1530 u32 endpoint_id = __ffs(initialized);
1532 initialized ^= BIT(endpoint_id);
1534 ipa_endpoint_setup_one(&ipa->endpoint[endpoint_id]);
1538 void ipa_endpoint_teardown(struct ipa *ipa)
1540 u32 set_up = ipa->set_up;
1543 u32 endpoint_id = __fls(set_up);
1545 set_up ^= BIT(endpoint_id);
1547 ipa_endpoint_teardown_one(&ipa->endpoint[endpoint_id]);
1552 int ipa_endpoint_config(struct ipa *ipa)
1554 struct device *dev = &ipa->pdev->dev;
1563 /* Find out about the endpoints supplied by the hardware, and ensure
1564 * the highest one doesn't exceed the number we support.
1566 val = ioread32(ipa->reg_virt + IPA_REG_FLAVOR_0_OFFSET);
1568 /* Our RX is an IPA producer */
1569 rx_base = u32_get_bits(val, IPA_PROD_LOWEST_FMASK);
1570 max = rx_base + u32_get_bits(val, IPA_MAX_PROD_PIPES_FMASK);
1571 if (max > IPA_ENDPOINT_MAX) {
1572 dev_err(dev, "too many endpoints (%u > %u)\n",
1573 max, IPA_ENDPOINT_MAX);
1576 rx_mask = GENMASK(max - 1, rx_base);
1578 /* Our TX is an IPA consumer */
1579 max = u32_get_bits(val, IPA_MAX_CONS_PIPES_FMASK);
1580 tx_mask = GENMASK(max - 1, 0);
1582 ipa->available = rx_mask | tx_mask;
1584 /* Check for initialized endpoints not supported by the hardware */
1585 if (ipa->initialized & ~ipa->available) {
1586 dev_err(dev, "unavailable endpoint id(s) 0x%08x\n",
1587 ipa->initialized & ~ipa->available);
1588 ret = -EINVAL; /* Report other errors too */
1591 initialized = ipa->initialized;
1592 while (initialized) {
1593 u32 endpoint_id = __ffs(initialized);
1594 struct ipa_endpoint *endpoint;
1596 initialized ^= BIT(endpoint_id);
1598 /* Make sure it's pointing in the right direction */
1599 endpoint = &ipa->endpoint[endpoint_id];
1600 if ((endpoint_id < rx_base) != !!endpoint->toward_ipa) {
1601 dev_err(dev, "endpoint id %u wrong direction\n",
1610 void ipa_endpoint_deconfig(struct ipa *ipa)
1612 ipa->available = 0; /* Nothing more to do */
1615 static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name,
1616 const struct ipa_gsi_endpoint_data *data)
1618 struct ipa_endpoint *endpoint;
1620 endpoint = &ipa->endpoint[data->endpoint_id];
1622 if (data->ee_id == GSI_EE_AP)
1623 ipa->channel_map[data->channel_id] = endpoint;
1624 ipa->name_map[name] = endpoint;
1626 endpoint->ipa = ipa;
1627 endpoint->ee_id = data->ee_id;
1628 endpoint->seq_type = data->endpoint.seq_type;
1629 endpoint->channel_id = data->channel_id;
1630 endpoint->endpoint_id = data->endpoint_id;
1631 endpoint->toward_ipa = data->toward_ipa;
1632 endpoint->data = &data->endpoint.config;
1634 ipa->initialized |= BIT(endpoint->endpoint_id);
1637 void ipa_endpoint_exit_one(struct ipa_endpoint *endpoint)
1639 endpoint->ipa->initialized &= ~BIT(endpoint->endpoint_id);
1641 memset(endpoint, 0, sizeof(*endpoint));
1644 void ipa_endpoint_exit(struct ipa *ipa)
1646 u32 initialized = ipa->initialized;
1648 while (initialized) {
1649 u32 endpoint_id = __fls(initialized);
1651 initialized ^= BIT(endpoint_id);
1653 ipa_endpoint_exit_one(&ipa->endpoint[endpoint_id]);
1655 memset(ipa->name_map, 0, sizeof(ipa->name_map));
1656 memset(ipa->channel_map, 0, sizeof(ipa->channel_map));
1659 /* Returns a bitmask of endpoints that support filtering, or 0 on error */
1660 u32 ipa_endpoint_init(struct ipa *ipa, u32 count,
1661 const struct ipa_gsi_endpoint_data *data)
1663 enum ipa_endpoint_name name;
1666 if (!ipa_endpoint_data_valid(ipa, count, data))
1667 return 0; /* Error */
1669 ipa->initialized = 0;
1672 for (name = 0; name < count; name++, data++) {
1673 if (ipa_gsi_endpoint_data_empty(data))
1674 continue; /* Skip over empty slots */
1676 ipa_endpoint_init_one(ipa, name, data);
1678 if (data->endpoint.filter_support)
1679 filter_map |= BIT(data->endpoint_id);
1682 if (!ipa_filter_map_valid(ipa, filter_map))
1683 goto err_endpoint_exit;
1685 return filter_map; /* Non-zero bitmask */
1688 ipa_endpoint_exit(ipa);
1690 return 0; /* Error */