drivers/net/ipa/ipa_data-v4.2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /* Copyright (C) 2019-2021 Linaro Ltd. */
   4
   5 #include <linux/log2.h>
   6
   7 #include "gsi.h"
   8 #include "ipa_data.h"
   9 #include "ipa_endpoint.h"
  10 #include "ipa_mem.h"
  11
  12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.2 */
  13 enum ipa_resource_type {
  14         /* Source resource types; first must have value 0 */
  15         IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS              = 0,
  16         IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
  17         IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
  18         IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
  19         IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
  20
  21         /* Destination resource types; first must have value 0 */
  22         IPA_RESOURCE_TYPE_DST_DATA_SECTORS              = 0,
  23         IPA_RESOURCE_TYPE_DST_DPS_DMARS,
  24 };
  25
  26 /* Resource groups used for an SoC having IPA v4.2 */
  27 enum ipa_rsrc_group_id {
  28         /* Source resource group identifiers */
  29         IPA_RSRC_GROUP_SRC_UL_DL        = 0,
  30         IPA_RSRC_GROUP_SRC_COUNT,       /* Last in set; not a source group */
  31
  32         /* Destination resource group identifiers */
  33         IPA_RSRC_GROUP_DST_UL_DL_DPL    = 0,
  34         IPA_RSRC_GROUP_DST_COUNT,       /* Last; not a destination group */
  35 };
  36
  37 /* QSB configuration data for an SoC having IPA v4.2 */
  38 static const struct ipa_qsb_data ipa_qsb_data[] = {
  39         [IPA_QSB_MASTER_DDR] = {
  40                 .max_writes     = 8,
  41                 .max_reads      = 12,
  42                 /* no outstanding read byte (beat) limit */
  43         },
  44 };
  45
  46 /* Endpoint configuration data for an SoC having IPA v4.2 */
  47 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
  48         [IPA_ENDPOINT_AP_COMMAND_TX] = {
  49                 .ee_id          = GSI_EE_AP,
  50                 .channel_id     = 1,
  51                 .endpoint_id    = 6,
  52                 .toward_ipa     = true,
  53                 .channel = {
  54                         .tre_count      = 256,
  55                         .event_count    = 256,
  56                         .tlv_count      = 20,
  57                 },
  58                 .endpoint = {
  59                         .config = {
  60                                 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
  61                                 .dma_mode       = true,
  62                                 .dma_endpoint   = IPA_ENDPOINT_AP_LAN_RX,
  63                                 .tx = {
  64                                         .seq_type = IPA_SEQ_DMA,
  65                                 },
  66                         },
  67                 },
  68         },
  69         [IPA_ENDPOINT_AP_LAN_RX] = {
  70                 .ee_id          = GSI_EE_AP,
  71                 .channel_id     = 2,
  72                 .endpoint_id    = 8,
  73                 .toward_ipa     = false,
  74                 .channel = {
  75                         .tre_count      = 256,
  76                         .event_count    = 256,
  77                         .tlv_count      = 6,
  78                 },
  79                 .endpoint = {
  80                         .config = {
  81                                 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
  82                                 .aggregation    = true,
  83                                 .status_enable  = true,
  84                                 .rx = {
  85                                         .pad_align      = ilog2(sizeof(u32)),
  86                                 },
  87                         },
  88                 },
  89         },
  90         [IPA_ENDPOINT_AP_MODEM_TX] = {
  91                 .ee_id          = GSI_EE_AP,
  92                 .channel_id     = 0,
  93                 .endpoint_id    = 1,
  94                 .toward_ipa     = true,
  95                 .channel = {
  96                         .tre_count      = 512,
  97                         .event_count    = 512,
  98                         .tlv_count      = 8,
  99                 },
 100                 .endpoint = {
 101                         .filter_support = true,
 102                         .config = {
 103                                 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
 104                                 .checksum       = true,
 105                                 .qmap           = true,
 106                                 .status_enable  = true,
 107                                 .tx = {
 108                                         .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC,
 109                                         .seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
 110                                         .status_endpoint =
 111                                                 IPA_ENDPOINT_MODEM_AP_RX,
 112                                 },
 113                         },
 114                 },
 115         },
 116         [IPA_ENDPOINT_AP_MODEM_RX] = {
 117                 .ee_id          = GSI_EE_AP,
 118                 .channel_id     = 3,
 119                 .endpoint_id    = 9,
 120                 .toward_ipa     = false,
 121                 .channel = {
 122                         .tre_count      = 256,
 123                         .event_count    = 256,
 124                         .tlv_count      = 6,
 125                 },
 126                 .endpoint = {
 127                         .config = {
 128                                 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
 129                                 .checksum       = true,
 130                                 .qmap           = true,
 131                                 .aggregation    = true,
 132                                 .rx = {
 133                                         .aggr_close_eof = true,
 134                                 },
 135                         },
 136                 },
 137         },
 138         [IPA_ENDPOINT_MODEM_COMMAND_TX] = {
 139                 .ee_id          = GSI_EE_MODEM,
 140                 .channel_id     = 1,
 141                 .endpoint_id    = 5,
 142                 .toward_ipa     = true,
 143         },
 144         [IPA_ENDPOINT_MODEM_LAN_RX] = {
 145                 .ee_id          = GSI_EE_MODEM,
 146                 .channel_id     = 3,
 147                 .endpoint_id    = 11,
 148                 .toward_ipa     = false,
 149         },
 150         [IPA_ENDPOINT_MODEM_AP_TX] = {
 151                 .ee_id          = GSI_EE_MODEM,
 152                 .channel_id     = 0,
 153                 .endpoint_id    = 4,
 154                 .toward_ipa     = true,
 155                 .endpoint = {
 156                         .filter_support = true,
 157                 },
 158         },
 159         [IPA_ENDPOINT_MODEM_AP_RX] = {
 160                 .ee_id          = GSI_EE_MODEM,
 161                 .channel_id     = 2,
 162                 .endpoint_id    = 10,
 163                 .toward_ipa     = false,
 164         },
 165 };
 166
 167 /* Source resource configuration data for an SoC having IPA v4.2 */
 168 static const struct ipa_resource ipa_resource_src[] = {
 169         [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
 170                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 171                         .min = 3,       .max = 63,
 172                 },
 173         },
 174         [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
 175                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 176                         .min = 3,       .max = 3,
 177                 },
 178         },
 179         [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
 180                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 181                         .min = 10,      .max = 10,
 182                 },
 183         },
 184         [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
 185                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 186                         .min = 1,       .max = 1,
 187                 },
 188         },
 189         [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
 190                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 191                         .min = 5,       .max = 5,
 192                 },
 193         },
 194 };
 195
 196 /* Destination resource configuration data for an SoC having IPA v4.2 */
 197 static const struct ipa_resource ipa_resource_dst[] = {
 198         [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
 199                 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
 200                         .min = 3,       .max = 3,
 201                 },
 202         },
 203         [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
 204                 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
 205                         .min = 1,       .max = 63,
 206                 },
 207         },
 208 };
 209
 210 /* Resource configuration data for an SoC having IPA v4.2 */
 211 static const struct ipa_resource_data ipa_resource_data = {
 212         .rsrc_group_src_count   = IPA_RSRC_GROUP_SRC_COUNT,
 213         .rsrc_group_dst_count   = IPA_RSRC_GROUP_DST_COUNT,
 214         .resource_src_count     = ARRAY_SIZE(ipa_resource_src),
 215         .resource_src           = ipa_resource_src,
 216         .resource_dst_count     = ARRAY_SIZE(ipa_resource_dst),
 217         .resource_dst           = ipa_resource_dst,
 218 };
 219
 220 /* IPA-resident memory region data for an SoC having IPA v4.2 */
 221 static const struct ipa_mem ipa_mem_local_data[] = {
 222         {
 223                 .id             = IPA_MEM_UC_SHARED,
 224                 .offset         = 0x0000,
 225                 .size           = 0x0080,
 226                 .canary_count   = 0,
 227         },
 228         {
 229                 .id             = IPA_MEM_UC_INFO,
 230                 .offset         = 0x0080,
 231                 .size           = 0x0200,
 232                 .canary_count   = 0,
 233         },
 234         {
 235                 .id             = IPA_MEM_V4_FILTER_HASHED,
 236                 .offset         = 0x0288,
 237                 .size           = 0,
 238                 .canary_count   = 2,
 239         },
 240         {
 241                 .id             = IPA_MEM_V4_FILTER,
 242                 .offset         = 0x0290,
 243                 .size           = 0x0078,
 244                 .canary_count   = 2,
 245         },
 246         {
 247                 .id             = IPA_MEM_V6_FILTER_HASHED,
 248                 .offset         = 0x0310,
 249                 .size           = 0,
 250                 .canary_count   = 2,
 251         },
 252         {
 253                 .id             = IPA_MEM_V6_FILTER,
 254                 .offset         = 0x0318,
 255                 .size           = 0x0078,
 256                 .canary_count   = 2,
 257         },
 258         {
 259                 .id             = IPA_MEM_V4_ROUTE_HASHED,
 260                 .offset         = 0x0398,
 261                 .size           = 0,
 262                 .canary_count   = 2,
 263         },
 264         {
 265                 .id             = IPA_MEM_V4_ROUTE,
 266                 .offset         = 0x03a0,
 267                 .size           = 0x0078,
 268                 .canary_count   = 2,
 269         },
 270         {
 271                 .id             = IPA_MEM_V6_ROUTE_HASHED,
 272                 .offset         = 0x0420,
 273                 .size           = 0,
 274                 .canary_count   = 2,
 275         },
 276         {
 277                 .id             = IPA_MEM_V6_ROUTE,
 278                 .offset         = 0x0428,
 279                 .size           = 0x0078,
 280                 .canary_count   = 2,
 281         },
 282         {
 283                 .id             = IPA_MEM_MODEM_HEADER,
 284                 .offset         = 0x04a8,
 285                 .size           = 0x0140,
 286                 .canary_count   = 2,
 287         },
 288         {
 289                 .id             = IPA_MEM_MODEM_PROC_CTX,
 290                 .offset         = 0x05f0,
 291                 .size           = 0x0200,
 292                 .canary_count   = 2,
 293         },
 294         {
 295                 .id             = IPA_MEM_AP_PROC_CTX,
 296                 .offset         = 0x07f0,
 297                 .size           = 0x0200,
 298                 .canary_count   = 0,
 299         },
 300         {
 301                 .id             = IPA_MEM_PDN_CONFIG,
 302                 .offset         = 0x09f8,
 303                 .size           = 0x0050,
 304                 .canary_count   = 2,
 305         },
 306         {
 307                 .id             = IPA_MEM_STATS_QUOTA_MODEM,
 308                 .offset         = 0x0a50,
 309                 .size           = 0x0060,
 310                 .canary_count   = 2,
 311         },
 312         {
 313                 .id             = IPA_MEM_STATS_TETHERING,
 314                 .offset         = 0x0ab0,
 315                 .size           = 0x0140,
 316                 .canary_count   = 0,
 317         },
 318         {
 319                 .id             = IPA_MEM_MODEM,
 320                 .offset         = 0x0bf0,
 321                 .size           = 0x140c,
 322                 .canary_count   = 0,
 323         },
 324         {
 325                 .id             = IPA_MEM_END_MARKER,
 326                 .offset         = 0x2000,
 327                 .size           = 0,
 328                 .canary_count   = 1,
 329         },
 330 };
 331
 332 /* Memory configuration data for an SoC having IPA v4.2 */
 333 static const struct ipa_mem_data ipa_mem_data = {
 334         .local_count    = ARRAY_SIZE(ipa_mem_local_data),
 335         .local          = ipa_mem_local_data,
 336         .imem_addr      = 0x146a8000,
 337         .imem_size      = 0x00002000,
 338         .smem_id        = 497,
 339         .smem_size      = 0x00002000,
 340 };
 341
 342 /* Interconnect rates are in 1000 byte/second units */
 343 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
 344         {
 345                 .name                   = "memory",
 346                 .peak_bandwidth         = 465000,       /* 465 MBps */
 347                 .average_bandwidth      = 80000,        /* 80 MBps */
 348         },
 349         /* Average bandwidth is unused for the next two interconnects */
 350         {
 351                 .name                   = "imem",
 352                 .peak_bandwidth         = 68570,        /* 68.570 MBps */
 353                 .average_bandwidth      = 0,            /* unused */
 354         },
 355         {
 356                 .name                   = "config",
 357                 .peak_bandwidth         = 30000,        /* 30 MBps */
 358                 .average_bandwidth      = 0,            /* unused */
 359         },
 360 };
 361
 362 /* Clock and interconnect configuration data for an SoC having IPA v4.2 */
 363 static const struct ipa_clock_data ipa_clock_data = {
 364         .core_clock_rate        = 100 * 1000 * 1000,    /* Hz */
 365         .interconnect_count     = ARRAY_SIZE(ipa_interconnect_data),
 366         .interconnect_data      = ipa_interconnect_data,
 367 };
 368
 369 /* Configuration data for an SoC having IPA v4.2 */
 370 const struct ipa_data ipa_data_v4_2 = {
 371         .version        = IPA_VERSION_4_2,
 372         /* backward_compat value is 0 */
 373         .qsb_count      = ARRAY_SIZE(ipa_qsb_data),
 374         .qsb_data       = ipa_qsb_data,
 375         .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
 376         .endpoint_data  = ipa_gsi_endpoint_data,
 377         .resource_data  = &ipa_resource_data,
 378         .mem_data       = &ipa_mem_data,
 379         .clock_data     = &ipa_clock_data,
 380 };