drivers/net/ipa/ipa_data-v3.1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2019-2021 Linaro Ltd.
   5  */
   6
   7 #include <linux/log2.h>
   8
   9 #include "gsi.h"
  10 #include "ipa_data.h"
  11 #include "ipa_endpoint.h"
  12 #include "ipa_mem.h"
  13
  14 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */
  15 enum ipa_resource_type {
  16         /* Source resource types; first must have value 0 */
  17         IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS              = 0,
  18         IPA_RESOURCE_TYPE_SRC_HDR_SECTORS,
  19         IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER,
  20         IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
  21         IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
  22         IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS,
  23         IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
  24         IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
  25
  26         /* Destination resource types; first must have value 0 */
  27         IPA_RESOURCE_TYPE_DST_DATA_SECTORS              = 0,
  28         IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS,
  29         IPA_RESOURCE_TYPE_DST_DPS_DMARS,
  30 };
  31
  32 /* Resource groups used for an SoC having IPA v3.1 */
  33 enum ipa_rsrc_group_id {
  34         /* Source resource group identifiers */
  35         IPA_RSRC_GROUP_SRC_UL           = 0,
  36         IPA_RSRC_GROUP_SRC_DL,
  37         IPA_RSRC_GROUP_SRC_DIAG,
  38         IPA_RSRC_GROUP_SRC_DMA,
  39         IPA_RSRC_GROUP_SRC_UNUSED,
  40         IPA_RSRC_GROUP_SRC_UC_RX_Q,
  41         IPA_RSRC_GROUP_SRC_COUNT,       /* Last in set; not a source group */
  42
  43         /* Destination resource group identifiers */
  44         IPA_RSRC_GROUP_DST_UL           = 0,
  45         IPA_RSRC_GROUP_DST_DL,
  46         IPA_RSRC_GROUP_DST_DIAG_DPL,
  47         IPA_RSRC_GROUP_DST_DMA,
  48         IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL,
  49         IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE,
  50         IPA_RSRC_GROUP_DST_COUNT,       /* Last; not a destination group */
  51 };
  52
  53 /* QSB configuration data for an SoC having IPA v3.1 */
  54 static const struct ipa_qsb_data ipa_qsb_data[] = {
  55         [IPA_QSB_MASTER_DDR] = {
  56                 .max_writes     = 8,
  57                 .max_reads      = 8,
  58         },
  59         [IPA_QSB_MASTER_PCIE] = {
  60                 .max_writes     = 2,
  61                 .max_reads      = 8,
  62         },
  63 };
  64
  65 /* Endpoint data for an SoC having IPA v3.1 */
  66 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
  67         [IPA_ENDPOINT_AP_COMMAND_TX] = {
  68                 .ee_id          = GSI_EE_AP,
  69                 .channel_id     = 6,
  70                 .endpoint_id    = 22,
  71                 .toward_ipa     = true,
  72                 .channel = {
  73                         .tre_count      = 256,
  74                         .event_count    = 256,
  75                         .tlv_count      = 18,
  76                 },
  77                 .endpoint = {
  78                         .config = {
  79                                 .resource_group = IPA_RSRC_GROUP_SRC_UL,
  80                                 .dma_mode       = true,
  81                                 .dma_endpoint   = IPA_ENDPOINT_AP_LAN_RX,
  82                                 .tx = {
  83                                         .seq_type = IPA_SEQ_DMA,
  84                                 },
  85                         },
  86                 },
  87         },
  88         [IPA_ENDPOINT_AP_LAN_RX] = {
  89                 .ee_id          = GSI_EE_AP,
  90                 .channel_id     = 7,
  91                 .endpoint_id    = 15,
  92                 .toward_ipa     = false,
  93                 .channel = {
  94                         .tre_count      = 256,
  95                         .event_count    = 256,
  96                         .tlv_count      = 8,
  97                 },
  98                 .endpoint = {
  99                         .config = {
 100                                 .resource_group = IPA_RSRC_GROUP_SRC_UL,
 101                                 .aggregation    = true,
 102                                 .status_enable  = true,
 103                                 .rx = {
 104                                         .pad_align      = ilog2(sizeof(u32)),
 105                                 },
 106                         },
 107                 },
 108         },
 109         [IPA_ENDPOINT_AP_MODEM_TX] = {
 110                 .ee_id          = GSI_EE_AP,
 111                 .channel_id     = 5,
 112                 .endpoint_id    = 3,
 113                 .toward_ipa     = true,
 114                 .channel = {
 115                         .tre_count      = 512,
 116                         .event_count    = 512,
 117                         .tlv_count      = 16,
 118                 },
 119                 .endpoint = {
 120                         .filter_support = true,
 121                         .config = {
 122                                 .resource_group = IPA_RSRC_GROUP_SRC_UL,
 123                                 .checksum       = true,
 124                                 .qmap           = true,
 125                                 .status_enable  = true,
 126                                 .tx = {
 127                                         .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
 128                                         .status_endpoint =
 129                                                 IPA_ENDPOINT_MODEM_AP_RX,
 130                                 },
 131                         },
 132                 },
 133         },
 134         [IPA_ENDPOINT_AP_MODEM_RX] = {
 135                 .ee_id          = GSI_EE_AP,
 136                 .channel_id     = 8,
 137                 .endpoint_id    = 16,
 138                 .toward_ipa     = false,
 139                 .channel = {
 140                         .tre_count      = 256,
 141                         .event_count    = 256,
 142                         .tlv_count      = 8,
 143                 },
 144                 .endpoint = {
 145                         .config = {
 146                                 .resource_group = IPA_RSRC_GROUP_DST_DL,
 147                                 .checksum       = true,
 148                                 .qmap           = true,
 149                                 .aggregation    = true,
 150                                 .rx = {
 151                                         .aggr_close_eof = true,
 152                                 },
 153                         },
 154                 },
 155         },
 156         [IPA_ENDPOINT_MODEM_LAN_TX] = {
 157                 .ee_id          = GSI_EE_MODEM,
 158                 .channel_id     = 4,
 159                 .endpoint_id    = 9,
 160                 .toward_ipa     = true,
 161                 .endpoint = {
 162                         .filter_support = true,
 163                 },
 164         },
 165         [IPA_ENDPOINT_MODEM_AP_TX] = {
 166                 .ee_id          = GSI_EE_MODEM,
 167                 .channel_id     = 0,
 168                 .endpoint_id    = 5,
 169                 .toward_ipa     = true,
 170                 .endpoint = {
 171                         .filter_support = true,
 172                 },
 173         },
 174         [IPA_ENDPOINT_MODEM_AP_RX] = {
 175                 .ee_id          = GSI_EE_MODEM,
 176                 .channel_id     = 5,
 177                 .endpoint_id    = 18,
 178                 .toward_ipa     = false,
 179         },
 180 };
 181
 182 /* Source resource configuration data for an SoC having IPA v3.1 */
 183 static const struct ipa_resource ipa_resource_src[] = {
 184         [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
 185                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 186                         .min = 3,       .max = 255,
 187                 },
 188                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 189                         .min = 3,       .max = 255,
 190                 },
 191                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 192                         .min = 1,       .max = 255,
 193                 },
 194                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 195                         .min = 1,       .max = 255,
 196                 },
 197                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 198                         .min = 2,       .max = 255,
 199                 },
 200         },
 201         [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = {
 202                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 203                         .min = 0,       .max = 255,
 204                 },
 205                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 206                         .min = 0,       .max = 255,
 207                 },
 208                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 209                         .min = 0,       .max = 255,
 210                 },
 211                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 212                         .min = 0,       .max = 255,
 213                 },
 214                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 215                         .min = 0,       .max = 255,
 216                 },
 217         },
 218         [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = {
 219                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 220                         .min = 0,       .max = 255,
 221                 },
 222                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 223                         .min = 0,       .max = 255,
 224                 },
 225                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 226                         .min = 0,       .max = 255,
 227                 },
 228                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 229                         .min = 0,       .max = 255,
 230                 },
 231                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 232                         .min = 0,       .max = 255,
 233                 },
 234         },
 235         [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
 236                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 237                         .min = 14,      .max = 14,
 238                 },
 239                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 240                         .min = 16,      .max = 16,
 241                 },
 242                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 243                         .min = 5,       .max = 5,
 244                 },
 245                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 246                         .min = 5,       .max = 5,
 247                 },
 248                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 249                         .min = 8,       .max = 8,
 250                 },
 251         },
 252         [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
 253                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 254                         .min = 19,      .max = 19,
 255                 },
 256                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 257                         .min = 26,      .max = 26,
 258                 },
 259                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 260                         .min = 5,       .max = 5,       /* 3 downstream */
 261                 },
 262                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 263                         .min = 5,       .max = 5,       /* 7 downstream */
 264                 },
 265                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 266                         .min = 8,       .max = 8,
 267                 },
 268         },
 269         [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = {
 270                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 271                         .min = 0,       .max = 255,
 272                 },
 273                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 274                         .min = 0,       .max = 255,
 275                 },
 276                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 277                         .min = 0,       .max = 255,
 278                 },
 279                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 280                         .min = 0,       .max = 255,
 281                 },
 282                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 283                         .min = 0,       .max = 255,
 284                 },
 285         },
 286         [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
 287                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 288                         .min = 0,       .max = 255,
 289                 },
 290                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 291                         .min = 0,       .max = 255,
 292                 },
 293                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 294                         .min = 0,       .max = 255,
 295                 },
 296                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 297                         .min = 0,       .max = 255,
 298                 },
 299                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 300                         .min = 0,       .max = 255,
 301                 },
 302         },
 303         [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
 304                 .limits[IPA_RSRC_GROUP_SRC_UL] = {
 305                         .min = 19,      .max = 19,
 306                 },
 307                 .limits[IPA_RSRC_GROUP_SRC_DL] = {
 308                         .min = 26,      .max = 26,
 309                 },
 310                 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
 311                         .min = 5,       .max = 5,
 312                 },
 313                 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
 314                         .min = 5,       .max = 5,
 315                 },
 316                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 317                         .min = 8,       .max = 8,
 318                 },
 319         },
 320 };
 321
 322 /* Destination resource configuration data for an SoC having IPA v3.1 */
 323 static const struct ipa_resource ipa_resource_dst[] = {
 324         [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
 325                 .limits[IPA_RSRC_GROUP_DST_UL] = {
 326                         .min = 3,       .max = 3,       /* 2 downstream */
 327                 },
 328                 .limits[IPA_RSRC_GROUP_DST_DL] = {
 329                         .min = 3,       .max = 3,
 330                 },
 331                 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
 332                         .min = 1,       .max = 1,       /* 0 downstream */
 333                 },
 334                 /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */
 335                 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
 336                         .min = 3,       .max = 3,
 337                 },
 338                 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
 339                         .min = 3,       .max = 3,
 340                 },
 341         },
 342         [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = {
 343                 .limits[IPA_RSRC_GROUP_DST_UL] = {
 344                         .min = 0,       .max = 255,
 345                 },
 346                 .limits[IPA_RSRC_GROUP_DST_DL] = {
 347                         .min = 0,       .max = 255,
 348                 },
 349                 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
 350                         .min = 0,       .max = 255,
 351                 },
 352                 .limits[IPA_RSRC_GROUP_DST_DMA] = {
 353                         .min = 0,       .max = 255,
 354                 },
 355                 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
 356                         .min = 0,       .max = 255,
 357                 },
 358                 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
 359                         .min = 0,       .max = 255,
 360                 },
 361         },
 362         [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
 363                 .limits[IPA_RSRC_GROUP_DST_UL] = {
 364                         .min = 1,       .max = 1,
 365                 },
 366                 .limits[IPA_RSRC_GROUP_DST_DL] = {
 367                         .min = 1,       .max = 1,
 368                 },
 369                 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
 370                         .min = 1,       .max = 1,
 371                 },
 372                 .limits[IPA_RSRC_GROUP_DST_DMA] = {
 373                         .min = 1,       .max = 1,
 374                 },
 375                 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
 376                         .min = 1,       .max = 1,
 377                 },
 378         },
 379 };
 380
 381 /* Resource configuration data for an SoC having IPA v3.1 */
 382 static const struct ipa_resource_data ipa_resource_data = {
 383         .rsrc_group_src_count   = IPA_RSRC_GROUP_SRC_COUNT,
 384         .rsrc_group_dst_count   = IPA_RSRC_GROUP_DST_COUNT,
 385         .resource_src_count     = ARRAY_SIZE(ipa_resource_src),
 386         .resource_src           = ipa_resource_src,
 387         .resource_dst_count     = ARRAY_SIZE(ipa_resource_dst),
 388         .resource_dst           = ipa_resource_dst,
 389 };
 390
 391 /* IPA-resident memory region data for an SoC having IPA v3.1 */
 392 static const struct ipa_mem ipa_mem_local_data[] = {
 393         {
 394                 .id             = IPA_MEM_UC_SHARED,
 395                 .offset         = 0x0000,
 396                 .size           = 0x0080,
 397                 .canary_count   = 0,
 398         },
 399         {
 400                 .id             = IPA_MEM_UC_INFO,
 401                 .offset         = 0x0080,
 402                 .size           = 0x0200,
 403                 .canary_count   = 0,
 404         },
 405         {
 406                 .id             = IPA_MEM_V4_FILTER_HASHED,
 407                 .offset         = 0x0288,
 408                 .size           = 0x0078,
 409                 .canary_count   = 2,
 410         },
 411         {
 412                 .id             = IPA_MEM_V4_FILTER,
 413                 .offset         = 0x0308,
 414                 .size           = 0x0078,
 415                 .canary_count   = 2,
 416         },
 417         {
 418                 .id             = IPA_MEM_V6_FILTER_HASHED,
 419                 .offset         = 0x0388,
 420                 .size           = 0x0078,
 421                 .canary_count   = 2,
 422         },
 423         {
 424                 .id             = IPA_MEM_V6_FILTER,
 425                 .offset         = 0x0408,
 426                 .size           = 0x0078,
 427                 .canary_count   = 2,
 428         },
 429         {
 430                 .id             = IPA_MEM_V4_ROUTE_HASHED,
 431                 .offset         = 0x0488,
 432                 .size           = 0x0078,
 433                 .canary_count   = 2,
 434         },
 435         {
 436                 .id             = IPA_MEM_V4_ROUTE,
 437                 .offset         = 0x0508,
 438                 .size           = 0x0078,
 439                 .canary_count   = 2,
 440         },
 441         {
 442                 .id             = IPA_MEM_V6_ROUTE_HASHED,
 443                 .offset         = 0x0588,
 444                 .size           = 0x0078,
 445                 .canary_count   = 2,
 446         },
 447         {
 448                 .id             = IPA_MEM_V6_ROUTE,
 449                 .offset         = 0x0608,
 450                 .size           = 0x0078,
 451                 .canary_count   = 2,
 452         },
 453         {
 454                 .id             = IPA_MEM_MODEM_HEADER,
 455                 .offset         = 0x0688,
 456                 .size           = 0x0140,
 457                 .canary_count   = 2,
 458         },
 459         {
 460                 .id             = IPA_MEM_MODEM_PROC_CTX,
 461                 .offset         = 0x07d0,
 462                 .size           = 0x0200,
 463                 .canary_count   = 2,
 464         },
 465         {
 466                 .id             = IPA_MEM_AP_PROC_CTX,
 467                 .offset         = 0x09d0,
 468                 .size           = 0x0200,
 469                 .canary_count   = 0,
 470         },
 471         {
 472                 .id             = IPA_MEM_MODEM,
 473                 .offset         = 0x0bd8,
 474                 .size           = 0x1424,
 475                 .canary_count   = 0,
 476         },
 477         {
 478                 .id             = IPA_MEM_END_MARKER,
 479                 .offset         = 0x2000,
 480                 .size           = 0,
 481                 .canary_count   = 1,
 482         },
 483 };
 484
 485 /* Memory configuration data for an SoC having IPA v3.1 */
 486 static const struct ipa_mem_data ipa_mem_data = {
 487         .local_count    = ARRAY_SIZE(ipa_mem_local_data),
 488         .local          = ipa_mem_local_data,
 489         .imem_addr      = 0x146bd000,
 490         .imem_size      = 0x00002000,
 491         .smem_id        = 497,
 492         .smem_size      = 0x00002000,
 493 };
 494
 495 /* Interconnect bandwidths are in 1000 byte/second units */
 496 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
 497         {
 498                 .name                   = "memory",
 499                 .peak_bandwidth         = 640000,       /* 640 MBps */
 500                 .average_bandwidth      = 80000,        /* 80 MBps */
 501         },
 502         {
 503                 .name                   = "imem",
 504                 .peak_bandwidth         = 640000,       /* 640 MBps */
 505                 .average_bandwidth      = 80000,        /* 80 MBps */
 506         },
 507         /* Average bandwidth is unused for the next interconnect */
 508         {
 509                 .name                   = "config",
 510                 .peak_bandwidth         = 80000,        /* 80 MBps */
 511                 .average_bandwidth      = 0,            /* unused */
 512         },
 513 };
 514
 515 /* Clock and interconnect configuration data for an SoC having IPA v3.1 */
 516 static const struct ipa_clock_data ipa_clock_data = {
 517         .core_clock_rate        = 16 * 1000 * 1000,     /* Hz */
 518         .interconnect_count     = ARRAY_SIZE(ipa_interconnect_data),
 519         .interconnect_data      = ipa_interconnect_data,
 520 };
 521
 522 /* Configuration data for an SoC having IPA v3.1 */
 523 const struct ipa_data ipa_data_v3_1 = {
 524         .version        = IPA_VERSION_3_1,
 525         .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK,
 526         .qsb_count      = ARRAY_SIZE(ipa_qsb_data),
 527         .qsb_data       = ipa_qsb_data,
 528         .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
 529         .endpoint_data  = ipa_gsi_endpoint_data,
 530         .resource_data  = &ipa_resource_data,
 531         .mem_data       = &ipa_mem_data,
 532         .clock_data     = &ipa_clock_data,
 533 };