1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2021 Linaro Ltd.
7 #include <linux/log2.h>
11 #include "ipa_endpoint.h"
14 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */
15 enum ipa_resource_type {
16 /* Source resource types; first must have value 0 */
17 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
18 IPA_RESOURCE_TYPE_SRC_HDR_SECTORS,
19 IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER,
20 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
21 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
22 IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS,
23 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
24 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
26 /* Destination resource types; first must have value 0 */
27 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
28 IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS,
29 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
32 /* Resource groups used for an SoC having IPA v3.1 */
33 enum ipa_rsrc_group_id {
34 /* Source resource group identifiers */
35 IPA_RSRC_GROUP_SRC_UL = 0,
36 IPA_RSRC_GROUP_SRC_DL,
37 IPA_RSRC_GROUP_SRC_DIAG,
38 IPA_RSRC_GROUP_SRC_DMA,
39 IPA_RSRC_GROUP_SRC_UNUSED,
40 IPA_RSRC_GROUP_SRC_UC_RX_Q,
41 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
43 /* Destination resource group identifiers */
44 IPA_RSRC_GROUP_DST_UL = 0,
45 IPA_RSRC_GROUP_DST_DL,
46 IPA_RSRC_GROUP_DST_DIAG_DPL,
47 IPA_RSRC_GROUP_DST_DMA,
48 IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL,
49 IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE,
50 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
53 /* QSB configuration data for an SoC having IPA v3.1 */
54 static const struct ipa_qsb_data ipa_qsb_data[] = {
55 [IPA_QSB_MASTER_DDR] = {
59 [IPA_QSB_MASTER_PCIE] = {
65 /* Endpoint data for an SoC having IPA v3.1 */
66 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
67 [IPA_ENDPOINT_AP_COMMAND_TX] = {
79 .resource_group = IPA_RSRC_GROUP_SRC_UL,
81 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
83 .seq_type = IPA_SEQ_DMA,
88 [IPA_ENDPOINT_AP_LAN_RX] = {
100 .resource_group = IPA_RSRC_GROUP_SRC_UL,
102 .status_enable = true,
104 .pad_align = ilog2(sizeof(u32)),
109 [IPA_ENDPOINT_AP_MODEM_TX] = {
120 .filter_support = true,
122 .resource_group = IPA_RSRC_GROUP_SRC_UL,
125 .status_enable = true,
127 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
129 IPA_ENDPOINT_MODEM_AP_RX,
134 [IPA_ENDPOINT_AP_MODEM_RX] = {
146 .resource_group = IPA_RSRC_GROUP_DST_DL,
151 .aggr_close_eof = true,
156 [IPA_ENDPOINT_MODEM_LAN_TX] = {
157 .ee_id = GSI_EE_MODEM,
162 .filter_support = true,
165 [IPA_ENDPOINT_MODEM_AP_TX] = {
166 .ee_id = GSI_EE_MODEM,
171 .filter_support = true,
174 [IPA_ENDPOINT_MODEM_AP_RX] = {
175 .ee_id = GSI_EE_MODEM,
182 /* Source resource configuration data for an SoC having IPA v3.1 */
183 static const struct ipa_resource ipa_resource_src[] = {
184 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
185 .limits[IPA_RSRC_GROUP_SRC_UL] = {
186 .min = 3, .max = 255,
188 .limits[IPA_RSRC_GROUP_SRC_DL] = {
189 .min = 3, .max = 255,
191 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
192 .min = 1, .max = 255,
194 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
195 .min = 1, .max = 255,
197 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
198 .min = 2, .max = 255,
201 [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = {
202 .limits[IPA_RSRC_GROUP_SRC_UL] = {
203 .min = 0, .max = 255,
205 .limits[IPA_RSRC_GROUP_SRC_DL] = {
206 .min = 0, .max = 255,
208 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
209 .min = 0, .max = 255,
211 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
212 .min = 0, .max = 255,
214 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
215 .min = 0, .max = 255,
218 [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = {
219 .limits[IPA_RSRC_GROUP_SRC_UL] = {
220 .min = 0, .max = 255,
222 .limits[IPA_RSRC_GROUP_SRC_DL] = {
223 .min = 0, .max = 255,
225 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
226 .min = 0, .max = 255,
228 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
229 .min = 0, .max = 255,
231 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
232 .min = 0, .max = 255,
235 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
236 .limits[IPA_RSRC_GROUP_SRC_UL] = {
237 .min = 14, .max = 14,
239 .limits[IPA_RSRC_GROUP_SRC_DL] = {
240 .min = 16, .max = 16,
242 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
245 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
248 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
252 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
253 .limits[IPA_RSRC_GROUP_SRC_UL] = {
254 .min = 19, .max = 19,
256 .limits[IPA_RSRC_GROUP_SRC_DL] = {
257 .min = 26, .max = 26,
259 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
260 .min = 5, .max = 5, /* 3 downstream */
262 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
263 .min = 5, .max = 5, /* 7 downstream */
265 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
269 [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = {
270 .limits[IPA_RSRC_GROUP_SRC_UL] = {
271 .min = 0, .max = 255,
273 .limits[IPA_RSRC_GROUP_SRC_DL] = {
274 .min = 0, .max = 255,
276 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
277 .min = 0, .max = 255,
279 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
280 .min = 0, .max = 255,
282 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
283 .min = 0, .max = 255,
286 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
287 .limits[IPA_RSRC_GROUP_SRC_UL] = {
288 .min = 0, .max = 255,
290 .limits[IPA_RSRC_GROUP_SRC_DL] = {
291 .min = 0, .max = 255,
293 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
294 .min = 0, .max = 255,
296 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
297 .min = 0, .max = 255,
299 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
300 .min = 0, .max = 255,
303 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
304 .limits[IPA_RSRC_GROUP_SRC_UL] = {
305 .min = 19, .max = 19,
307 .limits[IPA_RSRC_GROUP_SRC_DL] = {
308 .min = 26, .max = 26,
310 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
313 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
316 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
322 /* Destination resource configuration data for an SoC having IPA v3.1 */
323 static const struct ipa_resource ipa_resource_dst[] = {
324 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
325 .limits[IPA_RSRC_GROUP_DST_UL] = {
326 .min = 3, .max = 3, /* 2 downstream */
328 .limits[IPA_RSRC_GROUP_DST_DL] = {
331 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
332 .min = 1, .max = 1, /* 0 downstream */
334 /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */
335 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
338 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
342 [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = {
343 .limits[IPA_RSRC_GROUP_DST_UL] = {
344 .min = 0, .max = 255,
346 .limits[IPA_RSRC_GROUP_DST_DL] = {
347 .min = 0, .max = 255,
349 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
350 .min = 0, .max = 255,
352 .limits[IPA_RSRC_GROUP_DST_DMA] = {
353 .min = 0, .max = 255,
355 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
356 .min = 0, .max = 255,
358 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
359 .min = 0, .max = 255,
362 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
363 .limits[IPA_RSRC_GROUP_DST_UL] = {
366 .limits[IPA_RSRC_GROUP_DST_DL] = {
369 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
372 .limits[IPA_RSRC_GROUP_DST_DMA] = {
375 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
381 /* Resource configuration data for an SoC having IPA v3.1 */
382 static const struct ipa_resource_data ipa_resource_data = {
383 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
384 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
385 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
386 .resource_src = ipa_resource_src,
387 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
388 .resource_dst = ipa_resource_dst,
391 /* IPA-resident memory region data for an SoC having IPA v3.1 */
392 static const struct ipa_mem ipa_mem_local_data[] = {
394 .id = IPA_MEM_UC_SHARED,
400 .id = IPA_MEM_UC_INFO,
406 .id = IPA_MEM_V4_FILTER_HASHED,
412 .id = IPA_MEM_V4_FILTER,
418 .id = IPA_MEM_V6_FILTER_HASHED,
424 .id = IPA_MEM_V6_FILTER,
430 .id = IPA_MEM_V4_ROUTE_HASHED,
436 .id = IPA_MEM_V4_ROUTE,
442 .id = IPA_MEM_V6_ROUTE_HASHED,
448 .id = IPA_MEM_V6_ROUTE,
454 .id = IPA_MEM_MODEM_HEADER,
460 .id = IPA_MEM_MODEM_PROC_CTX,
466 .id = IPA_MEM_AP_PROC_CTX,
478 .id = IPA_MEM_END_MARKER,
485 /* Memory configuration data for an SoC having IPA v3.1 */
486 static const struct ipa_mem_data ipa_mem_data = {
487 .local_count = ARRAY_SIZE(ipa_mem_local_data),
488 .local = ipa_mem_local_data,
489 .imem_addr = 0x146bd000,
490 .imem_size = 0x00002000,
492 .smem_size = 0x00002000,
495 /* Interconnect bandwidths are in 1000 byte/second units */
496 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
499 .peak_bandwidth = 640000, /* 640 MBps */
500 .average_bandwidth = 80000, /* 80 MBps */
504 .peak_bandwidth = 640000, /* 640 MBps */
505 .average_bandwidth = 80000, /* 80 MBps */
507 /* Average bandwidth is unused for the next interconnect */
510 .peak_bandwidth = 80000, /* 80 MBps */
511 .average_bandwidth = 0, /* unused */
515 /* Clock and interconnect configuration data for an SoC having IPA v3.1 */
516 static const struct ipa_clock_data ipa_clock_data = {
517 .core_clock_rate = 16 * 1000 * 1000, /* Hz */
518 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
519 .interconnect_data = ipa_interconnect_data,
522 /* Configuration data for an SoC having IPA v3.1 */
523 const struct ipa_data ipa_data_v3_1 = {
524 .version = IPA_VERSION_3_1,
525 .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK,
526 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
527 .qsb_data = ipa_qsb_data,
528 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
529 .endpoint_data = ipa_gsi_endpoint_data,
530 .resource_data = &ipa_resource_data,
531 .mem_data = &ipa_mem_data,
532 .clock_data = &ipa_clock_data,