drivers/net/ipa/ipa_data-sdm845.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2019-2021 Linaro Ltd.
   5  */
   6
   7 #include <linux/log2.h>
   8
   9 #include "gsi.h"
  10 #include "ipa_data.h"
  11 #include "ipa_endpoint.h"
  12 #include "ipa_mem.h"
  13
  14 /** enum ipa_resource_type - IPA resource types */
  15 enum ipa_resource_type {
  16         /* Source resource types; first must have value 0 */
  17         IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS              = 0,
  18         IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
  19         IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
  20         IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
  21         IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
  22
  23         /* Destination resource types; first must have value 0 */
  24         IPA_RESOURCE_TYPE_DST_DATA_SECTORS              = 0,
  25         IPA_RESOURCE_TYPE_DST_DPS_DMARS,
  26 };
  27
  28 /* Resource groups used for the SDM845 SoC */
  29 enum ipa_rsrc_group_id {
  30         /* Source resource group identifiers */
  31         IPA_RSRC_GROUP_SRC_LWA_DL       = 0,
  32         IPA_RSRC_GROUP_SRC_UL_DL,
  33         IPA_RSRC_GROUP_SRC_MHI_DMA,
  34         IPA_RSRC_GROUP_SRC_UC_RX_Q,
  35
  36         /* Destination resource group identifiers */
  37         IPA_RSRC_GROUP_DST_LWA_DL       = 0,
  38         IPA_RSRC_GROUP_DST_UL_DL_DPL,
  39         IPA_RSRC_GROUP_DST_UNUSED_2,
  40 };
  41
  42 /* QSB configuration for the SDM845 SoC. */
  43 static const struct ipa_qsb_data ipa_qsb_data[] = {
  44         [IPA_QSB_MASTER_DDR] = {
  45                 .max_writes     = 8,
  46                 .max_reads      = 8,
  47         },
  48         [IPA_QSB_MASTER_PCIE] = {
  49                 .max_writes     = 4,
  50                 .max_reads      = 12,
  51         },
  52 };
  53
  54 /* Endpoint configuration for the SDM845 SoC. */
  55 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
  56         [IPA_ENDPOINT_AP_COMMAND_TX] = {
  57                 .ee_id          = GSI_EE_AP,
  58                 .channel_id     = 4,
  59                 .endpoint_id    = 5,
  60                 .toward_ipa     = true,
  61                 .channel = {
  62                         .tre_count      = 512,
  63                         .event_count    = 256,
  64                         .tlv_count      = 20,
  65                 },
  66                 .endpoint = {
  67                         .config = {
  68                                 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
  69                                 .dma_mode       = true,
  70                                 .dma_endpoint   = IPA_ENDPOINT_AP_LAN_RX,
  71                                 .tx = {
  72                                         .seq_type = IPA_SEQ_DMA,
  73                                 },
  74                         },
  75                 },
  76         },
  77         [IPA_ENDPOINT_AP_LAN_RX] = {
  78                 .ee_id          = GSI_EE_AP,
  79                 .channel_id     = 5,
  80                 .endpoint_id    = 9,
  81                 .toward_ipa     = false,
  82                 .channel = {
  83                         .tre_count      = 256,
  84                         .event_count    = 256,
  85                         .tlv_count      = 8,
  86                 },
  87                 .endpoint = {
  88                         .config = {
  89                                 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
  90                                 .aggregation    = true,
  91                                 .status_enable  = true,
  92                                 .rx = {
  93                                         .pad_align      = ilog2(sizeof(u32)),
  94                                 },
  95                         },
  96                 },
  97         },
  98         [IPA_ENDPOINT_AP_MODEM_TX] = {
  99                 .ee_id          = GSI_EE_AP,
 100                 .channel_id     = 3,
 101                 .endpoint_id    = 2,
 102                 .toward_ipa     = true,
 103                 .channel = {
 104                         .tre_count      = 512,
 105                         .event_count    = 512,
 106                         .tlv_count      = 16,
 107                 },
 108                 .endpoint = {
 109                         .filter_support = true,
 110                         .config = {
 111                                 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
 112                                 .checksum       = true,
 113                                 .qmap           = true,
 114                                 .status_enable  = true,
 115                                 .tx = {
 116                                         .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
 117                                         .status_endpoint =
 118                                                 IPA_ENDPOINT_MODEM_AP_RX,
 119                                 },
 120                         },
 121                 },
 122         },
 123         [IPA_ENDPOINT_AP_MODEM_RX] = {
 124                 .ee_id          = GSI_EE_AP,
 125                 .channel_id     = 6,
 126                 .endpoint_id    = 10,
 127                 .toward_ipa     = false,
 128                 .channel = {
 129                         .tre_count      = 256,
 130                         .event_count    = 256,
 131                         .tlv_count      = 8,
 132                 },
 133                 .endpoint = {
 134                         .config = {
 135                                 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
 136                                 .checksum       = true,
 137                                 .qmap           = true,
 138                                 .aggregation    = true,
 139                                 .rx = {
 140                                         .aggr_close_eof = true,
 141                                 },
 142                         },
 143                 },
 144         },
 145         [IPA_ENDPOINT_MODEM_COMMAND_TX] = {
 146                 .ee_id          = GSI_EE_MODEM,
 147                 .channel_id     = 1,
 148                 .endpoint_id    = 4,
 149                 .toward_ipa     = true,
 150         },
 151         [IPA_ENDPOINT_MODEM_LAN_TX] = {
 152                 .ee_id          = GSI_EE_MODEM,
 153                 .channel_id     = 0,
 154                 .endpoint_id    = 3,
 155                 .toward_ipa     = true,
 156                 .endpoint = {
 157                         .filter_support = true,
 158                 },
 159         },
 160         [IPA_ENDPOINT_MODEM_LAN_RX] = {
 161                 .ee_id          = GSI_EE_MODEM,
 162                 .channel_id     = 3,
 163                 .endpoint_id    = 13,
 164                 .toward_ipa     = false,
 165         },
 166         [IPA_ENDPOINT_MODEM_AP_TX] = {
 167                 .ee_id          = GSI_EE_MODEM,
 168                 .channel_id     = 4,
 169                 .endpoint_id    = 6,
 170                 .toward_ipa     = true,
 171                 .endpoint = {
 172                         .filter_support = true,
 173                 },
 174         },
 175         [IPA_ENDPOINT_MODEM_AP_RX] = {
 176                 .ee_id          = GSI_EE_MODEM,
 177                 .channel_id     = 2,
 178                 .endpoint_id    = 12,
 179                 .toward_ipa     = false,
 180         },
 181 };
 182
 183 /* Source resource configuration data for the SDM845 SoC */
 184 static const struct ipa_resource ipa_resource_src[] = {
 185         [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
 186                 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
 187                         .min = 1,       .max = 255,
 188                 },
 189                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 190                         .min = 1,       .max = 255,
 191                 },
 192                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 193                         .min = 1,       .max = 63,
 194                 },
 195         },
 196         [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
 197                 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
 198                         .min = 10,      .max = 10,
 199                 },
 200                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 201                         .min = 10,      .max = 10,
 202                 },
 203                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 204                         .min = 8,       .max = 8,
 205                 },
 206         },
 207         [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
 208                 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
 209                         .min = 12,      .max = 12,
 210                 },
 211                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 212                         .min = 14,      .max = 14,
 213                 },
 214                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 215                         .min = 8,       .max = 8,
 216                 },
 217         },
 218         [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
 219                 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
 220                         .min = 0,       .max = 63,
 221                 },
 222                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 223                         .min = 0,       .max = 63,
 224                 },
 225                 .limits[IPA_RSRC_GROUP_SRC_MHI_DMA] = {
 226                         .min = 0,       .max = 63,
 227                 },
 228                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 229                         .min = 0,       .max = 63,
 230                 },
 231         },
 232         [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
 233                 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
 234                         .min = 14,      .max = 14,
 235                 },
 236                 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
 237                         .min = 20,      .max = 20,
 238                 },
 239                 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
 240                         .min = 14,      .max = 14,
 241                 },
 242         },
 243 };
 244
 245 /* Destination resource configuration data for the SDM845 SoC */
 246 static const struct ipa_resource ipa_resource_dst[] = {
 247         [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
 248                 .limits[IPA_RSRC_GROUP_DST_LWA_DL] = {
 249                         .min = 4,       .max = 4,
 250                 },
 251                 .limits[1] = {
 252                         .min = 4,       .max = 4,
 253                 },
 254                 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
 255                         .min = 3,       .max = 3,
 256                 }
 257         },
 258         [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
 259                 .limits[IPA_RSRC_GROUP_DST_LWA_DL] = {
 260                         .min = 2,       .max = 63,
 261                 },
 262                 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
 263                         .min = 1,       .max = 63,
 264                 },
 265                 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
 266                         .min = 1,       .max = 2,
 267                 }
 268         },
 269 };
 270
 271 /* Resource configuration for the SDM845 SoC. */
 272 static const struct ipa_resource_data ipa_resource_data = {
 273         .resource_src_count     = ARRAY_SIZE(ipa_resource_src),
 274         .resource_src           = ipa_resource_src,
 275         .resource_dst_count     = ARRAY_SIZE(ipa_resource_dst),
 276         .resource_dst           = ipa_resource_dst,
 277 };
 278
 279 /* IPA-resident memory region configuration for the SDM845 SoC. */
 280 static const struct ipa_mem ipa_mem_local_data[] = {
 281         [IPA_MEM_UC_SHARED] = {
 282                 .offset         = 0x0000,
 283                 .size           = 0x0080,
 284                 .canary_count   = 0,
 285         },
 286         [IPA_MEM_UC_INFO] = {
 287                 .offset         = 0x0080,
 288                 .size           = 0x0200,
 289                 .canary_count   = 0,
 290         },
 291         [IPA_MEM_V4_FILTER_HASHED] = {
 292                 .offset         = 0x0288,
 293                 .size           = 0x0078,
 294                 .canary_count   = 2,
 295         },
 296         [IPA_MEM_V4_FILTER] = {
 297                 .offset         = 0x0308,
 298                 .size           = 0x0078,
 299                 .canary_count   = 2,
 300         },
 301         [IPA_MEM_V6_FILTER_HASHED] = {
 302                 .offset         = 0x0388,
 303                 .size           = 0x0078,
 304                 .canary_count   = 2,
 305         },
 306         [IPA_MEM_V6_FILTER] = {
 307                 .offset         = 0x0408,
 308                 .size           = 0x0078,
 309                 .canary_count   = 2,
 310         },
 311         [IPA_MEM_V4_ROUTE_HASHED] = {
 312                 .offset         = 0x0488,
 313                 .size           = 0x0078,
 314                 .canary_count   = 2,
 315         },
 316         [IPA_MEM_V4_ROUTE] = {
 317                 .offset         = 0x0508,
 318                 .size           = 0x0078,
 319                 .canary_count   = 2,
 320         },
 321         [IPA_MEM_V6_ROUTE_HASHED] = {
 322                 .offset         = 0x0588,
 323                 .size           = 0x0078,
 324                 .canary_count   = 2,
 325         },
 326         [IPA_MEM_V6_ROUTE] = {
 327                 .offset         = 0x0608,
 328                 .size           = 0x0078,
 329                 .canary_count   = 2,
 330         },
 331         [IPA_MEM_MODEM_HEADER] = {
 332                 .offset         = 0x0688,
 333                 .size           = 0x0140,
 334                 .canary_count   = 2,
 335         },
 336         [IPA_MEM_MODEM_PROC_CTX] = {
 337                 .offset         = 0x07d0,
 338                 .size           = 0x0200,
 339                 .canary_count   = 2,
 340         },
 341         [IPA_MEM_AP_PROC_CTX] = {
 342                 .offset         = 0x09d0,
 343                 .size           = 0x0200,
 344                 .canary_count   = 0,
 345         },
 346         [IPA_MEM_MODEM] = {
 347                 .offset         = 0x0bd8,
 348                 .size           = 0x1024,
 349                 .canary_count   = 0,
 350         },
 351         [IPA_MEM_UC_EVENT_RING] = {
 352                 .offset         = 0x1c00,
 353                 .size           = 0x0400,
 354                 .canary_count   = 1,
 355         },
 356 };
 357
 358 static const struct ipa_mem_data ipa_mem_data = {
 359         .local_count    = ARRAY_SIZE(ipa_mem_local_data),
 360         .local          = ipa_mem_local_data,
 361         .imem_addr      = 0x146bd000,
 362         .imem_size      = 0x00002000,
 363         .smem_id        = 497,
 364         .smem_size      = 0x00002000,
 365 };
 366
 367 /* Interconnect bandwidths are in 1000 byte/second units */
 368 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
 369         {
 370                 .name                   = "memory",
 371                 .peak_bandwidth         = 600000,       /* 600 MBps */
 372                 .average_bandwidth      = 80000,        /* 80 MBps */
 373         },
 374         /* Average bandwidth is unused for the next two interconnects */
 375         {
 376                 .name                   = "imem",
 377                 .peak_bandwidth         = 350000,       /* 350 MBps */
 378                 .average_bandwidth      = 0,            /* unused */
 379         },
 380         {
 381                 .name                   = "config",
 382                 .peak_bandwidth         = 40000,        /* 40 MBps */
 383                 .average_bandwidth      = 0,            /* unused */
 384         },
 385 };
 386
 387 static const struct ipa_clock_data ipa_clock_data = {
 388         .core_clock_rate        = 75 * 1000 * 1000,     /* Hz */
 389         .interconnect_count     = ARRAY_SIZE(ipa_interconnect_data),
 390         .interconnect_data      = ipa_interconnect_data,
 391 };
 392
 393 /* Configuration data for the SDM845 SoC. */
 394 const struct ipa_data ipa_data_sdm845 = {
 395         .version        = IPA_VERSION_3_5_1,
 396         .qsb_count      = ARRAY_SIZE(ipa_qsb_data),
 397         .qsb_data       = ipa_qsb_data,
 398         .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
 399         .endpoint_data  = ipa_gsi_endpoint_data,
 400         .resource_data  = &ipa_resource_data,
 401         .mem_data       = &ipa_mem_data,
 402         .clock_data     = &ipa_clock_data,
 403 };