2 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
4 * Copyright (C) 2018 Xue Liu <liuxuenetmail@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/spi/spi.h>
20 #include <linux/workqueue.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/skbuff.h>
24 #include <linux/of_gpio.h>
25 #include <linux/regmap.h>
26 #include <linux/ieee802154.h>
27 #include <linux/debugfs.h>
29 #include <net/mac802154.h>
30 #include <net/cfg802154.h>
32 #include <linux/device.h>
36 #define SPI_COMMAND_BUFFER 3
38 #define REGISTER_READ BIT(7)
39 #define REGISTER_WRITE (0 << 7)
40 #define REGISTER_ACCESS (0 << 6)
41 #define PACKET_BUFF_BURST_ACCESS BIT(6)
42 #define PACKET_BUFF_BYTE_ACCESS BIT(5)
44 #define MCR20A_WRITE_REG(x) (x)
45 #define MCR20A_READ_REG(x) (REGISTER_READ | (x))
46 #define MCR20A_BURST_READ_PACKET_BUF (0xC0)
47 #define MCR20A_BURST_WRITE_PACKET_BUF (0x40)
49 #define MCR20A_CMD_REG 0x80
50 #define MCR20A_CMD_REG_MASK 0x3f
51 #define MCR20A_CMD_WRITE 0x40
52 #define MCR20A_CMD_FB 0x20
54 /* Number of Interrupt Request Status Register */
55 #define MCR20A_IRQSTS_NUM 2 /* only IRQ_STS1 and IRQ_STS2 */
59 MCR20A_CCA_ED, // energy detect - CCA bit not active,
60 // not to be used for T and CCCA sequences
61 MCR20A_CCA_MODE1, // energy detect - CCA bit ACTIVE
62 MCR20A_CCA_MODE2, // 802.15.4 compliant signal detect - CCA bit ACTIVE
67 MCR20A_XCVSEQ_IDLE = 0x00,
68 MCR20A_XCVSEQ_RX = 0x01,
69 MCR20A_XCVSEQ_TX = 0x02,
70 MCR20A_XCVSEQ_CCA = 0x03,
71 MCR20A_XCVSEQ_TR = 0x04,
72 MCR20A_XCVSEQ_CCCA = 0x05,
75 /* IEEE-802.15.4 defined constants (2.4 GHz logical channels) */
76 #define MCR20A_MIN_CHANNEL (11)
77 #define MCR20A_MAX_CHANNEL (26)
78 #define MCR20A_CHANNEL_SPACING (5)
80 /* MCR20A CCA Threshold constans */
81 #define MCR20A_MIN_CCA_THRESHOLD (0x6EU)
82 #define MCR20A_MAX_CCA_THRESHOLD (0x00U)
85 #define MCR20A_OVERWRITE_VERSION (0x0C)
87 /* MCR20A PLL configurations */
88 static const u8 PLL_INT[16] = {
89 /* 2405 */ 0x0B, /* 2410 */ 0x0B, /* 2415 */ 0x0B,
90 /* 2420 */ 0x0B, /* 2425 */ 0x0B, /* 2430 */ 0x0B,
91 /* 2435 */ 0x0C, /* 2440 */ 0x0C, /* 2445 */ 0x0C,
92 /* 2450 */ 0x0C, /* 2455 */ 0x0C, /* 2460 */ 0x0C,
93 /* 2465 */ 0x0D, /* 2470 */ 0x0D, /* 2475 */ 0x0D,
97 static const u8 PLL_FRAC[16] = {
98 /* 2405 */ 0x28, /* 2410 */ 0x50, /* 2415 */ 0x78,
99 /* 2420 */ 0xA0, /* 2425 */ 0xC8, /* 2430 */ 0xF0,
100 /* 2435 */ 0x18, /* 2440 */ 0x40, /* 2445 */ 0x68,
101 /* 2450 */ 0x90, /* 2455 */ 0xB8, /* 2460 */ 0xE0,
102 /* 2465 */ 0x08, /* 2470 */ 0x30, /* 2475 */ 0x58,
106 static const struct reg_sequence mar20a_iar_overwrites[] = {
107 { IAR_MISC_PAD_CTRL, 0x02 },
108 { IAR_VCO_CTRL1, 0xB3 },
109 { IAR_VCO_CTRL2, 0x07 },
110 { IAR_PA_TUNING, 0x71 },
111 { IAR_CHF_IBUF, 0x2F },
112 { IAR_CHF_QBUF, 0x2F },
113 { IAR_CHF_IRIN, 0x24 },
114 { IAR_CHF_QRIN, 0x24 },
115 { IAR_CHF_IL, 0x24 },
116 { IAR_CHF_QL, 0x24 },
117 { IAR_CHF_CC1, 0x32 },
118 { IAR_CHF_CCL, 0x1D },
119 { IAR_CHF_CC2, 0x2D },
120 { IAR_CHF_IROUT, 0x24 },
121 { IAR_CHF_QROUT, 0x24 },
122 { IAR_PA_CAL, 0x28 },
123 { IAR_AGC_THR1, 0x55 },
124 { IAR_AGC_THR2, 0x2D },
125 { IAR_ATT_RSSI1, 0x5F },
126 { IAR_ATT_RSSI2, 0x8F },
127 { IAR_RSSI_OFFSET, 0x61 },
128 { IAR_CHF_PMA_GAIN, 0x03 },
129 { IAR_CCA1_THRESH, 0x50 },
130 { IAR_CORR_NVAL, 0x13 },
131 { IAR_ACKDELAY, 0x3D },
134 #define MCR20A_VALID_CHANNELS (0x07FFF800)
135 #define MCR20A_MAX_BUF (127)
137 #define printdev(X) (&X->spi->dev)
139 /* regmap information for Direct Access Register (DAR) access */
140 #define MCR20A_DAR_WRITE 0x01
141 #define MCR20A_DAR_READ 0x00
142 #define MCR20A_DAR_NUMREGS 0x3F
144 /* regmap information for Indirect Access Register (IAR) access */
145 #define MCR20A_IAR_ACCESS 0x80
146 #define MCR20A_IAR_NUMREGS 0xBEFF
148 /* Read/Write SPI Commands for DAR and IAR registers. */
149 #define MCR20A_READSHORT(reg) ((reg) << 1)
150 #define MCR20A_WRITESHORT(reg) ((reg) << 1 | 1)
151 #define MCR20A_READLONG(reg) (1 << 15 | (reg) << 5)
152 #define MCR20A_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
154 /* Type definitions for link configuration of instantiable layers */
155 #define MCR20A_PHY_INDIRECT_QUEUE_SIZE (12)
158 mcr20a_dar_writeable(struct device *dev, unsigned int reg)
169 case DAR_SRC_ADDRS_SUM_LSB:
170 case DAR_SRC_ADDRS_SUM_MSB:
174 case DAR_T2PRIMECMP_LSB:
175 case DAR_T2PRIMECMP_MSB:
186 case DAR_PLL_FRAC0_LSB:
187 case DAR_PLL_FRAC0_MSB:
190 case DAR_OVERWRITE_VER:
191 case DAR_CLK_OUT_CTRL:
200 mcr20a_dar_readable(struct device *dev, unsigned int reg)
204 /* all writeable are also readable */
205 rc = mcr20a_dar_writeable(dev, reg);
212 case DAR_CCA1_ED_FNL:
213 case DAR_EVENT_TMR_LSB:
214 case DAR_EVENT_TMR_MSB:
215 case DAR_EVENT_TMR_USB:
216 case DAR_TIMESTAMP_LSB:
217 case DAR_TIMESTAMP_MSB:
218 case DAR_TIMESTAMP_USB:
221 case DAR_RSSI_CCA_CONT:
229 mcr20a_dar_volatile(struct device *dev, unsigned int reg)
231 /* can be changed during runtime */
236 /* use them in spi_async and regmap so it's volatile */
244 mcr20a_dar_precious(struct device *dev, unsigned int reg)
246 /* don't clear irq line on read */
257 static const struct regmap_config mcr20a_dar_regmap = {
258 .name = "mcr20a_dar",
261 .write_flag_mask = REGISTER_ACCESS | REGISTER_WRITE,
262 .read_flag_mask = REGISTER_ACCESS | REGISTER_READ,
263 .cache_type = REGCACHE_RBTREE,
264 .writeable_reg = mcr20a_dar_writeable,
265 .readable_reg = mcr20a_dar_readable,
266 .volatile_reg = mcr20a_dar_volatile,
267 .precious_reg = mcr20a_dar_precious,
269 .can_multi_write = true,
273 mcr20a_iar_writeable(struct device *dev, unsigned int reg)
277 case IAR_PMC_LP_TRIM:
278 case IAR_MACPANID0_LSB:
279 case IAR_MACPANID0_MSB:
280 case IAR_MACSHORTADDRS0_LSB:
281 case IAR_MACSHORTADDRS0_MSB:
282 case IAR_MACLONGADDRS0_0:
283 case IAR_MACLONGADDRS0_8:
284 case IAR_MACLONGADDRS0_16:
285 case IAR_MACLONGADDRS0_24:
286 case IAR_MACLONGADDRS0_32:
287 case IAR_MACLONGADDRS0_40:
288 case IAR_MACLONGADDRS0_48:
289 case IAR_MACLONGADDRS0_56:
290 case IAR_RX_FRAME_FILTER:
292 case IAR_PLL_FRAC1_LSB:
293 case IAR_PLL_FRAC1_MSB:
294 case IAR_MACPANID1_LSB:
295 case IAR_MACPANID1_MSB:
296 case IAR_MACSHORTADDRS1_LSB:
297 case IAR_MACSHORTADDRS1_MSB:
298 case IAR_MACLONGADDRS1_0:
299 case IAR_MACLONGADDRS1_8:
300 case IAR_MACLONGADDRS1_16:
301 case IAR_MACLONGADDRS1_24:
302 case IAR_MACLONGADDRS1_32:
303 case IAR_MACLONGADDRS1_40:
304 case IAR_MACLONGADDRS1_48:
305 case IAR_MACLONGADDRS1_56:
306 case IAR_DUAL_PAN_CTRL:
307 case IAR_DUAL_PAN_DWELL:
308 case IAR_CCA1_THRESH:
309 case IAR_CCA1_ED_OFFSET_COMP:
310 case IAR_LQI_OFFSET_COMP:
312 case IAR_CCA2_CORR_PEAKS:
313 case IAR_CCA2_CORR_THRESH:
314 case IAR_TMR_PRESCALE:
315 case IAR_ANT_PAD_CTRL:
316 case IAR_MISC_PAD_CTRL:
319 case IAR_RX_WTR_MARK:
324 case IAR_ANT_AGC_CTRL:
330 case IAR_RSSI_OFFSET:
332 case IAR_CHF_PMA_GAIN:
354 mcr20a_iar_readable(struct device *dev, unsigned int reg)
358 /* all writeable are also readable */
359 rc = mcr20a_iar_writeable(dev, reg);
366 case IAR_DUAL_PAN_STS:
367 case IAR_RX_BYTE_COUNT:
368 case IAR_FILTERFAIL_CODE1:
369 case IAR_FILTERFAIL_CODE2:
378 mcr20a_iar_volatile(struct device *dev, unsigned int reg)
380 /* can be changed during runtime */
382 case IAR_DUAL_PAN_STS:
383 case IAR_RX_BYTE_COUNT:
384 case IAR_FILTERFAIL_CODE1:
385 case IAR_FILTERFAIL_CODE2:
393 static const struct regmap_config mcr20a_iar_regmap = {
394 .name = "mcr20a_iar",
397 .write_flag_mask = REGISTER_ACCESS | REGISTER_WRITE | IAR_INDEX,
398 .read_flag_mask = REGISTER_ACCESS | REGISTER_READ | IAR_INDEX,
399 .cache_type = REGCACHE_RBTREE,
400 .writeable_reg = mcr20a_iar_writeable,
401 .readable_reg = mcr20a_iar_readable,
402 .volatile_reg = mcr20a_iar_volatile,
406 struct mcr20a_local {
407 struct spi_device *spi;
409 struct ieee802154_hw *hw;
410 struct regmap *regmap_dar;
411 struct regmap *regmap_iar;
417 /* for writing tx buffer */
418 struct spi_message tx_buf_msg;
420 /* burst buffer write command */
421 struct spi_transfer tx_xfer_header;
423 /* len of tx packet */
424 struct spi_transfer tx_xfer_len;
425 /* data of tx packet */
426 struct spi_transfer tx_xfer_buf;
427 struct sk_buff *tx_skb;
429 /* for read length rxfifo */
430 struct spi_message reg_msg;
432 u8 reg_data[MCR20A_IRQSTS_NUM];
433 struct spi_transfer reg_xfer_cmd;
434 struct spi_transfer reg_xfer_data;
436 /* receive handling */
437 struct spi_message rx_buf_msg;
439 struct spi_transfer rx_xfer_header;
441 struct spi_transfer rx_xfer_lqi;
442 u8 rx_buf[MCR20A_MAX_BUF];
443 struct spi_transfer rx_xfer_buf;
445 /* isr handling for reading intstat */
446 struct spi_message irq_msg;
448 u8 irq_data[MCR20A_IRQSTS_NUM];
449 struct spi_transfer irq_xfer_data;
450 struct spi_transfer irq_xfer_header;
454 mcr20a_write_tx_buf_complete(void *context)
456 struct mcr20a_local *lp = context;
459 dev_dbg(printdev(lp), "%s\n", __func__);
461 lp->reg_msg.complete = NULL;
462 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1);
463 lp->reg_data[0] = MCR20A_XCVSEQ_TX;
464 lp->reg_xfer_data.len = 1;
466 ret = spi_async(lp->spi, &lp->reg_msg);
468 dev_err(printdev(lp), "failed to set SEQ TX\n");
472 mcr20a_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
474 struct mcr20a_local *lp = hw->priv;
476 dev_dbg(printdev(lp), "%s\n", __func__);
480 print_hex_dump_debug("mcr20a tx: ", DUMP_PREFIX_OFFSET, 16, 1,
481 skb->data, skb->len, 0);
485 lp->reg_msg.complete = NULL;
486 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1);
487 lp->reg_data[0] = MCR20A_XCVSEQ_IDLE;
488 lp->reg_xfer_data.len = 1;
490 return spi_async(lp->spi, &lp->reg_msg);
494 mcr20a_ed(struct ieee802154_hw *hw, u8 *level)
502 mcr20a_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
504 struct mcr20a_local *lp = hw->priv;
507 dev_dbg(printdev(lp), "%s\n", __func__);
509 /* freqency = ((PLL_INT+64) + (PLL_FRAC/65536)) * 32 MHz */
510 ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]);
513 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_LSB, 0x00);
516 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_MSB,
517 PLL_FRAC[channel - 11]);
525 mcr20a_start(struct ieee802154_hw *hw)
527 struct mcr20a_local *lp = hw->priv;
530 dev_dbg(printdev(lp), "%s\n", __func__);
532 /* No slotted operation */
533 dev_dbg(printdev(lp), "no slotted operation\n");
534 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
535 DAR_PHY_CTRL1_SLOTTED, 0x0);
538 enable_irq(lp->spi->irq);
540 /* Unmask SEQ interrupt */
541 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL2,
542 DAR_PHY_CTRL2_SEQMSK, 0x0);
544 /* Start the RX sequence */
545 dev_dbg(printdev(lp), "start the RX sequence\n");
546 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
547 DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_RX);
553 mcr20a_stop(struct ieee802154_hw *hw)
555 struct mcr20a_local *lp = hw->priv;
557 dev_dbg(printdev(lp), "%s\n", __func__);
559 /* stop all running sequence */
560 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
561 DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_IDLE);
564 disable_irq(lp->spi->irq);
568 mcr20a_set_hw_addr_filt(struct ieee802154_hw *hw,
569 struct ieee802154_hw_addr_filt *filt,
570 unsigned long changed)
572 struct mcr20a_local *lp = hw->priv;
574 dev_dbg(printdev(lp), "%s\n", __func__);
576 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
577 u16 addr = le16_to_cpu(filt->short_addr);
579 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_LSB, addr);
580 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_MSB, addr >> 8);
583 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
584 u16 pan = le16_to_cpu(filt->pan_id);
586 regmap_write(lp->regmap_iar, IAR_MACPANID0_LSB, pan);
587 regmap_write(lp->regmap_iar, IAR_MACPANID0_MSB, pan >> 8);
590 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
593 memcpy(addr, &filt->ieee_addr, 8);
594 for (i = 0; i < 8; i++)
595 regmap_write(lp->regmap_iar,
596 IAR_MACLONGADDRS0_0 + i, addr[i]);
599 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
600 if (filt->pan_coord) {
601 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
602 DAR_PHY_CTRL4_PANCORDNTR0, 0x10);
604 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
605 DAR_PHY_CTRL4_PANCORDNTR0, 0x00);
612 /* -30 dBm to 10 dBm */
613 #define MCR20A_MAX_TX_POWERS 0x14
614 static const s32 mcr20a_powers[MCR20A_MAX_TX_POWERS + 1] = {
615 -3000, -2800, -2600, -2400, -2200, -2000, -1800, -1600, -1400,
616 -1200, -1000, -800, -600, -400, -200, 0, 200, 400, 600, 800, 1000
620 mcr20a_set_txpower(struct ieee802154_hw *hw, s32 mbm)
622 struct mcr20a_local *lp = hw->priv;
625 dev_dbg(printdev(lp), "%s(%d)\n", __func__, mbm);
627 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
628 if (lp->hw->phy->supported.tx_powers[i] == mbm)
629 return regmap_write(lp->regmap_dar, DAR_PA_PWR,
636 #define MCR20A_MAX_ED_LEVELS MCR20A_MIN_CCA_THRESHOLD
637 static s32 mcr20a_ed_levels[MCR20A_MAX_ED_LEVELS + 1];
640 mcr20a_set_cca_mode(struct ieee802154_hw *hw,
641 const struct wpan_phy_cca *cca)
643 struct mcr20a_local *lp = hw->priv;
644 unsigned int cca_mode = 0xff;
645 bool cca_mode_and = false;
648 dev_dbg(printdev(lp), "%s\n", __func__);
650 /* mapping 802.15.4 to driver spec */
652 case NL802154_CCA_ENERGY:
653 cca_mode = MCR20A_CCA_MODE1;
655 case NL802154_CCA_CARRIER:
656 cca_mode = MCR20A_CCA_MODE2;
658 case NL802154_CCA_ENERGY_CARRIER:
660 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
661 cca_mode = MCR20A_CCA_MODE3;
664 case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
665 cca_mode = MCR20A_CCA_MODE3;
666 cca_mode_and = false;
675 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
676 DAR_PHY_CTRL4_CCATYPE_MASK,
677 cca_mode << DAR_PHY_CTRL4_CCATYPE_SHIFT);
681 if (cca_mode == MCR20A_CCA_MODE3) {
683 ret = regmap_update_bits(lp->regmap_iar, IAR_CCA_CTRL,
684 IAR_CCA_CTRL_CCA3_AND_NOT_OR,
687 ret = regmap_update_bits(lp->regmap_iar,
689 IAR_CCA_CTRL_CCA3_AND_NOT_OR,
700 mcr20a_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
702 struct mcr20a_local *lp = hw->priv;
705 dev_dbg(printdev(lp), "%s\n", __func__);
707 for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
708 if (hw->phy->supported.cca_ed_levels[i] == mbm)
709 return regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, i);
716 mcr20a_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
718 struct mcr20a_local *lp = hw->priv;
720 u8 rx_frame_filter_reg = 0x0;
722 dev_dbg(printdev(lp), "%s(%d)\n", __func__, on);
725 /* All frame types accepted*/
726 rx_frame_filter_reg &= ~(IAR_RX_FRAME_FLT_FRM_VER);
727 rx_frame_filter_reg |= (IAR_RX_FRAME_FLT_ACK_FT |
728 IAR_RX_FRAME_FLT_NS_FT);
730 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
731 DAR_PHY_CTRL4_PROMISCUOUS,
732 DAR_PHY_CTRL4_PROMISCUOUS);
736 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
737 rx_frame_filter_reg);
741 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4,
742 DAR_PHY_CTRL4_PROMISCUOUS, 0x0);
746 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
747 IAR_RX_FRAME_FLT_FRM_VER |
748 IAR_RX_FRAME_FLT_BEACON_FT |
749 IAR_RX_FRAME_FLT_DATA_FT |
750 IAR_RX_FRAME_FLT_CMD_FT);
758 static const struct ieee802154_ops mcr20a_hw_ops = {
759 .owner = THIS_MODULE,
760 .xmit_async = mcr20a_xmit,
762 .set_channel = mcr20a_set_channel,
763 .start = mcr20a_start,
765 .set_hw_addr_filt = mcr20a_set_hw_addr_filt,
766 .set_txpower = mcr20a_set_txpower,
767 .set_cca_mode = mcr20a_set_cca_mode,
768 .set_cca_ed_level = mcr20a_set_cca_ed_level,
769 .set_promiscuous_mode = mcr20a_set_promiscuous_mode,
773 mcr20a_request_rx(struct mcr20a_local *lp)
775 dev_dbg(printdev(lp), "%s\n", __func__);
777 /* Start the RX sequence */
778 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
779 DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_RX);
785 mcr20a_handle_rx_read_buf_complete(void *context)
787 struct mcr20a_local *lp = context;
788 u8 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;
791 dev_dbg(printdev(lp), "%s\n", __func__);
793 dev_dbg(printdev(lp), "RX is done\n");
795 if (!ieee802154_is_valid_psdu_len(len)) {
796 dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
797 len = IEEE802154_MTU;
800 len = len - 2; /* get rid of frame check field */
802 skb = dev_alloc_skb(len);
806 memcpy(skb_put(skb, len), lp->rx_buf, len);
807 ieee802154_rx_irqsafe(lp->hw, skb, lp->rx_lqi[0]);
809 print_hex_dump_debug("mcr20a rx: ", DUMP_PREFIX_OFFSET, 16, 1,
811 pr_debug("mcr20a rx: lqi: %02hhx\n", lp->rx_lqi[0]);
813 /* start RX sequence */
814 mcr20a_request_rx(lp);
818 mcr20a_handle_rx_read_len_complete(void *context)
820 struct mcr20a_local *lp = context;
824 dev_dbg(printdev(lp), "%s\n", __func__);
826 /* get the length of received frame */
827 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK;
828 dev_dbg(printdev(lp), "frame len : %d\n", len);
830 /* prepare to read the rx buf */
831 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;
832 lp->rx_header[0] = MCR20A_BURST_READ_PACKET_BUF;
833 lp->rx_xfer_buf.len = len;
835 ret = spi_async(lp->spi, &lp->rx_buf_msg);
837 dev_err(printdev(lp), "failed to read rx buffer length\n");
841 mcr20a_handle_rx(struct mcr20a_local *lp)
843 dev_dbg(printdev(lp), "%s\n", __func__);
844 lp->reg_msg.complete = mcr20a_handle_rx_read_len_complete;
845 lp->reg_cmd[0] = MCR20A_READ_REG(DAR_RX_FRM_LEN);
846 lp->reg_xfer_data.len = 1;
848 return spi_async(lp->spi, &lp->reg_msg);
852 mcr20a_handle_tx_complete(struct mcr20a_local *lp)
854 dev_dbg(printdev(lp), "%s\n", __func__);
856 ieee802154_xmit_complete(lp->hw, lp->tx_skb, false);
858 return mcr20a_request_rx(lp);
862 mcr20a_handle_tx(struct mcr20a_local *lp)
866 dev_dbg(printdev(lp), "%s\n", __func__);
868 /* write tx buffer */
869 lp->tx_header[0] = MCR20A_BURST_WRITE_PACKET_BUF;
870 /* add 2 bytes of FCS */
871 lp->tx_len[0] = lp->tx_skb->len + 2;
872 lp->tx_xfer_buf.tx_buf = lp->tx_skb->data;
873 /* add 1 byte psduLength */
874 lp->tx_xfer_buf.len = lp->tx_skb->len + 1;
876 ret = spi_async(lp->spi, &lp->tx_buf_msg);
878 dev_err(printdev(lp), "SPI write Failed for TX buf\n");
886 mcr20a_irq_clean_complete(void *context)
888 struct mcr20a_local *lp = context;
889 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK;
891 dev_dbg(printdev(lp), "%s\n", __func__);
893 enable_irq(lp->spi->irq);
895 dev_dbg(printdev(lp), "IRQ STA1 (%02x) STA2 (%02x)\n",
896 lp->irq_data[DAR_IRQ_STS1], lp->irq_data[DAR_IRQ_STS2]);
899 /* TX IRQ, RX IRQ and SEQ IRQ */
900 case (DAR_IRQSTS1_TXIRQ | DAR_IRQSTS1_SEQIRQ):
903 dev_dbg(printdev(lp), "TX is done. No ACK\n");
904 mcr20a_handle_tx_complete(lp);
907 case (DAR_IRQSTS1_RXIRQ | DAR_IRQSTS1_SEQIRQ):
909 dev_dbg(printdev(lp), "RX is starting\n");
910 mcr20a_handle_rx(lp);
912 case (DAR_IRQSTS1_RXIRQ | DAR_IRQSTS1_TXIRQ | DAR_IRQSTS1_SEQIRQ):
916 dev_dbg(printdev(lp), "TX is done. Get ACK\n");
917 mcr20a_handle_tx_complete(lp);
920 dev_dbg(printdev(lp), "RX is starting\n");
921 mcr20a_handle_rx(lp);
924 case (DAR_IRQSTS1_SEQIRQ):
926 dev_dbg(printdev(lp), "TX is starting\n");
927 mcr20a_handle_tx(lp);
929 dev_dbg(printdev(lp), "MCR20A is stop\n");
935 static void mcr20a_irq_status_complete(void *context)
938 struct mcr20a_local *lp = context;
940 dev_dbg(printdev(lp), "%s\n", __func__);
941 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1,
942 DAR_PHY_CTRL1_XCVSEQ_MASK, MCR20A_XCVSEQ_IDLE);
944 lp->reg_msg.complete = mcr20a_irq_clean_complete;
945 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_IRQ_STS1);
946 memcpy(lp->reg_data, lp->irq_data, MCR20A_IRQSTS_NUM);
947 lp->reg_xfer_data.len = MCR20A_IRQSTS_NUM;
949 ret = spi_async(lp->spi, &lp->reg_msg);
952 dev_err(printdev(lp), "failed to clean irq status\n");
955 static irqreturn_t mcr20a_irq_isr(int irq, void *data)
957 struct mcr20a_local *lp = data;
960 disable_irq_nosync(irq);
962 lp->irq_header[0] = MCR20A_READ_REG(DAR_IRQ_STS1);
964 ret = spi_async(lp->spi, &lp->irq_msg);
973 static void mcr20a_hw_setup(struct mcr20a_local *lp)
976 struct ieee802154_hw *hw = lp->hw;
977 struct wpan_phy *phy = lp->hw->phy;
979 dev_dbg(printdev(lp), "%s\n", __func__);
981 phy->symbol_duration = 16;
982 phy->lifs_period = 40;
983 phy->sifs_period = 12;
985 hw->flags = IEEE802154_HW_TX_OMIT_CKSUM |
986 IEEE802154_HW_AFILT |
987 IEEE802154_HW_PROMISCUOUS;
989 phy->flags = WPAN_PHY_FLAG_TXPOWER | WPAN_PHY_FLAG_CCA_ED_LEVEL |
990 WPAN_PHY_FLAG_CCA_MODE;
992 phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
993 BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
994 phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
995 BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
997 /* initiating cca_ed_levels */
998 for (i = MCR20A_MAX_CCA_THRESHOLD; i < MCR20A_MIN_CCA_THRESHOLD + 1;
1000 mcr20a_ed_levels[i] = -i * 100;
1003 phy->supported.cca_ed_levels = mcr20a_ed_levels;
1004 phy->supported.cca_ed_levels_size = ARRAY_SIZE(mcr20a_ed_levels);
1006 phy->cca.mode = NL802154_CCA_ENERGY;
1008 phy->supported.channels[0] = MCR20A_VALID_CHANNELS;
1009 phy->current_page = 0;
1010 /* MCR20A default reset value */
1011 phy->current_channel = 20;
1012 phy->symbol_duration = 16;
1013 phy->supported.tx_powers = mcr20a_powers;
1014 phy->supported.tx_powers_size = ARRAY_SIZE(mcr20a_powers);
1015 phy->cca_ed_level = phy->supported.cca_ed_levels[75];
1016 phy->transmit_power = phy->supported.tx_powers[0x0F];
1020 mcr20a_setup_tx_spi_messages(struct mcr20a_local *lp)
1022 spi_message_init(&lp->tx_buf_msg);
1023 lp->tx_buf_msg.context = lp;
1024 lp->tx_buf_msg.complete = mcr20a_write_tx_buf_complete;
1026 lp->tx_xfer_header.len = 1;
1027 lp->tx_xfer_header.tx_buf = lp->tx_header;
1029 lp->tx_xfer_len.len = 1;
1030 lp->tx_xfer_len.tx_buf = lp->tx_len;
1032 spi_message_add_tail(&lp->tx_xfer_header, &lp->tx_buf_msg);
1033 spi_message_add_tail(&lp->tx_xfer_len, &lp->tx_buf_msg);
1034 spi_message_add_tail(&lp->tx_xfer_buf, &lp->tx_buf_msg);
1038 mcr20a_setup_rx_spi_messages(struct mcr20a_local *lp)
1040 spi_message_init(&lp->reg_msg);
1041 lp->reg_msg.context = lp;
1043 lp->reg_xfer_cmd.len = 1;
1044 lp->reg_xfer_cmd.tx_buf = lp->reg_cmd;
1045 lp->reg_xfer_cmd.rx_buf = lp->reg_cmd;
1047 lp->reg_xfer_data.rx_buf = lp->reg_data;
1048 lp->reg_xfer_data.tx_buf = lp->reg_data;
1050 spi_message_add_tail(&lp->reg_xfer_cmd, &lp->reg_msg);
1051 spi_message_add_tail(&lp->reg_xfer_data, &lp->reg_msg);
1053 spi_message_init(&lp->rx_buf_msg);
1054 lp->rx_buf_msg.context = lp;
1055 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete;
1056 lp->rx_xfer_header.len = 1;
1057 lp->rx_xfer_header.tx_buf = lp->rx_header;
1058 lp->rx_xfer_header.rx_buf = lp->rx_header;
1060 lp->rx_xfer_buf.rx_buf = lp->rx_buf;
1062 lp->rx_xfer_lqi.len = 1;
1063 lp->rx_xfer_lqi.rx_buf = lp->rx_lqi;
1065 spi_message_add_tail(&lp->rx_xfer_header, &lp->rx_buf_msg);
1066 spi_message_add_tail(&lp->rx_xfer_buf, &lp->rx_buf_msg);
1067 spi_message_add_tail(&lp->rx_xfer_lqi, &lp->rx_buf_msg);
1071 mcr20a_setup_irq_spi_messages(struct mcr20a_local *lp)
1073 spi_message_init(&lp->irq_msg);
1074 lp->irq_msg.context = lp;
1075 lp->irq_msg.complete = mcr20a_irq_status_complete;
1076 lp->irq_xfer_header.len = 1;
1077 lp->irq_xfer_header.tx_buf = lp->irq_header;
1078 lp->irq_xfer_header.rx_buf = lp->irq_header;
1080 lp->irq_xfer_data.len = MCR20A_IRQSTS_NUM;
1081 lp->irq_xfer_data.rx_buf = lp->irq_data;
1083 spi_message_add_tail(&lp->irq_xfer_header, &lp->irq_msg);
1084 spi_message_add_tail(&lp->irq_xfer_data, &lp->irq_msg);
1088 mcr20a_phy_init(struct mcr20a_local *lp)
1091 unsigned int phy_reg = 0;
1094 dev_dbg(printdev(lp), "%s\n", __func__);
1096 /* Disable Tristate on COCO MISO for SPI reads */
1097 ret = regmap_write(lp->regmap_iar, IAR_MISC_PAD_CTRL, 0x02);
1101 /* Clear all PP IRQ bits in IRQSTS1 to avoid unexpected interrupts
1102 * immediately after init
1104 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS1, 0xEF);
1108 /* Clear all PP IRQ bits in IRQSTS2 */
1109 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS2,
1110 DAR_IRQSTS2_ASM_IRQ | DAR_IRQSTS2_PB_ERR_IRQ |
1111 DAR_IRQSTS2_WAKE_IRQ);
1115 /* Disable all timer interrupts */
1116 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS3, 0xFF);
1120 /* PHY_CTRL1 : default HW settings + AUTOACK enabled */
1121 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1,
1122 DAR_PHY_CTRL1_AUTOACK, DAR_PHY_CTRL1_AUTOACK);
1124 /* PHY_CTRL2 : disable all interrupts */
1125 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL2, 0xFF);
1129 /* PHY_CTRL3 : disable all timers and remaining interrupts */
1130 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL3,
1131 DAR_PHY_CTRL3_ASM_MSK | DAR_PHY_CTRL3_PB_ERR_MSK |
1132 DAR_PHY_CTRL3_WAKE_MSK);
1136 /* SRC_CTRL : enable Acknowledge Frame Pending and
1137 * Source Address Matching Enable
1139 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL,
1140 DAR_SRC_CTRL_ACK_FRM_PND |
1141 (DAR_SRC_CTRL_INDEX << DAR_SRC_CTRL_INDEX_SHIFT));
1145 /* RX_FRAME_FILTER */
1146 /* FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets */
1147 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,
1148 IAR_RX_FRAME_FLT_FRM_VER |
1149 IAR_RX_FRAME_FLT_BEACON_FT |
1150 IAR_RX_FRAME_FLT_DATA_FT |
1151 IAR_RX_FRAME_FLT_CMD_FT);
1155 dev_info(printdev(lp), "MCR20A DAR overwrites version: 0x%02x\n",
1156 MCR20A_OVERWRITE_VERSION);
1158 /* Overwrites direct registers */
1159 ret = regmap_write(lp->regmap_dar, DAR_OVERWRITE_VER,
1160 MCR20A_OVERWRITE_VERSION);
1164 /* Overwrites indirect registers */
1165 ret = regmap_multi_reg_write(lp->regmap_iar, mar20a_iar_overwrites,
1166 ARRAY_SIZE(mar20a_iar_overwrites));
1170 /* Clear HW indirect queue */
1171 dev_dbg(printdev(lp), "clear HW indirect queue\n");
1172 for (index = 0; index < MCR20A_PHY_INDIRECT_QUEUE_SIZE; index++) {
1173 phy_reg = (u8)(((index & DAR_SRC_CTRL_INDEX) <<
1174 DAR_SRC_CTRL_INDEX_SHIFT)
1175 | (DAR_SRC_CTRL_SRCADDR_EN)
1176 | (DAR_SRC_CTRL_INDEX_DISABLE));
1177 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg);
1183 /* Assign HW Indirect hash table to PAN0 */
1184 ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg);
1188 /* Clear current lvl */
1189 phy_reg &= ~IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK;
1192 phy_reg |= MCR20A_PHY_INDIRECT_QUEUE_SIZE <<
1193 IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT;
1194 ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg);
1198 /* Set CCA threshold to -75 dBm */
1199 ret = regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, 0x4B);
1203 /* Set prescaller to obtain 1 symbol (16us) timebase */
1204 ret = regmap_write(lp->regmap_iar, IAR_TMR_PRESCALE, 0x05);
1208 /* Enable autodoze mode. */
1209 ret = regmap_update_bits(lp->regmap_dar, DAR_PWR_MODES,
1210 DAR_PWR_MODES_AUTODOZE,
1211 DAR_PWR_MODES_AUTODOZE);
1215 /* Disable clk_out */
1216 ret = regmap_update_bits(lp->regmap_dar, DAR_CLK_OUT_CTRL,
1217 DAR_CLK_OUT_CTRL_EN, 0x0);
1228 mcr20a_probe(struct spi_device *spi)
1230 struct ieee802154_hw *hw;
1231 struct mcr20a_local *lp;
1232 struct gpio_desc *rst_b;
1236 dev_dbg(&spi->dev, "%s\n", __func__);
1239 dev_err(&spi->dev, "no IRQ specified\n");
1243 rst_b = devm_gpiod_get(&spi->dev, "rst_b", GPIOD_OUT_HIGH);
1244 if (IS_ERR(rst_b)) {
1245 ret = PTR_ERR(rst_b);
1246 if (ret != -EPROBE_DEFER)
1247 dev_err(&spi->dev, "Failed to get 'rst_b' gpio: %d", ret);
1252 usleep_range(10, 20);
1253 gpiod_set_value_cansleep(rst_b, 1);
1254 usleep_range(10, 20);
1255 gpiod_set_value_cansleep(rst_b, 0);
1256 usleep_range(120, 240);
1258 /* allocate ieee802154_hw and private data */
1259 hw = ieee802154_alloc_hw(sizeof(*lp), &mcr20a_hw_ops);
1261 dev_crit(&spi->dev, "ieee802154_alloc_hw failed\n");
1265 /* init mcr20a local data */
1270 /* init ieee802154_hw */
1271 hw->parent = &spi->dev;
1272 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
1275 lp->buf = devm_kzalloc(&spi->dev, SPI_COMMAND_BUFFER, GFP_KERNEL);
1282 mcr20a_setup_tx_spi_messages(lp);
1283 mcr20a_setup_rx_spi_messages(lp);
1284 mcr20a_setup_irq_spi_messages(lp);
1287 lp->regmap_dar = devm_regmap_init_spi(spi, &mcr20a_dar_regmap);
1288 if (IS_ERR(lp->regmap_dar)) {
1289 ret = PTR_ERR(lp->regmap_dar);
1290 dev_err(&spi->dev, "Failed to allocate dar map: %d\n",
1295 lp->regmap_iar = devm_regmap_init_spi(spi, &mcr20a_iar_regmap);
1296 if (IS_ERR(lp->regmap_iar)) {
1297 ret = PTR_ERR(lp->regmap_iar);
1298 dev_err(&spi->dev, "Failed to allocate iar map: %d\n", ret);
1302 mcr20a_hw_setup(lp);
1304 spi_set_drvdata(spi, lp);
1306 ret = mcr20a_phy_init(lp);
1308 dev_crit(&spi->dev, "mcr20a_phy_init failed\n");
1312 irq_type = irq_get_trigger_type(spi->irq);
1314 irq_type = IRQF_TRIGGER_FALLING;
1316 ret = devm_request_irq(&spi->dev, spi->irq, mcr20a_irq_isr,
1317 irq_type, dev_name(&spi->dev), lp);
1319 dev_err(&spi->dev, "could not request_irq for mcr20a\n");
1324 /* disable_irq by default and wait for starting hardware */
1325 disable_irq(spi->irq);
1327 ret = ieee802154_register_hw(hw);
1329 dev_crit(&spi->dev, "ieee802154_register_hw failed\n");
1336 ieee802154_free_hw(lp->hw);
1341 static int mcr20a_remove(struct spi_device *spi)
1343 struct mcr20a_local *lp = spi_get_drvdata(spi);
1345 dev_dbg(&spi->dev, "%s\n", __func__);
1347 ieee802154_unregister_hw(lp->hw);
1348 ieee802154_free_hw(lp->hw);
1353 static const struct of_device_id mcr20a_of_match[] = {
1354 { .compatible = "nxp,mcr20a", },
1357 MODULE_DEVICE_TABLE(of, mcr20a_of_match);
1359 static const struct spi_device_id mcr20a_device_id[] = {
1360 { .name = "mcr20a", },
1363 MODULE_DEVICE_TABLE(spi, mcr20a_device_id);
1365 static struct spi_driver mcr20a_driver = {
1366 .id_table = mcr20a_device_id,
1368 .of_match_table = of_match_ptr(mcr20a_of_match),
1371 .probe = mcr20a_probe,
1372 .remove = mcr20a_remove,
1375 module_spi_driver(mcr20a_driver);
1377 MODULE_DESCRIPTION("MCR20A Transceiver Driver");
1378 MODULE_LICENSE("GPL v2");
1379 MODULE_AUTHOR("Xue Liu <liuxuenetmail@gmail>");