drivers/net/ieee802154/at86rf230.c

   1 /*
   2  * AT86RF230/RF231 driver
   3  *
   4  * Copyright (C) 2009-2012 Siemens AG
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2
   8  * as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * Written by:
  16  * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
  17  * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
  18  * Alexander Aring <aar@pengutronix.de>
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/hrtimer.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/gpio.h>
  27 #include <linux/delay.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/at86rf230.h>
  30 #include <linux/regmap.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/ieee802154.h>
  34
  35 #include <net/mac802154.h>
  36 #include <net/cfg802154.h>
  37
  38 struct at86rf230_local;
  39 /* at86rf2xx chip depend data.
  40  * All timings are in us.
  41  */
  42 struct at86rf2xx_chip_data {
  43         u16 t_sleep_cycle;
  44         u16 t_channel_switch;
  45         u16 t_reset_to_off;
  46         u16 t_off_to_aack;
  47         u16 t_off_to_tx_on;
  48         u16 t_frame;
  49         u16 t_p_ack;
  50         int rssi_base_val;
  51
  52         int (*set_channel)(struct at86rf230_local *, u8, u8);
  53         int (*set_txpower)(struct at86rf230_local *, s32);
  54 };
  55
  56 #define AT86RF2XX_MAX_BUF               (127 + 3)
  57 /* tx retries to access the TX_ON state
  58  * if it's above then force change will be started.
  59  *
  60  * We assume the max_frame_retries (7) value of 802.15.4 here.
  61  */
  62 #define AT86RF2XX_MAX_TX_RETRIES        7
  63 /* We use the recommended 5 minutes timeout to recalibrate */
  64 #define AT86RF2XX_CAL_LOOP_TIMEOUT      (5 * 60 * HZ)
  65
  66 struct at86rf230_state_change {
  67         struct at86rf230_local *lp;
  68         int irq;
  69
  70         struct hrtimer timer;
  71         struct spi_message msg;
  72         struct spi_transfer trx;
  73         u8 buf[AT86RF2XX_MAX_BUF];
  74
  75         void (*complete)(void *context);
  76         u8 from_state;
  77         u8 to_state;
  78
  79         bool irq_enable;
  80 };
  81
  82 struct at86rf230_local {
  83         struct spi_device *spi;
  84
  85         struct ieee802154_hw *hw;
  86         struct at86rf2xx_chip_data *data;
  87         struct regmap *regmap;
  88         int slp_tr;
  89
  90         struct completion state_complete;
  91         struct at86rf230_state_change state;
  92
  93         struct at86rf230_state_change irq;
  94
  95         bool tx_aret;
  96         unsigned long cal_timeout;
  97         s8 max_frame_retries;
  98         bool is_tx;
  99         bool is_tx_from_off;
 100         u8 tx_retry;
 101         struct sk_buff *tx_skb;
 102         struct at86rf230_state_change tx;
 103 };
 104
 105 #define RG_TRX_STATUS   (0x01)
 106 #define SR_TRX_STATUS           0x01, 0x1f, 0
 107 #define SR_RESERVED_01_3        0x01, 0x20, 5
 108 #define SR_CCA_STATUS           0x01, 0x40, 6
 109 #define SR_CCA_DONE             0x01, 0x80, 7
 110 #define RG_TRX_STATE    (0x02)
 111 #define SR_TRX_CMD              0x02, 0x1f, 0
 112 #define SR_TRAC_STATUS          0x02, 0xe0, 5
 113 #define RG_TRX_CTRL_0   (0x03)
 114 #define SR_CLKM_CTRL            0x03, 0x07, 0
 115 #define SR_CLKM_SHA_SEL         0x03, 0x08, 3
 116 #define SR_PAD_IO_CLKM          0x03, 0x30, 4
 117 #define SR_PAD_IO               0x03, 0xc0, 6
 118 #define RG_TRX_CTRL_1   (0x04)
 119 #define SR_IRQ_POLARITY         0x04, 0x01, 0
 120 #define SR_IRQ_MASK_MODE        0x04, 0x02, 1
 121 #define SR_SPI_CMD_MODE         0x04, 0x0c, 2
 122 #define SR_RX_BL_CTRL           0x04, 0x10, 4
 123 #define SR_TX_AUTO_CRC_ON       0x04, 0x20, 5
 124 #define SR_IRQ_2_EXT_EN         0x04, 0x40, 6
 125 #define SR_PA_EXT_EN            0x04, 0x80, 7
 126 #define RG_PHY_TX_PWR   (0x05)
 127 #define SR_TX_PWR_23X           0x05, 0x0f, 0
 128 #define SR_PA_LT_230            0x05, 0x30, 4
 129 #define SR_PA_BUF_LT_230        0x05, 0xc0, 6
 130 #define SR_TX_PWR_212           0x05, 0x1f, 0
 131 #define SR_GC_PA_212            0x05, 0x60, 5
 132 #define SR_PA_BOOST_LT_212      0x05, 0x80, 7
 133 #define RG_PHY_RSSI     (0x06)
 134 #define SR_RSSI                 0x06, 0x1f, 0
 135 #define SR_RND_VALUE            0x06, 0x60, 5
 136 #define SR_RX_CRC_VALID         0x06, 0x80, 7
 137 #define RG_PHY_ED_LEVEL (0x07)
 138 #define SR_ED_LEVEL             0x07, 0xff, 0
 139 #define RG_PHY_CC_CCA   (0x08)
 140 #define SR_CHANNEL              0x08, 0x1f, 0
 141 #define SR_CCA_MODE             0x08, 0x60, 5
 142 #define SR_CCA_REQUEST          0x08, 0x80, 7
 143 #define RG_CCA_THRES    (0x09)
 144 #define SR_CCA_ED_THRES         0x09, 0x0f, 0
 145 #define SR_RESERVED_09_1        0x09, 0xf0, 4
 146 #define RG_RX_CTRL      (0x0a)
 147 #define SR_PDT_THRES            0x0a, 0x0f, 0
 148 #define SR_RESERVED_0a_1        0x0a, 0xf0, 4
 149 #define RG_SFD_VALUE    (0x0b)
 150 #define SR_SFD_VALUE            0x0b, 0xff, 0
 151 #define RG_TRX_CTRL_2   (0x0c)
 152 #define SR_OQPSK_DATA_RATE      0x0c, 0x03, 0
 153 #define SR_SUB_MODE             0x0c, 0x04, 2
 154 #define SR_BPSK_QPSK            0x0c, 0x08, 3
 155 #define SR_OQPSK_SUB1_RC_EN     0x0c, 0x10, 4
 156 #define SR_RESERVED_0c_5        0x0c, 0x60, 5
 157 #define SR_RX_SAFE_MODE         0x0c, 0x80, 7
 158 #define RG_ANT_DIV      (0x0d)
 159 #define SR_ANT_CTRL             0x0d, 0x03, 0
 160 #define SR_ANT_EXT_SW_EN        0x0d, 0x04, 2
 161 #define SR_ANT_DIV_EN           0x0d, 0x08, 3
 162 #define SR_RESERVED_0d_2        0x0d, 0x70, 4
 163 #define SR_ANT_SEL              0x0d, 0x80, 7
 164 #define RG_IRQ_MASK     (0x0e)
 165 #define SR_IRQ_MASK             0x0e, 0xff, 0
 166 #define RG_IRQ_STATUS   (0x0f)
 167 #define SR_IRQ_0_PLL_LOCK       0x0f, 0x01, 0
 168 #define SR_IRQ_1_PLL_UNLOCK     0x0f, 0x02, 1
 169 #define SR_IRQ_2_RX_START       0x0f, 0x04, 2
 170 #define SR_IRQ_3_TRX_END        0x0f, 0x08, 3
 171 #define SR_IRQ_4_CCA_ED_DONE    0x0f, 0x10, 4
 172 #define SR_IRQ_5_AMI            0x0f, 0x20, 5
 173 #define SR_IRQ_6_TRX_UR         0x0f, 0x40, 6
 174 #define SR_IRQ_7_BAT_LOW        0x0f, 0x80, 7
 175 #define RG_VREG_CTRL    (0x10)
 176 #define SR_RESERVED_10_6        0x10, 0x03, 0
 177 #define SR_DVDD_OK              0x10, 0x04, 2
 178 #define SR_DVREG_EXT            0x10, 0x08, 3
 179 #define SR_RESERVED_10_3        0x10, 0x30, 4
 180 #define SR_AVDD_OK              0x10, 0x40, 6
 181 #define SR_AVREG_EXT            0x10, 0x80, 7
 182 #define RG_BATMON       (0x11)
 183 #define SR_BATMON_VTH           0x11, 0x0f, 0
 184 #define SR_BATMON_HR            0x11, 0x10, 4
 185 #define SR_BATMON_OK            0x11, 0x20, 5
 186 #define SR_RESERVED_11_1        0x11, 0xc0, 6
 187 #define RG_XOSC_CTRL    (0x12)
 188 #define SR_XTAL_TRIM            0x12, 0x0f, 0
 189 #define SR_XTAL_MODE            0x12, 0xf0, 4
 190 #define RG_RX_SYN       (0x15)
 191 #define SR_RX_PDT_LEVEL         0x15, 0x0f, 0
 192 #define SR_RESERVED_15_2        0x15, 0x70, 4
 193 #define SR_RX_PDT_DIS           0x15, 0x80, 7
 194 #define RG_XAH_CTRL_1   (0x17)
 195 #define SR_RESERVED_17_8        0x17, 0x01, 0
 196 #define SR_AACK_PROM_MODE       0x17, 0x02, 1
 197 #define SR_AACK_ACK_TIME        0x17, 0x04, 2
 198 #define SR_RESERVED_17_5        0x17, 0x08, 3
 199 #define SR_AACK_UPLD_RES_FT     0x17, 0x10, 4
 200 #define SR_AACK_FLTR_RES_FT     0x17, 0x20, 5
 201 #define SR_CSMA_LBT_MODE        0x17, 0x40, 6
 202 #define SR_RESERVED_17_1        0x17, 0x80, 7
 203 #define RG_FTN_CTRL     (0x18)
 204 #define SR_RESERVED_18_2        0x18, 0x7f, 0
 205 #define SR_FTN_START            0x18, 0x80, 7
 206 #define RG_PLL_CF       (0x1a)
 207 #define SR_RESERVED_1a_2        0x1a, 0x7f, 0
 208 #define SR_PLL_CF_START         0x1a, 0x80, 7
 209 #define RG_PLL_DCU      (0x1b)
 210 #define SR_RESERVED_1b_3        0x1b, 0x3f, 0
 211 #define SR_RESERVED_1b_2        0x1b, 0x40, 6
 212 #define SR_PLL_DCU_START        0x1b, 0x80, 7
 213 #define RG_PART_NUM     (0x1c)
 214 #define SR_PART_NUM             0x1c, 0xff, 0
 215 #define RG_VERSION_NUM  (0x1d)
 216 #define SR_VERSION_NUM          0x1d, 0xff, 0
 217 #define RG_MAN_ID_0     (0x1e)
 218 #define SR_MAN_ID_0             0x1e, 0xff, 0
 219 #define RG_MAN_ID_1     (0x1f)
 220 #define SR_MAN_ID_1             0x1f, 0xff, 0
 221 #define RG_SHORT_ADDR_0 (0x20)
 222 #define SR_SHORT_ADDR_0         0x20, 0xff, 0
 223 #define RG_SHORT_ADDR_1 (0x21)
 224 #define SR_SHORT_ADDR_1         0x21, 0xff, 0
 225 #define RG_PAN_ID_0     (0x22)
 226 #define SR_PAN_ID_0             0x22, 0xff, 0
 227 #define RG_PAN_ID_1     (0x23)
 228 #define SR_PAN_ID_1             0x23, 0xff, 0
 229 #define RG_IEEE_ADDR_0  (0x24)
 230 #define SR_IEEE_ADDR_0          0x24, 0xff, 0
 231 #define RG_IEEE_ADDR_1  (0x25)
 232 #define SR_IEEE_ADDR_1          0x25, 0xff, 0
 233 #define RG_IEEE_ADDR_2  (0x26)
 234 #define SR_IEEE_ADDR_2          0x26, 0xff, 0
 235 #define RG_IEEE_ADDR_3  (0x27)
 236 #define SR_IEEE_ADDR_3          0x27, 0xff, 0
 237 #define RG_IEEE_ADDR_4  (0x28)
 238 #define SR_IEEE_ADDR_4          0x28, 0xff, 0
 239 #define RG_IEEE_ADDR_5  (0x29)
 240 #define SR_IEEE_ADDR_5          0x29, 0xff, 0
 241 #define RG_IEEE_ADDR_6  (0x2a)
 242 #define SR_IEEE_ADDR_6          0x2a, 0xff, 0
 243 #define RG_IEEE_ADDR_7  (0x2b)
 244 #define SR_IEEE_ADDR_7          0x2b, 0xff, 0
 245 #define RG_XAH_CTRL_0   (0x2c)
 246 #define SR_SLOTTED_OPERATION    0x2c, 0x01, 0
 247 #define SR_MAX_CSMA_RETRIES     0x2c, 0x0e, 1
 248 #define SR_MAX_FRAME_RETRIES    0x2c, 0xf0, 4
 249 #define RG_CSMA_SEED_0  (0x2d)
 250 #define SR_CSMA_SEED_0          0x2d, 0xff, 0
 251 #define RG_CSMA_SEED_1  (0x2e)
 252 #define SR_CSMA_SEED_1          0x2e, 0x07, 0
 253 #define SR_AACK_I_AM_COORD      0x2e, 0x08, 3
 254 #define SR_AACK_DIS_ACK         0x2e, 0x10, 4
 255 #define SR_AACK_SET_PD          0x2e, 0x20, 5
 256 #define SR_AACK_FVN_MODE        0x2e, 0xc0, 6
 257 #define RG_CSMA_BE      (0x2f)
 258 #define SR_MIN_BE               0x2f, 0x0f, 0
 259 #define SR_MAX_BE               0x2f, 0xf0, 4
 260
 261 #define CMD_REG         0x80
 262 #define CMD_REG_MASK    0x3f
 263 #define CMD_WRITE       0x40
 264 #define CMD_FB          0x20
 265
 266 #define IRQ_BAT_LOW     (1 << 7)
 267 #define IRQ_TRX_UR      (1 << 6)
 268 #define IRQ_AMI         (1 << 5)
 269 #define IRQ_CCA_ED      (1 << 4)
 270 #define IRQ_TRX_END     (1 << 3)
 271 #define IRQ_RX_START    (1 << 2)
 272 #define IRQ_PLL_UNL     (1 << 1)
 273 #define IRQ_PLL_LOCK    (1 << 0)
 274
 275 #define IRQ_ACTIVE_HIGH 0
 276 #define IRQ_ACTIVE_LOW  1
 277
 278 #define STATE_P_ON              0x00    /* BUSY */
 279 #define STATE_BUSY_RX           0x01
 280 #define STATE_BUSY_TX           0x02
 281 #define STATE_FORCE_TRX_OFF     0x03
 282 #define STATE_FORCE_TX_ON       0x04    /* IDLE */
 283 /* 0x05 */                              /* INVALID_PARAMETER */
 284 #define STATE_RX_ON             0x06
 285 /* 0x07 */                              /* SUCCESS */
 286 #define STATE_TRX_OFF           0x08
 287 #define STATE_TX_ON             0x09
 288 /* 0x0a - 0x0e */                       /* 0x0a - UNSUPPORTED_ATTRIBUTE */
 289 #define STATE_SLEEP             0x0F
 290 #define STATE_PREP_DEEP_SLEEP   0x10
 291 #define STATE_BUSY_RX_AACK      0x11
 292 #define STATE_BUSY_TX_ARET      0x12
 293 #define STATE_RX_AACK_ON        0x16
 294 #define STATE_TX_ARET_ON        0x19
 295 #define STATE_RX_ON_NOCLK       0x1C
 296 #define STATE_RX_AACK_ON_NOCLK  0x1D
 297 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
 298 #define STATE_TRANSITION_IN_PROGRESS 0x1F
 299
 300 #define TRX_STATE_MASK          (0x1F)
 301
 302 #define AT86RF2XX_NUMREGS 0x3F
 303
 304 static void
 305 at86rf230_async_state_change(struct at86rf230_local *lp,
 306                              struct at86rf230_state_change *ctx,
 307                              const u8 state, void (*complete)(void *context),
 308                              const bool irq_enable);
 309
 310 static inline int
 311 __at86rf230_write(struct at86rf230_local *lp,
 312                   unsigned int addr, unsigned int data)
 313 {
 314         return regmap_write(lp->regmap, addr, data);
 315 }
 316
 317 static inline int
 318 __at86rf230_read(struct at86rf230_local *lp,
 319                  unsigned int addr, unsigned int *data)
 320 {
 321         return regmap_read(lp->regmap, addr, data);
 322 }
 323
 324 static inline int
 325 at86rf230_read_subreg(struct at86rf230_local *lp,
 326                       unsigned int addr, unsigned int mask,
 327                       unsigned int shift, unsigned int *data)
 328 {
 329         int rc;
 330
 331         rc = __at86rf230_read(lp, addr, data);
 332         if (!rc)
 333                 *data = (*data & mask) >> shift;
 334
 335         return rc;
 336 }
 337
 338 static inline int
 339 at86rf230_write_subreg(struct at86rf230_local *lp,
 340                        unsigned int addr, unsigned int mask,
 341                        unsigned int shift, unsigned int data)
 342 {
 343         return regmap_update_bits(lp->regmap, addr, mask, data << shift);
 344 }
 345
 346 static inline void
 347 at86rf230_slp_tr_rising_edge(struct at86rf230_local *lp)
 348 {
 349         gpio_set_value(lp->slp_tr, 1);
 350         udelay(1);
 351         gpio_set_value(lp->slp_tr, 0);
 352 }
 353
 354 static bool
 355 at86rf230_reg_writeable(struct device *dev, unsigned int reg)
 356 {
 357         switch (reg) {
 358         case RG_TRX_STATE:
 359         case RG_TRX_CTRL_0:
 360         case RG_TRX_CTRL_1:
 361         case RG_PHY_TX_PWR:
 362         case RG_PHY_ED_LEVEL:
 363         case RG_PHY_CC_CCA:
 364         case RG_CCA_THRES:
 365         case RG_RX_CTRL:
 366         case RG_SFD_VALUE:
 367         case RG_TRX_CTRL_2:
 368         case RG_ANT_DIV:
 369         case RG_IRQ_MASK:
 370         case RG_VREG_CTRL:
 371         case RG_BATMON:
 372         case RG_XOSC_CTRL:
 373         case RG_RX_SYN:
 374         case RG_XAH_CTRL_1:
 375         case RG_FTN_CTRL:
 376         case RG_PLL_CF:
 377         case RG_PLL_DCU:
 378         case RG_SHORT_ADDR_0:
 379         case RG_SHORT_ADDR_1:
 380         case RG_PAN_ID_0:
 381         case RG_PAN_ID_1:
 382         case RG_IEEE_ADDR_0:
 383         case RG_IEEE_ADDR_1:
 384         case RG_IEEE_ADDR_2:
 385         case RG_IEEE_ADDR_3:
 386         case RG_IEEE_ADDR_4:
 387         case RG_IEEE_ADDR_5:
 388         case RG_IEEE_ADDR_6:
 389         case RG_IEEE_ADDR_7:
 390         case RG_XAH_CTRL_0:
 391         case RG_CSMA_SEED_0:
 392         case RG_CSMA_SEED_1:
 393         case RG_CSMA_BE:
 394                 return true;
 395         default:
 396                 return false;
 397         }
 398 }
 399
 400 static bool
 401 at86rf230_reg_readable(struct device *dev, unsigned int reg)
 402 {
 403         bool rc;
 404
 405         /* all writeable are also readable */
 406         rc = at86rf230_reg_writeable(dev, reg);
 407         if (rc)
 408                 return rc;
 409
 410         /* readonly regs */
 411         switch (reg) {
 412         case RG_TRX_STATUS:
 413         case RG_PHY_RSSI:
 414         case RG_IRQ_STATUS:
 415         case RG_PART_NUM:
 416         case RG_VERSION_NUM:
 417         case RG_MAN_ID_1:
 418         case RG_MAN_ID_0:
 419                 return true;
 420         default:
 421                 return false;
 422         }
 423 }
 424
 425 static bool
 426 at86rf230_reg_volatile(struct device *dev, unsigned int reg)
 427 {
 428         /* can be changed during runtime */
 429         switch (reg) {
 430         case RG_TRX_STATUS:
 431         case RG_TRX_STATE:
 432         case RG_PHY_RSSI:
 433         case RG_PHY_ED_LEVEL:
 434         case RG_IRQ_STATUS:
 435         case RG_VREG_CTRL:
 436         case RG_PLL_CF:
 437         case RG_PLL_DCU:
 438                 return true;
 439         default:
 440                 return false;
 441         }
 442 }
 443
 444 static bool
 445 at86rf230_reg_precious(struct device *dev, unsigned int reg)
 446 {
 447         /* don't clear irq line on read */
 448         switch (reg) {
 449         case RG_IRQ_STATUS:
 450                 return true;
 451         default:
 452                 return false;
 453         }
 454 }
 455
 456 static const struct regmap_config at86rf230_regmap_spi_config = {
 457         .reg_bits = 8,
 458         .val_bits = 8,
 459         .write_flag_mask = CMD_REG | CMD_WRITE,
 460         .read_flag_mask = CMD_REG,
 461         .cache_type = REGCACHE_RBTREE,
 462         .max_register = AT86RF2XX_NUMREGS,
 463         .writeable_reg = at86rf230_reg_writeable,
 464         .readable_reg = at86rf230_reg_readable,
 465         .volatile_reg = at86rf230_reg_volatile,
 466         .precious_reg = at86rf230_reg_precious,
 467 };
 468
 469 static void
 470 at86rf230_async_error_recover(void *context)
 471 {
 472         struct at86rf230_state_change *ctx = context;
 473         struct at86rf230_local *lp = ctx->lp;
 474
 475         lp->is_tx = 0;
 476         at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, NULL, false);
 477         ieee802154_wake_queue(lp->hw);
 478 }
 479
 480 static inline void
 481 at86rf230_async_error(struct at86rf230_local *lp,
 482                       struct at86rf230_state_change *ctx, int rc)
 483 {
 484         dev_err(&lp->spi->dev, "spi_async error %d\n", rc);
 485
 486         at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
 487                                      at86rf230_async_error_recover, false);
 488 }
 489
 490 /* Generic function to get some register value in async mode */
 491 static void
 492 at86rf230_async_read_reg(struct at86rf230_local *lp, const u8 reg,
 493                          struct at86rf230_state_change *ctx,
 494                          void (*complete)(void *context),
 495                          const bool irq_enable)
 496 {
 497         int rc;
 498
 499         u8 *tx_buf = ctx->buf;
 500
 501         tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
 502         ctx->msg.complete = complete;
 503         ctx->irq_enable = irq_enable;
 504         rc = spi_async(lp->spi, &ctx->msg);
 505         if (rc) {
 506                 if (irq_enable)
 507                         enable_irq(ctx->irq);
 508
 509                 at86rf230_async_error(lp, ctx, rc);
 510         }
 511 }
 512
 513 static inline u8 at86rf230_state_to_force(u8 state)
 514 {
 515         if (state == STATE_TX_ON)
 516                 return STATE_FORCE_TX_ON;
 517         else
 518                 return STATE_FORCE_TRX_OFF;
 519 }
 520
 521 static void
 522 at86rf230_async_state_assert(void *context)
 523 {
 524         struct at86rf230_state_change *ctx = context;
 525         struct at86rf230_local *lp = ctx->lp;
 526         const u8 *buf = ctx->buf;
 527         const u8 trx_state = buf[1] & TRX_STATE_MASK;
 528
 529         /* Assert state change */
 530         if (trx_state != ctx->to_state) {
 531                 /* Special handling if transceiver state is in
 532                  * STATE_BUSY_RX_AACK and a SHR was detected.
 533                  */
 534                 if  (trx_state == STATE_BUSY_RX_AACK) {
 535                         /* Undocumented race condition. If we send a state
 536                          * change to STATE_RX_AACK_ON the transceiver could
 537                          * change his state automatically to STATE_BUSY_RX_AACK
 538                          * if a SHR was detected. This is not an error, but we
 539                          * can't assert this.
 540                          */
 541                         if (ctx->to_state == STATE_RX_AACK_ON)
 542                                 goto done;
 543
 544                         /* If we change to STATE_TX_ON without forcing and
 545                          * transceiver state is STATE_BUSY_RX_AACK, we wait
 546                          * 'tFrame + tPAck' receiving time. In this time the
 547                          * PDU should be received. If the transceiver is still
 548                          * in STATE_BUSY_RX_AACK, we run a force state change
 549                          * to STATE_TX_ON. This is a timeout handling, if the
 550                          * transceiver stucks in STATE_BUSY_RX_AACK.
 551                          *
 552                          * Additional we do several retries to try to get into
 553                          * TX_ON state without forcing. If the retries are
 554                          * higher or equal than AT86RF2XX_MAX_TX_RETRIES we
 555                          * will do a force change.
 556                          */
 557                         if (ctx->to_state == STATE_TX_ON ||
 558                             ctx->to_state == STATE_TRX_OFF) {
 559                                 u8 state = ctx->to_state;
 560
 561                                 if (lp->tx_retry >= AT86RF2XX_MAX_TX_RETRIES)
 562                                         state = at86rf230_state_to_force(state);
 563                                 lp->tx_retry++;
 564
 565                                 at86rf230_async_state_change(lp, ctx, state,
 566                                                              ctx->complete,
 567                                                              ctx->irq_enable);
 568                                 return;
 569                         }
 570                 }
 571
 572                 dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n",
 573                          ctx->from_state, ctx->to_state, trx_state);
 574         }
 575
 576 done:
 577         if (ctx->complete)
 578                 ctx->complete(context);
 579 }
 580
 581 static enum hrtimer_restart at86rf230_async_state_timer(struct hrtimer *timer)
 582 {
 583         struct at86rf230_state_change *ctx =
 584                 container_of(timer, struct at86rf230_state_change, timer);
 585         struct at86rf230_local *lp = ctx->lp;
 586
 587         at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
 588                                  at86rf230_async_state_assert,
 589                                  ctx->irq_enable);
 590
 591         return HRTIMER_NORESTART;
 592 }
 593
 594 /* Do state change timing delay. */
 595 static void
 596 at86rf230_async_state_delay(void *context)
 597 {
 598         struct at86rf230_state_change *ctx = context;
 599         struct at86rf230_local *lp = ctx->lp;
 600         struct at86rf2xx_chip_data *c = lp->data;
 601         bool force = false;
 602         ktime_t tim;
 603
 604         /* The force state changes are will show as normal states in the
 605          * state status subregister. We change the to_state to the
 606          * corresponding one and remember if it was a force change, this
 607          * differs if we do a state change from STATE_BUSY_RX_AACK.
 608          */
 609         switch (ctx->to_state) {
 610         case STATE_FORCE_TX_ON:
 611                 ctx->to_state = STATE_TX_ON;
 612                 force = true;
 613                 break;
 614         case STATE_FORCE_TRX_OFF:
 615                 ctx->to_state = STATE_TRX_OFF;
 616                 force = true;
 617                 break;
 618         default:
 619                 break;
 620         }
 621
 622         switch (ctx->from_state) {
 623         case STATE_TRX_OFF:
 624                 switch (ctx->to_state) {
 625                 case STATE_RX_AACK_ON:
 626                         tim = ktime_set(0, c->t_off_to_aack * NSEC_PER_USEC);
 627                         /* state change from TRX_OFF to RX_AACK_ON to do a
 628                          * calibration, we need to reset the timeout for the
 629                          * next one.
 630                          */
 631                         lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
 632                         goto change;
 633                 case STATE_TX_ARET_ON:
 634                 case STATE_TX_ON:
 635                         tim = ktime_set(0, c->t_off_to_tx_on * NSEC_PER_USEC);
 636                         /* state change from TRX_OFF to TX_ON or ARET_ON to do
 637                          * a calibration, we need to reset the timeout for the
 638                          * next one.
 639                          */
 640                         lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
 641                         goto change;
 642                 default:
 643                         break;
 644                 }
 645                 break;
 646         case STATE_BUSY_RX_AACK:
 647                 switch (ctx->to_state) {
 648                 case STATE_TRX_OFF:
 649                 case STATE_TX_ON:
 650                         /* Wait for worst case receiving time if we
 651                          * didn't make a force change from BUSY_RX_AACK
 652                          * to TX_ON or TRX_OFF.
 653                          */
 654                         if (!force) {
 655                                 tim = ktime_set(0, (c->t_frame + c->t_p_ack) *
 656                                                    NSEC_PER_USEC);
 657                                 goto change;
 658                         }
 659                         break;
 660                 default:
 661                         break;
 662                 }
 663                 break;
 664         /* Default value, means RESET state */
 665         case STATE_P_ON:
 666                 switch (ctx->to_state) {
 667                 case STATE_TRX_OFF:
 668                         tim = ktime_set(0, c->t_reset_to_off * NSEC_PER_USEC);
 669                         goto change;
 670                 default:
 671                         break;
 672                 }
 673                 break;
 674         default:
 675                 break;
 676         }
 677
 678         /* Default delay is 1us in the most cases */
 679         tim = ktime_set(0, NSEC_PER_USEC);
 680
 681 change:
 682         hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
 683 }
 684
 685 static void
 686 at86rf230_async_state_change_start(void *context)
 687 {
 688         struct at86rf230_state_change *ctx = context;
 689         struct at86rf230_local *lp = ctx->lp;
 690         u8 *buf = ctx->buf;
 691         const u8 trx_state = buf[1] & TRX_STATE_MASK;
 692         int rc;
 693
 694         /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */
 695         if (trx_state == STATE_TRANSITION_IN_PROGRESS) {
 696                 udelay(1);
 697                 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
 698                                          at86rf230_async_state_change_start,
 699                                          ctx->irq_enable);
 700                 return;
 701         }
 702
 703         /* Check if we already are in the state which we change in */
 704         if (trx_state == ctx->to_state) {
 705                 if (ctx->complete)
 706                         ctx->complete(context);
 707                 return;
 708         }
 709
 710         /* Set current state to the context of state change */
 711         ctx->from_state = trx_state;
 712
 713         /* Going into the next step for a state change which do a timing
 714          * relevant delay.
 715          */
 716         buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
 717         buf[1] = ctx->to_state;
 718         ctx->msg.complete = at86rf230_async_state_delay;
 719         rc = spi_async(lp->spi, &ctx->msg);
 720         if (rc) {
 721                 if (ctx->irq_enable)
 722                         enable_irq(ctx->irq);
 723
 724                 at86rf230_async_error(lp, ctx, rc);
 725         }
 726 }
 727
 728 static void
 729 at86rf230_async_state_change(struct at86rf230_local *lp,
 730                              struct at86rf230_state_change *ctx,
 731                              const u8 state, void (*complete)(void *context),
 732                              const bool irq_enable)
 733 {
 734         /* Initialization for the state change context */
 735         ctx->to_state = state;
 736         ctx->complete = complete;
 737         ctx->irq_enable = irq_enable;
 738         at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
 739                                  at86rf230_async_state_change_start,
 740                                  irq_enable);
 741 }
 742
 743 static void
 744 at86rf230_sync_state_change_complete(void *context)
 745 {
 746         struct at86rf230_state_change *ctx = context;
 747         struct at86rf230_local *lp = ctx->lp;
 748
 749         complete(&lp->state_complete);
 750 }
 751
 752 /* This function do a sync framework above the async state change.
 753  * Some callbacks of the IEEE 802.15.4 driver interface need to be
 754  * handled synchronously.
 755  */
 756 static int
 757 at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state)
 758 {
 759         unsigned long rc;
 760
 761         at86rf230_async_state_change(lp, &lp->state, state,
 762                                      at86rf230_sync_state_change_complete,
 763                                      false);
 764
 765         rc = wait_for_completion_timeout(&lp->state_complete,
 766                                          msecs_to_jiffies(100));
 767         if (!rc) {
 768                 at86rf230_async_error(lp, &lp->state, -ETIMEDOUT);
 769                 return -ETIMEDOUT;
 770         }
 771
 772         return 0;
 773 }
 774
 775 static void
 776 at86rf230_tx_complete(void *context)
 777 {
 778         struct at86rf230_state_change *ctx = context;
 779         struct at86rf230_local *lp = ctx->lp;
 780
 781         enable_irq(ctx->irq);
 782
 783         ieee802154_xmit_complete(lp->hw, lp->tx_skb, !lp->tx_aret);
 784 }
 785
 786 static void
 787 at86rf230_tx_on(void *context)
 788 {
 789         struct at86rf230_state_change *ctx = context;
 790         struct at86rf230_local *lp = ctx->lp;
 791
 792         at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
 793                                      at86rf230_tx_complete, true);
 794 }
 795
 796 static void
 797 at86rf230_tx_trac_check(void *context)
 798 {
 799         struct at86rf230_state_change *ctx = context;
 800         struct at86rf230_local *lp = ctx->lp;
 801         const u8 *buf = ctx->buf;
 802         const u8 trac = (buf[1] & 0xe0) >> 5;
 803
 804         /* If trac status is different than zero we need to do a state change
 805          * to STATE_FORCE_TRX_OFF then STATE_RX_AACK_ON to recover the
 806          * transceiver.
 807          */
 808         if (trac)
 809                 at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
 810                                              at86rf230_tx_on, true);
 811         else
 812                 at86rf230_tx_on(context);
 813 }
 814
 815 static void
 816 at86rf230_tx_trac_status(void *context)
 817 {
 818         struct at86rf230_state_change *ctx = context;
 819         struct at86rf230_local *lp = ctx->lp;
 820
 821         at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
 822                                  at86rf230_tx_trac_check, true);
 823 }
 824
 825 static void
 826 at86rf230_rx_read_frame_complete(void *context)
 827 {
 828         struct at86rf230_state_change *ctx = context;
 829         struct at86rf230_local *lp = ctx->lp;
 830         u8 rx_local_buf[AT86RF2XX_MAX_BUF];
 831         const u8 *buf = ctx->buf;
 832         struct sk_buff *skb;
 833         u8 len, lqi;
 834
 835         len = buf[1];
 836         if (!ieee802154_is_valid_psdu_len(len)) {
 837                 dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
 838                 len = IEEE802154_MTU;
 839         }
 840         lqi = buf[2 + len];
 841
 842         memcpy(rx_local_buf, buf + 2, len);
 843         ctx->trx.len = 2;
 844         enable_irq(ctx->irq);
 845
 846         skb = dev_alloc_skb(IEEE802154_MTU);
 847         if (!skb) {
 848                 dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n");
 849                 return;
 850         }
 851
 852         memcpy(skb_put(skb, len), rx_local_buf, len);
 853         ieee802154_rx_irqsafe(lp->hw, skb, lqi);
 854 }
 855
 856 static void
 857 at86rf230_rx_read_frame(void *context)
 858 {
 859         struct at86rf230_state_change *ctx = context;
 860         struct at86rf230_local *lp = ctx->lp;
 861         u8 *buf = ctx->buf;
 862         int rc;
 863
 864         buf[0] = CMD_FB;
 865         ctx->trx.len = AT86RF2XX_MAX_BUF;
 866         ctx->msg.complete = at86rf230_rx_read_frame_complete;
 867         rc = spi_async(lp->spi, &ctx->msg);
 868         if (rc) {
 869                 ctx->trx.len = 2;
 870                 enable_irq(ctx->irq);
 871                 at86rf230_async_error(lp, ctx, rc);
 872         }
 873 }
 874
 875 static void
 876 at86rf230_rx_trac_check(void *context)
 877 {
 878         /* Possible check on trac status here. This could be useful to make
 879          * some stats why receive is failed. Not used at the moment, but it's
 880          * maybe timing relevant. Datasheet doesn't say anything about this.
 881          * The programming guide say do it so.
 882          */
 883
 884         at86rf230_rx_read_frame(context);
 885 }
 886
 887 static void
 888 at86rf230_irq_trx_end(struct at86rf230_local *lp)
 889 {
 890         if (lp->is_tx) {
 891                 lp->is_tx = 0;
 892
 893                 if (lp->tx_aret)
 894                         at86rf230_async_state_change(lp, &lp->irq,
 895                                                      STATE_FORCE_TX_ON,
 896                                                      at86rf230_tx_trac_status,
 897                                                      true);
 898                 else
 899                         at86rf230_async_state_change(lp, &lp->irq,
 900                                                      STATE_RX_AACK_ON,
 901                                                      at86rf230_tx_complete,
 902                                                      true);
 903         } else {
 904                 at86rf230_async_read_reg(lp, RG_TRX_STATE, &lp->irq,
 905                                          at86rf230_rx_trac_check, true);
 906         }
 907 }
 908
 909 static void
 910 at86rf230_irq_status(void *context)
 911 {
 912         struct at86rf230_state_change *ctx = context;
 913         struct at86rf230_local *lp = ctx->lp;
 914         const u8 *buf = ctx->buf;
 915         const u8 irq = buf[1];
 916
 917         if (irq & IRQ_TRX_END) {
 918                 at86rf230_irq_trx_end(lp);
 919         } else {
 920                 enable_irq(ctx->irq);
 921                 dev_err(&lp->spi->dev, "not supported irq %02x received\n",
 922                         irq);
 923         }
 924 }
 925
 926 static irqreturn_t at86rf230_isr(int irq, void *data)
 927 {
 928         struct at86rf230_local *lp = data;
 929         struct at86rf230_state_change *ctx = &lp->irq;
 930         u8 *buf = ctx->buf;
 931         int rc;
 932
 933         disable_irq_nosync(irq);
 934
 935         buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG;
 936         ctx->msg.complete = at86rf230_irq_status;
 937         rc = spi_async(lp->spi, &ctx->msg);
 938         if (rc) {
 939                 enable_irq(irq);
 940                 at86rf230_async_error(lp, ctx, rc);
 941                 return IRQ_NONE;
 942         }
 943
 944         return IRQ_HANDLED;
 945 }
 946
 947 static void
 948 at86rf230_write_frame_complete(void *context)
 949 {
 950         struct at86rf230_state_change *ctx = context;
 951         struct at86rf230_local *lp = ctx->lp;
 952         u8 *buf = ctx->buf;
 953         int rc;
 954
 955         ctx->trx.len = 2;
 956
 957         if (gpio_is_valid(lp->slp_tr)) {
 958                 at86rf230_slp_tr_rising_edge(lp);
 959         } else {
 960                 buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
 961                 buf[1] = STATE_BUSY_TX;
 962                 ctx->msg.complete = NULL;
 963                 rc = spi_async(lp->spi, &ctx->msg);
 964                 if (rc)
 965                         at86rf230_async_error(lp, ctx, rc);
 966         }
 967 }
 968
 969 static void
 970 at86rf230_write_frame(void *context)
 971 {
 972         struct at86rf230_state_change *ctx = context;
 973         struct at86rf230_local *lp = ctx->lp;
 974         struct sk_buff *skb = lp->tx_skb;
 975         u8 *buf = ctx->buf;
 976         int rc;
 977
 978         lp->is_tx = 1;
 979
 980         buf[0] = CMD_FB | CMD_WRITE;
 981         buf[1] = skb->len + 2;
 982         memcpy(buf + 2, skb->data, skb->len);
 983         ctx->trx.len = skb->len + 2;
 984         ctx->msg.complete = at86rf230_write_frame_complete;
 985         rc = spi_async(lp->spi, &ctx->msg);
 986         if (rc) {
 987                 ctx->trx.len = 2;
 988                 at86rf230_async_error(lp, ctx, rc);
 989         }
 990 }
 991
 992 static void
 993 at86rf230_xmit_tx_on(void *context)
 994 {
 995         struct at86rf230_state_change *ctx = context;
 996         struct at86rf230_local *lp = ctx->lp;
 997
 998         at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
 999                                      at86rf230_write_frame, false);
1000 }
1001
1002 static void
1003 at86rf230_xmit_start(void *context)
1004 {
1005         struct at86rf230_state_change *ctx = context;
1006         struct at86rf230_local *lp = ctx->lp;
1007
1008         /* In ARET mode we need to go into STATE_TX_ARET_ON after we
1009          * are in STATE_TX_ON. The pfad differs here, so we change
1010          * the complete handler.
1011          */
1012         if (lp->tx_aret) {
1013                 if (lp->is_tx_from_off) {
1014                         lp->is_tx_from_off = false;
1015                         at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
1016                                                      at86rf230_xmit_tx_on,
1017                                                      false);
1018                 } else {
1019                         at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
1020                                                      at86rf230_xmit_tx_on,
1021                                                      false);
1022                 }
1023         } else {
1024                 at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
1025                                              at86rf230_write_frame, false);
1026         }
1027 }
1028
1029 static int
1030 at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
1031 {
1032         struct at86rf230_local *lp = hw->priv;
1033         struct at86rf230_state_change *ctx = &lp->tx;
1034
1035         lp->tx_skb = skb;
1036         lp->tx_retry = 0;
1037
1038         /* After 5 minutes in PLL and the same frequency we run again the
1039          * calibration loops which is recommended by at86rf2xx datasheets.
1040          *
1041          * The calibration is initiate by a state change from TRX_OFF
1042          * to TX_ON, the lp->cal_timeout should be reinit by state_delay
1043          * function then to start in the next 5 minutes.
1044          */
1045         if (time_is_before_jiffies(lp->cal_timeout)) {
1046                 lp->is_tx_from_off = true;
1047                 at86rf230_async_state_change(lp, ctx, STATE_TRX_OFF,
1048                                              at86rf230_xmit_start, false);
1049         } else {
1050                 at86rf230_xmit_start(ctx);
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int
1057 at86rf230_ed(struct ieee802154_hw *hw, u8 *level)
1058 {
1059         BUG_ON(!level);
1060         *level = 0xbe;
1061         return 0;
1062 }
1063
1064 static int
1065 at86rf230_start(struct ieee802154_hw *hw)
1066 {
1067         return at86rf230_sync_state_change(hw->priv, STATE_RX_AACK_ON);
1068 }
1069
1070 static void
1071 at86rf230_stop(struct ieee802154_hw *hw)
1072 {
1073         at86rf230_sync_state_change(hw->priv, STATE_FORCE_TRX_OFF);
1074 }
1075
1076 static int
1077 at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
1078 {
1079         return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1080 }
1081
1082 #define AT86RF2XX_MAX_ED_LEVELS 0xF
1083 static const s32 at86rf23x_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
1084         -9100, -8900, -8700, -8500, -8300, -8100, -7900, -7700, -7500, -7300,
1085         -7100, -6900, -6700, -6500, -6300, -6100,
1086 };
1087
1088 static const s32 at86rf212_ed_levels_100[AT86RF2XX_MAX_ED_LEVELS + 1] = {
1089         -10000, -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200,
1090         -8000, -7800, -7600, -7400, -7200,
1091 };
1092
1093 static const s32 at86rf212_ed_levels_98[AT86RF2XX_MAX_ED_LEVELS + 1] = {
1094         -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000,
1095         -7800, -7600, -7400, -7200, -7000,
1096 };
1097
1098 static inline int
1099 at86rf212_update_cca_ed_level(struct at86rf230_local *lp, int rssi_base_val)
1100 {
1101         unsigned int cca_ed_thres;
1102         int rc;
1103
1104         rc = at86rf230_read_subreg(lp, SR_CCA_ED_THRES, &cca_ed_thres);
1105         if (rc < 0)
1106                 return rc;
1107
1108         switch (rssi_base_val) {
1109         case -98:
1110                 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_98;
1111                 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_98);
1112                 lp->hw->phy->cca_ed_level = at86rf212_ed_levels_98[cca_ed_thres];
1113                 break;
1114         case -100:
1115                 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
1116                 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
1117                 lp->hw->phy->cca_ed_level = at86rf212_ed_levels_100[cca_ed_thres];
1118                 break;
1119         default:
1120                 WARN_ON(1);
1121         }
1122
1123         return 0;
1124 }
1125
1126 static int
1127 at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
1128 {
1129         int rc;
1130
1131         if (channel == 0)
1132                 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
1133         else
1134                 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
1135         if (rc < 0)
1136                 return rc;
1137
1138         if (page == 0) {
1139                 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0);
1140                 lp->data->rssi_base_val = -100;
1141         } else {
1142                 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1);
1143                 lp->data->rssi_base_val = -98;
1144         }
1145         if (rc < 0)
1146                 return rc;
1147
1148         rc = at86rf212_update_cca_ed_level(lp, lp->data->rssi_base_val);
1149         if (rc < 0)
1150                 return rc;
1151
1152         /* This sets the symbol_duration according frequency on the 212.
1153          * TODO move this handling while set channel and page in cfg802154.
1154          * We can do that, this timings are according 802.15.4 standard.
1155          * If we do that in cfg802154, this is a more generic calculation.
1156          *
1157          * This should also protected from ifs_timer. Means cancel timer and
1158          * init with a new value. For now, this is okay.
1159          */
1160         if (channel == 0) {
1161                 if (page == 0) {
1162                         /* SUB:0 and BPSK:0 -> BPSK-20 */
1163                         lp->hw->phy->symbol_duration = 50;
1164                 } else {
1165                         /* SUB:1 and BPSK:0 -> BPSK-40 */
1166                         lp->hw->phy->symbol_duration = 25;
1167                 }
1168         } else {
1169                 if (page == 0)
1170                         /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */
1171                         lp->hw->phy->symbol_duration = 40;
1172                 else
1173                         /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */
1174                         lp->hw->phy->symbol_duration = 16;
1175         }
1176
1177         lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD *
1178                                    lp->hw->phy->symbol_duration;
1179         lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD *
1180                                    lp->hw->phy->symbol_duration;
1181
1182         return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1183 }
1184
1185 static int
1186 at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
1187 {
1188         struct at86rf230_local *lp = hw->priv;
1189         int rc;
1190
1191         rc = lp->data->set_channel(lp, page, channel);
1192         /* Wait for PLL */
1193         usleep_range(lp->data->t_channel_switch,
1194                      lp->data->t_channel_switch + 10);
1195
1196         lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
1197         return rc;
1198 }
1199
1200 static int
1201 at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
1202                            struct ieee802154_hw_addr_filt *filt,
1203                            unsigned long changed)
1204 {
1205         struct at86rf230_local *lp = hw->priv;
1206
1207         if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
1208                 u16 addr = le16_to_cpu(filt->short_addr);
1209
1210                 dev_vdbg(&lp->spi->dev,
1211                          "at86rf230_set_hw_addr_filt called for saddr\n");
1212                 __at86rf230_write(lp, RG_SHORT_ADDR_0, addr);
1213                 __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8);
1214         }
1215
1216         if (changed & IEEE802154_AFILT_PANID_CHANGED) {
1217                 u16 pan = le16_to_cpu(filt->pan_id);
1218
1219                 dev_vdbg(&lp->spi->dev,
1220                          "at86rf230_set_hw_addr_filt called for pan id\n");
1221                 __at86rf230_write(lp, RG_PAN_ID_0, pan);
1222                 __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8);
1223         }
1224
1225         if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
1226                 u8 i, addr[8];
1227
1228                 memcpy(addr, &filt->ieee_addr, 8);
1229                 dev_vdbg(&lp->spi->dev,
1230                          "at86rf230_set_hw_addr_filt called for IEEE addr\n");
1231                 for (i = 0; i < 8; i++)
1232                         __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]);
1233         }
1234
1235         if (changed & IEEE802154_AFILT_PANC_CHANGED) {
1236                 dev_vdbg(&lp->spi->dev,
1237                          "at86rf230_set_hw_addr_filt called for panc change\n");
1238                 if (filt->pan_coord)
1239                         at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
1240                 else
1241                         at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
1242         }
1243
1244         return 0;
1245 }
1246
1247 #define AT86RF23X_MAX_TX_POWERS 0xF
1248 static const s32 at86rf233_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
1249         400, 370, 340, 300, 250, 200, 100, 0, -100, -200, -300, -400, -600,
1250         -800, -1200, -1700,
1251 };
1252
1253 static const s32 at86rf231_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
1254         300, 280, 230, 180, 130, 70, 0, -100, -200, -300, -400, -500, -700,
1255         -900, -1200, -1700,
1256 };
1257
1258 #define AT86RF212_MAX_TX_POWERS 0x1F
1259 static const s32 at86rf212_powers[AT86RF212_MAX_TX_POWERS + 1] = {
1260         500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
1261         -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
1262         -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
1263 };
1264
1265 static int
1266 at86rf23x_set_txpower(struct at86rf230_local *lp, s32 mbm)
1267 {
1268         u32 i;
1269
1270         for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
1271                 if (lp->hw->phy->supported.tx_powers[i] == mbm)
1272                         return at86rf230_write_subreg(lp, SR_TX_PWR_23X, i);
1273         }
1274
1275         return -EINVAL;
1276 }
1277
1278 static int
1279 at86rf212_set_txpower(struct at86rf230_local *lp, s32 mbm)
1280 {
1281         u32 i;
1282
1283         for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
1284                 if (lp->hw->phy->supported.tx_powers[i] == mbm)
1285                         return at86rf230_write_subreg(lp, SR_TX_PWR_212, i);
1286         }
1287
1288         return -EINVAL;
1289 }
1290
1291 static int
1292 at86rf230_set_txpower(struct ieee802154_hw *hw, s32 mbm)
1293 {
1294         struct at86rf230_local *lp = hw->priv;
1295
1296         return lp->data->set_txpower(lp, mbm);
1297 }
1298
1299 static int
1300 at86rf230_set_lbt(struct ieee802154_hw *hw, bool on)
1301 {
1302         struct at86rf230_local *lp = hw->priv;
1303
1304         return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on);
1305 }
1306
1307 static int
1308 at86rf230_set_cca_mode(struct ieee802154_hw *hw,
1309                        const struct wpan_phy_cca *cca)
1310 {
1311         struct at86rf230_local *lp = hw->priv;
1312         u8 val;
1313
1314         /* mapping 802.15.4 to driver spec */
1315         switch (cca->mode) {
1316         case NL802154_CCA_ENERGY:
1317                 val = 1;
1318                 break;
1319         case NL802154_CCA_CARRIER:
1320                 val = 2;
1321                 break;
1322         case NL802154_CCA_ENERGY_CARRIER:
1323                 switch (cca->opt) {
1324                 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
1325                         val = 3;
1326                         break;
1327                 case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
1328                         val = 0;
1329                         break;
1330                 default:
1331                         return -EINVAL;
1332                 }
1333                 break;
1334         default:
1335                 return -EINVAL;
1336         }
1337
1338         return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
1339 }
1340
1341
1342 static int
1343 at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
1344 {
1345         struct at86rf230_local *lp = hw->priv;
1346         u32 i;
1347
1348         for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
1349                 if (hw->phy->supported.cca_ed_levels[i] == mbm)
1350                         return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, i);
1351         }
1352
1353         return -EINVAL;
1354 }
1355
1356 static int
1357 at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
1358                           u8 retries)
1359 {
1360         struct at86rf230_local *lp = hw->priv;
1361         int rc;
1362
1363         rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be);
1364         if (rc)
1365                 return rc;
1366
1367         rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be);
1368         if (rc)
1369                 return rc;
1370
1371         return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries);
1372 }
1373
1374 static int
1375 at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
1376 {
1377         struct at86rf230_local *lp = hw->priv;
1378         int rc = 0;
1379
1380         lp->tx_aret = retries >= 0;
1381         lp->max_frame_retries = retries;
1382
1383         if (retries >= 0)
1384                 rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries);
1385
1386         return rc;
1387 }
1388
1389 static int
1390 at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
1391 {
1392         struct at86rf230_local *lp = hw->priv;
1393         int rc;
1394
1395         if (on) {
1396                 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1);
1397                 if (rc < 0)
1398                         return rc;
1399
1400                 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1);
1401                 if (rc < 0)
1402                         return rc;
1403         } else {
1404                 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0);
1405                 if (rc < 0)
1406                         return rc;
1407
1408                 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0);
1409                 if (rc < 0)
1410                         return rc;
1411         }
1412
1413         return 0;
1414 }
1415
1416 static const struct ieee802154_ops at86rf230_ops = {
1417         .owner = THIS_MODULE,
1418         .xmit_async = at86rf230_xmit,
1419         .ed = at86rf230_ed,
1420         .set_channel = at86rf230_channel,
1421         .start = at86rf230_start,
1422         .stop = at86rf230_stop,
1423         .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
1424         .set_txpower = at86rf230_set_txpower,
1425         .set_lbt = at86rf230_set_lbt,
1426         .set_cca_mode = at86rf230_set_cca_mode,
1427         .set_cca_ed_level = at86rf230_set_cca_ed_level,
1428         .set_csma_params = at86rf230_set_csma_params,
1429         .set_frame_retries = at86rf230_set_frame_retries,
1430         .set_promiscuous_mode = at86rf230_set_promiscuous_mode,
1431 };
1432
1433 static struct at86rf2xx_chip_data at86rf233_data = {
1434         .t_sleep_cycle = 330,
1435         .t_channel_switch = 11,
1436         .t_reset_to_off = 26,
1437         .t_off_to_aack = 80,
1438         .t_off_to_tx_on = 80,
1439         .t_frame = 4096,
1440         .t_p_ack = 545,
1441         .rssi_base_val = -91,
1442         .set_channel = at86rf23x_set_channel,
1443         .set_txpower = at86rf23x_set_txpower,
1444 };
1445
1446 static struct at86rf2xx_chip_data at86rf231_data = {
1447         .t_sleep_cycle = 330,
1448         .t_channel_switch = 24,
1449         .t_reset_to_off = 37,
1450         .t_off_to_aack = 110,
1451         .t_off_to_tx_on = 110,
1452         .t_frame = 4096,
1453         .t_p_ack = 545,
1454         .rssi_base_val = -91,
1455         .set_channel = at86rf23x_set_channel,
1456         .set_txpower = at86rf23x_set_txpower,
1457 };
1458
1459 static struct at86rf2xx_chip_data at86rf212_data = {
1460         .t_sleep_cycle = 330,
1461         .t_channel_switch = 11,
1462         .t_reset_to_off = 26,
1463         .t_off_to_aack = 200,
1464         .t_off_to_tx_on = 200,
1465         .t_frame = 4096,
1466         .t_p_ack = 545,
1467         .rssi_base_val = -100,
1468         .set_channel = at86rf212_set_channel,
1469         .set_txpower = at86rf212_set_txpower,
1470 };
1471
1472 static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
1473 {
1474         int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH;
1475         unsigned int dvdd;
1476         u8 csma_seed[2];
1477
1478         rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
1479         if (rc)
1480                 return rc;
1481
1482         irq_type = irq_get_trigger_type(lp->spi->irq);
1483         if (irq_type == IRQ_TYPE_EDGE_RISING ||
1484             irq_type == IRQ_TYPE_EDGE_FALLING)
1485                 dev_warn(&lp->spi->dev,
1486                          "Using edge triggered irq's are not recommended!\n");
1487         if (irq_type == IRQ_TYPE_EDGE_FALLING ||
1488             irq_type == IRQ_TYPE_LEVEL_LOW)
1489                 irq_pol = IRQ_ACTIVE_LOW;
1490
1491         rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol);
1492         if (rc)
1493                 return rc;
1494
1495         rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
1496         if (rc)
1497                 return rc;
1498
1499         rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
1500         if (rc)
1501                 return rc;
1502
1503         /* reset values differs in at86rf231 and at86rf233 */
1504         rc = at86rf230_write_subreg(lp, SR_IRQ_MASK_MODE, 0);
1505         if (rc)
1506                 return rc;
1507
1508         get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
1509         rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
1510         if (rc)
1511                 return rc;
1512         rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
1513         if (rc)
1514                 return rc;
1515
1516         /* CLKM changes are applied immediately */
1517         rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
1518         if (rc)
1519                 return rc;
1520
1521         /* Turn CLKM Off */
1522         rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
1523         if (rc)
1524                 return rc;
1525         /* Wait the next SLEEP cycle */
1526         usleep_range(lp->data->t_sleep_cycle,
1527                      lp->data->t_sleep_cycle + 100);
1528
1529         /* xtal_trim value is calculated by:
1530          * CL = 0.5 * (CX + CTRIM + CPAR)
1531          *
1532          * whereas:
1533          * CL = capacitor of used crystal
1534          * CX = connected capacitors at xtal pins
1535          * CPAR = in all at86rf2xx datasheets this is a constant value 3 pF,
1536          *        but this is different on each board setup. You need to fine
1537          *        tuning this value via CTRIM.
1538          * CTRIM = variable capacitor setting. Resolution is 0.3 pF range is
1539          *         0 pF upto 4.5 pF.
1540          *
1541          * Examples:
1542          * atben transceiver:
1543          *
1544          * CL = 8 pF
1545          * CX = 12 pF
1546          * CPAR = 3 pF (We assume the magic constant from datasheet)
1547          * CTRIM = 0.9 pF
1548          *
1549          * (12+0.9+3)/2 = 7.95 which is nearly at 8 pF
1550          *
1551          * xtal_trim = 0x3
1552          *
1553          * openlabs transceiver:
1554          *
1555          * CL = 16 pF
1556          * CX = 22 pF
1557          * CPAR = 3 pF (We assume the magic constant from datasheet)
1558          * CTRIM = 4.5 pF
1559          *
1560          * (22+4.5+3)/2 = 14.75 which is the nearest value to 16 pF
1561          *
1562          * xtal_trim = 0xf
1563          */
1564         rc = at86rf230_write_subreg(lp, SR_XTAL_TRIM, xtal_trim);
1565         if (rc)
1566                 return rc;
1567
1568         rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd);
1569         if (rc)
1570                 return rc;
1571         if (!dvdd) {
1572                 dev_err(&lp->spi->dev, "DVDD error\n");
1573                 return -EINVAL;
1574         }
1575
1576         /* Force setting slotted operation bit to 0. Sometimes the atben
1577          * sets this bit and I don't know why. We set this always force
1578          * to zero while probing.
1579          */
1580         return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0);
1581 }
1582
1583 static int
1584 at86rf230_get_pdata(struct spi_device *spi, int *rstn, int *slp_tr,
1585                     u8 *xtal_trim)
1586 {
1587         struct at86rf230_platform_data *pdata = spi->dev.platform_data;
1588         int ret;
1589
1590         if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) {
1591                 if (!pdata)
1592                         return -ENOENT;
1593
1594                 *rstn = pdata->rstn;
1595                 *slp_tr = pdata->slp_tr;
1596                 *xtal_trim = pdata->xtal_trim;
1597                 return 0;
1598         }
1599
1600         *rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0);
1601         *slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0);
1602         ret = of_property_read_u8(spi->dev.of_node, "xtal-trim", xtal_trim);
1603         if (ret < 0 && ret != -EINVAL)
1604                 return ret;
1605
1606         return 0;
1607 }
1608
1609 static int
1610 at86rf230_detect_device(struct at86rf230_local *lp)
1611 {
1612         unsigned int part, version, val;
1613         u16 man_id = 0;
1614         const char *chip;
1615         int rc;
1616
1617         rc = __at86rf230_read(lp, RG_MAN_ID_0, &val);
1618         if (rc)
1619                 return rc;
1620         man_id |= val;
1621
1622         rc = __at86rf230_read(lp, RG_MAN_ID_1, &val);
1623         if (rc)
1624                 return rc;
1625         man_id |= (val << 8);
1626
1627         rc = __at86rf230_read(lp, RG_PART_NUM, &part);
1628         if (rc)
1629                 return rc;
1630
1631         rc = __at86rf230_read(lp, RG_VERSION_NUM, &version);
1632         if (rc)
1633                 return rc;
1634
1635         if (man_id != 0x001f) {
1636                 dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1637                         man_id >> 8, man_id & 0xFF);
1638                 return -EINVAL;
1639         }
1640
1641         lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AACK |
1642                         IEEE802154_HW_CSMA_PARAMS |
1643                         IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
1644                         IEEE802154_HW_PROMISCUOUS;
1645
1646         lp->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
1647                              WPAN_PHY_FLAG_CCA_ED_LEVEL |
1648                              WPAN_PHY_FLAG_CCA_MODE;
1649
1650         lp->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1651                 BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
1652         lp->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
1653                 BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
1654
1655         lp->hw->phy->supported.cca_ed_levels = at86rf23x_ed_levels;
1656         lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf23x_ed_levels);
1657
1658         lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
1659
1660         switch (part) {
1661         case 2:
1662                 chip = "at86rf230";
1663                 rc = -ENOTSUPP;
1664                 goto not_supp;
1665         case 3:
1666                 chip = "at86rf231";
1667                 lp->data = &at86rf231_data;
1668                 lp->hw->phy->supported.channels[0] = 0x7FFF800;
1669                 lp->hw->phy->current_channel = 11;
1670                 lp->hw->phy->symbol_duration = 16;
1671                 lp->hw->phy->supported.tx_powers = at86rf231_powers;
1672                 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf231_powers);
1673                 break;
1674         case 7:
1675                 chip = "at86rf212";
1676                 lp->data = &at86rf212_data;
1677                 lp->hw->flags |= IEEE802154_HW_LBT;
1678                 lp->hw->phy->supported.channels[0] = 0x00007FF;
1679                 lp->hw->phy->supported.channels[2] = 0x00007FF;
1680                 lp->hw->phy->current_channel = 5;
1681                 lp->hw->phy->symbol_duration = 25;
1682                 lp->hw->phy->supported.lbt = NL802154_SUPPORTED_BOOL_BOTH;
1683                 lp->hw->phy->supported.tx_powers = at86rf212_powers;
1684                 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf212_powers);
1685                 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
1686                 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
1687                 break;
1688         case 11:
1689                 chip = "at86rf233";
1690                 lp->data = &at86rf233_data;
1691                 lp->hw->phy->supported.channels[0] = 0x7FFF800;
1692                 lp->hw->phy->current_channel = 13;
1693                 lp->hw->phy->symbol_duration = 16;
1694                 lp->hw->phy->supported.tx_powers = at86rf233_powers;
1695                 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf233_powers);
1696                 break;
1697         default:
1698                 chip = "unknown";
1699                 rc = -ENOTSUPP;
1700                 goto not_supp;
1701         }
1702
1703         lp->hw->phy->cca_ed_level = lp->hw->phy->supported.cca_ed_levels[7];
1704
1705 not_supp:
1706         dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
1707
1708         return rc;
1709 }
1710
1711 static void
1712 at86rf230_setup_spi_messages(struct at86rf230_local *lp)
1713 {
1714         lp->state.lp = lp;
1715         lp->state.irq = lp->spi->irq;
1716         spi_message_init(&lp->state.msg);
1717         lp->state.msg.context = &lp->state;
1718         lp->state.trx.len = 2;
1719         lp->state.trx.tx_buf = lp->state.buf;
1720         lp->state.trx.rx_buf = lp->state.buf;
1721         spi_message_add_tail(&lp->state.trx, &lp->state.msg);
1722         hrtimer_init(&lp->state.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1723         lp->state.timer.function = at86rf230_async_state_timer;
1724
1725         lp->irq.lp = lp;
1726         lp->irq.irq = lp->spi->irq;
1727         spi_message_init(&lp->irq.msg);
1728         lp->irq.msg.context = &lp->irq;
1729         lp->irq.trx.len = 2;
1730         lp->irq.trx.tx_buf = lp->irq.buf;
1731         lp->irq.trx.rx_buf = lp->irq.buf;
1732         spi_message_add_tail(&lp->irq.trx, &lp->irq.msg);
1733         hrtimer_init(&lp->irq.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1734         lp->irq.timer.function = at86rf230_async_state_timer;
1735
1736         lp->tx.lp = lp;
1737         lp->tx.irq = lp->spi->irq;
1738         spi_message_init(&lp->tx.msg);
1739         lp->tx.msg.context = &lp->tx;
1740         lp->tx.trx.len = 2;
1741         lp->tx.trx.tx_buf = lp->tx.buf;
1742         lp->tx.trx.rx_buf = lp->tx.buf;
1743         spi_message_add_tail(&lp->tx.trx, &lp->tx.msg);
1744         hrtimer_init(&lp->tx.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1745         lp->tx.timer.function = at86rf230_async_state_timer;
1746 }
1747
1748 static int at86rf230_probe(struct spi_device *spi)
1749 {
1750         struct ieee802154_hw *hw;
1751         struct at86rf230_local *lp;
1752         unsigned int status;
1753         int rc, irq_type, rstn, slp_tr;
1754         u8 xtal_trim = 0;
1755
1756         if (!spi->irq) {
1757                 dev_err(&spi->dev, "no IRQ specified\n");
1758                 return -EINVAL;
1759         }
1760
1761         rc = at86rf230_get_pdata(spi, &rstn, &slp_tr, &xtal_trim);
1762         if (rc < 0) {
1763                 dev_err(&spi->dev, "failed to parse platform_data: %d\n", rc);
1764                 return rc;
1765         }
1766
1767         if (gpio_is_valid(rstn)) {
1768                 rc = devm_gpio_request_one(&spi->dev, rstn,
1769                                            GPIOF_OUT_INIT_HIGH, "rstn");
1770                 if (rc)
1771                         return rc;
1772         }
1773
1774         if (gpio_is_valid(slp_tr)) {
1775                 rc = devm_gpio_request_one(&spi->dev, slp_tr,
1776                                            GPIOF_OUT_INIT_LOW, "slp_tr");
1777                 if (rc)
1778                         return rc;
1779         }
1780
1781         /* Reset */
1782         if (gpio_is_valid(rstn)) {
1783                 udelay(1);
1784                 gpio_set_value(rstn, 0);
1785                 udelay(1);
1786                 gpio_set_value(rstn, 1);
1787                 usleep_range(120, 240);
1788         }
1789
1790         hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops);
1791         if (!hw)
1792                 return -ENOMEM;
1793
1794         lp = hw->priv;
1795         lp->hw = hw;
1796         lp->spi = spi;
1797         lp->slp_tr = slp_tr;
1798         hw->parent = &spi->dev;
1799         hw->vif_data_size = sizeof(*lp);
1800         ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
1801
1802         lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config);
1803         if (IS_ERR(lp->regmap)) {
1804                 rc = PTR_ERR(lp->regmap);
1805                 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1806                         rc);
1807                 goto free_dev;
1808         }
1809
1810         at86rf230_setup_spi_messages(lp);
1811
1812         rc = at86rf230_detect_device(lp);
1813         if (rc < 0)
1814                 goto free_dev;
1815
1816         init_completion(&lp->state_complete);
1817
1818         spi_set_drvdata(spi, lp);
1819
1820         rc = at86rf230_hw_init(lp, xtal_trim);
1821         if (rc)
1822                 goto free_dev;
1823
1824         /* Read irq status register to reset irq line */
1825         rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
1826         if (rc)
1827                 goto free_dev;
1828
1829         irq_type = irq_get_trigger_type(spi->irq);
1830         if (!irq_type)
1831                 irq_type = IRQF_TRIGGER_RISING;
1832
1833         rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr,
1834                               IRQF_SHARED | irq_type, dev_name(&spi->dev), lp);
1835         if (rc)
1836                 goto free_dev;
1837
1838         rc = ieee802154_register_hw(lp->hw);
1839         if (rc)
1840                 goto free_dev;
1841
1842         return rc;
1843
1844 free_dev:
1845         ieee802154_free_hw(lp->hw);
1846
1847         return rc;
1848 }
1849
1850 static int at86rf230_remove(struct spi_device *spi)
1851 {
1852         struct at86rf230_local *lp = spi_get_drvdata(spi);
1853
1854         /* mask all at86rf230 irq's */
1855         at86rf230_write_subreg(lp, SR_IRQ_MASK, 0);
1856         ieee802154_unregister_hw(lp->hw);
1857         ieee802154_free_hw(lp->hw);
1858         dev_dbg(&spi->dev, "unregistered at86rf230\n");
1859
1860         return 0;
1861 }
1862
1863 static const struct of_device_id at86rf230_of_match[] = {
1864         { .compatible = "atmel,at86rf230", },
1865         { .compatible = "atmel,at86rf231", },
1866         { .compatible = "atmel,at86rf233", },
1867         { .compatible = "atmel,at86rf212", },
1868         { },
1869 };
1870 MODULE_DEVICE_TABLE(of, at86rf230_of_match);
1871
1872 static const struct spi_device_id at86rf230_device_id[] = {
1873         { .name = "at86rf230", },
1874         { .name = "at86rf231", },
1875         { .name = "at86rf233", },
1876         { .name = "at86rf212", },
1877         { },
1878 };
1879 MODULE_DEVICE_TABLE(spi, at86rf230_device_id);
1880
1881 static struct spi_driver at86rf230_driver = {
1882         .id_table = at86rf230_device_id,
1883         .driver = {
1884                 .of_match_table = of_match_ptr(at86rf230_of_match),
1885                 .name   = "at86rf230",
1886                 .owner  = THIS_MODULE,
1887         },
1888         .probe      = at86rf230_probe,
1889         .remove     = at86rf230_remove,
1890 };
1891
1892 module_spi_driver(at86rf230_driver);
1893
1894 MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1895 MODULE_LICENSE("GPL v2");