1 /******************************************************************************
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
6 * See the file "skfddi.c" for further information.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * The information in this file is provided "AS IS" without warranty.
15 ******************************************************************************/
18 static char const ID_sccs[] = "@(#)hwmtm.c 1.40 99/05/31 (C) SK" ;
30 #include "h/supern_2.h"
31 #include "h/skfbiinc.h"
34 -------------------------------------------------------------
36 -------------------------------------------------------------
37 BEGIN_MANUAL_ENTRY(DOCUMENTATION)
44 -------------------------------------------------------------
46 -------------------------------------------------------------
49 static SMbuf *mb_start = 0 ;
50 static SMbuf *mb_free = 0 ;
51 static int mb_init = FALSE ;
52 static int call_count = 0 ;
56 -------------------------------------------------------------
58 -------------------------------------------------------------
63 extern struct smt_debug debug ;
68 extern u_char offDepth ;
69 extern u_char force_irq_pending ;
73 -------------------------------------------------------------
75 -------------------------------------------------------------
78 static void queue_llc_rx(struct s_smc *smc, SMbuf *mb);
79 static void smt_to_llc(struct s_smc *smc, SMbuf *mb);
80 static void init_txd_ring(struct s_smc *smc);
81 static void init_rxd_ring(struct s_smc *smc);
82 static void queue_txd_mb(struct s_smc *smc, SMbuf *mb);
83 static u_long init_descr_ring(struct s_smc *smc, union s_fp_descr volatile *start,
85 static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue);
86 static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue);
87 static SMbuf* get_llc_rx(struct s_smc *smc);
88 static SMbuf* get_txd_mb(struct s_smc *smc);
89 static void mac_drv_clear_txd(struct s_smc *smc);
92 -------------------------------------------------------------
94 -------------------------------------------------------------
96 /* The external SMT functions are listed in cmtdef.h */
98 extern void* mac_drv_get_space(struct s_smc *smc, unsigned int size);
99 extern void* mac_drv_get_desc_mem(struct s_smc *smc, unsigned int size);
100 extern void mac_drv_fill_rxd(struct s_smc *smc);
101 extern void mac_drv_tx_complete(struct s_smc *smc,
102 volatile struct s_smt_fp_txd *txd);
103 extern void mac_drv_rx_complete(struct s_smc *smc,
104 volatile struct s_smt_fp_rxd *rxd,
105 int frag_count, int len);
106 extern void mac_drv_requeue_rxd(struct s_smc *smc,
107 volatile struct s_smt_fp_rxd *rxd,
109 extern void mac_drv_clear_rxd(struct s_smc *smc,
110 volatile struct s_smt_fp_rxd *rxd, int frag_count);
113 extern void hwm_cpy_rxd2mb(void);
114 extern void hwm_cpy_txd2mb(void);
117 #ifdef ALL_RX_COMPLETE
118 extern void mac_drv_all_receives_complete(void);
121 extern u_long mac_drv_virt2phys(struct s_smc *smc, void *virt);
122 extern u_long dma_master(struct s_smc *smc, void *virt, int len, int flag);
125 extern void post_proc(void);
127 extern void dma_complete(struct s_smc *smc, volatile union s_fp_descr *descr,
131 extern int mac_drv_rx_init(struct s_smc *smc, int len, int fc, char *look_ahead,
135 -------------------------------------------------------------
137 -------------------------------------------------------------
139 void process_receive(struct s_smc *smc);
140 void fddi_isr(struct s_smc *smc);
141 void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
142 void init_driver_fplus(struct s_smc *smc);
143 void mac_drv_rx_mode(struct s_smc *smc, int mode);
144 void init_fddi_driver(struct s_smc *smc, u_char *mac_addr);
145 void mac_drv_clear_tx_queue(struct s_smc *smc);
146 void mac_drv_clear_rx_queue(struct s_smc *smc);
147 void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
149 void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
152 int mac_drv_init(struct s_smc *smc);
153 int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
156 u_int mac_drv_check_space(void);
158 SMbuf* smt_get_mbuf(struct s_smc *smc);
161 void mac_drv_debug_lev(struct s_smc *smc, int flag, int lev);
165 -------------------------------------------------------------
167 -------------------------------------------------------------
171 #define UNUSED(x) (x) = (x)
178 #define MA smc->hw.fddi_canon_addr.a
179 #define GROUP_ADDR_BIT 0x01
181 #define MA smc->hw.fddi_home_addr.a
182 #define GROUP_ADDR_BIT 0x80
185 #define RXD_TXD_COUNT (HWM_ASYNC_TXD_COUNT+HWM_SYNC_TXD_COUNT+\
186 SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT)
188 #ifdef MB_OUTSIDE_SMC
189 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd) +\
190 MAX_MBUF*sizeof(SMbuf))
191 #define EXT_VIRT_MEM_2 ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
193 #define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
197 * define critical read for 16 Bit drivers
199 #if defined(NDIS_OS2) || defined(ODI2)
200 #define CR_READ(var) ((var) & 0xffff0000 | ((var) & 0xffff))
202 #define CR_READ(var) (__le32)(var)
205 #define IMASK_SLOW (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
206 IS_MINTR1 | IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
207 IS_R1_C | IS_XA_C | IS_XS_C)
210 -------------------------------------------------------------
211 INIT- AND SMT FUNCTIONS:
212 -------------------------------------------------------------
217 * BEGIN_MANUAL_ENTRY(mac_drv_check_space)
218 * u_int mac_drv_check_space()
220 * function DOWNCALL (drvsr.c)
221 * This function calculates the needed non virtual
222 * memory for MBufs, RxD and TxD descriptors etc.
223 * needed by the driver.
225 * return u_int memory in bytes
229 u_int mac_drv_check_space(void)
231 #ifdef MB_OUTSIDE_SMC
232 #ifdef COMMON_MB_POOL
234 if (call_count == 1) {
238 return EXT_VIRT_MEM_2;
249 * BEGIN_MANUAL_ENTRY(mac_drv_init)
250 * void mac_drv_init(smc)
252 * function DOWNCALL (drvsr.c)
253 * In this function the hardware module allocates it's
255 * The operating system dependent module should call
256 * mac_drv_init once, after the adatper is detected.
259 int mac_drv_init(struct s_smc *smc)
261 if (sizeof(struct s_smt_fp_rxd) % 16) {
262 SMT_PANIC(smc,HWM_E0001,HWM_E0001_MSG) ;
264 if (sizeof(struct s_smt_fp_txd) % 16) {
265 SMT_PANIC(smc,HWM_E0002,HWM_E0002_MSG) ;
269 * get the required memory for the RxDs and TxDs
271 if (!(smc->os.hwm.descr_p = (union s_fp_descr volatile *)
272 mac_drv_get_desc_mem(smc,(u_int)
273 (RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd)))) {
274 return 1; /* no space the hwm modul can't work */
278 * get the memory for the SMT MBufs
280 #ifndef MB_OUTSIDE_SMC
281 smc->os.hwm.mbuf_pool.mb_start=(SMbuf *)(&smc->os.hwm.mbuf_pool.mb[0]) ;
283 #ifndef COMMON_MB_POOL
284 if (!(smc->os.hwm.mbuf_pool.mb_start = (SMbuf *) mac_drv_get_space(smc,
285 MAX_MBUF*sizeof(SMbuf)))) {
286 return 1; /* no space the hwm modul can't work */
290 if (!(mb_start = (SMbuf *) mac_drv_get_space(smc,
291 MAX_MBUF*sizeof(SMbuf)))) {
292 return 1; /* no space the hwm modul can't work */
301 * BEGIN_MANUAL_ENTRY(init_driver_fplus)
302 * init_driver_fplus(smc)
304 * Sets hardware modul specific values for the mode register 2
305 * (e.g. the byte alignment for the received frames, the position of the
306 * least significant byte etc.)
309 void init_driver_fplus(struct s_smc *smc)
311 smc->hw.fp.mdr2init = FM_LSB | FM_BMMODE | FM_ENNPRQ | FM_ENHSRQ | 3 ;
314 smc->hw.fp.mdr2init |= FM_CHKPAR | FM_PARITY ;
316 smc->hw.fp.mdr3init = FM_MENRQAUNLCK | FM_MENRS ;
319 /* enable address bit swapping */
320 smc->hw.fp.frselreg_init = FM_ENXMTADSWAP | FM_ENRCVADSWAP ;
324 static u_long init_descr_ring(struct s_smc *smc,
325 union s_fp_descr volatile *start,
329 union s_fp_descr volatile *d1 ;
330 union s_fp_descr volatile *d2 ;
333 DB_GEN(3, "descr ring starts at = %p", start);
334 for (i=count-1, d1=start; i ; i--) {
336 d1++ ; /* descr is owned by the host */
337 d2->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
338 d2->r.rxd_next = &d1->r ;
339 phys = mac_drv_virt2phys(smc,(void *)d1) ;
340 d2->r.rxd_nrdadr = cpu_to_le32(phys) ;
342 DB_GEN(3, "descr ring ends at = %p", d1);
343 d1->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
344 d1->r.rxd_next = &start->r ;
345 phys = mac_drv_virt2phys(smc,(void *)start) ;
346 d1->r.rxd_nrdadr = cpu_to_le32(phys) ;
348 for (i=count, d1=start; i ; i--) {
349 DRV_BUF_FLUSH(&d1->r,DDI_DMA_SYNC_FORDEV) ;
355 static void init_txd_ring(struct s_smc *smc)
357 struct s_smt_fp_txd volatile *ds ;
358 struct s_smt_tx_queue *queue ;
362 * initialize the transmit descriptors
364 ds = (struct s_smt_fp_txd volatile *) ((char *)smc->os.hwm.descr_p +
365 SMT_R1_RXD_COUNT*sizeof(struct s_smt_fp_rxd)) ;
366 queue = smc->hw.fp.tx[QUEUE_A0] ;
367 DB_GEN(3, "Init async TxD ring, %d TxDs", HWM_ASYNC_TXD_COUNT);
368 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
369 HWM_ASYNC_TXD_COUNT) ;
370 phys = le32_to_cpu(ds->txd_ntdadr) ;
372 queue->tx_curr_put = queue->tx_curr_get = ds ;
374 queue->tx_free = HWM_ASYNC_TXD_COUNT ;
376 outpd(ADDR(B5_XA_DA),phys) ;
378 ds = (struct s_smt_fp_txd volatile *) ((char *)ds +
379 HWM_ASYNC_TXD_COUNT*sizeof(struct s_smt_fp_txd)) ;
380 queue = smc->hw.fp.tx[QUEUE_S] ;
381 DB_GEN(3, "Init sync TxD ring, %d TxDs", HWM_SYNC_TXD_COUNT);
382 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
383 HWM_SYNC_TXD_COUNT) ;
384 phys = le32_to_cpu(ds->txd_ntdadr) ;
386 queue->tx_curr_put = queue->tx_curr_get = ds ;
387 queue->tx_free = HWM_SYNC_TXD_COUNT ;
389 outpd(ADDR(B5_XS_DA),phys) ;
392 static void init_rxd_ring(struct s_smc *smc)
394 struct s_smt_fp_rxd volatile *ds ;
395 struct s_smt_rx_queue *queue ;
399 * initialize the receive descriptors
401 ds = (struct s_smt_fp_rxd volatile *) smc->os.hwm.descr_p ;
402 queue = smc->hw.fp.rx[QUEUE_R1] ;
403 DB_GEN(3, "Init RxD ring, %d RxDs", SMT_R1_RXD_COUNT);
404 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
406 phys = le32_to_cpu(ds->rxd_nrdadr) ;
408 queue->rx_curr_put = queue->rx_curr_get = ds ;
409 queue->rx_free = SMT_R1_RXD_COUNT ;
411 outpd(ADDR(B4_R1_DA),phys) ;
415 * BEGIN_MANUAL_ENTRY(init_fddi_driver)
416 * void init_fddi_driver(smc,mac_addr)
418 * initializes the driver and it's variables
422 void init_fddi_driver(struct s_smc *smc, u_char *mac_addr)
427 init_board(smc,mac_addr) ;
428 (void)init_fplus(smc) ;
431 * initialize the SMbufs for the SMT
433 #ifndef COMMON_MB_POOL
434 mb = smc->os.hwm.mbuf_pool.mb_start ;
435 smc->os.hwm.mbuf_pool.mb_free = (SMbuf *)NULL ;
436 for (i = 0; i < MAX_MBUF; i++) {
437 mb->sm_use_count = 1 ;
438 smt_free_mbuf(smc,mb) ;
445 for (i = 0; i < MAX_MBUF; i++) {
446 mb->sm_use_count = 1 ;
447 smt_free_mbuf(smc,mb) ;
455 * initialize the other variables
457 smc->os.hwm.llc_rx_pipe = smc->os.hwm.llc_rx_tail = (SMbuf *)NULL ;
458 smc->os.hwm.txd_tx_pipe = smc->os.hwm.txd_tx_tail = NULL ;
459 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = smc->os.hwm.pass_DB = 0 ;
460 smc->os.hwm.pass_llc_promisc = TRUE ;
461 smc->os.hwm.queued_rx_frames = smc->os.hwm.queued_txd_mb = 0 ;
462 smc->os.hwm.detec_count = 0 ;
463 smc->os.hwm.rx_break = 0 ;
464 smc->os.hwm.rx_len_error = 0 ;
465 smc->os.hwm.isr_flag = FALSE ;
468 * make sure that the start pointer is 16 byte aligned
470 i = 16 - ((long)smc->os.hwm.descr_p & 0xf) ;
472 DB_GEN(3, "i = %d", i);
473 smc->os.hwm.descr_p = (union s_fp_descr volatile *)
474 ((char *)smc->os.hwm.descr_p+i) ;
476 DB_GEN(3, "pt to descr area = %p", smc->os.hwm.descr_p);
480 mac_drv_fill_rxd(smc) ;
486 SMbuf *smt_get_mbuf(struct s_smc *smc)
490 #ifndef COMMON_MB_POOL
491 mb = smc->os.hwm.mbuf_pool.mb_free ;
496 #ifndef COMMON_MB_POOL
497 smc->os.hwm.mbuf_pool.mb_free = mb->sm_next ;
499 mb_free = mb->sm_next ;
502 mb->sm_use_count = 1 ;
504 DB_GEN(3, "get SMbuf: mb = %p", mb);
505 return mb; /* May be NULL */
508 void smt_free_mbuf(struct s_smc *smc, SMbuf *mb)
513 DB_GEN(3, "free_mbuf: sm_use_count = %d", mb->sm_use_count);
515 * If the use_count is != zero the MBuf is queued
516 * more than once and must not queued into the
519 if (!mb->sm_use_count) {
520 DB_GEN(3, "free SMbuf: mb = %p", mb);
521 #ifndef COMMON_MB_POOL
522 mb->sm_next = smc->os.hwm.mbuf_pool.mb_free ;
523 smc->os.hwm.mbuf_pool.mb_free = mb ;
525 mb->sm_next = mb_free ;
531 SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ;
536 * BEGIN_MANUAL_ENTRY(mac_drv_repair_descr)
537 * void mac_drv_repair_descr(smc)
539 * function called from SMT (HWM / hwmtm.c)
540 * The BMU is idle when this function is called.
541 * Mac_drv_repair_descr sets up the physical address
542 * for all receive and transmit queues where the BMU
544 * It may be that the BMU was reseted during a fragmented
545 * transfer. In this case there are some fragments which will
546 * never completed by the BMU. The OWN bit of this fragments
547 * must be switched to be owned by the host.
549 * Give a start command to the receive BMU.
550 * Start the transmit BMUs if transmit frames pending.
554 void mac_drv_repair_descr(struct s_smc *smc)
558 if (smc->hw.hw_state != STOPPED) {
560 SMT_PANIC(smc,HWM_E0013,HWM_E0013_MSG) ;
565 * repair tx queues: don't start
567 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_A0]) ;
568 outpd(ADDR(B5_XA_DA),phys) ;
569 if (smc->hw.fp.tx_q[QUEUE_A0].tx_used) {
570 outpd(ADDR(B0_XA_CSR),CSR_START) ;
572 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_S]) ;
573 outpd(ADDR(B5_XS_DA),phys) ;
574 if (smc->hw.fp.tx_q[QUEUE_S].tx_used) {
575 outpd(ADDR(B0_XS_CSR),CSR_START) ;
581 phys = repair_rxd_ring(smc,smc->hw.fp.rx[QUEUE_R1]) ;
582 outpd(ADDR(B4_R1_DA),phys) ;
583 outpd(ADDR(B0_R1_CSR),CSR_START) ;
586 static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue)
592 struct s_smt_fp_txd volatile *t ;
596 t = queue->tx_curr_get ;
597 tx_used = queue->tx_used ;
598 for (i = tx_used+queue->tx_free-1 ; i ; i-- ) {
601 phys = le32_to_cpu(t->txd_ntdadr) ;
603 t = queue->tx_curr_get ;
605 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
606 tbctrl = le32_to_cpu(t->txd_tbctrl) ;
608 if (tbctrl & BMU_OWN) {
609 if (tbctrl & BMU_STF) {
610 break ; /* exit the loop */
614 * repair the descriptor
616 t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
619 phys = le32_to_cpu(t->txd_ntdadr) ;
620 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
628 * Repairs the receive descriptor ring and returns the physical address
629 * where the BMU should continue working.
631 * o The physical address where the BMU was stopped has to be
632 * determined. This is the next RxD after rx_curr_get with an OWN
634 * o The BMU should start working at beginning of the next frame.
635 * RxDs with an OWN bit set but with a reset STF bit should be
636 * skipped and owned by the driver (OWN = 0).
638 static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue)
644 struct s_smt_fp_rxd volatile *r ;
648 r = queue->rx_curr_get ;
649 rx_used = queue->rx_used ;
650 for (i = SMT_R1_RXD_COUNT-1 ; i ; i-- ) {
653 phys = le32_to_cpu(r->rxd_nrdadr) ;
655 r = queue->rx_curr_get ;
657 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
658 rbctrl = le32_to_cpu(r->rxd_rbctrl) ;
660 if (rbctrl & BMU_OWN) {
661 if (rbctrl & BMU_STF) {
662 break ; /* exit the loop */
666 * repair the descriptor
668 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
671 phys = le32_to_cpu(r->rxd_nrdadr) ;
672 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
681 -------------------------------------------------------------
682 INTERRUPT SERVICE ROUTINE:
683 -------------------------------------------------------------
687 * BEGIN_MANUAL_ENTRY(fddi_isr)
690 * function DOWNCALL (drvsr.c)
691 * interrupt service routine, handles the interrupt requests
692 * generated by the FDDI adapter.
694 * NOTE: The operating system dependent module must guarantee that the
695 * interrupts of the adapter are disabled when it calls fddi_isr.
697 * About the USE_BREAK_ISR mechanismn:
699 * The main requirement of this mechanismn is to force an timer IRQ when
700 * leaving process_receive() with leave_isr set. process_receive() may
701 * be called at any time from anywhere!
702 * To be sure we don't miss such event we set 'force_irq' per default.
703 * We have to force and Timer IRQ if 'smc->os.hwm.leave_isr' AND
704 * 'force_irq' are set. 'force_irq' may be reset if a receive complete
709 void fddi_isr(struct s_smc *smc)
711 u_long is ; /* ISR source */
720 if (smc->os.hwm.rx_break) {
721 mac_drv_fill_rxd(smc) ;
722 if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
723 smc->os.hwm.rx_break = 0 ;
724 process_receive(smc) ;
727 smc->os.hwm.detec_count = 0 ;
732 smc->os.hwm.isr_flag = TRUE ;
736 if (smc->os.hwm.leave_isr) {
737 smc->os.hwm.leave_isr = FALSE ;
738 process_receive(smc) ;
742 while ((is = GET_ISR() & ISR_MASK)) {
743 NDD_TRACE("CH0B",is,0,0) ;
744 DB_GEN(7, "ISA = 0x%lx", is);
746 if (is & IMASK_SLOW) {
747 NDD_TRACE("CH1b",is,0,0) ;
748 if (is & IS_PLINT1) { /* PLC1 */
751 if (is & IS_PLINT2) { /* PLC2 */
754 if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
755 stu = inpw(FM_A(FM_ST1U)) ;
756 stl = inpw(FM_A(FM_ST1L)) ;
757 DB_GEN(6, "Slow transmit complete");
758 mac1_irq(smc,stu,stl) ;
760 if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
761 stu= inpw(FM_A(FM_ST2U)) ;
762 stl= inpw(FM_A(FM_ST2L)) ;
763 DB_GEN(6, "Slow receive complete");
764 DB_GEN(7, "stl = %x : stu = %x", stl, stu);
765 mac2_irq(smc,stu,stl) ;
767 if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
768 stu= inpw(FM_A(FM_ST3U)) ;
769 stl= inpw(FM_A(FM_ST3L)) ;
770 DB_GEN(6, "FORMAC Mode Register 3");
771 mac3_irq(smc,stu,stl) ;
773 if (is & IS_TIMINT) { /* Timer 82C54-2 */
776 force_irq_pending = 0 ;
779 * out of RxD detection
781 if (++smc->os.hwm.detec_count > 4) {
783 * check out of RxD condition
785 process_receive(smc) ;
788 if (is & IS_TOKEN) { /* Restricted Token Monitor */
791 if (is & IS_R1_P) { /* Parity error rx queue 1 */
793 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
794 SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
796 if (is & IS_R1_C) { /* Encoding error rx queue 1 */
798 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
799 SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
801 if (is & IS_XA_C) { /* Encoding error async tx q */
803 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
804 SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
806 if (is & IS_XS_C) { /* Encoding error sync tx q */
808 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
809 SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
814 * Fast Tx complete Async/Sync Queue (BMU service)
816 if (is & (IS_XS_F|IS_XA_F)) {
817 DB_GEN(6, "Fast tx complete queue");
819 * clear IRQ, Note: no IRQ is lost, because
820 * we always service both queues
822 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
823 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
824 mac_drv_clear_txd(smc) ;
825 llc_restart_tx(smc) ;
829 * Fast Rx Complete (BMU service)
832 DB_GEN(6, "Fast receive complete");
834 #ifndef USE_BREAK_ISR
835 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
836 process_receive(smc) ;
838 process_receive(smc) ;
839 if (smc->os.hwm.leave_isr) {
842 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
843 process_receive(smc) ;
849 while ((mb = get_llc_rx(smc))) {
856 while (!offDepth && (mb = get_llc_rx(smc))) {
860 if (!offDepth && smc->os.hwm.rx_break) {
861 process_receive(smc) ;
864 if (smc->q.ev_get != smc->q.ev_put) {
865 NDD_TRACE("CH2a",0,0,0) ;
870 if (offDepth) { /* leave fddi_isr because */
871 break ; /* indications not allowed */
875 if (smc->os.hwm.leave_isr) {
876 break ; /* leave fddi_isr */
880 /* NOTE: when the isr is left, no rx is pending */
881 } /* end of interrupt source polling loop */
884 if (smc->os.hwm.leave_isr && force_irq) {
888 smc->os.hwm.isr_flag = FALSE ;
889 NDD_TRACE("CH0E",0,0,0) ;
894 -------------------------------------------------------------
896 -------------------------------------------------------------
901 * BEGIN_MANUAL_ENTRY(mac_drv_rx_mode)
902 * void mac_drv_rx_mode(smc,mode)
904 * function DOWNCALL (fplus.c)
905 * Corresponding to the parameter mode, the operating system
906 * dependent module can activate several receive modes.
908 * para mode = 1: RX_ENABLE_ALLMULTI enable all multicasts
909 * = 2: RX_DISABLE_ALLMULTI disable "enable all multicasts"
910 * = 3: RX_ENABLE_PROMISC enable promiscuous
911 * = 4: RX_DISABLE_PROMISC disable promiscuous
912 * = 5: RX_ENABLE_NSA enable rec. of all NSA frames
913 * (disabled after 'driver reset' & 'set station address')
914 * = 6: RX_DISABLE_NSA disable rec. of all NSA frames
916 * = 21: RX_ENABLE_PASS_SMT ( see description )
917 * = 22: RX_DISABLE_PASS_SMT ( " " )
918 * = 23: RX_ENABLE_PASS_NSA ( " " )
919 * = 24: RX_DISABLE_PASS_NSA ( " " )
920 * = 25: RX_ENABLE_PASS_DB ( " " )
921 * = 26: RX_DISABLE_PASS_DB ( " " )
922 * = 27: RX_DISABLE_PASS_ALL ( " " )
923 * = 28: RX_DISABLE_LLC_PROMISC ( " " )
924 * = 29: RX_ENABLE_LLC_PROMISC ( " " )
927 * RX_ENABLE_PASS_SMT / RX_DISABLE_PASS_SMT
929 * If the operating system dependent module activates the
930 * mode RX_ENABLE_PASS_SMT, the hardware module
931 * duplicates all SMT frames with the frame control
932 * FC_SMT_INFO and passes them to the LLC receive channel
933 * by calling mac_drv_rx_init.
934 * The SMT Frames which are sent by the local SMT and the NSA
935 * frames whose A- and C-Indicator is not set are also duplicated
937 * The receive mode RX_DISABLE_PASS_SMT disables the passing
940 * RX_ENABLE_PASS_NSA / RX_DISABLE_PASS_NSA
942 * If the operating system dependent module activates the
943 * mode RX_ENABLE_PASS_NSA, the hardware module
944 * duplicates all NSA frames with frame control FC_SMT_NSA
945 * and a set A-Indicator and passed them to the LLC
946 * receive channel by calling mac_drv_rx_init.
947 * All NSA Frames which are sent by the local SMT
948 * are also duplicated and passed.
949 * The receive mode RX_DISABLE_PASS_NSA disables the passing
950 * of NSA frames with the A- or C-Indicator set.
952 * NOTE: For fear that the hardware module receives NSA frames with
953 * a reset A-Indicator, the operating system dependent module
954 * has to call mac_drv_rx_mode with the mode RX_ENABLE_NSA
955 * before activate the RX_ENABLE_PASS_NSA mode and after every
956 * 'driver reset' and 'set station address'.
958 * RX_ENABLE_PASS_DB / RX_DISABLE_PASS_DB
960 * If the operating system dependent module activates the
961 * mode RX_ENABLE_PASS_DB, direct BEACON frames
962 * (FC_BEACON frame control) are passed to the LLC receive
963 * channel by mac_drv_rx_init.
964 * The receive mode RX_DISABLE_PASS_DB disables the passing
965 * of direct BEACON frames.
967 * RX_DISABLE_PASS_ALL
969 * Disables all special receives modes. It is equal to
970 * call mac_drv_set_rx_mode successively with the
971 * parameters RX_DISABLE_NSA, RX_DISABLE_PASS_SMT,
972 * RX_DISABLE_PASS_NSA and RX_DISABLE_PASS_DB.
974 * RX_ENABLE_LLC_PROMISC
976 * (default) all received LLC frames and all SMT/NSA/DBEACON
977 * frames depending on the attitude of the flags
978 * PASS_SMT/PASS_NSA/PASS_DBEACON will be delivered to the
981 * RX_DISABLE_LLC_PROMISC
983 * all received SMT/NSA/DBEACON frames depending on the
984 * attitude of the flags PASS_SMT/PASS_NSA/PASS_DBEACON
985 * will be delivered to the LLC layer.
986 * all received LLC frames with a directed address, Multicast
987 * or Broadcast address will be delivered to the LLC
992 void mac_drv_rx_mode(struct s_smc *smc, int mode)
995 case RX_ENABLE_PASS_SMT:
996 smc->os.hwm.pass_SMT = TRUE ;
998 case RX_DISABLE_PASS_SMT:
999 smc->os.hwm.pass_SMT = FALSE ;
1001 case RX_ENABLE_PASS_NSA:
1002 smc->os.hwm.pass_NSA = TRUE ;
1004 case RX_DISABLE_PASS_NSA:
1005 smc->os.hwm.pass_NSA = FALSE ;
1007 case RX_ENABLE_PASS_DB:
1008 smc->os.hwm.pass_DB = TRUE ;
1010 case RX_DISABLE_PASS_DB:
1011 smc->os.hwm.pass_DB = FALSE ;
1013 case RX_DISABLE_PASS_ALL:
1014 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = FALSE ;
1015 smc->os.hwm.pass_DB = FALSE ;
1016 smc->os.hwm.pass_llc_promisc = TRUE ;
1017 mac_set_rx_mode(smc,RX_DISABLE_NSA) ;
1019 case RX_DISABLE_LLC_PROMISC:
1020 smc->os.hwm.pass_llc_promisc = FALSE ;
1022 case RX_ENABLE_LLC_PROMISC:
1023 smc->os.hwm.pass_llc_promisc = TRUE ;
1025 case RX_ENABLE_ALLMULTI:
1026 case RX_DISABLE_ALLMULTI:
1027 case RX_ENABLE_PROMISC:
1028 case RX_DISABLE_PROMISC:
1030 case RX_DISABLE_NSA:
1032 mac_set_rx_mode(smc,mode) ;
1036 #endif /* ifndef NDIS_OS2 */
1039 * process receive queue
1041 void process_receive(struct s_smc *smc)
1045 int frag_count ; /* number of RxDs of the curr rx buf */
1046 int used_frags ; /* number of RxDs of the curr frame */
1047 struct s_smt_rx_queue *queue ; /* points to the queue ctl struct */
1048 struct s_smt_fp_rxd volatile *r ; /* rxd pointer */
1049 struct s_smt_fp_rxd volatile *rxd ; /* first rxd of rx frame */
1050 u_long rbctrl ; /* receive buffer control word */
1051 u_long rfsw ; /* receive frame status word */
1056 u_char fc ; /* Frame control */
1057 int len ; /* Frame length */
1059 smc->os.hwm.detec_count = 0 ;
1060 queue = smc->hw.fp.rx[QUEUE_R1] ;
1061 NDD_TRACE("RHxB",0,0,0) ;
1063 r = queue->rx_curr_get ;
1064 rx_used = queue->rx_used ;
1067 #ifdef USE_BREAK_ISR
1068 if (smc->os.hwm.leave_isr) {
1074 smc->os.hwm.rx_break = 1 ;
1077 smc->os.hwm.rx_break = 0 ;
1080 if (smc->os.hwm.rx_break) {
1086 DB_RX(5, "Check RxD %p for OWN and EOF", r);
1087 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1088 rbctrl = le32_to_cpu(CR_READ(r->rxd_rbctrl));
1090 if (rbctrl & BMU_OWN) {
1091 NDD_TRACE("RHxE",r,rfsw,rbctrl) ;
1092 DB_RX(4, "End of RxDs");
1096 * out of RxD detection
1100 SMT_PANIC(smc,HWM_E0009,HWM_E0009_MSG) ;
1101 /* Either we don't have an RxD or all
1102 * RxDs are filled. Therefore it's allowed
1103 * for to set the STOPPED flag */
1104 smc->hw.hw_state = STOPPED ;
1105 mac_drv_clear_rx_queue(smc) ;
1106 smc->hw.hw_state = STARTED ;
1107 mac_drv_fill_rxd(smc) ;
1108 smc->os.hwm.detec_count = 0 ;
1111 rfsw = le32_to_cpu(r->rxd_rfsw) ;
1112 if ((rbctrl & BMU_STF) != ((rbctrl & BMU_ST_BUF) <<5)) {
1114 * The BMU_STF bit is deleted, 1 frame is
1115 * placed into more than 1 rx buffer
1117 * skip frame by setting the rx len to 0
1119 * if fragment count == 0
1120 * The missing STF bit belongs to the
1121 * current frame, search for the
1122 * EOF bit to complete the frame
1124 * the fragment belongs to the next frame,
1125 * exit the loop and process the frame
1133 n += rbctrl & 0xffff ;
1137 } while (!(rbctrl & BMU_EOF)) ;
1138 used_frags = frag_count ;
1139 DB_RX(5, "EOF set in RxD, used_frags = %d", used_frags);
1141 /* may be next 2 DRV_BUF_FLUSH() can be skipped, because */
1142 /* BMU_ST_BUF will not be changed by the ASIC */
1143 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1144 while (rx_used && !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
1145 DB_RX(5, "Check STF bit in %p", r);
1147 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1151 DB_RX(5, "STF bit found");
1154 * The received frame is finished for the process receive
1156 rxd = queue->rx_curr_get ;
1157 queue->rx_curr_get = r ;
1158 queue->rx_free += frag_count ;
1159 queue->rx_used = rx_used ;
1162 * ASIC Errata no. 7 (STF - Bit Bug)
1164 rxd->rxd_rbctrl &= cpu_to_le32(~BMU_STF) ;
1166 for (r=rxd, i=frag_count ; i ; r=r->rxd_next, i--){
1167 DB_RX(5, "dma_complete for RxD %p", r);
1168 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1170 smc->hw.fp.err_stats.err_valid++ ;
1171 smc->mib.m[MAC0].fddiMACCopied_Ct++ ;
1173 /* the length of the data including the FC */
1174 len = (rfsw & RD_LENGTH) - 4 ;
1176 DB_RX(4, "frame length = %d", len);
1178 * check the frame_length and all error flags
1180 if (rfsw & (RX_MSRABT|RX_FS_E|RX_FS_CRC|RX_FS_IMPL)){
1181 if (rfsw & RD_S_MSRABT) {
1182 DB_RX(2, "Frame aborted by the FORMAC");
1183 smc->hw.fp.err_stats.err_abort++ ;
1186 * check frame status
1188 if (rfsw & RD_S_SEAC2) {
1189 DB_RX(2, "E-Indicator set");
1190 smc->hw.fp.err_stats.err_e_indicator++ ;
1192 if (rfsw & RD_S_SFRMERR) {
1193 DB_RX(2, "CRC error");
1194 smc->hw.fp.err_stats.err_crc++ ;
1196 if (rfsw & RX_FS_IMPL) {
1197 DB_RX(2, "Implementer frame");
1198 smc->hw.fp.err_stats.err_imp_frame++ ;
1202 if (len > FDDI_RAW_MTU-4) {
1203 DB_RX(2, "Frame too long error");
1204 smc->hw.fp.err_stats.err_too_long++ ;
1208 * SUPERNET 3 Bug: FORMAC delivers status words
1209 * of aborded frames to the BMU
1212 DB_RX(2, "Frame length = 0");
1217 DB_RX(4, "BMU: rx len differs: [%d:%d]", len, n);
1218 smc->os.hwm.rx_len_error++ ;
1225 virt = (u_char far *) rxd->rxd_virt ;
1226 DB_RX(2, "FC = %x", *virt);
1227 if (virt[12] == MA[5] &&
1228 virt[11] == MA[4] &&
1229 virt[10] == MA[3] &&
1232 (virt[7] & ~GROUP_ADDR_BIT) == MA[0]) {
1239 if (rfsw & RX_FS_LLC) {
1241 * if pass_llc_promisc is disable
1242 * if DA != Multicast or Broadcast or DA!=MA
1245 if (!smc->os.hwm.pass_llc_promisc) {
1246 if(!(virt[1] & GROUP_ADDR_BIT)) {
1247 if (virt[6] != MA[5] ||
1253 DB_RX(2, "DA != MA and not multi- or broadcast");
1260 * LLC frame received
1262 DB_RX(4, "LLC - receive");
1263 mac_drv_rx_complete(smc,rxd,frag_count,len) ;
1266 if (!(mb = smt_get_mbuf(smc))) {
1267 smc->hw.fp.err_stats.err_no_buf++ ;
1268 DB_RX(4, "No SMbuf; receive terminated");
1271 data = smtod(mb,char *) - 1 ;
1274 * copy the frame into a SMT_MBuf
1277 hwm_cpy_rxd2mb(rxd,data,len) ;
1279 for (r=rxd, i=used_frags ; i ; r=r->rxd_next, i--){
1280 n = le32_to_cpu(r->rxd_rbctrl) & RD_LENGTH ;
1281 DB_RX(6, "cp SMT frame to mb: len = %d", n);
1282 memcpy(data,r->rxd_virt,n) ;
1285 data = smtod(mb,char *) - 1 ;
1287 fc = *(char *)mb->sm_data = *data ;
1288 mb->sm_len = len - 1 ; /* len - fc */
1292 * SMT frame received
1296 smc->hw.fp.err_stats.err_smt_frame++ ;
1297 DB_RX(5, "SMT frame received");
1299 if (smc->os.hwm.pass_SMT) {
1300 DB_RX(5, "pass SMT frame");
1301 mac_drv_rx_complete(smc, rxd,
1305 DB_RX(5, "requeue RxD");
1306 mac_drv_requeue_rxd(smc,rxd,frag_count);
1309 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1312 smc->hw.fp.err_stats.err_smt_frame++ ;
1313 DB_RX(5, "SMT frame received");
1315 /* if pass_NSA set pass the NSA frame or */
1316 /* pass_SMT set and the A-Indicator */
1317 /* is not set, pass the NSA frame */
1318 if (smc->os.hwm.pass_NSA ||
1319 (smc->os.hwm.pass_SMT &&
1320 !(rfsw & A_INDIC))) {
1321 DB_RX(5, "pass SMT frame");
1322 mac_drv_rx_complete(smc, rxd,
1326 DB_RX(5, "requeue RxD");
1327 mac_drv_requeue_rxd(smc,rxd,frag_count);
1330 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1333 if (smc->os.hwm.pass_DB) {
1334 DB_RX(5, "pass DB frame");
1335 mac_drv_rx_complete(smc, rxd,
1339 DB_RX(5, "requeue RxD");
1340 mac_drv_requeue_rxd(smc,rxd,frag_count);
1342 smt_free_mbuf(smc,mb) ;
1346 * unknown FC abord the frame
1348 DB_RX(2, "unknown FC error");
1349 smt_free_mbuf(smc,mb) ;
1350 DB_RX(5, "requeue RxD");
1351 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1352 if ((fc & 0xf0) == FC_MAC)
1353 smc->hw.fp.err_stats.err_mac_frame++ ;
1355 smc->hw.fp.err_stats.err_imp_frame++ ;
1361 DB_RX(3, "next RxD is %p", queue->rx_curr_get);
1362 NDD_TRACE("RHx1",queue->rx_curr_get,0,0) ;
1365 /*--------------------------------------------------------------------*/
1367 DB_RX(5, "requeue RxD");
1368 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1370 DB_RX(3, "next RxD is %p", queue->rx_curr_get);
1371 NDD_TRACE("RHx2",queue->rx_curr_get,0,0) ;
1374 #ifdef ALL_RX_COMPLETE
1375 mac_drv_all_receives_complete(smc) ;
1377 return ; /* lint bug: needs return detect end of function */
1380 static void smt_to_llc(struct s_smc *smc, SMbuf *mb)
1384 DB_RX(4, "send a queued frame to the llc layer");
1385 smc->os.hwm.r.len = mb->sm_len ;
1386 smc->os.hwm.r.mb_pos = smtod(mb,char *) ;
1387 fc = *smc->os.hwm.r.mb_pos ;
1388 (void)mac_drv_rx_init(smc,(int)mb->sm_len,(int)fc,
1389 smc->os.hwm.r.mb_pos,(int)mb->sm_len) ;
1390 smt_free_mbuf(smc,mb) ;
1394 * BEGIN_MANUAL_ENTRY(hwm_rx_frag)
1395 * void hwm_rx_frag(smc,virt,phys,len,frame_status)
1397 * function MACRO (hardware module, hwmtm.h)
1398 * This function calls dma_master for preparing the
1399 * system hardware for the DMA transfer and initializes
1400 * the current RxD with the length and the physical and
1401 * virtual address of the fragment. Furthermore, it sets the
1402 * STF and EOF bits depending on the frame status byte,
1403 * switches the OWN flag of the RxD, so that it is owned by the
1404 * adapter and issues an rx_start.
1406 * para virt virtual pointer to the fragment
1407 * len the length of the fragment
1408 * frame_status status of the frame, see design description
1410 * NOTE: It is possible to call this function with a fragment length
1415 void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1418 struct s_smt_fp_rxd volatile *r ;
1421 NDD_TRACE("RHfB",virt,len,frame_status) ;
1422 DB_RX(2, "hwm_rx_frag: len = %d, frame_status = %x", len, frame_status);
1423 r = smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put ;
1424 r->rxd_virt = virt ;
1425 r->rxd_rbadr = cpu_to_le32(phys) ;
1426 rbctrl = cpu_to_le32( (((__u32)frame_status &
1427 (FIRST_FRAG|LAST_FRAG))<<26) |
1428 (((u_long) frame_status & FIRST_FRAG) << 21) |
1429 BMU_OWN | BMU_CHECK | BMU_EN_IRQ_EOF | len) ;
1430 r->rxd_rbctrl = rbctrl ;
1432 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1433 outpd(ADDR(B0_R1_CSR),CSR_START) ;
1434 smc->hw.fp.rx_q[QUEUE_R1].rx_free-- ;
1435 smc->hw.fp.rx_q[QUEUE_R1].rx_used++ ;
1436 smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put = r->rxd_next ;
1437 NDD_TRACE("RHfE",r,le32_to_cpu(r->rxd_rbadr),0) ;
1441 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue)
1443 * void mac_drv_clear_rx_queue(smc)
1444 * struct s_smc *smc ;
1446 * function DOWNCALL (hardware module, hwmtm.c)
1447 * mac_drv_clear_rx_queue is called by the OS-specific module
1448 * after it has issued a card_stop.
1449 * In this case, the frames in the receive queue are obsolete and
1450 * should be removed. For removing mac_drv_clear_rx_queue
1451 * calls dma_master for each RxD and mac_drv_clear_rxd for each
1454 * NOTE: calling sequence card_stop:
1455 * CLI_FBI(), card_stop(),
1456 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
1458 * NOTE: The caller is responsible that the BMUs are idle
1459 * when this function is called.
1463 void mac_drv_clear_rx_queue(struct s_smc *smc)
1465 struct s_smt_fp_rxd volatile *r ;
1466 struct s_smt_fp_rxd volatile *next_rxd ;
1467 struct s_smt_rx_queue *queue ;
1471 if (smc->hw.hw_state != STOPPED) {
1473 SMT_PANIC(smc,HWM_E0012,HWM_E0012_MSG) ;
1477 queue = smc->hw.fp.rx[QUEUE_R1] ;
1478 DB_RX(5, "clear_rx_queue");
1481 * dma_complete and mac_drv_clear_rxd for all RxDs / receive buffers
1483 r = queue->rx_curr_get ;
1484 while (queue->rx_used) {
1485 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1486 DB_RX(5, "switch OWN bit of RxD 0x%p", r);
1487 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
1489 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1491 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1492 while (r != queue->rx_curr_put &&
1493 !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
1494 DB_RX(5, "Check STF bit in %p", r);
1495 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
1496 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1498 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1501 DB_RX(5, "STF bit found");
1504 for (r=queue->rx_curr_get,i=frag_count; i ; r=r->rxd_next,i--){
1505 DB_RX(5, "dma_complete for RxD %p", r);
1506 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1509 DB_RX(5, "mac_drv_clear_rxd: RxD %p frag_count %d",
1510 queue->rx_curr_get, frag_count);
1511 mac_drv_clear_rxd(smc,queue->rx_curr_get,frag_count) ;
1513 queue->rx_curr_get = next_rxd ;
1514 queue->rx_used -= frag_count ;
1515 queue->rx_free += frag_count ;
1521 -------------------------------------------------------------
1523 -------------------------------------------------------------
1527 * BEGIN_MANUAL_ENTRY(hwm_tx_init)
1528 * int hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)
1530 * function DOWN_CALL (hardware module, hwmtm.c)
1531 * hwm_tx_init checks if the frame can be sent through the
1532 * corresponding send queue.
1534 * para fc the frame control. To determine through which
1535 * send queue the frame should be transmitted.
1536 * 0x50 - 0x57: asynchronous LLC frame
1537 * 0xD0 - 0xD7: synchronous LLC frame
1538 * 0x41, 0x4F: SMT frame to the network
1539 * 0x42: SMT frame to the network and to the local SMT
1540 * 0x43: SMT frame to the local SMT
1541 * frag_count count of the fragments for this frame
1542 * frame_len length of the frame
1543 * frame_status status of the frame, the send queue bit is already
1546 * return frame_status
1550 int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
1553 NDD_TRACE("THiB",fc,frag_count,frame_len) ;
1554 smc->os.hwm.tx_p = smc->hw.fp.tx[frame_status & QUEUE_A0] ;
1555 smc->os.hwm.tx_descr = TX_DESCRIPTOR | (((u_long)(frame_len-1)&3)<<27) ;
1556 smc->os.hwm.tx_len = frame_len ;
1557 DB_TX(3, "hwm_tx_init: fc = %x, len = %d", fc, frame_len);
1558 if ((fc & ~(FC_SYNC_BIT|FC_LLC_PRIOR)) == FC_ASYNC_LLC) {
1559 frame_status |= LAN_TX ;
1565 frame_status |= LAN_TX ;
1568 frame_status |= LOC_TX ;
1570 case FC_SMT_LAN_LOC :
1571 frame_status |= LAN_TX | LOC_TX ;
1574 SMT_PANIC(smc,HWM_E0010,HWM_E0010_MSG) ;
1577 if (!smc->hw.mac_ring_is_up) {
1578 frame_status &= ~LAN_TX ;
1579 frame_status |= RING_DOWN ;
1580 DB_TX(2, "Ring is down: terminate LAN_TX");
1582 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1584 mac_drv_clear_txd(smc) ;
1585 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1586 DB_TX(2, "Out of TxDs, terminate LAN_TX");
1587 frame_status &= ~LAN_TX ;
1588 frame_status |= OUT_OF_TXD ;
1591 DB_TX(2, "Out of TxDs, terminate LAN_TX");
1592 frame_status &= ~LAN_TX ;
1593 frame_status |= OUT_OF_TXD ;
1596 DB_TX(3, "frame_status = %x", frame_status);
1597 NDD_TRACE("THiE",frame_status,smc->os.hwm.tx_p->tx_free,0) ;
1598 return frame_status;
1602 * BEGIN_MANUAL_ENTRY(hwm_tx_frag)
1603 * void hwm_tx_frag(smc,virt,phys,len,frame_status)
1605 * function DOWNCALL (hardware module, hwmtm.c)
1606 * If the frame should be sent to the LAN, this function calls
1607 * dma_master, fills the current TxD with the virtual and the
1608 * physical address, sets the STF and EOF bits dependent on
1609 * the frame status, and requests the BMU to start the
1611 * If the frame should be sent to the local SMT, an SMT_MBuf
1612 * is allocated if the FIRST_FRAG bit is set in the frame_status.
1613 * The fragment of the frame is copied into the SMT MBuf.
1614 * The function smt_received_pack is called if the LAST_FRAG
1615 * bit is set in the frame_status word.
1617 * para virt virtual pointer to the fragment
1618 * len the length of the fragment
1619 * frame_status status of the frame, see design description
1621 * return nothing returned, no parameter is modified
1623 * NOTE: It is possible to invoke this macro with a fragment length
1628 void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1631 struct s_smt_fp_txd volatile *t ;
1632 struct s_smt_tx_queue *queue ;
1635 queue = smc->os.hwm.tx_p ;
1637 NDD_TRACE("THfB",virt,len,frame_status) ;
1638 /* Bug fix: AF / May 31 1999 (#missing)
1639 * snmpinfo problem reported by IBM is caused by invalid
1640 * t-pointer (txd) if LAN_TX is not set but LOC_TX only.
1641 * Set: t = queue->tx_curr_put here !
1643 t = queue->tx_curr_put ;
1645 DB_TX(2, "hwm_tx_frag: len = %d, frame_status = %x", len, frame_status);
1646 if (frame_status & LAN_TX) {
1647 /* '*t' is already defined */
1648 DB_TX(3, "LAN_TX: TxD = %p, virt = %p", t, virt);
1649 t->txd_virt = virt ;
1650 t->txd_txdscr = cpu_to_le32(smc->os.hwm.tx_descr) ;
1651 t->txd_tbadr = cpu_to_le32(phys) ;
1652 tbctrl = cpu_to_le32((((__u32)frame_status &
1653 (FIRST_FRAG|LAST_FRAG|EN_IRQ_EOF))<< 26) |
1654 BMU_OWN|BMU_CHECK |len) ;
1655 t->txd_tbctrl = tbctrl ;
1658 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1659 outpd(queue->tx_bmu_ctl,CSR_START) ;
1660 #else /* ifndef AIX */
1661 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1662 if (frame_status & QUEUE_A0) {
1663 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1666 outpd(ADDR(B0_XS_CSR),CSR_START) ;
1671 queue->tx_curr_put = t->txd_next ;
1672 if (frame_status & LAST_FRAG) {
1673 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1676 if (frame_status & LOC_TX) {
1677 DB_TX(3, "LOC_TX:");
1678 if (frame_status & FIRST_FRAG) {
1679 if(!(smc->os.hwm.tx_mb = smt_get_mbuf(smc))) {
1680 smc->hw.fp.err_stats.err_no_buf++ ;
1681 DB_TX(4, "No SMbuf; transmit terminated");
1684 smc->os.hwm.tx_data =
1685 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1687 #ifdef PASS_1ST_TXD_2_TX_COMP
1688 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1689 smc->os.hwm.tx_len) ;
1694 if (smc->os.hwm.tx_mb) {
1696 DB_TX(3, "copy fragment into MBuf");
1697 memcpy(smc->os.hwm.tx_data,virt,len) ;
1698 smc->os.hwm.tx_data += len ;
1700 if (frame_status & LAST_FRAG) {
1702 #ifndef PASS_1ST_TXD_2_TX_COMP
1704 * hwm_cpy_txd2mb(txd,data,len) copies 'len'
1705 * bytes from the virtual pointer in 'rxd'
1706 * to 'data'. The virtual pointer of the
1707 * os-specific tx-buffer should be written
1710 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1711 smc->os.hwm.tx_len) ;
1712 #endif /* nPASS_1ST_TXD_2_TX_COMP */
1713 #endif /* USE_OS_CPY */
1714 smc->os.hwm.tx_data =
1715 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1716 *(char *)smc->os.hwm.tx_mb->sm_data =
1717 *smc->os.hwm.tx_data ;
1718 smc->os.hwm.tx_data++ ;
1719 smc->os.hwm.tx_mb->sm_len =
1720 smc->os.hwm.tx_len - 1 ;
1721 DB_TX(3, "pass LLC frame to SMT");
1722 smt_received_pack(smc,smc->os.hwm.tx_mb,
1727 NDD_TRACE("THfE",t,queue->tx_free,0) ;
1732 * queues a receive for later send
1734 static void queue_llc_rx(struct s_smc *smc, SMbuf *mb)
1736 DB_GEN(4, "queue_llc_rx: mb = %p", mb);
1737 smc->os.hwm.queued_rx_frames++ ;
1738 mb->sm_next = (SMbuf *)NULL ;
1739 if (smc->os.hwm.llc_rx_pipe == NULL) {
1740 smc->os.hwm.llc_rx_pipe = mb ;
1743 smc->os.hwm.llc_rx_tail->sm_next = mb ;
1745 smc->os.hwm.llc_rx_tail = mb ;
1748 * force an timer IRQ to receive the data
1750 if (!smc->os.hwm.isr_flag) {
1751 smt_force_irq(smc) ;
1756 * get a SMbuf from the llc_rx_queue
1758 static SMbuf *get_llc_rx(struct s_smc *smc)
1762 if ((mb = smc->os.hwm.llc_rx_pipe)) {
1763 smc->os.hwm.queued_rx_frames-- ;
1764 smc->os.hwm.llc_rx_pipe = mb->sm_next ;
1766 DB_GEN(4, "get_llc_rx: mb = 0x%p", mb);
1771 * queues a transmit SMT MBuf during the time were the MBuf is
1772 * queued the TxD ring
1774 static void queue_txd_mb(struct s_smc *smc, SMbuf *mb)
1776 DB_GEN(4, "_rx: queue_txd_mb = %p", mb);
1777 smc->os.hwm.queued_txd_mb++ ;
1778 mb->sm_next = (SMbuf *)NULL ;
1779 if (smc->os.hwm.txd_tx_pipe == NULL) {
1780 smc->os.hwm.txd_tx_pipe = mb ;
1783 smc->os.hwm.txd_tx_tail->sm_next = mb ;
1785 smc->os.hwm.txd_tx_tail = mb ;
1789 * get a SMbuf from the txd_tx_queue
1791 static SMbuf *get_txd_mb(struct s_smc *smc)
1795 if ((mb = smc->os.hwm.txd_tx_pipe)) {
1796 smc->os.hwm.queued_txd_mb-- ;
1797 smc->os.hwm.txd_tx_pipe = mb->sm_next ;
1799 DB_GEN(4, "get_txd_mb: mb = 0x%p", mb);
1806 void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc)
1814 SK_LOC_DECL(char far,*virt[3]) ;
1816 struct s_smt_tx_queue *queue ;
1817 struct s_smt_fp_txd volatile *t ;
1821 NDD_TRACE("THSB",mb,fc,0) ;
1822 DB_TX(4, "smt_send_mbuf: mb = 0x%p, fc = 0x%x", mb, fc);
1824 mb->sm_off-- ; /* set to fc */
1825 mb->sm_len++ ; /* + fc */
1826 data = smtod(mb,char *) ;
1828 if (fc == FC_SMT_LOC)
1829 *data = FC_SMT_INFO ;
1832 * determine the frag count and the virt addresses of the frags
1837 n = SMT_PAGESIZE - ((long)data & (SMT_PAGESIZE-1)) ;
1841 DB_TX(5, "frag: virt/len = 0x%p/%d", data, n);
1842 virt[frag_count] = data ;
1843 frag_len[frag_count] = n ;
1850 * determine the frame status
1852 queue = smc->hw.fp.tx[QUEUE_A0] ;
1853 if (fc == FC_BEACON || fc == FC_SMT_LOC) {
1854 frame_status = LOC_TX ;
1857 frame_status = LAN_TX ;
1858 if ((smc->os.hwm.pass_NSA &&(fc == FC_SMT_NSA)) ||
1859 (smc->os.hwm.pass_SMT &&(fc == FC_SMT_INFO)))
1860 frame_status |= LOC_TX ;
1863 if (!smc->hw.mac_ring_is_up || frag_count > queue->tx_free) {
1864 frame_status &= ~LAN_TX;
1866 DB_TX(2, "Ring is down: terminate LAN_TX");
1869 DB_TX(2, "Ring is down: terminate transmission");
1870 smt_free_mbuf(smc,mb) ;
1874 DB_TX(5, "frame_status = 0x%x", frame_status);
1876 if ((frame_status & LAN_TX) && (frame_status & LOC_TX)) {
1877 mb->sm_use_count = 2 ;
1880 if (frame_status & LAN_TX) {
1881 t = queue->tx_curr_put ;
1882 frame_status |= FIRST_FRAG ;
1883 for (i = 0; i < frag_count; i++) {
1884 DB_TX(5, "init TxD = 0x%p", t);
1885 if (i == frag_count-1) {
1886 frame_status |= LAST_FRAG ;
1887 t->txd_txdscr = cpu_to_le32(TX_DESCRIPTOR |
1888 (((__u32)(mb->sm_len-1)&3) << 27)) ;
1890 t->txd_virt = virt[i] ;
1891 phys = dma_master(smc, (void far *)virt[i],
1892 frag_len[i], DMA_RD|SMT_BUF) ;
1893 t->txd_tbadr = cpu_to_le32(phys) ;
1894 tbctrl = cpu_to_le32((((__u32)frame_status &
1895 (FIRST_FRAG|LAST_FRAG)) << 26) |
1896 BMU_OWN | BMU_CHECK | BMU_SMT_TX |frag_len[i]) ;
1897 t->txd_tbctrl = tbctrl ;
1899 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1900 outpd(queue->tx_bmu_ctl,CSR_START) ;
1902 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1903 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1905 frame_status &= ~FIRST_FRAG ;
1906 queue->tx_curr_put = t = t->txd_next ;
1910 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1911 queue_txd_mb(smc,mb) ;
1914 if (frame_status & LOC_TX) {
1915 DB_TX(5, "pass Mbuf to LLC queue");
1916 queue_llc_rx(smc,mb) ;
1920 * We need to unqueue the free SMT_MBUFs here, because it may
1921 * be that the SMT want's to send more than 1 frame for one down call
1923 mac_drv_clear_txd(smc) ;
1924 NDD_TRACE("THSE",t,queue->tx_free,frag_count) ;
1927 /* BEGIN_MANUAL_ENTRY(mac_drv_clear_txd)
1928 * void mac_drv_clear_txd(smc)
1930 * function DOWNCALL (hardware module, hwmtm.c)
1931 * mac_drv_clear_txd searches in both send queues for TxD's
1932 * which were finished by the adapter. It calls dma_complete
1933 * for each TxD. If the last fragment of an LLC frame is
1934 * reached, it calls mac_drv_tx_complete to release the
1941 static void mac_drv_clear_txd(struct s_smc *smc)
1943 struct s_smt_tx_queue *queue ;
1944 struct s_smt_fp_txd volatile *t1 ;
1945 struct s_smt_fp_txd volatile *t2 = NULL ;
1952 NDD_TRACE("THcB",0,0,0) ;
1953 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
1954 queue = smc->hw.fp.tx[i] ;
1955 t1 = queue->tx_curr_get ;
1956 DB_TX(5, "clear_txd: QUEUE = %d (0=sync/1=async)", i);
1962 DRV_BUF_FLUSH(t1,DDI_DMA_SYNC_FORCPU) ;
1963 DB_TX(5, "check OWN/EOF bit of TxD 0x%p", t1);
1964 tbctrl = le32_to_cpu(CR_READ(t1->txd_tbctrl));
1966 if (tbctrl & BMU_OWN || !queue->tx_used){
1967 DB_TX(4, "End of TxDs queue %d", i);
1968 goto free_next_queue ; /* next queue */
1972 } while (!(tbctrl & BMU_EOF)) ;
1974 t1 = queue->tx_curr_get ;
1975 for (n = frag_count; n; n--) {
1976 tbctrl = le32_to_cpu(t1->txd_tbctrl) ;
1978 (union s_fp_descr volatile *) t1,
1980 ((tbctrl & BMU_SMT_TX) >> 18))) ;
1985 if (tbctrl & BMU_SMT_TX) {
1986 mb = get_txd_mb(smc) ;
1987 smt_free_mbuf(smc,mb) ;
1990 #ifndef PASS_1ST_TXD_2_TX_COMP
1991 DB_TX(4, "mac_drv_tx_comp for TxD 0x%p", t2);
1992 mac_drv_tx_complete(smc,t2) ;
1994 DB_TX(4, "mac_drv_tx_comp for TxD 0x%x",
1995 queue->tx_curr_get);
1996 mac_drv_tx_complete(smc,queue->tx_curr_get) ;
1999 queue->tx_curr_get = t1 ;
2000 queue->tx_free += frag_count ;
2001 queue->tx_used -= frag_count ;
2005 NDD_TRACE("THcE",0,0,0) ;
2009 * BEGINN_MANUAL_ENTRY(mac_drv_clear_tx_queue)
2011 * void mac_drv_clear_tx_queue(smc)
2012 * struct s_smc *smc ;
2014 * function DOWNCALL (hardware module, hwmtm.c)
2015 * mac_drv_clear_tx_queue is called from the SMT when
2016 * the RMT state machine has entered the ISOLATE state.
2017 * This function is also called by the os-specific module
2018 * after it has called the function card_stop().
2019 * In this case, the frames in the send queues are obsolete and
2020 * should be removed.
2022 * note calling sequence:
2023 * CLI_FBI(), card_stop(),
2024 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
2026 * NOTE: The caller is responsible that the BMUs are idle
2027 * when this function is called.
2031 void mac_drv_clear_tx_queue(struct s_smc *smc)
2033 struct s_smt_fp_txd volatile *t ;
2034 struct s_smt_tx_queue *queue ;
2038 if (smc->hw.hw_state != STOPPED) {
2040 SMT_PANIC(smc,HWM_E0011,HWM_E0011_MSG) ;
2044 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2045 queue = smc->hw.fp.tx[i] ;
2046 DB_TX(5, "clear_tx_queue: QUEUE = %d (0=sync/1=async)", i);
2049 * switch the OWN bit of all pending frames to the host
2051 t = queue->tx_curr_get ;
2052 tx_used = queue->tx_used ;
2054 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
2055 DB_TX(5, "switch OWN bit of TxD 0x%p", t);
2056 t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
2057 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
2064 * release all TxD's for both send queues
2066 mac_drv_clear_txd(smc) ;
2068 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2069 queue = smc->hw.fp.tx[i] ;
2070 t = queue->tx_curr_get ;
2073 * write the phys pointer of the NEXT descriptor into the
2074 * BMU's current address descriptor pointer and set
2075 * tx_curr_get and tx_curr_put to this position
2078 outpd(ADDR(B5_XS_DA),le32_to_cpu(t->txd_ntdadr)) ;
2081 outpd(ADDR(B5_XA_DA),le32_to_cpu(t->txd_ntdadr)) ;
2084 queue->tx_curr_put = queue->tx_curr_get->txd_next ;
2085 queue->tx_curr_get = queue->tx_curr_put ;
2091 -------------------------------------------------------------
2093 -------------------------------------------------------------
2098 * BEGIN_MANUAL_ENTRY(mac_drv_debug_lev)
2099 * void mac_drv_debug_lev(smc,flag,lev)
2101 * function DOWNCALL (drvsr.c)
2102 * To get a special debug info the user can assign a debug level
2103 * to any debug flag.
2105 * para flag debug flag, possible values are:
2106 * = 0: reset all debug flags (the defined level is
2115 * = 10: debug.d_os.hwm_rx (hardware module receive path)
2116 * = 11: debug.d_os.hwm_tx(hardware module transmit path)
2117 * = 12: debug.d_os.hwm_gen(hardware module general flag)
2123 void mac_drv_debug_lev(struct s_smc *smc, int flag, int lev)
2127 DB_P.d_smtf = DB_P.d_smt = DB_P.d_ecm = DB_P.d_rmt = 0 ;
2129 DB_P.d_os.hwm_rx = DB_P.d_os.hwm_tx = DB_P.d_os.hwm_gen = 0 ;
2166 DB_P.d_os.hwm_rx = lev ;
2169 DB_P.d_os.hwm_tx = lev ;
2172 DB_P.d_os.hwm_gen = lev ;