drivers/net/ethernet/xilinx/ll_temac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for Xilinx TEMAC Ethernet device
   4  *
   5  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
   6  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
   7  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
   8  *
   9  * This is a driver for the Xilinx ll_temac ipcore which is often used
  10  * in the Virtex and Spartan series of chips.
  11  *
  12  * Notes:
  13  * - The ll_temac hardware uses indirect access for many of the TEMAC
  14  *   registers, include the MDIO bus.  However, indirect access to MDIO
  15  *   registers take considerably more clock cycles than to TEMAC registers.
  16  *   MDIO accesses are long, so threads doing them should probably sleep
  17  *   rather than busywait.  However, since only one indirect access can be
  18  *   in progress at any given time, that means that *all* indirect accesses
  19  *   could end up sleeping (to wait for an MDIO access to complete).
  20  *   Fortunately none of the indirect accesses are on the 'hot' path for tx
  21  *   or rx, so this should be okay.
  22  *
  23  * TODO:
  24  * - Factor out locallink DMA code into separate driver
  25  * - Fix support for hardware checksumming.
  26  * - Testing.  Lots and lots of testing.
  27  *
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/mii.h>
  33 #include <linux/module.h>
  34 #include <linux/mutex.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/if_ether.h>
  37 #include <linux/of.h>
  38 #include <linux/of_device.h>
  39 #include <linux/of_irq.h>
  40 #include <linux/of_mdio.h>
  41 #include <linux/of_net.h>
  42 #include <linux/of_platform.h>
  43 #include <linux/of_address.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/spinlock.h>
  46 #include <linux/tcp.h>      /* needed for sizeof(tcphdr) */
  47 #include <linux/udp.h>      /* needed for sizeof(udphdr) */
  48 #include <linux/phy.h>
  49 #include <linux/in.h>
  50 #include <linux/io.h>
  51 #include <linux/ip.h>
  52 #include <linux/slab.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/workqueue.h>
  55 #include <linux/dma-mapping.h>
  56 #include <linux/processor.h>
  57 #include <linux/platform_data/xilinx-ll-temac.h>
  58
  59 #include "ll_temac.h"
  60
  61 /* Descriptors defines for Tx and Rx DMA */
  62 #define TX_BD_NUM_DEFAULT               64
  63 #define RX_BD_NUM_DEFAULT               1024
  64 #define TX_BD_NUM_MAX                   4096
  65 #define RX_BD_NUM_MAX                   4096
  66
  67 /* ---------------------------------------------------------------------
  68  * Low level register access functions
  69  */
  70
  71 static u32 _temac_ior_be(struct temac_local *lp, int offset)
  72 {
  73         return ioread32be(lp->regs + offset);
  74 }
  75
  76 static void _temac_iow_be(struct temac_local *lp, int offset, u32 value)
  77 {
  78         return iowrite32be(value, lp->regs + offset);
  79 }
  80
  81 static u32 _temac_ior_le(struct temac_local *lp, int offset)
  82 {
  83         return ioread32(lp->regs + offset);
  84 }
  85
  86 static void _temac_iow_le(struct temac_local *lp, int offset, u32 value)
  87 {
  88         return iowrite32(value, lp->regs + offset);
  89 }
  90
  91 static bool hard_acs_rdy(struct temac_local *lp)
  92 {
  93         return temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK;
  94 }
  95
  96 static bool hard_acs_rdy_or_timeout(struct temac_local *lp, ktime_t timeout)
  97 {
  98         ktime_t cur = ktime_get();
  99
 100         return hard_acs_rdy(lp) || ktime_after(cur, timeout);
 101 }
 102
 103 /* Poll for maximum 20 ms.  This is similar to the 2 jiffies @ 100 Hz
 104  * that was used before, and should cover MDIO bus speed down to 3200
 105  * Hz.
 106  */
 107 #define HARD_ACS_RDY_POLL_NS (20 * NSEC_PER_MSEC)
 108
 109 /*
 110  * temac_indirect_busywait - Wait for current indirect register access
 111  * to complete.
 112  */
 113 int temac_indirect_busywait(struct temac_local *lp)
 114 {
 115         ktime_t timeout = ktime_add_ns(ktime_get(), HARD_ACS_RDY_POLL_NS);
 116
 117         spin_until_cond(hard_acs_rdy_or_timeout(lp, timeout));
 118         if (WARN_ON(!hard_acs_rdy(lp)))
 119                 return -ETIMEDOUT;
 120         else
 121                 return 0;
 122 }
 123
 124 /*
 125  * temac_indirect_in32 - Indirect register read access.  This function
 126  * must be called without lp->indirect_lock being held.
 127  */
 128 u32 temac_indirect_in32(struct temac_local *lp, int reg)
 129 {
 130         unsigned long flags;
 131         int val;
 132
 133         spin_lock_irqsave(lp->indirect_lock, flags);
 134         val = temac_indirect_in32_locked(lp, reg);
 135         spin_unlock_irqrestore(lp->indirect_lock, flags);
 136         return val;
 137 }
 138
 139 /*
 140  * temac_indirect_in32_locked - Indirect register read access.  This
 141  * function must be called with lp->indirect_lock being held.  Use
 142  * this together with spin_lock_irqsave/spin_lock_irqrestore to avoid
 143  * repeated lock/unlock and to ensure uninterrupted access to indirect
 144  * registers.
 145  */
 146 u32 temac_indirect_in32_locked(struct temac_local *lp, int reg)
 147 {
 148         /* This initial wait should normally not spin, as we always
 149          * try to wait for indirect access to complete before
 150          * releasing the indirect_lock.
 151          */
 152         if (WARN_ON(temac_indirect_busywait(lp)))
 153                 return -ETIMEDOUT;
 154         /* Initiate read from indirect register */
 155         temac_iow(lp, XTE_CTL0_OFFSET, reg);
 156         /* Wait for indirect register access to complete.  We really
 157          * should not see timeouts, and could even end up causing
 158          * problem for following indirect access, so let's make a bit
 159          * of WARN noise.
 160          */
 161         if (WARN_ON(temac_indirect_busywait(lp)))
 162                 return -ETIMEDOUT;
 163         /* Value is ready now */
 164         return temac_ior(lp, XTE_LSW0_OFFSET);
 165 }
 166
 167 /*
 168  * temac_indirect_out32 - Indirect register write access.  This function
 169  * must be called without lp->indirect_lock being held.
 170  */
 171 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
 172 {
 173         unsigned long flags;
 174
 175         spin_lock_irqsave(lp->indirect_lock, flags);
 176         temac_indirect_out32_locked(lp, reg, value);
 177         spin_unlock_irqrestore(lp->indirect_lock, flags);
 178 }
 179
 180 /*
 181  * temac_indirect_out32_locked - Indirect register write access.  This
 182  * function must be called with lp->indirect_lock being held.  Use
 183  * this together with spin_lock_irqsave/spin_lock_irqrestore to avoid
 184  * repeated lock/unlock and to ensure uninterrupted access to indirect
 185  * registers.
 186  */
 187 void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value)
 188 {
 189         /* As in temac_indirect_in32_locked(), we should normally not
 190          * spin here.  And if it happens, we actually end up silently
 191          * ignoring the write request.  Ouch.
 192          */
 193         if (WARN_ON(temac_indirect_busywait(lp)))
 194                 return;
 195         /* Initiate write to indirect register */
 196         temac_iow(lp, XTE_LSW0_OFFSET, value);
 197         temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
 198         /* As in temac_indirect_in32_locked(), we should not see timeouts
 199          * here.  And if it happens, we continue before the write has
 200          * completed.  Not good.
 201          */
 202         WARN_ON(temac_indirect_busywait(lp));
 203 }
 204
 205 /*
 206  * temac_dma_in32_* - Memory mapped DMA read, these function expects a
 207  * register input that is based on DCR word addresses which are then
 208  * converted to memory mapped byte addresses.  To be assigned to
 209  * lp->dma_in32.
 210  */
 211 static u32 temac_dma_in32_be(struct temac_local *lp, int reg)
 212 {
 213         return ioread32be(lp->sdma_regs + (reg << 2));
 214 }
 215
 216 static u32 temac_dma_in32_le(struct temac_local *lp, int reg)
 217 {
 218         return ioread32(lp->sdma_regs + (reg << 2));
 219 }
 220
 221 /*
 222  * temac_dma_out32_* - Memory mapped DMA read, these function expects
 223  * a register input that is based on DCR word addresses which are then
 224  * converted to memory mapped byte addresses.  To be assigned to
 225  * lp->dma_out32.
 226  */
 227 static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value)
 228 {
 229         iowrite32be(value, lp->sdma_regs + (reg << 2));
 230 }
 231
 232 static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value)
 233 {
 234         iowrite32(value, lp->sdma_regs + (reg << 2));
 235 }
 236
 237 /* DMA register access functions can be DCR based or memory mapped.
 238  * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
 239  * memory mapped.
 240  */
 241 #ifdef CONFIG_PPC_DCR
 242
 243 /*
 244  * temac_dma_dcr_in32 - DCR based DMA read
 245  */
 246 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
 247 {
 248         return dcr_read(lp->sdma_dcrs, reg);
 249 }
 250
 251 /*
 252  * temac_dma_dcr_out32 - DCR based DMA write
 253  */
 254 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
 255 {
 256         dcr_write(lp->sdma_dcrs, reg, value);
 257 }
 258
 259 /*
 260  * temac_dcr_setup - If the DMA is DCR based, then setup the address and
 261  * I/O  functions
 262  */
 263 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
 264                                 struct device_node *np)
 265 {
 266         unsigned int dcrs;
 267
 268         /* setup the dcr address mapping if it's in the device tree */
 269
 270         dcrs = dcr_resource_start(np, 0);
 271         if (dcrs != 0) {
 272                 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
 273                 lp->dma_in = temac_dma_dcr_in;
 274                 lp->dma_out = temac_dma_dcr_out;
 275                 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
 276                 return 0;
 277         }
 278         /* no DCR in the device tree, indicate a failure */
 279         return -1;
 280 }
 281
 282 #else
 283
 284 /*
 285  * temac_dcr_setup - This is a stub for when DCR is not supported,
 286  * such as with MicroBlaze and x86
 287  */
 288 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
 289                                 struct device_node *np)
 290 {
 291         return -1;
 292 }
 293
 294 #endif
 295
 296 /*
 297  * temac_dma_bd_release - Release buffer descriptor rings
 298  */
 299 static void temac_dma_bd_release(struct net_device *ndev)
 300 {
 301         struct temac_local *lp = netdev_priv(ndev);
 302         int i;
 303
 304         /* Reset Local Link (DMA) */
 305         lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
 306
 307         for (i = 0; i < lp->rx_bd_num; i++) {
 308                 if (!lp->rx_skb[i])
 309                         break;
 310                 else {
 311                         dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
 312                                         XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
 313                         dev_kfree_skb(lp->rx_skb[i]);
 314                 }
 315         }
 316         if (lp->rx_bd_v)
 317                 dma_free_coherent(ndev->dev.parent,
 318                                   sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
 319                                   lp->rx_bd_v, lp->rx_bd_p);
 320         if (lp->tx_bd_v)
 321                 dma_free_coherent(ndev->dev.parent,
 322                                   sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
 323                                   lp->tx_bd_v, lp->tx_bd_p);
 324 }
 325
 326 /*
 327  * temac_dma_bd_init - Setup buffer descriptor rings
 328  */
 329 static int temac_dma_bd_init(struct net_device *ndev)
 330 {
 331         struct temac_local *lp = netdev_priv(ndev);
 332         struct sk_buff *skb;
 333         dma_addr_t skb_dma_addr;
 334         int i;
 335
 336         lp->rx_skb = devm_kcalloc(&ndev->dev, lp->rx_bd_num,
 337                                   sizeof(*lp->rx_skb), GFP_KERNEL);
 338         if (!lp->rx_skb)
 339                 goto out;
 340
 341         /* allocate the tx and rx ring buffer descriptors. */
 342         /* returns a virtual address and a physical address. */
 343         lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 344                                          sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
 345                                          &lp->tx_bd_p, GFP_KERNEL);
 346         if (!lp->tx_bd_v)
 347                 goto out;
 348
 349         lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 350                                          sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
 351                                          &lp->rx_bd_p, GFP_KERNEL);
 352         if (!lp->rx_bd_v)
 353                 goto out;
 354
 355         for (i = 0; i < lp->tx_bd_num; i++) {
 356                 lp->tx_bd_v[i].next = cpu_to_be32(lp->tx_bd_p
 357                         + sizeof(*lp->tx_bd_v) * ((i + 1) % lp->tx_bd_num));
 358         }
 359
 360         for (i = 0; i < lp->rx_bd_num; i++) {
 361                 lp->rx_bd_v[i].next = cpu_to_be32(lp->rx_bd_p
 362                         + sizeof(*lp->rx_bd_v) * ((i + 1) % lp->rx_bd_num));
 363
 364                 skb = netdev_alloc_skb_ip_align(ndev,
 365                                                 XTE_MAX_JUMBO_FRAME_SIZE);
 366                 if (!skb)
 367                         goto out;
 368
 369                 lp->rx_skb[i] = skb;
 370                 /* returns physical address of skb->data */
 371                 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
 372                                               XTE_MAX_JUMBO_FRAME_SIZE,
 373                                               DMA_FROM_DEVICE);
 374                 if (dma_mapping_error(ndev->dev.parent, skb_dma_addr))
 375                         goto out;
 376                 lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);
 377                 lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
 378                 lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
 379         }
 380
 381         /* Configure DMA channel (irq setup) */
 382         lp->dma_out(lp, TX_CHNL_CTRL,
 383                     lp->coalesce_delay_tx << 24 | lp->coalesce_count_tx << 16 |
 384                     0x00000400 | // Use 1 Bit Wide Counters. Currently Not Used!
 385                     CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
 386                     CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
 387         lp->dma_out(lp, RX_CHNL_CTRL,
 388                     lp->coalesce_delay_rx << 24 | lp->coalesce_count_rx << 16 |
 389                     CHNL_CTRL_IRQ_IOE |
 390                     CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
 391                     CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
 392
 393         /* Init descriptor indexes */
 394         lp->tx_bd_ci = 0;
 395         lp->tx_bd_tail = 0;
 396         lp->rx_bd_ci = 0;
 397         lp->rx_bd_tail = lp->rx_bd_num - 1;
 398
 399         /* Enable RX DMA transfers */
 400         wmb();
 401         lp->dma_out(lp, RX_CURDESC_PTR,  lp->rx_bd_p);
 402         lp->dma_out(lp, RX_TAILDESC_PTR,
 403                        lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * lp->rx_bd_tail));
 404
 405         /* Prepare for TX DMA transfer */
 406         lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
 407
 408         return 0;
 409
 410 out:
 411         temac_dma_bd_release(ndev);
 412         return -ENOMEM;
 413 }
 414
 415 /* ---------------------------------------------------------------------
 416  * net_device_ops
 417  */
 418
 419 static void temac_do_set_mac_address(struct net_device *ndev)
 420 {
 421         struct temac_local *lp = netdev_priv(ndev);
 422         unsigned long flags;
 423
 424         /* set up unicast MAC address filter set its mac address */
 425         spin_lock_irqsave(lp->indirect_lock, flags);
 426         temac_indirect_out32_locked(lp, XTE_UAW0_OFFSET,
 427                                     (ndev->dev_addr[0]) |
 428                                     (ndev->dev_addr[1] << 8) |
 429                                     (ndev->dev_addr[2] << 16) |
 430                                     (ndev->dev_addr[3] << 24));
 431         /* There are reserved bits in EUAW1
 432          * so don't affect them Set MAC bits [47:32] in EUAW1 */
 433         temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET,
 434                                     (ndev->dev_addr[4] & 0x000000ff) |
 435                                     (ndev->dev_addr[5] << 8));
 436         spin_unlock_irqrestore(lp->indirect_lock, flags);
 437 }
 438
 439 static int temac_init_mac_address(struct net_device *ndev, const void *address)
 440 {
 441         eth_hw_addr_set(ndev, address);
 442         if (!is_valid_ether_addr(ndev->dev_addr))
 443                 eth_hw_addr_random(ndev);
 444         temac_do_set_mac_address(ndev);
 445         return 0;
 446 }
 447
 448 static int temac_set_mac_address(struct net_device *ndev, void *p)
 449 {
 450         struct sockaddr *addr = p;
 451
 452         if (!is_valid_ether_addr(addr->sa_data))
 453                 return -EADDRNOTAVAIL;
 454         eth_hw_addr_set(ndev, addr->sa_data);
 455         temac_do_set_mac_address(ndev);
 456         return 0;
 457 }
 458
 459 static void temac_set_multicast_list(struct net_device *ndev)
 460 {
 461         struct temac_local *lp = netdev_priv(ndev);
 462         u32 multi_addr_msw, multi_addr_lsw;
 463         int i = 0;
 464         unsigned long flags;
 465         bool promisc_mode_disabled = false;
 466
 467         if (ndev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
 468             (netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM)) {
 469                 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
 470                 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
 471                 return;
 472         }
 473
 474         spin_lock_irqsave(lp->indirect_lock, flags);
 475
 476         if (!netdev_mc_empty(ndev)) {
 477                 struct netdev_hw_addr *ha;
 478
 479                 netdev_for_each_mc_addr(ha, ndev) {
 480                         if (WARN_ON(i >= MULTICAST_CAM_TABLE_NUM))
 481                                 break;
 482                         multi_addr_msw = ((ha->addr[3] << 24) |
 483                                           (ha->addr[2] << 16) |
 484                                           (ha->addr[1] << 8) |
 485                                           (ha->addr[0]));
 486                         temac_indirect_out32_locked(lp, XTE_MAW0_OFFSET,
 487                                                     multi_addr_msw);
 488                         multi_addr_lsw = ((ha->addr[5] << 8) |
 489                                           (ha->addr[4]) | (i << 16));
 490                         temac_indirect_out32_locked(lp, XTE_MAW1_OFFSET,
 491                                                     multi_addr_lsw);
 492                         i++;
 493                 }
 494         }
 495
 496         /* Clear all or remaining/unused address table entries */
 497         while (i < MULTICAST_CAM_TABLE_NUM) {
 498                 temac_indirect_out32_locked(lp, XTE_MAW0_OFFSET, 0);
 499                 temac_indirect_out32_locked(lp, XTE_MAW1_OFFSET, i << 16);
 500                 i++;
 501         }
 502
 503         /* Enable address filter block if currently disabled */
 504         if (temac_indirect_in32_locked(lp, XTE_AFM_OFFSET)
 505             & XTE_AFM_EPPRM_MASK) {
 506                 temac_indirect_out32_locked(lp, XTE_AFM_OFFSET, 0);
 507                 promisc_mode_disabled = true;
 508         }
 509
 510         spin_unlock_irqrestore(lp->indirect_lock, flags);
 511
 512         if (promisc_mode_disabled)
 513                 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
 514 }
 515
 516 static struct temac_option {
 517         int flg;
 518         u32 opt;
 519         u32 reg;
 520         u32 m_or;
 521         u32 m_and;
 522 } temac_options[] = {
 523         /* Turn on jumbo packet support for both Rx and Tx */
 524         {
 525                 .opt = XTE_OPTION_JUMBO,
 526                 .reg = XTE_TXC_OFFSET,
 527                 .m_or = XTE_TXC_TXJMBO_MASK,
 528         },
 529         {
 530                 .opt = XTE_OPTION_JUMBO,
 531                 .reg = XTE_RXC1_OFFSET,
 532                 .m_or =XTE_RXC1_RXJMBO_MASK,
 533         },
 534         /* Turn on VLAN packet support for both Rx and Tx */
 535         {
 536                 .opt = XTE_OPTION_VLAN,
 537                 .reg = XTE_TXC_OFFSET,
 538                 .m_or =XTE_TXC_TXVLAN_MASK,
 539         },
 540         {
 541                 .opt = XTE_OPTION_VLAN,
 542                 .reg = XTE_RXC1_OFFSET,
 543                 .m_or =XTE_RXC1_RXVLAN_MASK,
 544         },
 545         /* Turn on FCS stripping on receive packets */
 546         {
 547                 .opt = XTE_OPTION_FCS_STRIP,
 548                 .reg = XTE_RXC1_OFFSET,
 549                 .m_or =XTE_RXC1_RXFCS_MASK,
 550         },
 551         /* Turn on FCS insertion on transmit packets */
 552         {
 553                 .opt = XTE_OPTION_FCS_INSERT,
 554                 .reg = XTE_TXC_OFFSET,
 555                 .m_or =XTE_TXC_TXFCS_MASK,
 556         },
 557         /* Turn on length/type field checking on receive packets */
 558         {
 559                 .opt = XTE_OPTION_LENTYPE_ERR,
 560                 .reg = XTE_RXC1_OFFSET,
 561                 .m_or =XTE_RXC1_RXLT_MASK,
 562         },
 563         /* Turn on flow control */
 564         {
 565                 .opt = XTE_OPTION_FLOW_CONTROL,
 566                 .reg = XTE_FCC_OFFSET,
 567                 .m_or =XTE_FCC_RXFLO_MASK,
 568         },
 569         /* Turn on flow control */
 570         {
 571                 .opt = XTE_OPTION_FLOW_CONTROL,
 572                 .reg = XTE_FCC_OFFSET,
 573                 .m_or =XTE_FCC_TXFLO_MASK,
 574         },
 575         /* Turn on promiscuous frame filtering (all frames are received ) */
 576         {
 577                 .opt = XTE_OPTION_PROMISC,
 578                 .reg = XTE_AFM_OFFSET,
 579                 .m_or =XTE_AFM_EPPRM_MASK,
 580         },
 581         /* Enable transmitter if not already enabled */
 582         {
 583                 .opt = XTE_OPTION_TXEN,
 584                 .reg = XTE_TXC_OFFSET,
 585                 .m_or =XTE_TXC_TXEN_MASK,
 586         },
 587         /* Enable receiver? */
 588         {
 589                 .opt = XTE_OPTION_RXEN,
 590                 .reg = XTE_RXC1_OFFSET,
 591                 .m_or =XTE_RXC1_RXEN_MASK,
 592         },
 593         {}
 594 };
 595
 596 /*
 597  * temac_setoptions
 598  */
 599 static u32 temac_setoptions(struct net_device *ndev, u32 options)
 600 {
 601         struct temac_local *lp = netdev_priv(ndev);
 602         struct temac_option *tp = &temac_options[0];
 603         int reg;
 604         unsigned long flags;
 605
 606         spin_lock_irqsave(lp->indirect_lock, flags);
 607         while (tp->opt) {
 608                 reg = temac_indirect_in32_locked(lp, tp->reg) & ~tp->m_or;
 609                 if (options & tp->opt) {
 610                         reg |= tp->m_or;
 611                         temac_indirect_out32_locked(lp, tp->reg, reg);
 612                 }
 613                 tp++;
 614         }
 615         spin_unlock_irqrestore(lp->indirect_lock, flags);
 616         lp->options |= options;
 617
 618         return 0;
 619 }
 620
 621 /* Initialize temac */
 622 static void temac_device_reset(struct net_device *ndev)
 623 {
 624         struct temac_local *lp = netdev_priv(ndev);
 625         u32 timeout;
 626         u32 val;
 627         unsigned long flags;
 628
 629         /* Perform a software reset */
 630
 631         /* 0x300 host enable bit ? */
 632         /* reset PHY through control register ?:1 */
 633
 634         dev_dbg(&ndev->dev, "%s()\n", __func__);
 635
 636         /* Reset the receiver and wait for it to finish reset */
 637         temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
 638         timeout = 1000;
 639         while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
 640                 udelay(1);
 641                 if (--timeout == 0) {
 642                         dev_err(&ndev->dev,
 643                                 "temac_device_reset RX reset timeout!!\n");
 644                         break;
 645                 }
 646         }
 647
 648         /* Reset the transmitter and wait for it to finish reset */
 649         temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
 650         timeout = 1000;
 651         while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
 652                 udelay(1);
 653                 if (--timeout == 0) {
 654                         dev_err(&ndev->dev,
 655                                 "temac_device_reset TX reset timeout!!\n");
 656                         break;
 657                 }
 658         }
 659
 660         /* Disable the receiver */
 661         spin_lock_irqsave(lp->indirect_lock, flags);
 662         val = temac_indirect_in32_locked(lp, XTE_RXC1_OFFSET);
 663         temac_indirect_out32_locked(lp, XTE_RXC1_OFFSET,
 664                                     val & ~XTE_RXC1_RXEN_MASK);
 665         spin_unlock_irqrestore(lp->indirect_lock, flags);
 666
 667         /* Reset Local Link (DMA) */
 668         lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
 669         timeout = 1000;
 670         while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
 671                 udelay(1);
 672                 if (--timeout == 0) {
 673                         dev_err(&ndev->dev,
 674                                 "temac_device_reset DMA reset timeout!!\n");
 675                         break;
 676                 }
 677         }
 678         lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
 679
 680         if (temac_dma_bd_init(ndev)) {
 681                 dev_err(&ndev->dev,
 682                                 "temac_device_reset descriptor allocation failed\n");
 683         }
 684
 685         spin_lock_irqsave(lp->indirect_lock, flags);
 686         temac_indirect_out32_locked(lp, XTE_RXC0_OFFSET, 0);
 687         temac_indirect_out32_locked(lp, XTE_RXC1_OFFSET, 0);
 688         temac_indirect_out32_locked(lp, XTE_TXC_OFFSET, 0);
 689         temac_indirect_out32_locked(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
 690         spin_unlock_irqrestore(lp->indirect_lock, flags);
 691
 692         /* Sync default options with HW
 693          * but leave receiver and transmitter disabled.  */
 694         temac_setoptions(ndev,
 695                          lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
 696
 697         temac_do_set_mac_address(ndev);
 698
 699         /* Set address filter table */
 700         temac_set_multicast_list(ndev);
 701         if (temac_setoptions(ndev, lp->options))
 702                 dev_err(&ndev->dev, "Error setting TEMAC options\n");
 703
 704         /* Init Driver variable */
 705         netif_trans_update(ndev); /* prevent tx timeout */
 706 }
 707
 708 static void temac_adjust_link(struct net_device *ndev)
 709 {
 710         struct temac_local *lp = netdev_priv(ndev);
 711         struct phy_device *phy = ndev->phydev;
 712         u32 mii_speed;
 713         int link_state;
 714         unsigned long flags;
 715
 716         /* hash together the state values to decide if something has changed */
 717         link_state = phy->speed | (phy->duplex << 1) | phy->link;
 718
 719         if (lp->last_link != link_state) {
 720                 spin_lock_irqsave(lp->indirect_lock, flags);
 721                 mii_speed = temac_indirect_in32_locked(lp, XTE_EMCFG_OFFSET);
 722                 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
 723
 724                 switch (phy->speed) {
 725                 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
 726                 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
 727                 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
 728                 }
 729
 730                 /* Write new speed setting out to TEMAC */
 731                 temac_indirect_out32_locked(lp, XTE_EMCFG_OFFSET, mii_speed);
 732                 spin_unlock_irqrestore(lp->indirect_lock, flags);
 733
 734                 lp->last_link = link_state;
 735                 phy_print_status(phy);
 736         }
 737 }
 738
 739 #ifdef CONFIG_64BIT
 740
 741 static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
 742 {
 743         bd->app3 = (u32)(((u64)p) >> 32);
 744         bd->app4 = (u32)((u64)p & 0xFFFFFFFF);
 745 }
 746
 747 static void *ptr_from_txbd(struct cdmac_bd *bd)
 748 {
 749         return (void *)(((u64)(bd->app3) << 32) | bd->app4);
 750 }
 751
 752 #else
 753
 754 static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
 755 {
 756         bd->app4 = (u32)p;
 757 }
 758
 759 static void *ptr_from_txbd(struct cdmac_bd *bd)
 760 {
 761         return (void *)(bd->app4);
 762 }
 763
 764 #endif
 765
 766 static void temac_start_xmit_done(struct net_device *ndev)
 767 {
 768         struct temac_local *lp = netdev_priv(ndev);
 769         struct cdmac_bd *cur_p;
 770         unsigned int stat = 0;
 771         struct sk_buff *skb;
 772
 773         cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
 774         stat = be32_to_cpu(cur_p->app0);
 775
 776         while (stat & STS_CTRL_APP0_CMPLT) {
 777                 /* Make sure that the other fields are read after bd is
 778                  * released by dma
 779                  */
 780                 rmb();
 781                 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
 782                                  be32_to_cpu(cur_p->len), DMA_TO_DEVICE);
 783                 skb = (struct sk_buff *)ptr_from_txbd(cur_p);
 784                 if (skb)
 785                         dev_consume_skb_irq(skb);
 786                 cur_p->app1 = 0;
 787                 cur_p->app2 = 0;
 788                 cur_p->app3 = 0;
 789                 cur_p->app4 = 0;
 790
 791                 ndev->stats.tx_packets++;
 792                 ndev->stats.tx_bytes += be32_to_cpu(cur_p->len);
 793
 794                 /* app0 must be visible last, as it is used to flag
 795                  * availability of the bd
 796                  */
 797                 smp_mb();
 798                 cur_p->app0 = 0;
 799
 800                 lp->tx_bd_ci++;
 801                 if (lp->tx_bd_ci >= lp->tx_bd_num)
 802                         lp->tx_bd_ci = 0;
 803
 804                 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
 805                 stat = be32_to_cpu(cur_p->app0);
 806         }
 807
 808         /* Matches barrier in temac_start_xmit */
 809         smp_mb();
 810
 811         netif_wake_queue(ndev);
 812 }
 813
 814 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
 815 {
 816         struct cdmac_bd *cur_p;
 817         int tail;
 818
 819         tail = lp->tx_bd_tail;
 820         cur_p = &lp->tx_bd_v[tail];
 821
 822         do {
 823                 if (cur_p->app0)
 824                         return NETDEV_TX_BUSY;
 825
 826                 /* Make sure to read next bd app0 after this one */
 827                 rmb();
 828
 829                 tail++;
 830                 if (tail >= lp->tx_bd_num)
 831                         tail = 0;
 832
 833                 cur_p = &lp->tx_bd_v[tail];
 834                 num_frag--;
 835         } while (num_frag >= 0);
 836
 837         return 0;
 838 }
 839
 840 static netdev_tx_t
 841 temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 842 {
 843         struct temac_local *lp = netdev_priv(ndev);
 844         struct cdmac_bd *cur_p;
 845         dma_addr_t tail_p, skb_dma_addr;
 846         int ii;
 847         unsigned long num_frag;
 848         skb_frag_t *frag;
 849
 850         num_frag = skb_shinfo(skb)->nr_frags;
 851         frag = &skb_shinfo(skb)->frags[0];
 852         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 853
 854         if (temac_check_tx_bd_space(lp, num_frag + 1)) {
 855                 if (netif_queue_stopped(ndev))
 856                         return NETDEV_TX_BUSY;
 857
 858                 netif_stop_queue(ndev);
 859
 860                 /* Matches barrier in temac_start_xmit_done */
 861                 smp_mb();
 862
 863                 /* Space might have just been freed - check again */
 864                 if (temac_check_tx_bd_space(lp, num_frag + 1))
 865                         return NETDEV_TX_BUSY;
 866
 867                 netif_wake_queue(ndev);
 868         }
 869
 870         cur_p->app0 = 0;
 871         if (skb->ip_summed == CHECKSUM_PARTIAL) {
 872                 unsigned int csum_start_off = skb_checksum_start_offset(skb);
 873                 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
 874
 875                 cur_p->app0 |= cpu_to_be32(0x000001); /* TX Checksum Enabled */
 876                 cur_p->app1 = cpu_to_be32((csum_start_off << 16)
 877                                           | csum_index_off);
 878                 cur_p->app2 = 0;  /* initial checksum seed */
 879         }
 880
 881         cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_SOP);
 882         skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
 883                                       skb_headlen(skb), DMA_TO_DEVICE);
 884         cur_p->len = cpu_to_be32(skb_headlen(skb));
 885         if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent, skb_dma_addr))) {
 886                 dev_kfree_skb_any(skb);
 887                 ndev->stats.tx_dropped++;
 888                 return NETDEV_TX_OK;
 889         }
 890         cur_p->phys = cpu_to_be32(skb_dma_addr);
 891
 892         for (ii = 0; ii < num_frag; ii++) {
 893                 if (++lp->tx_bd_tail >= lp->tx_bd_num)
 894                         lp->tx_bd_tail = 0;
 895
 896                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 897                 skb_dma_addr = dma_map_single(ndev->dev.parent,
 898                                               skb_frag_address(frag),
 899                                               skb_frag_size(frag),
 900                                               DMA_TO_DEVICE);
 901                 if (dma_mapping_error(ndev->dev.parent, skb_dma_addr)) {
 902                         if (--lp->tx_bd_tail < 0)
 903                                 lp->tx_bd_tail = lp->tx_bd_num - 1;
 904                         cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 905                         while (--ii >= 0) {
 906                                 --frag;
 907                                 dma_unmap_single(ndev->dev.parent,
 908                                                  be32_to_cpu(cur_p->phys),
 909                                                  skb_frag_size(frag),
 910                                                  DMA_TO_DEVICE);
 911                                 if (--lp->tx_bd_tail < 0)
 912                                         lp->tx_bd_tail = lp->tx_bd_num - 1;
 913                                 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
 914                         }
 915                         dma_unmap_single(ndev->dev.parent,
 916                                          be32_to_cpu(cur_p->phys),
 917                                          skb_headlen(skb), DMA_TO_DEVICE);
 918                         dev_kfree_skb_any(skb);
 919                         ndev->stats.tx_dropped++;
 920                         return NETDEV_TX_OK;
 921                 }
 922                 cur_p->phys = cpu_to_be32(skb_dma_addr);
 923                 cur_p->len = cpu_to_be32(skb_frag_size(frag));
 924                 cur_p->app0 = 0;
 925                 frag++;
 926         }
 927         cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_EOP);
 928
 929         /* Mark last fragment with skb address, so it can be consumed
 930          * in temac_start_xmit_done()
 931          */
 932         ptr_to_txbd((void *)skb, cur_p);
 933
 934         tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
 935         lp->tx_bd_tail++;
 936         if (lp->tx_bd_tail >= lp->tx_bd_num)
 937                 lp->tx_bd_tail = 0;
 938
 939         skb_tx_timestamp(skb);
 940
 941         /* Kick off the transfer */
 942         wmb();
 943         lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
 944
 945         if (temac_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
 946                 netif_stop_queue(ndev);
 947
 948         return NETDEV_TX_OK;
 949 }
 950
 951 static int ll_temac_recv_buffers_available(struct temac_local *lp)
 952 {
 953         int available;
 954
 955         if (!lp->rx_skb[lp->rx_bd_ci])
 956                 return 0;
 957         available = 1 + lp->rx_bd_tail - lp->rx_bd_ci;
 958         if (available <= 0)
 959                 available += lp->rx_bd_num;
 960         return available;
 961 }
 962
 963 static void ll_temac_recv(struct net_device *ndev)
 964 {
 965         struct temac_local *lp = netdev_priv(ndev);
 966         unsigned long flags;
 967         int rx_bd;
 968         bool update_tail = false;
 969
 970         spin_lock_irqsave(&lp->rx_lock, flags);
 971
 972         /* Process all received buffers, passing them on network
 973          * stack.  After this, the buffer descriptors will be in an
 974          * un-allocated stage, where no skb is allocated for it, and
 975          * they are therefore not available for TEMAC/DMA.
 976          */
 977         do {
 978                 struct cdmac_bd *bd = &lp->rx_bd_v[lp->rx_bd_ci];
 979                 struct sk_buff *skb = lp->rx_skb[lp->rx_bd_ci];
 980                 unsigned int bdstat = be32_to_cpu(bd->app0);
 981                 int length;
 982
 983                 /* While this should not normally happen, we can end
 984                  * here when GFP_ATOMIC allocations fail, and we
 985                  * therefore have un-allocated buffers.
 986                  */
 987                 if (!skb)
 988                         break;
 989
 990                 /* Loop over all completed buffer descriptors */
 991                 if (!(bdstat & STS_CTRL_APP0_CMPLT))
 992                         break;
 993
 994                 dma_unmap_single(ndev->dev.parent, be32_to_cpu(bd->phys),
 995                                  XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
 996                 /* The buffer is not valid for DMA anymore */
 997                 bd->phys = 0;
 998                 bd->len = 0;
 999
1000                 length = be32_to_cpu(bd->app4) & 0x3FFF;
1001                 skb_put(skb, length);
1002                 skb->protocol = eth_type_trans(skb, ndev);
1003                 skb_checksum_none_assert(skb);
1004
1005                 /* if we're doing rx csum offload, set it up */
1006                 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
1007                     (skb->protocol == htons(ETH_P_IP)) &&
1008                     (skb->len > 64)) {
1009
1010                         /* Convert from device endianness (be32) to cpu
1011                          * endiannes, and if necessary swap the bytes
1012                          * (back) for proper IP checksum byte order
1013                          * (be16).
1014                          */
1015                         skb->csum = htons(be32_to_cpu(bd->app3) & 0xFFFF);
1016                         skb->ip_summed = CHECKSUM_COMPLETE;
1017                 }
1018
1019                 if (!skb_defer_rx_timestamp(skb))
1020                         netif_rx(skb);
1021                 /* The skb buffer is now owned by network stack above */
1022                 lp->rx_skb[lp->rx_bd_ci] = NULL;
1023
1024                 ndev->stats.rx_packets++;
1025                 ndev->stats.rx_bytes += length;
1026
1027                 rx_bd = lp->rx_bd_ci;
1028                 if (++lp->rx_bd_ci >= lp->rx_bd_num)
1029                         lp->rx_bd_ci = 0;
1030         } while (rx_bd != lp->rx_bd_tail);
1031
1032         /* DMA operations will halt when the last buffer descriptor is
1033          * processed (ie. the one pointed to by RX_TAILDESC_PTR).
1034          * When that happens, no more interrupt events will be
1035          * generated.  No IRQ_COAL or IRQ_DLY, and not even an
1036          * IRQ_ERR.  To avoid stalling, we schedule a delayed work
1037          * when there is a potential risk of that happening.  The work
1038          * will call this function, and thus re-schedule itself until
1039          * enough buffers are available again.
1040          */
1041         if (ll_temac_recv_buffers_available(lp) < lp->coalesce_count_rx)
1042                 schedule_delayed_work(&lp->restart_work, HZ / 1000);
1043
1044         /* Allocate new buffers for those buffer descriptors that were
1045          * passed to network stack.  Note that GFP_ATOMIC allocations
1046          * can fail (e.g. when a larger burst of GFP_ATOMIC
1047          * allocations occurs), so while we try to allocate all
1048          * buffers in the same interrupt where they were processed, we
1049          * continue with what we could get in case of allocation
1050          * failure.  Allocation of remaining buffers will be retried
1051          * in following calls.
1052          */
1053         while (1) {
1054                 struct sk_buff *skb;
1055                 struct cdmac_bd *bd;
1056                 dma_addr_t skb_dma_addr;
1057
1058                 rx_bd = lp->rx_bd_tail + 1;
1059                 if (rx_bd >= lp->rx_bd_num)
1060                         rx_bd = 0;
1061                 bd = &lp->rx_bd_v[rx_bd];
1062
1063                 if (bd->phys)
1064                         break;  /* All skb's allocated */
1065
1066                 skb = netdev_alloc_skb_ip_align(ndev, XTE_MAX_JUMBO_FRAME_SIZE);
1067                 if (!skb) {
1068                         dev_warn(&ndev->dev, "skb alloc failed\n");
1069                         break;
1070                 }
1071
1072                 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
1073                                               XTE_MAX_JUMBO_FRAME_SIZE,
1074                                               DMA_FROM_DEVICE);
1075                 if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent,
1076                                                    skb_dma_addr))) {
1077                         dev_kfree_skb_any(skb);
1078                         break;
1079                 }
1080
1081                 bd->phys = cpu_to_be32(skb_dma_addr);
1082                 bd->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
1083                 bd->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
1084                 lp->rx_skb[rx_bd] = skb;
1085
1086                 lp->rx_bd_tail = rx_bd;
1087                 update_tail = true;
1088         }
1089
1090         /* Move tail pointer when buffers have been allocated */
1091         if (update_tail) {
1092                 lp->dma_out(lp, RX_TAILDESC_PTR,
1093                         lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_tail);
1094         }
1095
1096         spin_unlock_irqrestore(&lp->rx_lock, flags);
1097 }
1098
1099 /* Function scheduled to ensure a restart in case of DMA halt
1100  * condition caused by running out of buffer descriptors.
1101  */
1102 static void ll_temac_restart_work_func(struct work_struct *work)
1103 {
1104         struct temac_local *lp = container_of(work, struct temac_local,
1105                                               restart_work.work);
1106         struct net_device *ndev = lp->ndev;
1107
1108         ll_temac_recv(ndev);
1109 }
1110
1111 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
1112 {
1113         struct net_device *ndev = _ndev;
1114         struct temac_local *lp = netdev_priv(ndev);
1115         unsigned int status;
1116
1117         status = lp->dma_in(lp, TX_IRQ_REG);
1118         lp->dma_out(lp, TX_IRQ_REG, status);
1119
1120         if (status & (IRQ_COAL | IRQ_DLY))
1121                 temac_start_xmit_done(lp->ndev);
1122         if (status & (IRQ_ERR | IRQ_DMAERR))
1123                 dev_err_ratelimited(&ndev->dev,
1124                                     "TX error 0x%x TX_CHNL_STS=0x%08x\n",
1125                                     status, lp->dma_in(lp, TX_CHNL_STS));
1126
1127         return IRQ_HANDLED;
1128 }
1129
1130 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
1131 {
1132         struct net_device *ndev = _ndev;
1133         struct temac_local *lp = netdev_priv(ndev);
1134         unsigned int status;
1135
1136         /* Read and clear the status registers */
1137         status = lp->dma_in(lp, RX_IRQ_REG);
1138         lp->dma_out(lp, RX_IRQ_REG, status);
1139
1140         if (status & (IRQ_COAL | IRQ_DLY))
1141                 ll_temac_recv(lp->ndev);
1142         if (status & (IRQ_ERR | IRQ_DMAERR))
1143                 dev_err_ratelimited(&ndev->dev,
1144                                     "RX error 0x%x RX_CHNL_STS=0x%08x\n",
1145                                     status, lp->dma_in(lp, RX_CHNL_STS));
1146
1147         return IRQ_HANDLED;
1148 }
1149
1150 static int temac_open(struct net_device *ndev)
1151 {
1152         struct temac_local *lp = netdev_priv(ndev);
1153         struct phy_device *phydev = NULL;
1154         int rc;
1155
1156         dev_dbg(&ndev->dev, "temac_open()\n");
1157
1158         if (lp->phy_node) {
1159                 phydev = of_phy_connect(lp->ndev, lp->phy_node,
1160                                         temac_adjust_link, 0, 0);
1161                 if (!phydev) {
1162                         dev_err(lp->dev, "of_phy_connect() failed\n");
1163                         return -ENODEV;
1164                 }
1165                 phy_start(phydev);
1166         } else if (strlen(lp->phy_name) > 0) {
1167                 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link,
1168                                      lp->phy_interface);
1169                 if (IS_ERR(phydev)) {
1170                         dev_err(lp->dev, "phy_connect() failed\n");
1171                         return PTR_ERR(phydev);
1172                 }
1173                 phy_start(phydev);
1174         }
1175
1176         temac_device_reset(ndev);
1177
1178         rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
1179         if (rc)
1180                 goto err_tx_irq;
1181         rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
1182         if (rc)
1183                 goto err_rx_irq;
1184
1185         return 0;
1186
1187  err_rx_irq:
1188         free_irq(lp->tx_irq, ndev);
1189  err_tx_irq:
1190         if (phydev)
1191                 phy_disconnect(phydev);
1192         dev_err(lp->dev, "request_irq() failed\n");
1193         return rc;
1194 }
1195
1196 static int temac_stop(struct net_device *ndev)
1197 {
1198         struct temac_local *lp = netdev_priv(ndev);
1199         struct phy_device *phydev = ndev->phydev;
1200
1201         dev_dbg(&ndev->dev, "temac_close()\n");
1202
1203         cancel_delayed_work_sync(&lp->restart_work);
1204
1205         free_irq(lp->tx_irq, ndev);
1206         free_irq(lp->rx_irq, ndev);
1207
1208         if (phydev)
1209                 phy_disconnect(phydev);
1210
1211         temac_dma_bd_release(ndev);
1212
1213         return 0;
1214 }
1215
1216 #ifdef CONFIG_NET_POLL_CONTROLLER
1217 static void
1218 temac_poll_controller(struct net_device *ndev)
1219 {
1220         struct temac_local *lp = netdev_priv(ndev);
1221
1222         disable_irq(lp->tx_irq);
1223         disable_irq(lp->rx_irq);
1224
1225         ll_temac_rx_irq(lp->tx_irq, ndev);
1226         ll_temac_tx_irq(lp->rx_irq, ndev);
1227
1228         enable_irq(lp->tx_irq);
1229         enable_irq(lp->rx_irq);
1230 }
1231 #endif
1232
1233 static const struct net_device_ops temac_netdev_ops = {
1234         .ndo_open = temac_open,
1235         .ndo_stop = temac_stop,
1236         .ndo_start_xmit = temac_start_xmit,
1237         .ndo_set_rx_mode = temac_set_multicast_list,
1238         .ndo_set_mac_address = temac_set_mac_address,
1239         .ndo_validate_addr = eth_validate_addr,
1240         .ndo_eth_ioctl = phy_do_ioctl_running,
1241 #ifdef CONFIG_NET_POLL_CONTROLLER
1242         .ndo_poll_controller = temac_poll_controller,
1243 #endif
1244 };
1245
1246 /* ---------------------------------------------------------------------
1247  * SYSFS device attributes
1248  */
1249 static ssize_t temac_show_llink_regs(struct device *dev,
1250                                      struct device_attribute *attr, char *buf)
1251 {
1252         struct net_device *ndev = dev_get_drvdata(dev);
1253         struct temac_local *lp = netdev_priv(ndev);
1254         int i, len = 0;
1255
1256         for (i = 0; i < 0x11; i++)
1257                 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
1258                                (i % 8) == 7 ? "\n" : " ");
1259         len += sprintf(buf + len, "\n");
1260
1261         return len;
1262 }
1263
1264 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
1265
1266 static struct attribute *temac_device_attrs[] = {
1267         &dev_attr_llink_regs.attr,
1268         NULL,
1269 };
1270
1271 static const struct attribute_group temac_attr_group = {
1272         .attrs = temac_device_attrs,
1273 };
1274
1275 /* ---------------------------------------------------------------------
1276  * ethtool support
1277  */
1278
1279 static void
1280 ll_temac_ethtools_get_ringparam(struct net_device *ndev,
1281                                 struct ethtool_ringparam *ering,
1282                                 struct kernel_ethtool_ringparam *kernel_ering,
1283                                 struct netlink_ext_ack *extack)
1284 {
1285         struct temac_local *lp = netdev_priv(ndev);
1286
1287         ering->rx_max_pending = RX_BD_NUM_MAX;
1288         ering->rx_mini_max_pending = 0;
1289         ering->rx_jumbo_max_pending = 0;
1290         ering->tx_max_pending = TX_BD_NUM_MAX;
1291         ering->rx_pending = lp->rx_bd_num;
1292         ering->rx_mini_pending = 0;
1293         ering->rx_jumbo_pending = 0;
1294         ering->tx_pending = lp->tx_bd_num;
1295 }
1296
1297 static int
1298 ll_temac_ethtools_set_ringparam(struct net_device *ndev,
1299                                 struct ethtool_ringparam *ering,
1300                                 struct kernel_ethtool_ringparam *kernel_ering,
1301                                 struct netlink_ext_ack *extack)
1302 {
1303         struct temac_local *lp = netdev_priv(ndev);
1304
1305         if (ering->rx_pending > RX_BD_NUM_MAX ||
1306             ering->rx_mini_pending ||
1307             ering->rx_jumbo_pending ||
1308             ering->rx_pending > TX_BD_NUM_MAX)
1309                 return -EINVAL;
1310
1311         if (netif_running(ndev))
1312                 return -EBUSY;
1313
1314         lp->rx_bd_num = ering->rx_pending;
1315         lp->tx_bd_num = ering->tx_pending;
1316         return 0;
1317 }
1318
1319 static int
1320 ll_temac_ethtools_get_coalesce(struct net_device *ndev,
1321                                struct ethtool_coalesce *ec,
1322                                struct kernel_ethtool_coalesce *kernel_coal,
1323                                struct netlink_ext_ack *extack)
1324 {
1325         struct temac_local *lp = netdev_priv(ndev);
1326
1327         ec->rx_max_coalesced_frames = lp->coalesce_count_rx;
1328         ec->tx_max_coalesced_frames = lp->coalesce_count_tx;
1329         ec->rx_coalesce_usecs = (lp->coalesce_delay_rx * 512) / 100;
1330         ec->tx_coalesce_usecs = (lp->coalesce_delay_tx * 512) / 100;
1331         return 0;
1332 }
1333
1334 static int
1335 ll_temac_ethtools_set_coalesce(struct net_device *ndev,
1336                                struct ethtool_coalesce *ec,
1337                                struct kernel_ethtool_coalesce *kernel_coal,
1338                                struct netlink_ext_ack *extack)
1339 {
1340         struct temac_local *lp = netdev_priv(ndev);
1341
1342         if (netif_running(ndev)) {
1343                 netdev_err(ndev,
1344                            "Please stop netif before applying configuration\n");
1345                 return -EFAULT;
1346         }
1347
1348         if (ec->rx_max_coalesced_frames)
1349                 lp->coalesce_count_rx = ec->rx_max_coalesced_frames;
1350         if (ec->tx_max_coalesced_frames)
1351                 lp->coalesce_count_tx = ec->tx_max_coalesced_frames;
1352         /* With typical LocalLink clock speed of 200 MHz and
1353          * C_PRESCALAR=1023, each delay count corresponds to 5.12 us.
1354          */
1355         if (ec->rx_coalesce_usecs)
1356                 lp->coalesce_delay_rx =
1357                         min(255U, (ec->rx_coalesce_usecs * 100) / 512);
1358         if (ec->tx_coalesce_usecs)
1359                 lp->coalesce_delay_tx =
1360                         min(255U, (ec->tx_coalesce_usecs * 100) / 512);
1361
1362         return 0;
1363 }
1364
1365 static const struct ethtool_ops temac_ethtool_ops = {
1366         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1367                                      ETHTOOL_COALESCE_MAX_FRAMES,
1368         .nway_reset = phy_ethtool_nway_reset,
1369         .get_link = ethtool_op_get_link,
1370         .get_ts_info = ethtool_op_get_ts_info,
1371         .get_link_ksettings = phy_ethtool_get_link_ksettings,
1372         .set_link_ksettings = phy_ethtool_set_link_ksettings,
1373         .get_ringparam  = ll_temac_ethtools_get_ringparam,
1374         .set_ringparam  = ll_temac_ethtools_set_ringparam,
1375         .get_coalesce   = ll_temac_ethtools_get_coalesce,
1376         .set_coalesce   = ll_temac_ethtools_set_coalesce,
1377 };
1378
1379 static int temac_probe(struct platform_device *pdev)
1380 {
1381         struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1382         struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;
1383         struct temac_local *lp;
1384         struct net_device *ndev;
1385         u8 addr[ETH_ALEN];
1386         __be32 *p;
1387         bool little_endian;
1388         int rc = 0;
1389
1390         /* Init network device structure */
1391         ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));
1392         if (!ndev)
1393                 return -ENOMEM;
1394
1395         platform_set_drvdata(pdev, ndev);
1396         SET_NETDEV_DEV(ndev, &pdev->dev);
1397         ndev->features = NETIF_F_SG;
1398         ndev->netdev_ops = &temac_netdev_ops;
1399         ndev->ethtool_ops = &temac_ethtool_ops;
1400 #if 0
1401         ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1402         ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1403         ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1404         ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1405         ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1406         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1407         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1408         ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1409         ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1410         ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1411         ndev->features |= NETIF_F_LRO; /* large receive offload */
1412 #endif
1413
1414         /* setup temac private info structure */
1415         lp = netdev_priv(ndev);
1416         lp->ndev = ndev;
1417         lp->dev = &pdev->dev;
1418         lp->options = XTE_OPTION_DEFAULTS;
1419         lp->rx_bd_num = RX_BD_NUM_DEFAULT;
1420         lp->tx_bd_num = TX_BD_NUM_DEFAULT;
1421         spin_lock_init(&lp->rx_lock);
1422         INIT_DELAYED_WORK(&lp->restart_work, ll_temac_restart_work_func);
1423
1424         /* Setup mutex for synchronization of indirect register access */
1425         if (pdata) {
1426                 if (!pdata->indirect_lock) {
1427                         dev_err(&pdev->dev,
1428                                 "indirect_lock missing in platform_data\n");
1429                         return -EINVAL;
1430                 }
1431                 lp->indirect_lock = pdata->indirect_lock;
1432         } else {
1433                 lp->indirect_lock = devm_kmalloc(&pdev->dev,
1434                                                  sizeof(*lp->indirect_lock),
1435                                                  GFP_KERNEL);
1436                 spin_lock_init(lp->indirect_lock);
1437         }
1438
1439         /* map device registers */
1440         lp->regs = devm_platform_ioremap_resource_byname(pdev, 0);
1441         if (IS_ERR(lp->regs)) {
1442                 dev_err(&pdev->dev, "could not map TEMAC registers\n");
1443                 return -ENOMEM;
1444         }
1445
1446         /* Select register access functions with the specified
1447          * endianness mode.  Default for OF devices is big-endian.
1448          */
1449         little_endian = false;
1450         if (temac_np) {
1451                 if (of_get_property(temac_np, "little-endian", NULL))
1452                         little_endian = true;
1453         } else if (pdata) {
1454                 little_endian = pdata->reg_little_endian;
1455         }
1456         if (little_endian) {
1457                 lp->temac_ior = _temac_ior_le;
1458                 lp->temac_iow = _temac_iow_le;
1459         } else {
1460                 lp->temac_ior = _temac_ior_be;
1461                 lp->temac_iow = _temac_iow_be;
1462         }
1463
1464         /* Setup checksum offload, but default to off if not specified */
1465         lp->temac_features = 0;
1466         if (temac_np) {
1467                 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL);
1468                 if (p && be32_to_cpu(*p))
1469                         lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1470                 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL);
1471                 if (p && be32_to_cpu(*p))
1472                         lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1473         } else if (pdata) {
1474                 if (pdata->txcsum)
1475                         lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1476                 if (pdata->rxcsum)
1477                         lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1478         }
1479         if (lp->temac_features & TEMAC_FEATURE_TX_CSUM)
1480                 /* Can checksum TCP/UDP over IPv4. */
1481                 ndev->features |= NETIF_F_IP_CSUM;
1482
1483         /* Defaults for IRQ delay/coalescing setup.  These are
1484          * configuration values, so does not belong in device-tree.
1485          */
1486         lp->coalesce_delay_tx = 0x10;
1487         lp->coalesce_count_tx = 0x22;
1488         lp->coalesce_delay_rx = 0xff;
1489         lp->coalesce_count_rx = 0x07;
1490
1491         /* Setup LocalLink DMA */
1492         if (temac_np) {
1493                 /* Find the DMA node, map the DMA registers, and
1494                  * decode the DMA IRQs.
1495                  */
1496                 dma_np = of_parse_phandle(temac_np, "llink-connected", 0);
1497                 if (!dma_np) {
1498                         dev_err(&pdev->dev, "could not find DMA node\n");
1499                         return -ENODEV;
1500                 }
1501
1502                 /* Setup the DMA register accesses, could be DCR or
1503                  * memory mapped.
1504                  */
1505                 if (temac_dcr_setup(lp, pdev, dma_np)) {
1506                         /* no DCR in the device tree, try non-DCR */
1507                         lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0,
1508                                                       NULL);
1509                         if (IS_ERR(lp->sdma_regs)) {
1510                                 dev_err(&pdev->dev,
1511                                         "unable to map DMA registers\n");
1512                                 of_node_put(dma_np);
1513                                 return PTR_ERR(lp->sdma_regs);
1514                         }
1515                         if (of_get_property(dma_np, "little-endian", NULL)) {
1516                                 lp->dma_in = temac_dma_in32_le;
1517                                 lp->dma_out = temac_dma_out32_le;
1518                         } else {
1519                                 lp->dma_in = temac_dma_in32_be;
1520                                 lp->dma_out = temac_dma_out32_be;
1521                         }
1522                         dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs);
1523                 }
1524
1525                 /* Get DMA RX and TX interrupts */
1526                 lp->rx_irq = irq_of_parse_and_map(dma_np, 0);
1527                 lp->tx_irq = irq_of_parse_and_map(dma_np, 1);
1528
1529                 /* Finished with the DMA node; drop the reference */
1530                 of_node_put(dma_np);
1531         } else if (pdata) {
1532                 /* 2nd memory resource specifies DMA registers */
1533                 lp->sdma_regs = devm_platform_ioremap_resource(pdev, 1);
1534                 if (IS_ERR(lp->sdma_regs)) {
1535                         dev_err(&pdev->dev,
1536                                 "could not map DMA registers\n");
1537                         return PTR_ERR(lp->sdma_regs);
1538                 }
1539                 if (pdata->dma_little_endian) {
1540                         lp->dma_in = temac_dma_in32_le;
1541                         lp->dma_out = temac_dma_out32_le;
1542                 } else {
1543                         lp->dma_in = temac_dma_in32_be;
1544                         lp->dma_out = temac_dma_out32_be;
1545                 }
1546
1547                 /* Get DMA RX and TX interrupts */
1548                 lp->rx_irq = platform_get_irq(pdev, 0);
1549                 lp->tx_irq = platform_get_irq(pdev, 1);
1550
1551                 /* IRQ delay/coalescing setup */
1552                 if (pdata->tx_irq_timeout || pdata->tx_irq_count) {
1553                         lp->coalesce_delay_tx = pdata->tx_irq_timeout;
1554                         lp->coalesce_count_tx = pdata->tx_irq_count;
1555                 }
1556                 if (pdata->rx_irq_timeout || pdata->rx_irq_count) {
1557                         lp->coalesce_delay_rx = pdata->rx_irq_timeout;
1558                         lp->coalesce_count_rx = pdata->rx_irq_count;
1559                 }
1560         }
1561
1562         /* Error handle returned DMA RX and TX interrupts */
1563         if (lp->rx_irq < 0) {
1564                 if (lp->rx_irq != -EPROBE_DEFER)
1565                         dev_err(&pdev->dev, "could not get DMA RX irq\n");
1566                 return lp->rx_irq;
1567         }
1568         if (lp->tx_irq < 0) {
1569                 if (lp->tx_irq != -EPROBE_DEFER)
1570                         dev_err(&pdev->dev, "could not get DMA TX irq\n");
1571                 return lp->tx_irq;
1572         }
1573
1574         if (temac_np) {
1575                 /* Retrieve the MAC address */
1576                 rc = of_get_mac_address(temac_np, addr);
1577                 if (rc) {
1578                         dev_err(&pdev->dev, "could not find MAC address\n");
1579                         return -ENODEV;
1580                 }
1581                 temac_init_mac_address(ndev, addr);
1582         } else if (pdata) {
1583                 temac_init_mac_address(ndev, pdata->mac_addr);
1584         }
1585
1586         rc = temac_mdio_setup(lp, pdev);
1587         if (rc)
1588                 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1589
1590         if (temac_np) {
1591                 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0);
1592                 if (lp->phy_node)
1593                         dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np);
1594         } else if (pdata) {
1595                 snprintf(lp->phy_name, sizeof(lp->phy_name),
1596                          PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr);
1597                 lp->phy_interface = pdata->phy_interface;
1598         }
1599
1600         /* Add the device attributes */
1601         rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1602         if (rc) {
1603                 dev_err(lp->dev, "Error creating sysfs files\n");
1604                 goto err_sysfs_create;
1605         }
1606
1607         rc = register_netdev(lp->ndev);
1608         if (rc) {
1609                 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1610                 goto err_register_ndev;
1611         }
1612
1613         return 0;
1614
1615 err_register_ndev:
1616         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1617 err_sysfs_create:
1618         if (lp->phy_node)
1619                 of_node_put(lp->phy_node);
1620         temac_mdio_teardown(lp);
1621         return rc;
1622 }
1623
1624 static int temac_remove(struct platform_device *pdev)
1625 {
1626         struct net_device *ndev = platform_get_drvdata(pdev);
1627         struct temac_local *lp = netdev_priv(ndev);
1628
1629         unregister_netdev(ndev);
1630         sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1631         if (lp->phy_node)
1632                 of_node_put(lp->phy_node);
1633         temac_mdio_teardown(lp);
1634         return 0;
1635 }
1636
1637 static const struct of_device_id temac_of_match[] = {
1638         { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1639         { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1640         { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1641         { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1642         {},
1643 };
1644 MODULE_DEVICE_TABLE(of, temac_of_match);
1645
1646 static struct platform_driver temac_driver = {
1647         .probe = temac_probe,
1648         .remove = temac_remove,
1649         .driver = {
1650                 .name = "xilinx_temac",
1651                 .of_match_table = temac_of_match,
1652         },
1653 };
1654
1655 module_platform_driver(temac_driver);
1656
1657 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1658 MODULE_AUTHOR("Yoshio Kashiwagi");
1659 MODULE_LICENSE("GPL");