2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
38 #include <linux/of_device.h>
39 #include <linux/of_irq.h>
40 #include <linux/of_mdio.h>
41 #include <linux/of_platform.h>
42 #include <linux/of_address.h>
43 #include <linux/skbuff.h>
44 #include <linux/spinlock.h>
45 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
46 #include <linux/udp.h> /* needed for sizeof(udphdr) */
47 #include <linux/phy.h>
51 #include <linux/slab.h>
52 #include <linux/interrupt.h>
53 #include <linux/dma-mapping.h>
60 /* ---------------------------------------------------------------------
61 * Low level register access functions
64 u32 temac_ior(struct temac_local *lp, int offset)
66 return in_be32((u32 *)(lp->regs + offset));
69 void temac_iow(struct temac_local *lp, int offset, u32 value)
71 out_be32((u32 *) (lp->regs + offset), value);
74 int temac_indirect_busywait(struct temac_local *lp)
76 long end = jiffies + 2;
78 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
79 if (end - jiffies <= 0) {
91 * lp->indirect_mutex must be held when calling this function
93 u32 temac_indirect_in32(struct temac_local *lp, int reg)
97 if (temac_indirect_busywait(lp))
99 temac_iow(lp, XTE_CTL0_OFFSET, reg);
100 if (temac_indirect_busywait(lp))
102 val = temac_ior(lp, XTE_LSW0_OFFSET);
108 * temac_indirect_out32
110 * lp->indirect_mutex must be held when calling this function
112 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
114 if (temac_indirect_busywait(lp))
116 temac_iow(lp, XTE_LSW0_OFFSET, value);
117 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
118 temac_indirect_busywait(lp);
122 * temac_dma_in32 - Memory mapped DMA read, this function expects a
123 * register input that is based on DCR word addresses which
124 * are then converted to memory mapped byte addresses
126 static u32 temac_dma_in32(struct temac_local *lp, int reg)
128 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
132 * temac_dma_out32 - Memory mapped DMA read, this function expects a
133 * register input that is based on DCR word addresses which
134 * are then converted to memory mapped byte addresses
136 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
138 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
141 /* DMA register access functions can be DCR based or memory mapped.
142 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
145 #ifdef CONFIG_PPC_DCR
148 * temac_dma_dcr_in32 - DCR based DMA read
150 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
152 return dcr_read(lp->sdma_dcrs, reg);
156 * temac_dma_dcr_out32 - DCR based DMA write
158 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
160 dcr_write(lp->sdma_dcrs, reg, value);
164 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
167 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
168 struct device_node *np)
172 /* setup the dcr address mapping if it's in the device tree */
174 dcrs = dcr_resource_start(np, 0);
176 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
177 lp->dma_in = temac_dma_dcr_in;
178 lp->dma_out = temac_dma_dcr_out;
179 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
182 /* no DCR in the device tree, indicate a failure */
189 * temac_dcr_setup - This is a stub for when DCR is not supported,
190 * such as with MicroBlaze
192 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
193 struct device_node *np)
201 * temac_dma_bd_release - Release buffer descriptor rings
203 static void temac_dma_bd_release(struct net_device *ndev)
205 struct temac_local *lp = netdev_priv(ndev);
208 /* Reset Local Link (DMA) */
209 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
211 for (i = 0; i < RX_BD_NUM; i++) {
215 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
216 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
217 dev_kfree_skb(lp->rx_skb[i]);
221 dma_free_coherent(ndev->dev.parent,
222 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
223 lp->rx_bd_v, lp->rx_bd_p);
225 dma_free_coherent(ndev->dev.parent,
226 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
227 lp->tx_bd_v, lp->tx_bd_p);
233 * temac_dma_bd_init - Setup buffer descriptor rings
235 static int temac_dma_bd_init(struct net_device *ndev)
237 struct temac_local *lp = netdev_priv(ndev);
241 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
245 /* allocate the tx and rx ring buffer descriptors. */
246 /* returns a virtual address and a physical address. */
247 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
248 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
249 &lp->tx_bd_p, GFP_KERNEL);
253 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
254 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
255 &lp->rx_bd_p, GFP_KERNEL);
259 for (i = 0; i < TX_BD_NUM; i++) {
260 lp->tx_bd_v[i].next = lp->tx_bd_p +
261 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
264 for (i = 0; i < RX_BD_NUM; i++) {
265 lp->rx_bd_v[i].next = lp->rx_bd_p +
266 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
268 skb = netdev_alloc_skb_ip_align(ndev,
269 XTE_MAX_JUMBO_FRAME_SIZE);
274 /* returns physical address of skb->data */
275 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
277 XTE_MAX_JUMBO_FRAME_SIZE,
279 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
280 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
283 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
285 CHNL_CTRL_IRQ_DLY_EN |
286 CHNL_CTRL_IRQ_COAL_EN);
289 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
291 CHNL_CTRL_IRQ_DLY_EN |
292 CHNL_CTRL_IRQ_COAL_EN |
296 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
297 lp->dma_out(lp, RX_TAILDESC_PTR,
298 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
299 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
301 /* Init descriptor indexes */
310 temac_dma_bd_release(ndev);
314 /* ---------------------------------------------------------------------
318 static void temac_do_set_mac_address(struct net_device *ndev)
320 struct temac_local *lp = netdev_priv(ndev);
322 /* set up unicast MAC address filter set its mac address */
323 mutex_lock(&lp->indirect_mutex);
324 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
325 (ndev->dev_addr[0]) |
326 (ndev->dev_addr[1] << 8) |
327 (ndev->dev_addr[2] << 16) |
328 (ndev->dev_addr[3] << 24));
329 /* There are reserved bits in EUAW1
330 * so don't affect them Set MAC bits [47:32] in EUAW1 */
331 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
332 (ndev->dev_addr[4] & 0x000000ff) |
333 (ndev->dev_addr[5] << 8));
334 mutex_unlock(&lp->indirect_mutex);
337 static int temac_init_mac_address(struct net_device *ndev, void *address)
339 memcpy(ndev->dev_addr, address, ETH_ALEN);
340 if (!is_valid_ether_addr(ndev->dev_addr))
341 eth_hw_addr_random(ndev);
342 temac_do_set_mac_address(ndev);
346 static int temac_set_mac_address(struct net_device *ndev, void *p)
348 struct sockaddr *addr = p;
350 if (!is_valid_ether_addr(addr->sa_data))
351 return -EADDRNOTAVAIL;
352 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
353 temac_do_set_mac_address(ndev);
357 static void temac_set_multicast_list(struct net_device *ndev)
359 struct temac_local *lp = netdev_priv(ndev);
360 u32 multi_addr_msw, multi_addr_lsw, val;
363 mutex_lock(&lp->indirect_mutex);
364 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
365 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
367 * We must make the kernel realise we had to move
368 * into promisc mode or we start all out war on
369 * the cable. If it was a promisc request the
370 * flag is already set. If not we assert it.
372 ndev->flags |= IFF_PROMISC;
373 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
374 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
375 } else if (!netdev_mc_empty(ndev)) {
376 struct netdev_hw_addr *ha;
379 netdev_for_each_mc_addr(ha, ndev) {
380 if (i >= MULTICAST_CAM_TABLE_NUM)
382 multi_addr_msw = ((ha->addr[3] << 24) |
383 (ha->addr[2] << 16) |
386 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
388 multi_addr_lsw = ((ha->addr[5] << 8) |
389 (ha->addr[4]) | (i << 16));
390 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
395 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
396 temac_indirect_out32(lp, XTE_AFM_OFFSET,
397 val & ~XTE_AFM_EPPRM_MASK);
398 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
399 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
400 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
402 mutex_unlock(&lp->indirect_mutex);
405 struct temac_option {
411 } temac_options[] = {
412 /* Turn on jumbo packet support for both Rx and Tx */
414 .opt = XTE_OPTION_JUMBO,
415 .reg = XTE_TXC_OFFSET,
416 .m_or = XTE_TXC_TXJMBO_MASK,
419 .opt = XTE_OPTION_JUMBO,
420 .reg = XTE_RXC1_OFFSET,
421 .m_or =XTE_RXC1_RXJMBO_MASK,
423 /* Turn on VLAN packet support for both Rx and Tx */
425 .opt = XTE_OPTION_VLAN,
426 .reg = XTE_TXC_OFFSET,
427 .m_or =XTE_TXC_TXVLAN_MASK,
430 .opt = XTE_OPTION_VLAN,
431 .reg = XTE_RXC1_OFFSET,
432 .m_or =XTE_RXC1_RXVLAN_MASK,
434 /* Turn on FCS stripping on receive packets */
436 .opt = XTE_OPTION_FCS_STRIP,
437 .reg = XTE_RXC1_OFFSET,
438 .m_or =XTE_RXC1_RXFCS_MASK,
440 /* Turn on FCS insertion on transmit packets */
442 .opt = XTE_OPTION_FCS_INSERT,
443 .reg = XTE_TXC_OFFSET,
444 .m_or =XTE_TXC_TXFCS_MASK,
446 /* Turn on length/type field checking on receive packets */
448 .opt = XTE_OPTION_LENTYPE_ERR,
449 .reg = XTE_RXC1_OFFSET,
450 .m_or =XTE_RXC1_RXLT_MASK,
452 /* Turn on flow control */
454 .opt = XTE_OPTION_FLOW_CONTROL,
455 .reg = XTE_FCC_OFFSET,
456 .m_or =XTE_FCC_RXFLO_MASK,
458 /* Turn on flow control */
460 .opt = XTE_OPTION_FLOW_CONTROL,
461 .reg = XTE_FCC_OFFSET,
462 .m_or =XTE_FCC_TXFLO_MASK,
464 /* Turn on promiscuous frame filtering (all frames are received ) */
466 .opt = XTE_OPTION_PROMISC,
467 .reg = XTE_AFM_OFFSET,
468 .m_or =XTE_AFM_EPPRM_MASK,
470 /* Enable transmitter if not already enabled */
472 .opt = XTE_OPTION_TXEN,
473 .reg = XTE_TXC_OFFSET,
474 .m_or =XTE_TXC_TXEN_MASK,
476 /* Enable receiver? */
478 .opt = XTE_OPTION_RXEN,
479 .reg = XTE_RXC1_OFFSET,
480 .m_or =XTE_RXC1_RXEN_MASK,
488 static u32 temac_setoptions(struct net_device *ndev, u32 options)
490 struct temac_local *lp = netdev_priv(ndev);
491 struct temac_option *tp = &temac_options[0];
494 mutex_lock(&lp->indirect_mutex);
496 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
497 if (options & tp->opt)
499 temac_indirect_out32(lp, tp->reg, reg);
502 lp->options |= options;
503 mutex_unlock(&lp->indirect_mutex);
508 /* Initialize temac */
509 static void temac_device_reset(struct net_device *ndev)
511 struct temac_local *lp = netdev_priv(ndev);
515 /* Perform a software reset */
517 /* 0x300 host enable bit ? */
518 /* reset PHY through control register ?:1 */
520 dev_dbg(&ndev->dev, "%s()\n", __func__);
522 mutex_lock(&lp->indirect_mutex);
523 /* Reset the receiver and wait for it to finish reset */
524 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
526 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
528 if (--timeout == 0) {
530 "temac_device_reset RX reset timeout!!\n");
535 /* Reset the transmitter and wait for it to finish reset */
536 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
538 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
540 if (--timeout == 0) {
542 "temac_device_reset TX reset timeout!!\n");
547 /* Disable the receiver */
548 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
549 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
551 /* Reset Local Link (DMA) */
552 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
554 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
556 if (--timeout == 0) {
558 "temac_device_reset DMA reset timeout!!\n");
562 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
564 if (temac_dma_bd_init(ndev)) {
566 "temac_device_reset descriptor allocation failed\n");
569 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
570 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
571 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
572 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
574 mutex_unlock(&lp->indirect_mutex);
576 /* Sync default options with HW
577 * but leave receiver and transmitter disabled. */
578 temac_setoptions(ndev,
579 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
581 temac_do_set_mac_address(ndev);
583 /* Set address filter table */
584 temac_set_multicast_list(ndev);
585 if (temac_setoptions(ndev, lp->options))
586 dev_err(&ndev->dev, "Error setting TEMAC options\n");
588 /* Init Driver variable */
589 ndev->trans_start = jiffies; /* prevent tx timeout */
592 void temac_adjust_link(struct net_device *ndev)
594 struct temac_local *lp = netdev_priv(ndev);
595 struct phy_device *phy = lp->phy_dev;
599 /* hash together the state values to decide if something has changed */
600 link_state = phy->speed | (phy->duplex << 1) | phy->link;
602 mutex_lock(&lp->indirect_mutex);
603 if (lp->last_link != link_state) {
604 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
605 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
607 switch (phy->speed) {
608 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
609 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
610 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
613 /* Write new speed setting out to TEMAC */
614 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
615 lp->last_link = link_state;
616 phy_print_status(phy);
618 mutex_unlock(&lp->indirect_mutex);
621 static void temac_start_xmit_done(struct net_device *ndev)
623 struct temac_local *lp = netdev_priv(ndev);
624 struct cdmac_bd *cur_p;
625 unsigned int stat = 0;
627 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
630 while (stat & STS_CTRL_APP0_CMPLT) {
631 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
634 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
641 ndev->stats.tx_packets++;
642 ndev->stats.tx_bytes += cur_p->len;
645 if (lp->tx_bd_ci >= TX_BD_NUM)
648 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
652 netif_wake_queue(ndev);
655 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
657 struct cdmac_bd *cur_p;
660 tail = lp->tx_bd_tail;
661 cur_p = &lp->tx_bd_v[tail];
665 return NETDEV_TX_BUSY;
668 if (tail >= TX_BD_NUM)
671 cur_p = &lp->tx_bd_v[tail];
673 } while (num_frag >= 0);
678 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
680 struct temac_local *lp = netdev_priv(ndev);
681 struct cdmac_bd *cur_p;
682 dma_addr_t start_p, tail_p;
684 unsigned long num_frag;
687 num_frag = skb_shinfo(skb)->nr_frags;
688 frag = &skb_shinfo(skb)->frags[0];
689 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
690 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
692 if (temac_check_tx_bd_space(lp, num_frag)) {
693 if (!netif_queue_stopped(ndev)) {
694 netif_stop_queue(ndev);
695 return NETDEV_TX_BUSY;
697 return NETDEV_TX_BUSY;
701 if (skb->ip_summed == CHECKSUM_PARTIAL) {
702 unsigned int csum_start_off = skb_checksum_start_offset(skb);
703 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
705 cur_p->app0 |= 1; /* TX Checksum Enabled */
706 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
707 cur_p->app2 = 0; /* initial checksum seed */
710 cur_p->app0 |= STS_CTRL_APP0_SOP;
711 cur_p->len = skb_headlen(skb);
712 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
714 cur_p->app4 = (unsigned long)skb;
716 for (ii = 0; ii < num_frag; ii++) {
718 if (lp->tx_bd_tail >= TX_BD_NUM)
721 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
722 cur_p->phys = dma_map_single(ndev->dev.parent,
723 skb_frag_address(frag),
724 skb_frag_size(frag), DMA_TO_DEVICE);
725 cur_p->len = skb_frag_size(frag);
729 cur_p->app0 |= STS_CTRL_APP0_EOP;
731 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
733 if (lp->tx_bd_tail >= TX_BD_NUM)
736 skb_tx_timestamp(skb);
738 /* Kick off the transfer */
739 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
745 static void ll_temac_recv(struct net_device *ndev)
747 struct temac_local *lp = netdev_priv(ndev);
748 struct sk_buff *skb, *new_skb;
750 struct cdmac_bd *cur_p;
755 spin_lock_irqsave(&lp->rx_lock, flags);
757 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
758 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
760 bdstat = cur_p->app0;
761 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
763 skb = lp->rx_skb[lp->rx_bd_ci];
764 length = cur_p->app4 & 0x3FFF;
766 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
769 skb_put(skb, length);
770 skb->protocol = eth_type_trans(skb, ndev);
771 skb_checksum_none_assert(skb);
773 /* if we're doing rx csum offload, set it up */
774 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
775 (skb->protocol == __constant_htons(ETH_P_IP)) &&
778 skb->csum = cur_p->app3 & 0xFFFF;
779 skb->ip_summed = CHECKSUM_COMPLETE;
782 if (!skb_defer_rx_timestamp(skb))
785 ndev->stats.rx_packets++;
786 ndev->stats.rx_bytes += length;
788 new_skb = netdev_alloc_skb_ip_align(ndev,
789 XTE_MAX_JUMBO_FRAME_SIZE);
791 spin_unlock_irqrestore(&lp->rx_lock, flags);
795 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
796 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
797 XTE_MAX_JUMBO_FRAME_SIZE,
799 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
800 lp->rx_skb[lp->rx_bd_ci] = new_skb;
803 if (lp->rx_bd_ci >= RX_BD_NUM)
806 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
807 bdstat = cur_p->app0;
809 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
811 spin_unlock_irqrestore(&lp->rx_lock, flags);
814 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
816 struct net_device *ndev = _ndev;
817 struct temac_local *lp = netdev_priv(ndev);
820 status = lp->dma_in(lp, TX_IRQ_REG);
821 lp->dma_out(lp, TX_IRQ_REG, status);
823 if (status & (IRQ_COAL | IRQ_DLY))
824 temac_start_xmit_done(lp->ndev);
826 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
831 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
833 struct net_device *ndev = _ndev;
834 struct temac_local *lp = netdev_priv(ndev);
837 /* Read and clear the status registers */
838 status = lp->dma_in(lp, RX_IRQ_REG);
839 lp->dma_out(lp, RX_IRQ_REG, status);
841 if (status & (IRQ_COAL | IRQ_DLY))
842 ll_temac_recv(lp->ndev);
847 static int temac_open(struct net_device *ndev)
849 struct temac_local *lp = netdev_priv(ndev);
852 dev_dbg(&ndev->dev, "temac_open()\n");
855 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
856 temac_adjust_link, 0, 0);
858 dev_err(lp->dev, "of_phy_connect() failed\n");
862 phy_start(lp->phy_dev);
865 temac_device_reset(ndev);
867 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
870 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
877 free_irq(lp->tx_irq, ndev);
880 phy_disconnect(lp->phy_dev);
882 dev_err(lp->dev, "request_irq() failed\n");
886 static int temac_stop(struct net_device *ndev)
888 struct temac_local *lp = netdev_priv(ndev);
890 dev_dbg(&ndev->dev, "temac_close()\n");
892 free_irq(lp->tx_irq, ndev);
893 free_irq(lp->rx_irq, ndev);
896 phy_disconnect(lp->phy_dev);
899 temac_dma_bd_release(ndev);
904 #ifdef CONFIG_NET_POLL_CONTROLLER
906 temac_poll_controller(struct net_device *ndev)
908 struct temac_local *lp = netdev_priv(ndev);
910 disable_irq(lp->tx_irq);
911 disable_irq(lp->rx_irq);
913 ll_temac_rx_irq(lp->tx_irq, ndev);
914 ll_temac_tx_irq(lp->rx_irq, ndev);
916 enable_irq(lp->tx_irq);
917 enable_irq(lp->rx_irq);
921 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
923 struct temac_local *lp = netdev_priv(ndev);
925 if (!netif_running(ndev))
931 return phy_mii_ioctl(lp->phy_dev, rq, cmd);
934 static const struct net_device_ops temac_netdev_ops = {
935 .ndo_open = temac_open,
936 .ndo_stop = temac_stop,
937 .ndo_start_xmit = temac_start_xmit,
938 .ndo_set_mac_address = temac_set_mac_address,
939 .ndo_validate_addr = eth_validate_addr,
940 .ndo_do_ioctl = temac_ioctl,
941 #ifdef CONFIG_NET_POLL_CONTROLLER
942 .ndo_poll_controller = temac_poll_controller,
946 /* ---------------------------------------------------------------------
947 * SYSFS device attributes
949 static ssize_t temac_show_llink_regs(struct device *dev,
950 struct device_attribute *attr, char *buf)
952 struct net_device *ndev = dev_get_drvdata(dev);
953 struct temac_local *lp = netdev_priv(ndev);
956 for (i = 0; i < 0x11; i++)
957 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
958 (i % 8) == 7 ? "\n" : " ");
959 len += sprintf(buf + len, "\n");
964 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
966 static struct attribute *temac_device_attrs[] = {
967 &dev_attr_llink_regs.attr,
971 static const struct attribute_group temac_attr_group = {
972 .attrs = temac_device_attrs,
975 /* ethtool support */
976 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
978 struct temac_local *lp = netdev_priv(ndev);
979 return phy_ethtool_gset(lp->phy_dev, cmd);
982 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
984 struct temac_local *lp = netdev_priv(ndev);
985 return phy_ethtool_sset(lp->phy_dev, cmd);
988 static int temac_nway_reset(struct net_device *ndev)
990 struct temac_local *lp = netdev_priv(ndev);
991 return phy_start_aneg(lp->phy_dev);
994 static const struct ethtool_ops temac_ethtool_ops = {
995 .get_settings = temac_get_settings,
996 .set_settings = temac_set_settings,
997 .nway_reset = temac_nway_reset,
998 .get_link = ethtool_op_get_link,
999 .get_ts_info = ethtool_op_get_ts_info,
1002 static int temac_of_probe(struct platform_device *op)
1004 struct device_node *np;
1005 struct temac_local *lp;
1006 struct net_device *ndev;
1011 /* Init network device structure */
1012 ndev = alloc_etherdev(sizeof(*lp));
1017 platform_set_drvdata(op, ndev);
1018 SET_NETDEV_DEV(ndev, &op->dev);
1019 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1020 ndev->features = NETIF_F_SG;
1021 ndev->netdev_ops = &temac_netdev_ops;
1022 ndev->ethtool_ops = &temac_ethtool_ops;
1024 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1025 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1026 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1027 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1028 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1029 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1030 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1031 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1032 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1033 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1034 ndev->features |= NETIF_F_LRO; /* large receive offload */
1037 /* setup temac private info structure */
1038 lp = netdev_priv(ndev);
1041 lp->options = XTE_OPTION_DEFAULTS;
1042 spin_lock_init(&lp->rx_lock);
1043 mutex_init(&lp->indirect_mutex);
1045 /* map device registers */
1046 lp->regs = of_iomap(op->dev.of_node, 0);
1048 dev_err(&op->dev, "could not map temac regs.\n");
1052 /* Setup checksum offload, but default to off if not specified */
1053 lp->temac_features = 0;
1054 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1055 if (p && be32_to_cpu(*p)) {
1056 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1057 /* Can checksum TCP/UDP over IPv4. */
1058 ndev->features |= NETIF_F_IP_CSUM;
1060 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1061 if (p && be32_to_cpu(*p))
1062 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1064 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1065 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1067 dev_err(&op->dev, "could not find DMA node\n");
1071 /* Setup the DMA register accesses, could be DCR or memory mapped */
1072 if (temac_dcr_setup(lp, op, np)) {
1074 /* no DCR in the device tree, try non-DCR */
1075 lp->sdma_regs = of_iomap(np, 0);
1076 if (lp->sdma_regs) {
1077 lp->dma_in = temac_dma_in32;
1078 lp->dma_out = temac_dma_out32;
1079 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1081 dev_err(&op->dev, "unable to map DMA registers\n");
1087 lp->rx_irq = irq_of_parse_and_map(np, 0);
1088 lp->tx_irq = irq_of_parse_and_map(np, 1);
1090 of_node_put(np); /* Finished with the DMA node; drop the reference */
1092 if (!lp->rx_irq || !lp->tx_irq) {
1093 dev_err(&op->dev, "could not determine irqs\n");
1099 /* Retrieve the MAC address */
1100 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1101 if ((!addr) || (size != 6)) {
1102 dev_err(&op->dev, "could not find MAC address\n");
1106 temac_init_mac_address(ndev, (void *)addr);
1108 rc = temac_mdio_setup(lp, op->dev.of_node);
1110 dev_warn(&op->dev, "error registering MDIO bus\n");
1112 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1114 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1116 /* Add the device attributes */
1117 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1119 dev_err(lp->dev, "Error creating sysfs files\n");
1123 rc = register_netdev(lp->ndev);
1125 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1126 goto err_register_ndev;
1132 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1135 iounmap(lp->sdma_regs);
1144 static int temac_of_remove(struct platform_device *op)
1146 struct net_device *ndev = platform_get_drvdata(op);
1147 struct temac_local *lp = netdev_priv(ndev);
1149 temac_mdio_teardown(lp);
1150 unregister_netdev(ndev);
1151 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1153 of_node_put(lp->phy_node);
1154 lp->phy_node = NULL;
1157 iounmap(lp->sdma_regs);
1162 static struct of_device_id temac_of_match[] = {
1163 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1164 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1165 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1166 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1169 MODULE_DEVICE_TABLE(of, temac_of_match);
1171 static struct platform_driver temac_of_driver = {
1172 .probe = temac_of_probe,
1173 .remove = temac_of_remove,
1175 .owner = THIS_MODULE,
1176 .name = "xilinx_temac",
1177 .of_match_table = temac_of_match,
1181 module_platform_driver(temac_of_driver);
1183 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1184 MODULE_AUTHOR("Yoshio Kashiwagi");
1185 MODULE_LICENSE("GPL");