1 // SPDX-License-Identifier: GPL-2.0+
3 * DaVinci Ethernet Medium Access Controller
5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
7 * Copyright (C) 2009 Texas Instruments.
9 * ---------------------------------------------------------------------------
11 * 0-5 A number of folks worked on this driver in bits and pieces but the major
12 * contribution came from Suraj Iyer and Anant Gole
13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/sched.h>
21 #include <linux/string.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/highmem.h>
35 #include <linux/proc_fs.h>
36 #include <linux/ctype.h>
37 #include <linux/spinlock.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/clk.h>
40 #include <linux/platform_device.h>
41 #include <linux/regmap.h>
42 #include <linux/semaphore.h>
43 #include <linux/phy.h>
44 #include <linux/bitops.h>
46 #include <linux/uaccess.h>
47 #include <linux/pm_runtime.h>
48 #include <linux/davinci_emac.h>
50 #include <linux/of_address.h>
51 #include <linux/of_device.h>
52 #include <linux/of_mdio.h>
53 #include <linux/of_irq.h>
54 #include <linux/of_net.h>
55 #include <linux/mfd/syscon.h>
61 #include "davinci_cpdma.h"
63 static int debug_level;
64 module_param(debug_level, int, 0);
65 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
67 /* Netif debug messages possible */
68 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
76 NETIF_MSG_TX_QUEUED | \
79 NETIF_MSG_RX_STATUS | \
85 #define EMAC_MAJOR_VERSION 6
86 #define EMAC_MINOR_VERSION 1
87 #define EMAC_MODULE_VERSION "6.1"
88 MODULE_VERSION(EMAC_MODULE_VERSION);
89 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
91 /* Configuration items */
92 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
93 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
94 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
95 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
96 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
97 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
98 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
99 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
100 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
101 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
102 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
103 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
105 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
106 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
108 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
109 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
110 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
111 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
112 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
113 #define EMAC_DEF_RX_NUM_DESC (128)
114 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
115 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
116 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
118 /* Buffer descriptor parameters */
119 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
120 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
122 /* EMAC register related defines */
123 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
124 #define EMAC_NUM_MULTICAST_BITS (64)
125 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
126 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
127 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
128 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
129 #define EMAC_INT_MASK_CLEAR (0xFF)
131 /* RX MBP register bit positions */
132 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
133 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
134 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
135 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
136 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
137 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
138 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
139 #define EMAC_RXMBP_PROMCH_SHIFT (16)
140 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
141 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
142 #define EMAC_RXMBP_BROADCH_SHIFT (8)
143 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
144 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
145 #define EMAC_RXMBP_MULTICH_SHIFT (0)
146 #define EMAC_RXMBP_MULTICH_MASK (0x7)
147 #define EMAC_RXMBP_CHMASK (0x7)
149 /* EMAC register definitions/bit maps used */
150 # define EMAC_MBP_RXPROMISC (0x00200000)
151 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
152 # define EMAC_MBP_RXBCAST (0x00002000)
153 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
154 # define EMAC_MBP_RXMCAST (0x00000020)
155 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
157 /* EMAC mac_control register */
158 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
159 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
160 #define EMAC_MACCONTROL_GMIIEN BIT(5)
161 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
162 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
163 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
165 /* GIGABIT MODE related bits */
166 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
167 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
169 /* EMAC mac_status register */
170 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
171 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
172 #define EMAC_MACSTATUS_TXERRCH_MASK (0x70000)
173 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
174 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
175 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
176 #define EMAC_MACSTATUS_RXERRCH_MASK (0x700)
177 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
179 /* EMAC RX register masks */
180 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
181 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
183 /* MAC_IN_VECTOR (0x180) register bit fields */
184 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
185 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
186 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
187 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
189 /** NOTE:: For DM646x the IN_VECTOR has changed */
190 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
191 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
192 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
193 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
195 /* CPPI bit positions */
196 #define EMAC_CPPI_SOP_BIT BIT(31)
197 #define EMAC_CPPI_EOP_BIT BIT(30)
198 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
199 #define EMAC_CPPI_EOQ_BIT BIT(28)
200 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
201 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
202 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
203 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
204 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
206 /* Max hardware defines */
207 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
208 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
210 /* EMAC Peripheral Device Register Memory Layout structure */
211 #define EMAC_MACINVECTOR 0x90
213 #define EMAC_DM646X_MACEOIVECTOR 0x94
215 #define EMAC_MACINTSTATRAW 0xB0
216 #define EMAC_MACINTSTATMASKED 0xB4
217 #define EMAC_MACINTMASKSET 0xB8
218 #define EMAC_MACINTMASKCLEAR 0xBC
220 #define EMAC_RXMBPENABLE 0x100
221 #define EMAC_RXUNICASTSET 0x104
222 #define EMAC_RXUNICASTCLEAR 0x108
223 #define EMAC_RXMAXLEN 0x10C
224 #define EMAC_RXBUFFEROFFSET 0x110
225 #define EMAC_RXFILTERLOWTHRESH 0x114
227 #define EMAC_MACCONTROL 0x160
228 #define EMAC_MACSTATUS 0x164
229 #define EMAC_EMCONTROL 0x168
230 #define EMAC_FIFOCONTROL 0x16C
231 #define EMAC_MACCONFIG 0x170
232 #define EMAC_SOFTRESET 0x174
233 #define EMAC_MACSRCADDRLO 0x1D0
234 #define EMAC_MACSRCADDRHI 0x1D4
235 #define EMAC_MACHASH1 0x1D8
236 #define EMAC_MACHASH2 0x1DC
237 #define EMAC_MACADDRLO 0x500
238 #define EMAC_MACADDRHI 0x504
239 #define EMAC_MACINDEX 0x508
241 /* EMAC statistics registers */
242 #define EMAC_RXGOODFRAMES 0x200
243 #define EMAC_RXBCASTFRAMES 0x204
244 #define EMAC_RXMCASTFRAMES 0x208
245 #define EMAC_RXPAUSEFRAMES 0x20C
246 #define EMAC_RXCRCERRORS 0x210
247 #define EMAC_RXALIGNCODEERRORS 0x214
248 #define EMAC_RXOVERSIZED 0x218
249 #define EMAC_RXJABBER 0x21C
250 #define EMAC_RXUNDERSIZED 0x220
251 #define EMAC_RXFRAGMENTS 0x224
252 #define EMAC_RXFILTERED 0x228
253 #define EMAC_RXQOSFILTERED 0x22C
254 #define EMAC_RXOCTETS 0x230
255 #define EMAC_TXGOODFRAMES 0x234
256 #define EMAC_TXBCASTFRAMES 0x238
257 #define EMAC_TXMCASTFRAMES 0x23C
258 #define EMAC_TXPAUSEFRAMES 0x240
259 #define EMAC_TXDEFERRED 0x244
260 #define EMAC_TXCOLLISION 0x248
261 #define EMAC_TXSINGLECOLL 0x24C
262 #define EMAC_TXMULTICOLL 0x250
263 #define EMAC_TXEXCESSIVECOLL 0x254
264 #define EMAC_TXLATECOLL 0x258
265 #define EMAC_TXUNDERRUN 0x25C
266 #define EMAC_TXCARRIERSENSE 0x260
267 #define EMAC_TXOCTETS 0x264
268 #define EMAC_NETOCTETS 0x280
269 #define EMAC_RXSOFOVERRUNS 0x284
270 #define EMAC_RXMOFOVERRUNS 0x288
271 #define EMAC_RXDMAOVERRUNS 0x28C
273 /* EMAC DM644x control registers */
274 #define EMAC_CTRL_EWCTL (0x4)
275 #define EMAC_CTRL_EWINTTCNT (0x8)
277 /* EMAC DM644x control module masks */
278 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
279 #define EMAC_DM644X_INTMIN_INTVL 0x1
280 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
282 /* EMAC DM646X control module registers */
283 #define EMAC_DM646X_CMINTCTRL 0x0C
284 #define EMAC_DM646X_CMRXINTEN 0x14
285 #define EMAC_DM646X_CMTXINTEN 0x18
286 #define EMAC_DM646X_CMRXINTMAX 0x70
287 #define EMAC_DM646X_CMTXINTMAX 0x74
289 /* EMAC DM646X control module masks */
290 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
291 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
292 #define EMAC_DM646X_CMINTMAX_CNT 63
293 #define EMAC_DM646X_CMINTMIN_CNT 2
294 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
295 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
298 /* EMAC EOI codes for C0 */
299 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
300 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
302 /* EMAC Stats Clear Mask */
303 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
305 /* emac_priv: EMAC private data structure
307 * EMAC adapter private data structure
311 struct net_device *ndev;
312 struct platform_device *pdev;
313 struct napi_struct napi;
315 void __iomem *remap_addr;
317 void __iomem *emac_base;
318 void __iomem *ctrl_base;
319 struct cpdma_ctlr *dma;
320 struct cpdma_chan *txchan;
321 struct cpdma_chan *rxchan;
322 u32 link; /* 1=link on, 0=link off */
323 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
324 u32 duplex; /* Link duplex: 0=Half, 1=Full */
333 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
336 struct device_node *phy_node;
338 /*platform specific members*/
339 void (*int_enable) (void);
340 void (*int_disable) (void);
343 /* EMAC TX Host Error description strings */
344 static char *emac_txhost_errcodes[16] = {
345 "No error", "SOP error", "Ownership bit not set in SOP buffer",
346 "Zero Next Buffer Descriptor Pointer Without EOP",
347 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
348 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
349 "Reserved", "Reserved", "Reserved", "Reserved"
352 /* EMAC RX Host Error description strings */
353 static char *emac_rxhost_errcodes[16] = {
354 "No error", "Reserved", "Ownership bit not set in input buffer",
355 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
356 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
357 "Reserved", "Reserved", "Reserved", "Reserved"
361 #define emac_read(reg) ioread32(priv->emac_base + (reg))
362 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
364 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
365 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
368 * emac_get_drvinfo - Get EMAC driver information
369 * @ndev: The DaVinci EMAC network adapter
370 * @info: ethtool info structure containing name and version
372 * Returns EMAC driver information (name and version)
375 static void emac_get_drvinfo(struct net_device *ndev,
376 struct ethtool_drvinfo *info)
378 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
379 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
383 * emac_get_coalesce - Get interrupt coalesce settings for this device
384 * @ndev : The DaVinci EMAC network adapter
385 * @coal : ethtool coalesce settings structure
386 * @kernel_coal: ethtool CQE mode setting structure
387 * @extack: extack for reporting error messages
389 * Fetch the current interrupt coalesce settings
392 static int emac_get_coalesce(struct net_device *ndev,
393 struct ethtool_coalesce *coal,
394 struct kernel_ethtool_coalesce *kernel_coal,
395 struct netlink_ext_ack *extack)
397 struct emac_priv *priv = netdev_priv(ndev);
399 coal->rx_coalesce_usecs = priv->coal_intvl;
405 * emac_set_coalesce - Set interrupt coalesce settings for this device
406 * @ndev : The DaVinci EMAC network adapter
407 * @coal : ethtool coalesce settings structure
408 * @kernel_coal: ethtool CQE mode setting structure
409 * @extack: extack for reporting error messages
411 * Set interrupt coalesce parameters
414 static int emac_set_coalesce(struct net_device *ndev,
415 struct ethtool_coalesce *coal,
416 struct kernel_ethtool_coalesce *kernel_coal,
417 struct netlink_ext_ack *extack)
419 struct emac_priv *priv = netdev_priv(ndev);
420 u32 int_ctrl, num_interrupts = 0;
421 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
423 if (!coal->rx_coalesce_usecs) {
424 priv->coal_intvl = 0;
426 switch (priv->version) {
428 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0);
431 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0);
438 coal_intvl = coal->rx_coalesce_usecs;
440 switch (priv->version) {
442 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
443 prescale = priv->bus_freq_mhz * 4;
445 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
446 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
448 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
450 * Interrupt pacer works with 4us Pulse, we can
451 * throttle further by dilating the 4us pulse.
453 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
455 if (addnl_dvdr > 1) {
456 prescale *= addnl_dvdr;
457 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
459 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
463 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
467 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
469 int_ctrl |= EMAC_DM646X_INTPACEEN;
470 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
471 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
472 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
474 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
475 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
479 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
480 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
481 prescale = coal_intvl * priv->bus_freq_mhz;
482 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
483 prescale = EMAC_DM644X_EWINTCNT_MASK;
484 coal_intvl = prescale / priv->bus_freq_mhz;
486 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
491 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
492 priv->coal_intvl = coal_intvl;
499 /* ethtool_ops: DaVinci EMAC Ethtool structure
501 * Ethtool support for EMAC adapter
503 static const struct ethtool_ops ethtool_ops = {
504 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
505 .get_drvinfo = emac_get_drvinfo,
506 .get_link = ethtool_op_get_link,
507 .get_coalesce = emac_get_coalesce,
508 .set_coalesce = emac_set_coalesce,
509 .get_ts_info = ethtool_op_get_ts_info,
510 .get_link_ksettings = phy_ethtool_get_link_ksettings,
511 .set_link_ksettings = phy_ethtool_set_link_ksettings,
515 * emac_update_phystatus - Update Phy status
516 * @priv: The DaVinci EMAC private adapter structure
518 * Updates phy status and takes action for network queue if required
519 * based upon link status
522 static void emac_update_phystatus(struct emac_priv *priv)
527 struct net_device *ndev = priv->ndev;
529 mac_control = emac_read(EMAC_MACCONTROL);
530 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
531 DUPLEX_FULL : DUPLEX_HALF;
533 new_duplex = ndev->phydev->duplex;
535 new_duplex = DUPLEX_FULL;
537 /* We get called only if link has changed (speed/duplex/status) */
538 if ((priv->link) && (new_duplex != cur_duplex)) {
539 priv->duplex = new_duplex;
540 if (DUPLEX_FULL == priv->duplex)
541 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
543 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
546 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
547 mac_control = emac_read(EMAC_MACCONTROL);
548 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
549 EMAC_DM646X_MACCONTORL_GIGFORCE);
551 /* Clear the GIG bit and GIGFORCE bit */
552 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
553 EMAC_DM646X_MACCONTORL_GIG);
555 if (priv->rmii_en && (priv->speed == SPEED_100))
556 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
558 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
561 /* Update mac_control if changed */
562 emac_write(EMAC_MACCONTROL, mac_control);
566 if (!netif_carrier_ok(ndev))
567 netif_carrier_on(ndev);
568 /* reactivate the transmit queue if it is stopped */
569 if (netif_running(ndev) && netif_queue_stopped(ndev))
570 netif_wake_queue(ndev);
573 if (netif_carrier_ok(ndev))
574 netif_carrier_off(ndev);
575 if (!netif_queue_stopped(ndev))
576 netif_stop_queue(ndev);
581 * hash_get - Calculate hash value from mac address
582 * @addr: mac address to delete from hash table
584 * Calculates hash value from mac address
587 static u32 hash_get(u8 *addr)
594 for (cnt = 0; cnt < 2; cnt++) {
596 hash ^= (tmpval >> 2) ^ (tmpval << 4);
598 hash ^= (tmpval >> 4) ^ (tmpval << 2);
600 hash ^= (tmpval >> 6) ^ (tmpval);
607 * emac_hash_add - Hash function to add mac addr from hash table
608 * @priv: The DaVinci EMAC private adapter structure
609 * @mac_addr: mac address to delete from hash table
611 * Adds mac address to the internal hash table
614 static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
616 struct device *emac_dev = &priv->ndev->dev;
619 u32 hash_value = hash_get(mac_addr);
621 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
622 if (netif_msg_drv(priv)) {
623 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
624 "Hash %08x, should not be greater than %08x",
625 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
630 /* set the hash bit only if not previously set */
631 if (priv->multicast_hash_cnt[hash_value] == 0) {
632 rc = 1; /* hash value changed */
633 if (hash_value < 32) {
634 hash_bit = BIT(hash_value);
635 priv->mac_hash1 |= hash_bit;
637 hash_bit = BIT((hash_value - 32));
638 priv->mac_hash2 |= hash_bit;
642 /* incr counter for num of mcast addr's mapped to "this" hash bit */
643 ++priv->multicast_hash_cnt[hash_value];
649 * emac_hash_del - Hash function to delete mac addr from hash table
650 * @priv: The DaVinci EMAC private adapter structure
651 * @mac_addr: mac address to delete from hash table
653 * Removes mac address from the internal hash table
656 static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
661 hash_value = hash_get(mac_addr);
662 if (priv->multicast_hash_cnt[hash_value] > 0) {
663 /* dec cntr for num of mcast addr's mapped to this hash bit */
664 --priv->multicast_hash_cnt[hash_value];
667 /* if counter still > 0, at least one multicast address refers
668 * to this hash bit. so return 0 */
669 if (priv->multicast_hash_cnt[hash_value] > 0)
672 if (hash_value < 32) {
673 hash_bit = BIT(hash_value);
674 priv->mac_hash1 &= ~hash_bit;
676 hash_bit = BIT((hash_value - 32));
677 priv->mac_hash2 &= ~hash_bit;
680 /* return 1 to indicate change in mac_hash registers reqd */
684 /* EMAC multicast operation */
685 #define EMAC_MULTICAST_ADD 0
686 #define EMAC_MULTICAST_DEL 1
687 #define EMAC_ALL_MULTI_SET 2
688 #define EMAC_ALL_MULTI_CLR 3
691 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
692 * @priv: The DaVinci EMAC private adapter structure
693 * @action: multicast operation to perform
694 * @mac_addr: mac address to set
696 * Set multicast addresses in EMAC adapter - internal function
699 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
701 struct device *emac_dev = &priv->ndev->dev;
705 case EMAC_MULTICAST_ADD:
706 update = emac_hash_add(priv, mac_addr);
708 case EMAC_MULTICAST_DEL:
709 update = emac_hash_del(priv, mac_addr);
711 case EMAC_ALL_MULTI_SET:
713 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
714 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
716 case EMAC_ALL_MULTI_CLR:
720 memset(&(priv->multicast_hash_cnt[0]), 0,
721 sizeof(priv->multicast_hash_cnt[0]) *
722 EMAC_NUM_MULTICAST_BITS);
725 if (netif_msg_drv(priv))
726 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
727 ": bad operation %d", action);
731 /* write to the hardware only if the register status chances */
733 emac_write(EMAC_MACHASH1, priv->mac_hash1);
734 emac_write(EMAC_MACHASH2, priv->mac_hash2);
739 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
740 * @ndev: The DaVinci EMAC network adapter
742 * Set multicast addresses in EMAC adapter
745 static void emac_dev_mcast_set(struct net_device *ndev)
748 struct emac_priv *priv = netdev_priv(ndev);
750 mbp_enable = emac_read(EMAC_RXMBPENABLE);
751 if (ndev->flags & IFF_PROMISC) {
752 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
753 mbp_enable |= (EMAC_MBP_RXPROMISC);
755 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
756 if ((ndev->flags & IFF_ALLMULTI) ||
757 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
758 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
759 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
760 } else if (!netdev_mc_empty(ndev)) {
761 struct netdev_hw_addr *ha;
763 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
764 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
765 /* program multicast address list into EMAC hardware */
766 netdev_for_each_mc_addr(ha, ndev) {
767 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
771 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
772 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
775 /* Set mbp config register */
776 emac_write(EMAC_RXMBPENABLE, mbp_enable);
779 /*************************************************************************
780 * EMAC Hardware manipulation
781 *************************************************************************/
784 * emac_int_disable - Disable EMAC module interrupt (from adapter)
785 * @priv: The DaVinci EMAC private adapter structure
787 * Disable EMAC interrupt on the adapter
790 static void emac_int_disable(struct emac_priv *priv)
792 if (priv->version == EMAC_VERSION_2) {
795 local_irq_save(flags);
797 /* Program C0_Int_En to zero to turn off
798 * interrupts to the CPU */
799 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
800 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
801 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
802 if (priv->int_disable)
805 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
807 /* ack rxen only then a new pulse will be generated */
808 emac_write(EMAC_DM646X_MACEOIVECTOR,
809 EMAC_DM646X_MAC_EOI_C0_RXEN);
811 /* ack txen- only then a new pulse will be generated */
812 emac_write(EMAC_DM646X_MACEOIVECTOR,
813 EMAC_DM646X_MAC_EOI_C0_TXEN);
815 local_irq_restore(flags);
818 /* Set DM644x control registers for interrupt control */
819 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
824 * emac_int_enable - Enable EMAC module interrupt (from adapter)
825 * @priv: The DaVinci EMAC private adapter structure
827 * Enable EMAC interrupt on the adapter
830 static void emac_int_enable(struct emac_priv *priv)
832 if (priv->version == EMAC_VERSION_2) {
833 if (priv->int_enable)
836 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
837 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
839 /* In addition to turning on interrupt Enable, we need
840 * ack by writing appropriate values to the EOI
843 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
845 /* Set DM644x control registers for interrupt control */
846 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
851 * emac_irq - EMAC interrupt handler
852 * @irq: interrupt number
853 * @dev_id: EMAC network adapter data structure ptr
855 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
856 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
858 * Returns interrupt handled condition
860 static irqreturn_t emac_irq(int irq, void *dev_id)
862 struct net_device *ndev = (struct net_device *)dev_id;
863 struct emac_priv *priv = netdev_priv(ndev);
866 if (likely(netif_running(priv->ndev))) {
867 emac_int_disable(priv);
868 napi_schedule(&priv->napi);
870 /* we are closing down, so dont process anything */
875 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
877 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
880 skb_reserve(skb, NET_IP_ALIGN);
884 static void emac_rx_handler(void *token, int len, int status)
886 struct sk_buff *skb = token;
887 struct net_device *ndev = skb->dev;
888 struct emac_priv *priv = netdev_priv(ndev);
889 struct device *emac_dev = &ndev->dev;
892 /* free and bail if we are shutting down */
893 if (unlikely(!netif_running(ndev))) {
894 dev_kfree_skb_any(skb);
898 /* recycle on receive error */
900 ndev->stats.rx_errors++;
904 /* feed received packet up the stack */
906 skb->protocol = eth_type_trans(skb, ndev);
907 netif_receive_skb(skb);
908 ndev->stats.rx_bytes += len;
909 ndev->stats.rx_packets++;
911 /* alloc a new packet for receive */
912 skb = emac_rx_alloc(priv);
914 if (netif_msg_rx_err(priv) && net_ratelimit())
915 dev_err(emac_dev, "failed rx buffer alloc\n");
920 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
921 skb_tailroom(skb), 0);
923 WARN_ON(ret == -ENOMEM);
924 if (unlikely(ret < 0))
925 dev_kfree_skb_any(skb);
928 static void emac_tx_handler(void *token, int len, int status)
930 struct sk_buff *skb = token;
931 struct net_device *ndev = skb->dev;
933 /* Check whether the queue is stopped due to stalled tx dma, if the
934 * queue is stopped then start the queue as we have free desc for tx
936 if (unlikely(netif_queue_stopped(ndev)))
937 netif_wake_queue(ndev);
938 ndev->stats.tx_packets++;
939 ndev->stats.tx_bytes += len;
940 dev_kfree_skb_any(skb);
944 * emac_dev_xmit - EMAC Transmit function
946 * @ndev: The DaVinci EMAC network adapter
948 * Called by the system to transmit a packet - we queue the packet in
949 * EMAC hardware transmit queue
951 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
953 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
955 struct device *emac_dev = &ndev->dev;
957 struct emac_priv *priv = netdev_priv(ndev);
959 /* If no link, return */
960 if (unlikely(!priv->link)) {
961 if (netif_msg_tx_err(priv) && net_ratelimit())
962 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
966 ret_code = skb_put_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
967 if (unlikely(ret_code < 0)) {
968 if (netif_msg_tx_err(priv) && net_ratelimit())
969 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
973 skb_tx_timestamp(skb);
975 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
977 if (unlikely(ret_code != 0)) {
978 if (netif_msg_tx_err(priv) && net_ratelimit())
979 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
983 /* If there is no more tx desc left free then we need to
984 * tell the kernel to stop sending us tx frames.
986 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
987 netif_stop_queue(ndev);
992 ndev->stats.tx_dropped++;
993 netif_stop_queue(ndev);
994 return NETDEV_TX_BUSY;
998 * emac_dev_tx_timeout - EMAC Transmit timeout function
999 * @ndev: The DaVinci EMAC network adapter
1000 * @txqueue: the index of the hung transmit queue
1002 * Called when system detects that a skb timeout period has expired
1003 * potentially due to a fault in the adapter in not being able to send
1004 * it out on the wire. We teardown the TX channel assuming a hardware
1005 * error and re-initialize the TX channel for hardware operation
1008 static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1010 struct emac_priv *priv = netdev_priv(ndev);
1011 struct device *emac_dev = &ndev->dev;
1013 if (netif_msg_tx_err(priv))
1014 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1016 ndev->stats.tx_errors++;
1017 emac_int_disable(priv);
1018 cpdma_chan_stop(priv->txchan);
1019 cpdma_chan_start(priv->txchan);
1020 emac_int_enable(priv);
1024 * emac_set_type0addr - Set EMAC Type0 mac address
1025 * @priv: The DaVinci EMAC private adapter structure
1026 * @ch: RX channel number
1027 * @mac_addr: MAC address to set in device
1029 * Called internally to set Type0 mac address of the adapter (Device)
1031 * Returns success (0) or appropriate error code (none as of now)
1033 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1036 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1037 emac_write(EMAC_MACSRCADDRLO, val);
1039 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1040 (mac_addr[1] << 8) | (mac_addr[0]));
1041 emac_write(EMAC_MACSRCADDRHI, val);
1042 val = emac_read(EMAC_RXUNICASTSET);
1044 emac_write(EMAC_RXUNICASTSET, val);
1045 val = emac_read(EMAC_RXUNICASTCLEAR);
1047 emac_write(EMAC_RXUNICASTCLEAR, val);
1051 * emac_set_type1addr - Set EMAC Type1 mac address
1052 * @priv: The DaVinci EMAC private adapter structure
1053 * @ch: RX channel number
1054 * @mac_addr: MAC address to set in device
1056 * Called internally to set Type1 mac address of the adapter (Device)
1058 * Returns success (0) or appropriate error code (none as of now)
1060 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1063 emac_write(EMAC_MACINDEX, ch);
1064 val = ((mac_addr[5] << 8) | mac_addr[4]);
1065 emac_write(EMAC_MACADDRLO, val);
1066 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1067 (mac_addr[1] << 8) | (mac_addr[0]));
1068 emac_write(EMAC_MACADDRHI, val);
1069 emac_set_type0addr(priv, ch, mac_addr);
1073 * emac_set_type2addr - Set EMAC Type2 mac address
1074 * @priv: The DaVinci EMAC private adapter structure
1075 * @ch: RX channel number
1076 * @mac_addr: MAC address to set in device
1077 * @index: index into RX address entries
1078 * @match: match parameter for RX address matching logic
1080 * Called internally to set Type2 mac address of the adapter (Device)
1082 * Returns success (0) or appropriate error code (none as of now)
1084 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1085 char *mac_addr, int index, int match)
1088 emac_write(EMAC_MACINDEX, index);
1089 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1090 (mac_addr[1] << 8) | (mac_addr[0]));
1091 emac_write(EMAC_MACADDRHI, val);
1092 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1093 (match << 19) | BIT(20));
1094 emac_write(EMAC_MACADDRLO, val);
1095 emac_set_type0addr(priv, ch, mac_addr);
1099 * emac_setmac - Set mac address in the adapter (internal function)
1100 * @priv: The DaVinci EMAC private adapter structure
1101 * @ch: RX channel number
1102 * @mac_addr: MAC address to set in device
1104 * Called internally to set the mac address of the adapter (Device)
1106 * Returns success (0) or appropriate error code (none as of now)
1108 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1110 struct device *emac_dev = &priv->ndev->dev;
1112 if (priv->rx_addr_type == 0) {
1113 emac_set_type0addr(priv, ch, mac_addr);
1114 } else if (priv->rx_addr_type == 1) {
1116 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1117 emac_set_type1addr(priv, ch, mac_addr);
1118 } else if (priv->rx_addr_type == 2) {
1119 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1120 emac_set_type0addr(priv, ch, mac_addr);
1122 if (netif_msg_drv(priv))
1123 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1128 * emac_dev_setmac_addr - Set mac address in the adapter
1129 * @ndev: The DaVinci EMAC network adapter
1130 * @addr: MAC address to set in device
1132 * Called by the system to set the mac address of the adapter (Device)
1134 * Returns success (0) or appropriate error code (none as of now)
1136 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1138 struct emac_priv *priv = netdev_priv(ndev);
1139 struct device *emac_dev = &priv->ndev->dev;
1140 struct sockaddr *sa = addr;
1142 if (!is_valid_ether_addr(sa->sa_data))
1143 return -EADDRNOTAVAIL;
1145 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1146 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1147 eth_hw_addr_set(ndev, sa->sa_data);
1149 /* MAC address is configured only after the interface is enabled. */
1150 if (netif_running(ndev)) {
1151 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1154 if (netif_msg_drv(priv))
1155 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1162 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1163 * @priv: The DaVinci EMAC private adapter structure
1165 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1166 * for packet reception and enables device interrupts and then NAPI
1168 * Returns success (0) or appropriate error code (none right now)
1170 static int emac_hw_enable(struct emac_priv *priv)
1172 u32 val, mbp_enable, mac_control;
1175 emac_write(EMAC_SOFTRESET, 1);
1176 while (emac_read(EMAC_SOFTRESET))
1179 /* Disable interrupt & Set pacing for more interrupts initially */
1180 emac_int_disable(priv);
1182 /* Full duplex enable bit set when auto negotiation happens */
1184 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1185 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1186 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1187 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1188 emac_write(EMAC_MACCONTROL, mac_control);
1191 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1192 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1193 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1194 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1195 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1196 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1197 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1198 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1199 EMAC_RXMBP_PROMCH_SHIFT) |
1200 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1201 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1202 EMAC_RXMBP_BROADCH_SHIFT) |
1203 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1204 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1205 EMAC_RXMBP_MULTICH_SHIFT));
1206 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1207 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1208 EMAC_RX_MAX_LEN_MASK));
1209 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1210 EMAC_RX_BUFFER_OFFSET_MASK));
1211 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1212 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1213 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1215 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1217 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1220 val = emac_read(EMAC_MACCONTROL);
1221 val |= (EMAC_MACCONTROL_GMIIEN);
1222 emac_write(EMAC_MACCONTROL, val);
1224 /* Enable NAPI and interrupts */
1225 napi_enable(&priv->napi);
1226 emac_int_enable(priv);
1232 * emac_poll - EMAC NAPI Poll function
1233 * @napi: pointer to the napi_struct containing The DaVinci EMAC network adapter
1234 * @budget: Number of receive packets to process (as told by NAPI layer)
1236 * NAPI Poll function implemented to process packets as per budget. We check
1237 * the type of interrupt on the device and accordingly call the TX or RX
1238 * packet processing functions. We follow the budget for RX processing and
1239 * also put a cap on number of TX pkts processed through config param. The
1240 * NAPI schedule function is called if more packets pending.
1242 * Returns number of packets received (in most cases; else TX pkts - rarely)
1244 static int emac_poll(struct napi_struct *napi, int budget)
1247 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1248 struct net_device *ndev = priv->ndev;
1249 struct device *emac_dev = &ndev->dev;
1251 u32 num_rx_pkts = 0;
1253 /* Check interrupt vectors and call packet processing */
1254 status = emac_read(EMAC_MACINVECTOR);
1256 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1258 if (priv->version == EMAC_VERSION_2)
1259 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1261 if (status & mask) {
1262 cpdma_chan_process(priv->txchan, EMAC_DEF_TX_MAX_SERVICE);
1263 } /* TX processing */
1265 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1267 if (priv->version == EMAC_VERSION_2)
1268 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1270 if (status & mask) {
1271 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1272 } /* RX processing */
1274 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1275 if (priv->version == EMAC_VERSION_2)
1276 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1278 if (unlikely(status & mask)) {
1280 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1281 netif_stop_queue(ndev);
1282 napi_disable(&priv->napi);
1284 status = emac_read(EMAC_MACSTATUS);
1285 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1286 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1288 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1289 EMAC_MACSTATUS_TXERRCH_SHIFT);
1290 if (net_ratelimit()) {
1291 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1292 &emac_txhost_errcodes[cause][0], ch);
1295 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1296 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1298 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1299 EMAC_MACSTATUS_RXERRCH_SHIFT);
1300 if (netif_msg_hw(priv) && net_ratelimit())
1301 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1302 &emac_rxhost_errcodes[cause][0], ch);
1304 } else if (num_rx_pkts < budget) {
1305 napi_complete_done(napi, num_rx_pkts);
1306 emac_int_enable(priv);
1312 #ifdef CONFIG_NET_POLL_CONTROLLER
1314 * emac_poll_controller - EMAC Poll controller function
1315 * @ndev: The DaVinci EMAC network adapter
1317 * Polled functionality used by netconsole and others in non interrupt mode
1320 static void emac_poll_controller(struct net_device *ndev)
1322 struct emac_priv *priv = netdev_priv(ndev);
1324 emac_int_disable(priv);
1325 emac_irq(ndev->irq, ndev);
1326 emac_int_enable(priv);
1330 static void emac_adjust_link(struct net_device *ndev)
1332 struct emac_priv *priv = netdev_priv(ndev);
1333 struct phy_device *phydev = ndev->phydev;
1334 unsigned long flags;
1337 spin_lock_irqsave(&priv->lock, flags);
1340 /* check the mode of operation - full/half duplex */
1341 if (phydev->duplex != priv->duplex) {
1343 priv->duplex = phydev->duplex;
1345 if (phydev->speed != priv->speed) {
1347 priv->speed = phydev->speed;
1354 } else if (priv->link) {
1361 emac_update_phystatus(priv);
1362 phy_print_status(ndev->phydev);
1365 spin_unlock_irqrestore(&priv->lock, flags);
1368 /*************************************************************************
1369 * Linux Driver Model
1370 *************************************************************************/
1373 * emac_devioctl - EMAC adapter ioctl
1374 * @ndev: The DaVinci EMAC network adapter
1375 * @ifrq: request parameter
1376 * @cmd: command parameter
1378 * EMAC driver ioctl function
1380 * Returns success(0) or appropriate error code
1382 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1384 if (!(netif_running(ndev)))
1387 /* TODO: Add phy read and write and private statistics get feature */
1390 return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
1395 static int match_first_device(struct device *dev, const void *data)
1397 if (dev->parent && dev->parent->of_node)
1398 return of_device_is_compatible(dev->parent->of_node,
1401 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1405 * emac_dev_open - EMAC device open
1406 * @ndev: The DaVinci EMAC network adapter
1408 * Called when system wants to start the interface. We init TX/RX channels
1409 * and enable the hardware for packet reception/transmission and start the
1412 * Returns 0 for a successful open, or appropriate error code
1414 static int emac_dev_open(struct net_device *ndev)
1416 struct device *emac_dev = &ndev->dev;
1417 struct resource *res;
1419 int res_num = 0, irq_num = 0;
1421 struct emac_priv *priv = netdev_priv(ndev);
1422 struct phy_device *phydev = NULL;
1423 struct device *phy = NULL;
1425 ret = pm_runtime_get_sync(&priv->pdev->dev);
1427 pm_runtime_put_noidle(&priv->pdev->dev);
1428 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1433 netif_carrier_off(ndev);
1434 eth_hw_addr_set(ndev, priv->mac_addr);
1436 /* Configuration items */
1437 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1439 priv->mac_hash1 = 0;
1440 priv->mac_hash2 = 0;
1441 emac_write(EMAC_MACHASH1, 0);
1442 emac_write(EMAC_MACHASH2, 0);
1444 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1445 struct sk_buff *skb = emac_rx_alloc(priv);
1450 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data,
1451 skb_tailroom(skb), 0);
1452 if (WARN_ON(ret < 0))
1457 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1459 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1460 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1463 "DaVinci EMAC: request_irq() failed\n");
1471 /* prepare counters for rollback in case of an error */
1475 /* Start/Enable EMAC hardware */
1476 emac_hw_enable(priv);
1478 /* Enable Interrupt pacing if configured */
1479 if (priv->coal_intvl != 0) {
1480 struct ethtool_coalesce coal;
1482 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1483 emac_set_coalesce(ndev, &coal, NULL, NULL);
1486 cpdma_ctlr_start(priv->dma);
1488 if (priv->phy_node) {
1489 phydev = of_phy_connect(ndev, priv->phy_node,
1490 &emac_adjust_link, 0, 0);
1492 dev_err(emac_dev, "could not connect to phy %pOF\n",
1499 /* use the first phy on the bus if pdata did not give us a phy id */
1500 if (!phydev && !priv->phy_id) {
1501 /* NOTE: we can't use bus_find_device_by_name() here because
1502 * the device name is not guaranteed to be 'davinci_mdio'. On
1503 * some systems it can be 'davinci_mdio.0' so we need to use
1504 * strncmp() against the first part of the string to correctly
1507 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1508 match_first_device);
1510 priv->phy_id = dev_name(phy);
1511 if (!priv->phy_id || !*priv->phy_id)
1516 if (!phydev && priv->phy_id && *priv->phy_id) {
1517 phydev = phy_connect(ndev, priv->phy_id,
1519 PHY_INTERFACE_MODE_MII);
1520 put_device(phy); /* reference taken by bus_find_device */
1521 if (IS_ERR(phydev)) {
1522 dev_err(emac_dev, "could not connect to phy %s\n",
1524 ret = PTR_ERR(phydev);
1532 phy_attached_info(phydev);
1536 /* No PHY , fix the link, speed and duplex settings */
1537 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1539 priv->speed = SPEED_100;
1540 priv->duplex = DUPLEX_FULL;
1541 emac_update_phystatus(priv);
1544 if (netif_msg_drv(priv))
1545 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1553 emac_int_disable(priv);
1554 napi_disable(&priv->napi);
1557 for (q = res_num; q >= 0; q--) {
1558 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1559 /* at the first iteration, irq_num is already set to the
1565 for (m = irq_num; m >= res->start; m--)
1568 cpdma_ctlr_stop(priv->dma);
1569 pm_runtime_put(&priv->pdev->dev);
1574 * emac_dev_stop - EMAC device stop
1575 * @ndev: The DaVinci EMAC network adapter
1577 * Called when system wants to stop or down the interface. We stop the network
1578 * queue, disable interrupts and cleanup TX/RX channels.
1580 * We return the statistics in net_device_stats structure pulled from emac
1582 static int emac_dev_stop(struct net_device *ndev)
1584 struct resource *res;
1587 struct emac_priv *priv = netdev_priv(ndev);
1588 struct device *emac_dev = &ndev->dev;
1590 /* inform the upper layers. */
1591 netif_stop_queue(ndev);
1592 napi_disable(&priv->napi);
1594 netif_carrier_off(ndev);
1595 emac_int_disable(priv);
1596 cpdma_ctlr_stop(priv->dma);
1597 emac_write(EMAC_SOFTRESET, 1);
1600 phy_disconnect(ndev->phydev);
1603 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1604 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1605 free_irq(irq_num, priv->ndev);
1609 if (netif_msg_drv(priv))
1610 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1612 pm_runtime_put(&priv->pdev->dev);
1617 * emac_dev_getnetstats - EMAC get statistics function
1618 * @ndev: The DaVinci EMAC network adapter
1620 * Called when system wants to get statistics from the device.
1622 * We return the statistics in net_device_stats structure pulled from emac
1624 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1626 struct emac_priv *priv = netdev_priv(ndev);
1628 u32 stats_clear_mask;
1631 err = pm_runtime_get_sync(&priv->pdev->dev);
1633 pm_runtime_put_noidle(&priv->pdev->dev);
1634 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1636 return &ndev->stats;
1639 /* update emac hardware stats and reset the registers*/
1641 mac_control = emac_read(EMAC_MACCONTROL);
1643 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1644 stats_clear_mask = EMAC_STATS_CLR_MASK;
1646 stats_clear_mask = 0;
1648 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1649 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1651 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1652 emac_read(EMAC_TXSINGLECOLL) +
1653 emac_read(EMAC_TXMULTICOLL));
1654 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1655 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1656 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1658 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1659 emac_read(EMAC_RXJABBER) +
1660 emac_read(EMAC_RXUNDERSIZED));
1661 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1662 emac_write(EMAC_RXJABBER, stats_clear_mask);
1663 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1665 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1666 emac_read(EMAC_RXMOFOVERRUNS));
1667 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1668 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1670 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1671 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1673 ndev->stats.tx_carrier_errors +=
1674 emac_read(EMAC_TXCARRIERSENSE);
1675 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1677 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1678 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1680 pm_runtime_put(&priv->pdev->dev);
1682 return &ndev->stats;
1685 static const struct net_device_ops emac_netdev_ops = {
1686 .ndo_open = emac_dev_open,
1687 .ndo_stop = emac_dev_stop,
1688 .ndo_start_xmit = emac_dev_xmit,
1689 .ndo_set_rx_mode = emac_dev_mcast_set,
1690 .ndo_set_mac_address = emac_dev_setmac_addr,
1691 .ndo_eth_ioctl = emac_devioctl,
1692 .ndo_tx_timeout = emac_dev_tx_timeout,
1693 .ndo_get_stats = emac_dev_getnetstats,
1694 #ifdef CONFIG_NET_POLL_CONTROLLER
1695 .ndo_poll_controller = emac_poll_controller,
1699 static const struct of_device_id davinci_emac_of_match[];
1701 static struct emac_platform_data *
1702 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1704 struct device_node *np;
1705 const struct of_device_id *match;
1706 const struct emac_platform_data *auxdata;
1707 struct emac_platform_data *pdata = NULL;
1709 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1710 return dev_get_platdata(&pdev->dev);
1712 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1716 np = pdev->dev.of_node;
1717 pdata->version = EMAC_VERSION_2;
1719 if (!is_valid_ether_addr(pdata->mac_addr))
1720 of_get_mac_address(np, pdata->mac_addr);
1722 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1723 &pdata->ctrl_reg_offset);
1725 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1726 &pdata->ctrl_mod_reg_offset);
1728 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1729 &pdata->ctrl_ram_offset);
1731 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1732 &pdata->ctrl_ram_size);
1734 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1736 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1738 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1739 if (!priv->phy_node) {
1740 if (!of_phy_is_fixed_link(np))
1741 pdata->phy_id = NULL;
1742 else if (of_phy_register_fixed_link(np) >= 0)
1743 priv->phy_node = of_node_get(np);
1746 auxdata = pdev->dev.platform_data;
1748 pdata->interrupt_enable = auxdata->interrupt_enable;
1749 pdata->interrupt_disable = auxdata->interrupt_disable;
1752 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1753 if (match && match->data) {
1754 auxdata = match->data;
1755 pdata->version = auxdata->version;
1756 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1762 static int davinci_emac_try_get_mac(struct platform_device *pdev,
1763 int instance, u8 *mac_addr)
1765 if (!pdev->dev.of_node)
1768 return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1772 * davinci_emac_probe - EMAC device probe
1773 * @pdev: The DaVinci EMAC device that we are removing
1775 * Called when probing for emac devicesr. We get details of instances and
1776 * resource information from platform init and register a network device
1777 * and allocate resources necessary for driver to perform
1779 static int davinci_emac_probe(struct platform_device *pdev)
1781 struct device_node *np = pdev->dev.of_node;
1783 struct resource *res, *res_ctrl;
1784 struct net_device *ndev;
1785 struct emac_priv *priv;
1786 unsigned long hw_ram_addr;
1787 struct emac_platform_data *pdata;
1788 struct cpdma_params dma_params;
1789 struct clk *emac_clk;
1790 unsigned long emac_bus_frequency;
1793 /* obtain emac clock from kernel */
1794 emac_clk = devm_clk_get(&pdev->dev, NULL);
1795 if (IS_ERR(emac_clk)) {
1796 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1799 emac_bus_frequency = clk_get_rate(emac_clk);
1800 devm_clk_put(&pdev->dev, emac_clk);
1802 /* TODO: Probe PHY here if possible */
1804 ndev = alloc_etherdev(sizeof(struct emac_priv));
1808 platform_set_drvdata(pdev, ndev);
1809 priv = netdev_priv(ndev);
1812 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1814 spin_lock_init(&priv->lock);
1816 pdata = davinci_emac_of_get_pdata(pdev, priv);
1818 dev_err(&pdev->dev, "no platform data\n");
1820 goto err_free_netdev;
1823 /* MAC addr and PHY mask , RMII enable info from platform_data */
1824 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1825 priv->phy_id = pdata->phy_id;
1826 priv->rmii_en = pdata->rmii_en;
1827 priv->version = pdata->version;
1828 priv->int_enable = pdata->interrupt_enable;
1829 priv->int_disable = pdata->interrupt_disable;
1831 priv->coal_intvl = 0;
1832 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1834 /* Get EMAC platform data */
1835 priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1836 if (IS_ERR(priv->remap_addr)) {
1837 rc = PTR_ERR(priv->remap_addr);
1840 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1842 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1845 devm_ioremap_resource(&pdev->dev, res_ctrl);
1846 if (IS_ERR(priv->ctrl_base)) {
1847 rc = PTR_ERR(priv->ctrl_base);
1851 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1854 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1855 ndev->base_addr = (unsigned long)priv->remap_addr;
1857 hw_ram_addr = pdata->hw_ram_addr;
1859 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1861 memset(&dma_params, 0, sizeof(dma_params));
1862 dma_params.dev = &pdev->dev;
1863 dma_params.dmaregs = priv->emac_base;
1864 dma_params.rxthresh = priv->emac_base + 0x120;
1865 dma_params.rxfree = priv->emac_base + 0x140;
1866 dma_params.txhdp = priv->emac_base + 0x600;
1867 dma_params.rxhdp = priv->emac_base + 0x620;
1868 dma_params.txcp = priv->emac_base + 0x640;
1869 dma_params.rxcp = priv->emac_base + 0x660;
1870 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1871 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1872 dma_params.desc_hw_addr = hw_ram_addr;
1873 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1874 dma_params.desc_align = 16;
1876 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1877 (u32 __force)res->start + pdata->ctrl_ram_offset;
1879 priv->dma = cpdma_ctlr_create(&dma_params);
1881 dev_err(&pdev->dev, "error initializing DMA\n");
1886 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH,
1887 emac_tx_handler, 0);
1888 if (IS_ERR(priv->txchan)) {
1889 dev_err(&pdev->dev, "error initializing tx dma channel\n");
1890 rc = PTR_ERR(priv->txchan);
1894 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH,
1895 emac_rx_handler, 1);
1896 if (IS_ERR(priv->rxchan)) {
1897 dev_err(&pdev->dev, "error initializing rx dma channel\n");
1898 rc = PTR_ERR(priv->rxchan);
1899 goto err_free_txchan;
1902 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1904 dev_err(&pdev->dev, "error getting irq res\n");
1906 goto err_free_rxchan;
1908 ndev->irq = res->start;
1910 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
1912 eth_hw_addr_set(ndev, priv->mac_addr);
1914 if (!is_valid_ether_addr(priv->mac_addr)) {
1915 /* Use random MAC if still none obtained. */
1916 eth_hw_addr_random(ndev);
1917 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1918 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1922 ndev->netdev_ops = &emac_netdev_ops;
1923 ndev->ethtool_ops = ðtool_ops;
1924 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1926 pm_runtime_enable(&pdev->dev);
1927 rc = pm_runtime_get_sync(&pdev->dev);
1929 pm_runtime_put_noidle(&pdev->dev);
1930 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
1935 /* register the network device */
1936 SET_NETDEV_DEV(ndev, &pdev->dev);
1937 rc = register_netdev(ndev);
1939 dev_err(&pdev->dev, "error in register_netdev\n");
1941 pm_runtime_put(&pdev->dev);
1946 if (netif_msg_probe(priv)) {
1947 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
1948 "(regs: %pa, irq: %d)\n",
1949 &priv->emac_base_phys, ndev->irq);
1951 pm_runtime_put(&pdev->dev);
1956 netif_napi_del(&priv->napi);
1958 cpdma_chan_destroy(priv->rxchan);
1960 cpdma_chan_destroy(priv->txchan);
1962 cpdma_ctlr_destroy(priv->dma);
1964 if (of_phy_is_fixed_link(np))
1965 of_phy_deregister_fixed_link(np);
1966 of_node_put(priv->phy_node);
1973 * davinci_emac_remove - EMAC device remove
1974 * @pdev: The DaVinci EMAC device that we are removing
1976 * Called when removing the device driver. We disable clock usage and release
1977 * the resources taken up by the driver and unregister network device
1979 static int davinci_emac_remove(struct platform_device *pdev)
1981 struct net_device *ndev = platform_get_drvdata(pdev);
1982 struct emac_priv *priv = netdev_priv(ndev);
1983 struct device_node *np = pdev->dev.of_node;
1985 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1988 cpdma_chan_destroy(priv->txchan);
1990 cpdma_chan_destroy(priv->rxchan);
1991 cpdma_ctlr_destroy(priv->dma);
1993 unregister_netdev(ndev);
1994 of_node_put(priv->phy_node);
1995 pm_runtime_disable(&pdev->dev);
1996 if (of_phy_is_fixed_link(np))
1997 of_phy_deregister_fixed_link(np);
2003 static int davinci_emac_suspend(struct device *dev)
2005 struct net_device *ndev = dev_get_drvdata(dev);
2007 if (netif_running(ndev))
2008 emac_dev_stop(ndev);
2013 static int davinci_emac_resume(struct device *dev)
2015 struct net_device *ndev = dev_get_drvdata(dev);
2017 if (netif_running(ndev))
2018 emac_dev_open(ndev);
2023 static const struct dev_pm_ops davinci_emac_pm_ops = {
2024 .suspend = davinci_emac_suspend,
2025 .resume = davinci_emac_resume,
2028 static const struct emac_platform_data am3517_emac_data = {
2029 .version = EMAC_VERSION_2,
2030 .hw_ram_addr = 0x01e20000,
2033 static const struct emac_platform_data dm816_emac_data = {
2034 .version = EMAC_VERSION_2,
2037 static const struct of_device_id davinci_emac_of_match[] = {
2038 {.compatible = "ti,davinci-dm6467-emac", },
2039 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2040 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2043 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2045 /* davinci_emac_driver: EMAC platform driver structure */
2046 static struct platform_driver davinci_emac_driver = {
2048 .name = "davinci_emac",
2049 .pm = &davinci_emac_pm_ops,
2050 .of_match_table = davinci_emac_of_match,
2052 .probe = davinci_emac_probe,
2053 .remove = davinci_emac_remove,
2057 * davinci_emac_init - EMAC driver module init
2059 * Called when initializing the driver. We register the driver with
2062 static int __init davinci_emac_init(void)
2064 return platform_driver_register(&davinci_emac_driver);
2066 late_initcall(davinci_emac_init);
2069 * davinci_emac_exit - EMAC driver module exit
2071 * Called when exiting the driver completely. We unregister the driver with
2072 * the platform and exit
2074 static void __exit davinci_emac_exit(void)
2076 platform_driver_unregister(&davinci_emac_driver);
2078 module_exit(davinci_emac_exit);
2080 MODULE_LICENSE("GPL");
2081 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2082 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2083 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");