drivers/net/ethernet/ti/cpsw_ale.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments N-Port Ethernet Switch Address Lookup Engine
   4  *
   5  * Copyright (C) 2012 Texas Instruments
   6  *
   7  */
   8 #include <linux/bitmap.h>
   9 #include <linux/if_vlan.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/slab.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/stat.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/etherdevice.h>
  20
  21 #include "cpsw_ale.h"
  22
  23 #define BITMASK(bits)           (BIT(bits) - 1)
  24
  25 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask))
  26 #define ALE_VERSION_MINOR(rev)  (rev & 0xff)
  27 #define ALE_VERSION_1R3         0x0103
  28 #define ALE_VERSION_1R4         0x0104
  29
  30 /* ALE Registers */
  31 #define ALE_IDVER               0x00
  32 #define ALE_STATUS              0x04
  33 #define ALE_CONTROL             0x08
  34 #define ALE_PRESCALE            0x10
  35 #define ALE_AGING_TIMER         0x14
  36 #define ALE_UNKNOWNVLAN         0x18
  37 #define ALE_TABLE_CONTROL       0x20
  38 #define ALE_TABLE               0x34
  39 #define ALE_PORTCTL             0x40
  40
  41 /* ALE NetCP NU switch specific Registers */
  42 #define ALE_UNKNOWNVLAN_MEMBER                  0x90
  43 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD       0x94
  44 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD         0x98
  45 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS      0x9C
  46 #define ALE_VLAN_MASK_MUX(reg)                  (0xc0 + (0x4 * (reg)))
  47
  48 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134
  49
  50 /* ALE_AGING_TIMER */
  51 #define ALE_AGING_TIMER_MASK    GENMASK(23, 0)
  52
  53 /**
  54  * struct ale_entry_fld - The ALE tbl entry field description
  55  * @start_bit: field start bit
  56  * @num_bits: field bit length
  57  * @flags: field flags
  58  */
  59 struct ale_entry_fld {
  60         u8 start_bit;
  61         u8 num_bits;
  62         u8 flags;
  63 };
  64
  65 enum {
  66         CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */
  67         CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */
  68
  69         CPSW_ALE_F_COUNT
  70 };
  71
  72 /**
  73  * struct ale_dev_id - The ALE version/SoC specific configuration
  74  * @dev_id: ALE version/SoC id
  75  * @features: features supported by ALE
  76  * @tbl_entries: number of ALE entries
  77  * @major_ver_mask: mask of ALE Major Version Value in ALE_IDVER reg.
  78  * @nu_switch_ale: NU Switch ALE
  79  * @vlan_entry_tbl: ALE vlan entry fields description tbl
  80  */
  81 struct cpsw_ale_dev_id {
  82         const char *dev_id;
  83         u32 features;
  84         u32 tbl_entries;
  85         u32 major_ver_mask;
  86         bool nu_switch_ale;
  87         const struct ale_entry_fld *vlan_entry_tbl;
  88 };
  89
  90 #define ALE_TABLE_WRITE         BIT(31)
  91
  92 #define ALE_TYPE_FREE                   0
  93 #define ALE_TYPE_ADDR                   1
  94 #define ALE_TYPE_VLAN                   2
  95 #define ALE_TYPE_VLAN_ADDR              3
  96
  97 #define ALE_UCAST_PERSISTANT            0
  98 #define ALE_UCAST_UNTOUCHED             1
  99 #define ALE_UCAST_OUI                   2
 100 #define ALE_UCAST_TOUCHED               3
 101
 102 #define ALE_TABLE_SIZE_MULTIPLIER       1024
 103 #define ALE_STATUS_SIZE_MASK            0x1f
 104
 105 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 106 {
 107         int idx;
 108
 109         idx    = start / 32;
 110         start -= idx * 32;
 111         idx    = 2 - idx; /* flip */
 112         return (ale_entry[idx] >> start) & BITMASK(bits);
 113 }
 114
 115 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 116                                       u32 value)
 117 {
 118         int idx;
 119
 120         value &= BITMASK(bits);
 121         idx    = start / 32;
 122         start -= idx * 32;
 123         idx    = 2 - idx; /* flip */
 124         ale_entry[idx] &= ~(BITMASK(bits) << start);
 125         ale_entry[idx] |=  (value << start);
 126 }
 127
 128 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 129 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 130 {                                                                       \
 131         return cpsw_ale_get_field(ale_entry, start, bits);              \
 132 }                                                                       \
 133 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 134 {                                                                       \
 135         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 136 }
 137
 138 #define DEFINE_ALE_FIELD1(name, start)                                  \
 139 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits)         \
 140 {                                                                       \
 141         return cpsw_ale_get_field(ale_entry, start, bits);              \
 142 }                                                                       \
 143 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value,       \
 144                 u32 bits)                                               \
 145 {                                                                       \
 146         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 147 }
 148
 149 enum {
 150         ALE_ENT_VID_MEMBER_LIST = 0,
 151         ALE_ENT_VID_UNREG_MCAST_MSK,
 152         ALE_ENT_VID_REG_MCAST_MSK,
 153         ALE_ENT_VID_FORCE_UNTAGGED_MSK,
 154         ALE_ENT_VID_UNREG_MCAST_IDX,
 155         ALE_ENT_VID_REG_MCAST_IDX,
 156         ALE_ENT_VID_LAST,
 157 };
 158
 159 #define ALE_FLD_ALLOWED                 BIT(0)
 160 #define ALE_FLD_SIZE_PORT_MASK_BITS     BIT(1)
 161 #define ALE_FLD_SIZE_PORT_NUM_BITS      BIT(2)
 162
 163 #define ALE_ENTRY_FLD(id, start, bits)  \
 164 [id] = {                                \
 165         .start_bit = start,             \
 166         .num_bits = bits,               \
 167         .flags = ALE_FLD_ALLOWED,       \
 168 }
 169
 170 #define ALE_ENTRY_FLD_DYN_MSK_SIZE(id, start)   \
 171 [id] = {                                        \
 172         .start_bit = start,                     \
 173         .num_bits = 0,                          \
 174         .flags = ALE_FLD_ALLOWED |              \
 175                  ALE_FLD_SIZE_PORT_MASK_BITS,   \
 176 }
 177
 178 /* dm814x, am3/am4/am5, k2hk */
 179 static const struct ale_entry_fld vlan_entry_cpsw[ALE_ENT_VID_LAST] = {
 180         ALE_ENTRY_FLD(ALE_ENT_VID_MEMBER_LIST, 0, 3),
 181         ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_MSK, 8, 3),
 182         ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_MSK, 16, 3),
 183         ALE_ENTRY_FLD(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24, 3),
 184 };
 185
 186 /* k2e/k2l, k3 am65/j721e cpsw2g  */
 187 static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = {
 188         ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0),
 189         ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_IDX, 20, 3),
 190         ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24),
 191         ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3),
 192 };
 193
 194 DEFINE_ALE_FIELD(entry_type,            60,     2)
 195 DEFINE_ALE_FIELD(vlan_id,               48,     12)
 196 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 197 DEFINE_ALE_FIELD1(port_mask,            66)
 198 DEFINE_ALE_FIELD(super,                 65,     1)
 199 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 200 DEFINE_ALE_FIELD1(port_num,             66)
 201 DEFINE_ALE_FIELD(blocked,               65,     1)
 202 DEFINE_ALE_FIELD(secure,                64,     1)
 203 DEFINE_ALE_FIELD(mcast,                 40,     1)
 204
 205 #define NU_VLAN_UNREG_MCAST_IDX 1
 206
 207 static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale,
 208                                   u32 *ale_entry,
 209                                   const struct ale_entry_fld *entry_tbl,
 210                                   int fld_id)
 211 {
 212         const struct ale_entry_fld *entry_fld;
 213         u32 bits;
 214
 215         if (!ale || !ale_entry)
 216                 return -EINVAL;
 217
 218         entry_fld = &entry_tbl[fld_id];
 219         if (!(entry_fld->flags & ALE_FLD_ALLOWED)) {
 220                 dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id);
 221                 return -ENOENT;
 222         }
 223
 224         bits = entry_fld->num_bits;
 225         if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS)
 226                 bits = ale->port_mask_bits;
 227
 228         return cpsw_ale_get_field(ale_entry, entry_fld->start_bit, bits);
 229 }
 230
 231 static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale,
 232                                    u32 *ale_entry,
 233                                    const struct ale_entry_fld *entry_tbl,
 234                                    int fld_id,
 235                                    u32 value)
 236 {
 237         const struct ale_entry_fld *entry_fld;
 238         u32 bits;
 239
 240         if (!ale || !ale_entry)
 241                 return;
 242
 243         entry_fld = &entry_tbl[fld_id];
 244         if (!(entry_fld->flags & ALE_FLD_ALLOWED)) {
 245                 dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id);
 246                 return;
 247         }
 248
 249         bits = entry_fld->num_bits;
 250         if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS)
 251                 bits = ale->port_mask_bits;
 252
 253         cpsw_ale_set_field(ale_entry, entry_fld->start_bit, bits, value);
 254 }
 255
 256 static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale,
 257                                  u32 *ale_entry,
 258                                  int fld_id)
 259 {
 260         return cpsw_ale_entry_get_fld(ale, ale_entry,
 261                                       ale->vlan_entry_tbl, fld_id);
 262 }
 263
 264 static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale,
 265                                   u32 *ale_entry,
 266                                   int fld_id,
 267                                   u32 value)
 268 {
 269         cpsw_ale_entry_set_fld(ale, ale_entry,
 270                                ale->vlan_entry_tbl, fld_id, value);
 271 }
 272
 273 /* The MAC address field in the ALE entry cannot be macroized as above */
 274 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 275 {
 276         int i;
 277
 278         for (i = 0; i < 6; i++)
 279                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 280 }
 281
 282 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 283 {
 284         int i;
 285
 286         for (i = 0; i < 6; i++)
 287                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 288 }
 289
 290 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
 291 {
 292         int i;
 293
 294         WARN_ON(idx > ale->params.ale_entries);
 295
 296         writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
 297
 298         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 299                 ale_entry[i] = readl_relaxed(ale->params.ale_regs +
 300                                              ALE_TABLE + 4 * i);
 301
 302         return idx;
 303 }
 304
 305 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
 306 {
 307         int i;
 308
 309         WARN_ON(idx > ale->params.ale_entries);
 310
 311         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 312                 writel_relaxed(ale_entry[i], ale->params.ale_regs +
 313                                ALE_TABLE + 4 * i);
 314
 315         writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
 316                        ALE_TABLE_CONTROL);
 317
 318         return idx;
 319 }
 320
 321 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid)
 322 {
 323         u32 ale_entry[ALE_ENTRY_WORDS];
 324         int type, idx;
 325
 326         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 327                 u8 entry_addr[6];
 328
 329                 cpsw_ale_read(ale, idx, ale_entry);
 330                 type = cpsw_ale_get_entry_type(ale_entry);
 331                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 332                         continue;
 333                 if (cpsw_ale_get_vlan_id(ale_entry) != vid)
 334                         continue;
 335                 cpsw_ale_get_addr(ale_entry, entry_addr);
 336                 if (ether_addr_equal(entry_addr, addr))
 337                         return idx;
 338         }
 339         return -ENOENT;
 340 }
 341
 342 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
 343 {
 344         u32 ale_entry[ALE_ENTRY_WORDS];
 345         int type, idx;
 346
 347         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 348                 cpsw_ale_read(ale, idx, ale_entry);
 349                 type = cpsw_ale_get_entry_type(ale_entry);
 350                 if (type != ALE_TYPE_VLAN)
 351                         continue;
 352                 if (cpsw_ale_get_vlan_id(ale_entry) == vid)
 353                         return idx;
 354         }
 355         return -ENOENT;
 356 }
 357
 358 static int cpsw_ale_match_free(struct cpsw_ale *ale)
 359 {
 360         u32 ale_entry[ALE_ENTRY_WORDS];
 361         int type, idx;
 362
 363         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 364                 cpsw_ale_read(ale, idx, ale_entry);
 365                 type = cpsw_ale_get_entry_type(ale_entry);
 366                 if (type == ALE_TYPE_FREE)
 367                         return idx;
 368         }
 369         return -ENOENT;
 370 }
 371
 372 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
 373 {
 374         u32 ale_entry[ALE_ENTRY_WORDS];
 375         int type, idx;
 376
 377         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 378                 cpsw_ale_read(ale, idx, ale_entry);
 379                 type = cpsw_ale_get_entry_type(ale_entry);
 380                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 381                         continue;
 382                 if (cpsw_ale_get_mcast(ale_entry))
 383                         continue;
 384                 type = cpsw_ale_get_ucast_type(ale_entry);
 385                 if (type != ALE_UCAST_PERSISTANT &&
 386                     type != ALE_UCAST_OUI)
 387                         return idx;
 388         }
 389         return -ENOENT;
 390 }
 391
 392 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
 393                                  int port_mask)
 394 {
 395         int mask;
 396
 397         mask = cpsw_ale_get_port_mask(ale_entry,
 398                                       ale->port_mask_bits);
 399         if ((mask & port_mask) == 0)
 400                 return; /* ports dont intersect, not interested */
 401         mask &= ~port_mask;
 402
 403         /* free if only remaining port is host port */
 404         if (mask)
 405                 cpsw_ale_set_port_mask(ale_entry, mask,
 406                                        ale->port_mask_bits);
 407         else
 408                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 409 }
 410
 411 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
 412 {
 413         u32 ale_entry[ALE_ENTRY_WORDS];
 414         int ret, idx;
 415
 416         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 417                 cpsw_ale_read(ale, idx, ale_entry);
 418                 ret = cpsw_ale_get_entry_type(ale_entry);
 419                 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
 420                         continue;
 421
 422                 /* if vid passed is -1 then remove all multicast entry from
 423                  * the table irrespective of vlan id, if a valid vlan id is
 424                  * passed then remove only multicast added to that vlan id.
 425                  * if vlan id doesn't match then move on to next entry.
 426                  */
 427                 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
 428                         continue;
 429
 430                 if (cpsw_ale_get_mcast(ale_entry)) {
 431                         u8 addr[6];
 432
 433                         if (cpsw_ale_get_super(ale_entry))
 434                                 continue;
 435
 436                         cpsw_ale_get_addr(ale_entry, addr);
 437                         if (!is_broadcast_ether_addr(addr))
 438                                 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
 439                 }
 440
 441                 cpsw_ale_write(ale, idx, ale_entry);
 442         }
 443         return 0;
 444 }
 445
 446 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
 447                                                 int flags, u16 vid)
 448 {
 449         if (flags & ALE_VLAN) {
 450                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
 451                 cpsw_ale_set_vlan_id(ale_entry, vid);
 452         } else {
 453                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 454         }
 455 }
 456
 457 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
 458                        int flags, u16 vid)
 459 {
 460         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 461         int idx;
 462
 463         cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
 464
 465         cpsw_ale_set_addr(ale_entry, addr);
 466         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 467         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 468         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 469         cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits);
 470
 471         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 472         if (idx < 0)
 473                 idx = cpsw_ale_match_free(ale);
 474         if (idx < 0)
 475                 idx = cpsw_ale_find_ageable(ale);
 476         if (idx < 0)
 477                 return -ENOMEM;
 478
 479         cpsw_ale_write(ale, idx, ale_entry);
 480         return 0;
 481 }
 482
 483 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
 484                        int flags, u16 vid)
 485 {
 486         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 487         int idx;
 488
 489         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 490         if (idx < 0)
 491                 return -ENOENT;
 492
 493         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 494         cpsw_ale_write(ale, idx, ale_entry);
 495         return 0;
 496 }
 497
 498 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
 499                        int flags, u16 vid, int mcast_state)
 500 {
 501         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 502         int idx, mask;
 503
 504         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 505         if (idx >= 0)
 506                 cpsw_ale_read(ale, idx, ale_entry);
 507
 508         cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
 509
 510         cpsw_ale_set_addr(ale_entry, addr);
 511         cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0);
 512         cpsw_ale_set_mcast_state(ale_entry, mcast_state);
 513
 514         mask = cpsw_ale_get_port_mask(ale_entry,
 515                                       ale->port_mask_bits);
 516         port_mask |= mask;
 517         cpsw_ale_set_port_mask(ale_entry, port_mask,
 518                                ale->port_mask_bits);
 519
 520         if (idx < 0)
 521                 idx = cpsw_ale_match_free(ale);
 522         if (idx < 0)
 523                 idx = cpsw_ale_find_ageable(ale);
 524         if (idx < 0)
 525                 return -ENOMEM;
 526
 527         cpsw_ale_write(ale, idx, ale_entry);
 528         return 0;
 529 }
 530
 531 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
 532                        int flags, u16 vid)
 533 {
 534         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 535         int mcast_members = 0;
 536         int idx;
 537
 538         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 539         if (idx < 0)
 540                 return -ENOENT;
 541
 542         cpsw_ale_read(ale, idx, ale_entry);
 543
 544         if (port_mask) {
 545                 mcast_members = cpsw_ale_get_port_mask(ale_entry,
 546                                                        ale->port_mask_bits);
 547                 mcast_members &= ~port_mask;
 548         }
 549
 550         if (mcast_members)
 551                 cpsw_ale_set_port_mask(ale_entry, mcast_members,
 552                                        ale->port_mask_bits);
 553         else
 554                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 555
 556         cpsw_ale_write(ale, idx, ale_entry);
 557         return 0;
 558 }
 559
 560 /* ALE NetCP NU switch specific vlan functions */
 561 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
 562                                     int reg_mcast, int unreg_mcast)
 563 {
 564         int idx;
 565
 566         /* Set VLAN registered multicast flood mask */
 567         idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
 568                                     ALE_ENT_VID_REG_MCAST_IDX);
 569         writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
 570
 571         /* Set VLAN unregistered multicast flood mask */
 572         idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
 573                                     ALE_ENT_VID_UNREG_MCAST_IDX);
 574         writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
 575 }
 576
 577 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry,
 578                                     u16 vid, int untag_mask)
 579 {
 580         cpsw_ale_vlan_set_fld(ale, ale_entry,
 581                               ALE_ENT_VID_FORCE_UNTAGGED_MSK,
 582                               untag_mask);
 583         if (untag_mask & ALE_PORT_HOST)
 584                 bitmap_set(ale->p0_untag_vid_mask, vid, 1);
 585         else
 586                 bitmap_clear(ale->p0_untag_vid_mask, vid, 1);
 587 }
 588
 589 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag,
 590                       int reg_mcast, int unreg_mcast)
 591 {
 592         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 593         int idx;
 594
 595         idx = cpsw_ale_match_vlan(ale, vid);
 596         if (idx >= 0)
 597                 cpsw_ale_read(ale, idx, ale_entry);
 598
 599         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
 600         cpsw_ale_set_vlan_id(ale_entry, vid);
 601         cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
 602
 603         if (!ale->params.nu_switch_ale) {
 604                 cpsw_ale_vlan_set_fld(ale, ale_entry,
 605                                       ALE_ENT_VID_REG_MCAST_MSK, reg_mcast);
 606                 cpsw_ale_vlan_set_fld(ale, ale_entry,
 607                                       ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
 608         } else {
 609                 cpsw_ale_vlan_set_fld(ale, ale_entry,
 610                                       ALE_ENT_VID_UNREG_MCAST_IDX,
 611                                       NU_VLAN_UNREG_MCAST_IDX);
 612                 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast);
 613         }
 614
 615         cpsw_ale_vlan_set_fld(ale, ale_entry,
 616                               ALE_ENT_VID_MEMBER_LIST, port_mask);
 617
 618         if (idx < 0)
 619                 idx = cpsw_ale_match_free(ale);
 620         if (idx < 0)
 621                 idx = cpsw_ale_find_ageable(ale);
 622         if (idx < 0)
 623                 return -ENOMEM;
 624
 625         cpsw_ale_write(ale, idx, ale_entry);
 626         return 0;
 627 }
 628
 629 static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry,
 630                                      u16 vid, int port_mask)
 631 {
 632         int reg_mcast, unreg_mcast;
 633         int members, untag;
 634
 635         members = cpsw_ale_vlan_get_fld(ale, ale_entry,
 636                                         ALE_ENT_VID_MEMBER_LIST);
 637         members &= ~port_mask;
 638         if (!members) {
 639                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 640                 return;
 641         }
 642
 643         untag = cpsw_ale_vlan_get_fld(ale, ale_entry,
 644                                       ALE_ENT_VID_FORCE_UNTAGGED_MSK);
 645         reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
 646                                           ALE_ENT_VID_REG_MCAST_MSK);
 647         unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
 648                                             ALE_ENT_VID_UNREG_MCAST_MSK);
 649         untag &= members;
 650         reg_mcast &= members;
 651         unreg_mcast &= members;
 652
 653         cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
 654
 655         if (!ale->params.nu_switch_ale) {
 656                 cpsw_ale_vlan_set_fld(ale, ale_entry,
 657                                       ALE_ENT_VID_REG_MCAST_MSK, reg_mcast);
 658                 cpsw_ale_vlan_set_fld(ale, ale_entry,
 659                                       ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
 660         } else {
 661                 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast,
 662                                         unreg_mcast);
 663         }
 664         cpsw_ale_vlan_set_fld(ale, ale_entry,
 665                               ALE_ENT_VID_MEMBER_LIST, members);
 666 }
 667
 668 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
 669 {
 670         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 671         int idx;
 672
 673         idx = cpsw_ale_match_vlan(ale, vid);
 674         if (idx < 0)
 675                 return -ENOENT;
 676
 677         cpsw_ale_read(ale, idx, ale_entry);
 678
 679         if (port_mask) {
 680                 cpsw_ale_del_vlan_modify(ale, ale_entry, vid, port_mask);
 681         } else {
 682                 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
 683                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 684         }
 685
 686         cpsw_ale_write(ale, idx, ale_entry);
 687
 688         return 0;
 689 }
 690
 691 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
 692                              int untag_mask, int reg_mask, int unreg_mask)
 693 {
 694         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 695         int reg_mcast_members, unreg_mcast_members;
 696         int vlan_members, untag_members;
 697         int idx, ret = 0;
 698
 699         idx = cpsw_ale_match_vlan(ale, vid);
 700         if (idx >= 0)
 701                 cpsw_ale_read(ale, idx, ale_entry);
 702
 703         vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
 704                                              ALE_ENT_VID_MEMBER_LIST);
 705         reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
 706                                                   ALE_ENT_VID_REG_MCAST_MSK);
 707         unreg_mcast_members =
 708                 cpsw_ale_vlan_get_fld(ale, ale_entry,
 709                                       ALE_ENT_VID_UNREG_MCAST_MSK);
 710         untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
 711                                               ALE_ENT_VID_FORCE_UNTAGGED_MSK);
 712
 713         vlan_members |= port_mask;
 714         untag_members = (untag_members & ~port_mask) | untag_mask;
 715         reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask;
 716         unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask;
 717
 718         ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members,
 719                                 reg_mcast_members, unreg_mcast_members);
 720         if (ret) {
 721                 dev_err(ale->params.dev, "Unable to add vlan\n");
 722                 return ret;
 723         }
 724         dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members,
 725                 untag_mask);
 726
 727         return ret;
 728 }
 729
 730 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
 731                               bool add)
 732 {
 733         u32 ale_entry[ALE_ENTRY_WORDS];
 734         int unreg_members = 0;
 735         int type, idx;
 736
 737         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 738                 cpsw_ale_read(ale, idx, ale_entry);
 739                 type = cpsw_ale_get_entry_type(ale_entry);
 740                 if (type != ALE_TYPE_VLAN)
 741                         continue;
 742
 743                 unreg_members =
 744                         cpsw_ale_vlan_get_fld(ale, ale_entry,
 745                                               ALE_ENT_VID_UNREG_MCAST_MSK);
 746                 if (add)
 747                         unreg_members |= unreg_mcast_mask;
 748                 else
 749                         unreg_members &= ~unreg_mcast_mask;
 750                 cpsw_ale_vlan_set_fld(ale, ale_entry,
 751                                       ALE_ENT_VID_UNREG_MCAST_MSK,
 752                                       unreg_members);
 753                 cpsw_ale_write(ale, idx, ale_entry);
 754         }
 755 }
 756
 757 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry,
 758                                           int allmulti)
 759 {
 760         int unreg_mcast;
 761
 762         unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
 763                                             ALE_ENT_VID_UNREG_MCAST_MSK);
 764         if (allmulti)
 765                 unreg_mcast |= ALE_PORT_HOST;
 766         else
 767                 unreg_mcast &= ~ALE_PORT_HOST;
 768
 769         cpsw_ale_vlan_set_fld(ale, ale_entry,
 770                               ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
 771 }
 772
 773 static void
 774 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry,
 775                                   int allmulti)
 776 {
 777         int unreg_mcast;
 778         int idx;
 779
 780         idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
 781                                     ALE_ENT_VID_UNREG_MCAST_IDX);
 782
 783         unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
 784
 785         if (allmulti)
 786                 unreg_mcast |= ALE_PORT_HOST;
 787         else
 788                 unreg_mcast &= ~ALE_PORT_HOST;
 789
 790         writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
 791 }
 792
 793 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
 794 {
 795         u32 ale_entry[ALE_ENTRY_WORDS];
 796         int type, idx;
 797
 798         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 799                 int vlan_members;
 800
 801                 cpsw_ale_read(ale, idx, ale_entry);
 802                 type = cpsw_ale_get_entry_type(ale_entry);
 803                 if (type != ALE_TYPE_VLAN)
 804                         continue;
 805
 806                 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
 807                                                      ALE_ENT_VID_MEMBER_LIST);
 808
 809                 if (port != -1 && !(vlan_members & BIT(port)))
 810                         continue;
 811
 812                 if (!ale->params.nu_switch_ale)
 813                         cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti);
 814                 else
 815                         cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry,
 816                                                           allmulti);
 817
 818                 cpsw_ale_write(ale, idx, ale_entry);
 819         }
 820 }
 821
 822 struct ale_control_info {
 823         const char      *name;
 824         int             offset, port_offset;
 825         int             shift, port_shift;
 826         int             bits;
 827 };
 828
 829 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
 830         [ALE_ENABLE]            = {
 831                 .name           = "enable",
 832                 .offset         = ALE_CONTROL,
 833                 .port_offset    = 0,
 834                 .shift          = 31,
 835                 .port_shift     = 0,
 836                 .bits           = 1,
 837         },
 838         [ALE_CLEAR]             = {
 839                 .name           = "clear",
 840                 .offset         = ALE_CONTROL,
 841                 .port_offset    = 0,
 842                 .shift          = 30,
 843                 .port_shift     = 0,
 844                 .bits           = 1,
 845         },
 846         [ALE_AGEOUT]            = {
 847                 .name           = "ageout",
 848                 .offset         = ALE_CONTROL,
 849                 .port_offset    = 0,
 850                 .shift          = 29,
 851                 .port_shift     = 0,
 852                 .bits           = 1,
 853         },
 854         [ALE_P0_UNI_FLOOD]      = {
 855                 .name           = "port0_unicast_flood",
 856                 .offset         = ALE_CONTROL,
 857                 .port_offset    = 0,
 858                 .shift          = 8,
 859                 .port_shift     = 0,
 860                 .bits           = 1,
 861         },
 862         [ALE_VLAN_NOLEARN]      = {
 863                 .name           = "vlan_nolearn",
 864                 .offset         = ALE_CONTROL,
 865                 .port_offset    = 0,
 866                 .shift          = 7,
 867                 .port_shift     = 0,
 868                 .bits           = 1,
 869         },
 870         [ALE_NO_PORT_VLAN]      = {
 871                 .name           = "no_port_vlan",
 872                 .offset         = ALE_CONTROL,
 873                 .port_offset    = 0,
 874                 .shift          = 6,
 875                 .port_shift     = 0,
 876                 .bits           = 1,
 877         },
 878         [ALE_OUI_DENY]          = {
 879                 .name           = "oui_deny",
 880                 .offset         = ALE_CONTROL,
 881                 .port_offset    = 0,
 882                 .shift          = 5,
 883                 .port_shift     = 0,
 884                 .bits           = 1,
 885         },
 886         [ALE_BYPASS]            = {
 887                 .name           = "bypass",
 888                 .offset         = ALE_CONTROL,
 889                 .port_offset    = 0,
 890                 .shift          = 4,
 891                 .port_shift     = 0,
 892                 .bits           = 1,
 893         },
 894         [ALE_RATE_LIMIT_TX]     = {
 895                 .name           = "rate_limit_tx",
 896                 .offset         = ALE_CONTROL,
 897                 .port_offset    = 0,
 898                 .shift          = 3,
 899                 .port_shift     = 0,
 900                 .bits           = 1,
 901         },
 902         [ALE_VLAN_AWARE]        = {
 903                 .name           = "vlan_aware",
 904                 .offset         = ALE_CONTROL,
 905                 .port_offset    = 0,
 906                 .shift          = 2,
 907                 .port_shift     = 0,
 908                 .bits           = 1,
 909         },
 910         [ALE_AUTH_ENABLE]       = {
 911                 .name           = "auth_enable",
 912                 .offset         = ALE_CONTROL,
 913                 .port_offset    = 0,
 914                 .shift          = 1,
 915                 .port_shift     = 0,
 916                 .bits           = 1,
 917         },
 918         [ALE_RATE_LIMIT]        = {
 919                 .name           = "rate_limit",
 920                 .offset         = ALE_CONTROL,
 921                 .port_offset    = 0,
 922                 .shift          = 0,
 923                 .port_shift     = 0,
 924                 .bits           = 1,
 925         },
 926         [ALE_PORT_STATE]        = {
 927                 .name           = "port_state",
 928                 .offset         = ALE_PORTCTL,
 929                 .port_offset    = 4,
 930                 .shift          = 0,
 931                 .port_shift     = 0,
 932                 .bits           = 2,
 933         },
 934         [ALE_PORT_DROP_UNTAGGED] = {
 935                 .name           = "drop_untagged",
 936                 .offset         = ALE_PORTCTL,
 937                 .port_offset    = 4,
 938                 .shift          = 2,
 939                 .port_shift     = 0,
 940                 .bits           = 1,
 941         },
 942         [ALE_PORT_DROP_UNKNOWN_VLAN] = {
 943                 .name           = "drop_unknown",
 944                 .offset         = ALE_PORTCTL,
 945                 .port_offset    = 4,
 946                 .shift          = 3,
 947                 .port_shift     = 0,
 948                 .bits           = 1,
 949         },
 950         [ALE_PORT_NOLEARN]      = {
 951                 .name           = "nolearn",
 952                 .offset         = ALE_PORTCTL,
 953                 .port_offset    = 4,
 954                 .shift          = 4,
 955                 .port_shift     = 0,
 956                 .bits           = 1,
 957         },
 958         [ALE_PORT_NO_SA_UPDATE] = {
 959                 .name           = "no_source_update",
 960                 .offset         = ALE_PORTCTL,
 961                 .port_offset    = 4,
 962                 .shift          = 5,
 963                 .port_shift     = 0,
 964                 .bits           = 1,
 965         },
 966         [ALE_PORT_MACONLY]      = {
 967                 .name           = "mac_only_port_mode",
 968                 .offset         = ALE_PORTCTL,
 969                 .port_offset    = 4,
 970                 .shift          = 11,
 971                 .port_shift     = 0,
 972                 .bits           = 1,
 973         },
 974         [ALE_PORT_MACONLY_CAF]  = {
 975                 .name           = "mac_only_port_caf",
 976                 .offset         = ALE_PORTCTL,
 977                 .port_offset    = 4,
 978                 .shift          = 13,
 979                 .port_shift     = 0,
 980                 .bits           = 1,
 981         },
 982         [ALE_PORT_MCAST_LIMIT]  = {
 983                 .name           = "mcast_limit",
 984                 .offset         = ALE_PORTCTL,
 985                 .port_offset    = 4,
 986                 .shift          = 16,
 987                 .port_shift     = 0,
 988                 .bits           = 8,
 989         },
 990         [ALE_PORT_BCAST_LIMIT]  = {
 991                 .name           = "bcast_limit",
 992                 .offset         = ALE_PORTCTL,
 993                 .port_offset    = 4,
 994                 .shift          = 24,
 995                 .port_shift     = 0,
 996                 .bits           = 8,
 997         },
 998         [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
 999                 .name           = "unknown_vlan_member",
1000                 .offset         = ALE_UNKNOWNVLAN,
1001                 .port_offset    = 0,
1002                 .shift          = 0,
1003                 .port_shift     = 0,
1004                 .bits           = 6,
1005         },
1006         [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
1007                 .name           = "unknown_mcast_flood",
1008                 .offset         = ALE_UNKNOWNVLAN,
1009                 .port_offset    = 0,
1010                 .shift          = 8,
1011                 .port_shift     = 0,
1012                 .bits           = 6,
1013         },
1014         [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
1015                 .name           = "unknown_reg_flood",
1016                 .offset         = ALE_UNKNOWNVLAN,
1017                 .port_offset    = 0,
1018                 .shift          = 16,
1019                 .port_shift     = 0,
1020                 .bits           = 6,
1021         },
1022         [ALE_PORT_UNTAGGED_EGRESS] = {
1023                 .name           = "untagged_egress",
1024                 .offset         = ALE_UNKNOWNVLAN,
1025                 .port_offset    = 0,
1026                 .shift          = 24,
1027                 .port_shift     = 0,
1028                 .bits           = 6,
1029         },
1030         [ALE_DEFAULT_THREAD_ID] = {
1031                 .name           = "default_thread_id",
1032                 .offset         = AM65_CPSW_ALE_THREAD_DEF_REG,
1033                 .port_offset    = 0,
1034                 .shift          = 0,
1035                 .port_shift     = 0,
1036                 .bits           = 6,
1037         },
1038         [ALE_DEFAULT_THREAD_ENABLE] = {
1039                 .name           = "default_thread_id_enable",
1040                 .offset         = AM65_CPSW_ALE_THREAD_DEF_REG,
1041                 .port_offset    = 0,
1042                 .shift          = 15,
1043                 .port_shift     = 0,
1044                 .bits           = 1,
1045         },
1046 };
1047
1048 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
1049                          int value)
1050 {
1051         const struct ale_control_info *info;
1052         int offset, shift;
1053         u32 tmp, mask;
1054
1055         if (control < 0 || control >= ARRAY_SIZE(ale_controls))
1056                 return -EINVAL;
1057
1058         info = &ale_controls[control];
1059         if (info->port_offset == 0 && info->port_shift == 0)
1060                 port = 0; /* global, port is a dont care */
1061
1062         if (port < 0 || port >= ale->params.ale_ports)
1063                 return -EINVAL;
1064
1065         mask = BITMASK(info->bits);
1066         if (value & ~mask)
1067                 return -EINVAL;
1068
1069         offset = info->offset + (port * info->port_offset);
1070         shift  = info->shift  + (port * info->port_shift);
1071
1072         tmp = readl_relaxed(ale->params.ale_regs + offset);
1073         tmp = (tmp & ~(mask << shift)) | (value << shift);
1074         writel_relaxed(tmp, ale->params.ale_regs + offset);
1075
1076         return 0;
1077 }
1078
1079 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
1080 {
1081         const struct ale_control_info *info;
1082         int offset, shift;
1083         u32 tmp;
1084
1085         if (control < 0 || control >= ARRAY_SIZE(ale_controls))
1086                 return -EINVAL;
1087
1088         info = &ale_controls[control];
1089         if (info->port_offset == 0 && info->port_shift == 0)
1090                 port = 0; /* global, port is a dont care */
1091
1092         if (port < 0 || port >= ale->params.ale_ports)
1093                 return -EINVAL;
1094
1095         offset = info->offset + (port * info->port_offset);
1096         shift  = info->shift  + (port * info->port_shift);
1097
1098         tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
1099         return tmp & BITMASK(info->bits);
1100 }
1101
1102 static void cpsw_ale_timer(struct timer_list *t)
1103 {
1104         struct cpsw_ale *ale = from_timer(ale, t, timer);
1105
1106         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
1107
1108         if (ale->ageout) {
1109                 ale->timer.expires = jiffies + ale->ageout;
1110                 add_timer(&ale->timer);
1111         }
1112 }
1113
1114 static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale)
1115 {
1116         u32 aging_timer;
1117
1118         aging_timer = ale->params.bus_freq / 1000000;
1119         aging_timer *= ale->params.ale_ageout;
1120
1121         if (aging_timer & ~ALE_AGING_TIMER_MASK) {
1122                 aging_timer = ALE_AGING_TIMER_MASK;
1123                 dev_warn(ale->params.dev,
1124                          "ALE aging timer overflow, set to max\n");
1125         }
1126
1127         writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER);
1128 }
1129
1130 static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale)
1131 {
1132         writel(0, ale->params.ale_regs + ALE_AGING_TIMER);
1133 }
1134
1135 static void cpsw_ale_aging_start(struct cpsw_ale *ale)
1136 {
1137         if (!ale->params.ale_ageout)
1138                 return;
1139
1140         if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1141                 cpsw_ale_hw_aging_timer_start(ale);
1142                 return;
1143         }
1144
1145         timer_setup(&ale->timer, cpsw_ale_timer, 0);
1146         ale->timer.expires = jiffies + ale->ageout;
1147         add_timer(&ale->timer);
1148 }
1149
1150 static void cpsw_ale_aging_stop(struct cpsw_ale *ale)
1151 {
1152         if (!ale->params.ale_ageout)
1153                 return;
1154
1155         if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1156                 cpsw_ale_hw_aging_timer_stop(ale);
1157                 return;
1158         }
1159
1160         del_timer_sync(&ale->timer);
1161 }
1162
1163 void cpsw_ale_start(struct cpsw_ale *ale)
1164 {
1165         cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
1166         cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1167
1168         cpsw_ale_aging_start(ale);
1169 }
1170
1171 void cpsw_ale_stop(struct cpsw_ale *ale)
1172 {
1173         cpsw_ale_aging_stop(ale);
1174         cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1175         cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
1176 }
1177
1178 static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = {
1179         {
1180                 /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */
1181                 .dev_id = "cpsw",
1182                 .tbl_entries = 1024,
1183                 .major_ver_mask = 0xff,
1184                 .vlan_entry_tbl = vlan_entry_cpsw,
1185         },
1186         {
1187                 /* 66ak2h_xgbe */
1188                 .dev_id = "66ak2h-xgbe",
1189                 .tbl_entries = 2048,
1190                 .major_ver_mask = 0xff,
1191                 .vlan_entry_tbl = vlan_entry_cpsw,
1192         },
1193         {
1194                 .dev_id = "66ak2el",
1195                 .features = CPSW_ALE_F_STATUS_REG,
1196                 .major_ver_mask = 0x7,
1197                 .nu_switch_ale = true,
1198                 .vlan_entry_tbl = vlan_entry_nu,
1199         },
1200         {
1201                 .dev_id = "66ak2g",
1202                 .features = CPSW_ALE_F_STATUS_REG,
1203                 .tbl_entries = 64,
1204                 .major_ver_mask = 0x7,
1205                 .nu_switch_ale = true,
1206                 .vlan_entry_tbl = vlan_entry_nu,
1207         },
1208         {
1209                 .dev_id = "am65x-cpsw2g",
1210                 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING,
1211                 .tbl_entries = 64,
1212                 .major_ver_mask = 0x7,
1213                 .nu_switch_ale = true,
1214                 .vlan_entry_tbl = vlan_entry_nu,
1215         },
1216         { },
1217 };
1218
1219 static const struct
1220 cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id,
1221                                    const char *dev_id)
1222 {
1223         if (!dev_id)
1224                 return NULL;
1225
1226         while (id->dev_id) {
1227                 if (strcmp(dev_id, id->dev_id) == 0)
1228                         return id;
1229                 id++;
1230         }
1231         return NULL;
1232 }
1233
1234 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
1235 {
1236         const struct cpsw_ale_dev_id *ale_dev_id;
1237         struct cpsw_ale *ale;
1238         u32 rev, ale_entries;
1239
1240         ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id);
1241         if (!ale_dev_id)
1242                 return ERR_PTR(-EINVAL);
1243
1244         params->ale_entries = ale_dev_id->tbl_entries;
1245         params->major_ver_mask = ale_dev_id->major_ver_mask;
1246         params->nu_switch_ale = ale_dev_id->nu_switch_ale;
1247
1248         ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL);
1249         if (!ale)
1250                 return ERR_PTR(-ENOMEM);
1251
1252         ale->p0_untag_vid_mask =
1253                 devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID),
1254                                    sizeof(unsigned long),
1255                                    GFP_KERNEL);
1256         if (!ale->p0_untag_vid_mask)
1257                 return ERR_PTR(-ENOMEM);
1258
1259         ale->params = *params;
1260         ale->ageout = ale->params.ale_ageout * HZ;
1261         ale->features = ale_dev_id->features;
1262         ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl;
1263
1264         rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER);
1265         ale->version =
1266                 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) |
1267                  ALE_VERSION_MINOR(rev);
1268         dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n",
1269                  ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask),
1270                  ALE_VERSION_MINOR(rev));
1271
1272         if (ale->features & CPSW_ALE_F_STATUS_REG &&
1273             !ale->params.ale_entries) {
1274                 ale_entries =
1275                         readl_relaxed(ale->params.ale_regs + ALE_STATUS) &
1276                         ALE_STATUS_SIZE_MASK;
1277                 /* ALE available on newer NetCP switches has introduced
1278                  * a register, ALE_STATUS, to indicate the size of ALE
1279                  * table which shows the size as a multiple of 1024 entries.
1280                  * For these, params.ale_entries will be set to zero. So
1281                  * read the register and update the value of ale_entries.
1282                  * return error if ale_entries is zero in ALE_STATUS.
1283                  */
1284                 if (!ale_entries)
1285                         return ERR_PTR(-EINVAL);
1286
1287                 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER;
1288                 ale->params.ale_entries = ale_entries;
1289         }
1290         dev_info(ale->params.dev,
1291                  "ALE Table size %ld\n", ale->params.ale_entries);
1292
1293         /* set default bits for existing h/w */
1294         ale->port_mask_bits = ale->params.ale_ports;
1295         ale->port_num_bits = order_base_2(ale->params.ale_ports);
1296         ale->vlan_field_bits = ale->params.ale_ports;
1297
1298         /* Set defaults override for ALE on NetCP NU switch and for version
1299          * 1R3
1300          */
1301         if (ale->params.nu_switch_ale) {
1302                 /* Separate registers for unknown vlan configuration.
1303                  * Also there are N bits, where N is number of ale
1304                  * ports and shift value should be 0
1305                  */
1306                 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits =
1307                                         ale->params.ale_ports;
1308                 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset =
1309                                         ALE_UNKNOWNVLAN_MEMBER;
1310                 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits =
1311                                         ale->params.ale_ports;
1312                 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0;
1313                 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset =
1314                                         ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD;
1315                 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits =
1316                                         ale->params.ale_ports;
1317                 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0;
1318                 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset =
1319                                         ALE_UNKNOWNVLAN_REG_MCAST_FLOOD;
1320                 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits =
1321                                         ale->params.ale_ports;
1322                 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0;
1323                 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset =
1324                                         ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS;
1325         }
1326
1327         cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1328         return ale;
1329 }
1330
1331 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
1332 {
1333         int i;
1334
1335         for (i = 0; i < ale->params.ale_entries; i++) {
1336                 cpsw_ale_read(ale, i, data);
1337                 data += ALE_ENTRY_WORDS;
1338         }
1339 }
1340
1341 u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale)
1342 {
1343         return ale ? ale->params.ale_entries : 0;
1344 }