2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/phy/phy.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/gpio/consumer.h>
35 #include <linux/of_mdio.h>
36 #include <linux/of_net.h>
37 #include <linux/of_device.h>
38 #include <linux/if_vlan.h>
39 #include <linux/kmemleak.h>
40 #include <linux/sys_soc.h>
42 #include <linux/pinctrl/consumer.h>
43 #include <net/pkt_cls.h>
48 #include "davinci_cpdma.h"
50 #include <net/pkt_sched.h>
52 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
53 NETIF_MSG_DRV | NETIF_MSG_LINK | \
54 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
55 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
56 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
58 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
61 #define cpsw_info(priv, type, format, ...) \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_info(priv->dev, format, ## __VA_ARGS__); \
67 #define cpsw_err(priv, type, format, ...) \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_err(priv->dev, format, ## __VA_ARGS__); \
73 #define cpsw_dbg(priv, type, format, ...) \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
79 #define cpsw_notice(priv, type, format, ...) \
81 if (netif_msg_##type(priv) && net_ratelimit()) \
82 dev_notice(priv->dev, format, ## __VA_ARGS__); \
85 #define ALE_ALL_PORTS 0x7
87 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
88 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
89 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
91 #define CPSW_VERSION_1 0x19010a
92 #define CPSW_VERSION_2 0x19010c
93 #define CPSW_VERSION_3 0x19010f
94 #define CPSW_VERSION_4 0x190112
96 #define HOST_PORT_NUM 0
97 #define CPSW_ALE_PORTS_NUM 3
98 #define SLIVER_SIZE 0x40
100 #define CPSW1_HOST_PORT_OFFSET 0x028
101 #define CPSW1_SLAVE_OFFSET 0x050
102 #define CPSW1_SLAVE_SIZE 0x040
103 #define CPSW1_CPDMA_OFFSET 0x100
104 #define CPSW1_STATERAM_OFFSET 0x200
105 #define CPSW1_HW_STATS 0x400
106 #define CPSW1_CPTS_OFFSET 0x500
107 #define CPSW1_ALE_OFFSET 0x600
108 #define CPSW1_SLIVER_OFFSET 0x700
110 #define CPSW2_HOST_PORT_OFFSET 0x108
111 #define CPSW2_SLAVE_OFFSET 0x200
112 #define CPSW2_SLAVE_SIZE 0x100
113 #define CPSW2_CPDMA_OFFSET 0x800
114 #define CPSW2_HW_STATS 0x900
115 #define CPSW2_STATERAM_OFFSET 0xa00
116 #define CPSW2_CPTS_OFFSET 0xc00
117 #define CPSW2_ALE_OFFSET 0xd00
118 #define CPSW2_SLIVER_OFFSET 0xd80
119 #define CPSW2_BD_OFFSET 0x2000
121 #define CPDMA_RXTHRESH 0x0c0
122 #define CPDMA_RXFREE 0x0e0
123 #define CPDMA_TXHDP 0x00
124 #define CPDMA_RXHDP 0x20
125 #define CPDMA_TXCP 0x40
126 #define CPDMA_RXCP 0x60
128 #define CPSW_POLL_WEIGHT 64
129 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4
130 #define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN)
131 #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\
133 CPSW_RX_VLAN_ENCAP_HDR_SIZE)
135 #define RX_PRIORITY_MAPPING 0x76543210
136 #define TX_PRIORITY_MAPPING 0x33221100
137 #define CPDMA_TX_PRIORITY_MAP 0x76543210
139 #define CPSW_VLAN_AWARE BIT(1)
140 #define CPSW_RX_VLAN_ENCAP BIT(2)
141 #define CPSW_ALE_VLAN_AWARE 1
143 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
144 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
145 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
147 #define CPSW_INTPACEEN (0x3f << 16)
148 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
149 #define CPSW_CMINTMAX_CNT 63
150 #define CPSW_CMINTMIN_CNT 2
151 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
152 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
154 #define cpsw_slave_index(cpsw, priv) \
155 ((cpsw->data.dual_emac) ? priv->emac_port : \
156 cpsw->data.active_slave)
158 #define CPSW_MAX_QUEUES 8
159 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
160 #define CPSW_FIFO_QUEUE_TYPE_SHIFT 16
161 #define CPSW_FIFO_SHAPE_EN_SHIFT 16
162 #define CPSW_FIFO_RATE_EN_SHIFT 20
163 #define CPSW_TC_NUM 4
164 #define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
165 #define CPSW_PCT_MASK 0x7f
167 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
168 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
169 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16
170 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8
171 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
173 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
174 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
175 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
176 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
179 static int debug_level;
180 module_param(debug_level, int, 0);
181 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
183 static int ale_ageout = 10;
184 module_param(ale_ageout, int, 0);
185 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
187 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
188 module_param(rx_packet_max, int, 0);
189 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
191 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
192 module_param(descs_pool_size, int, 0444);
193 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
195 struct cpsw_wr_regs {
215 struct cpsw_ss_regs {
232 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
233 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
234 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
235 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
236 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
237 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
238 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
239 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
242 #define CPSW2_CONTROL 0x00 /* Control Register */
243 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
244 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
245 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
246 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
247 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
248 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
250 /* CPSW_PORT_V1 and V2 */
251 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
252 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
253 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
255 /* CPSW_PORT_V2 only */
256 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
257 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
258 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
259 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
260 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
261 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
262 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
263 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
265 /* Bit definitions for the CPSW2_CONTROL register */
266 #define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */
267 #define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */
268 #define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */
269 #define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */
270 #define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */
271 #define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */
272 #define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */
273 #define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */
274 #define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */
275 #define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */
276 #define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */
277 #define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */
278 #define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */
279 #define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */
280 #define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */
281 #define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */
282 #define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */
283 #define TS_RX_EN BIT(0) /* Time Sync Receive Enable */
285 #define CTRL_V2_TS_BITS \
286 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
287 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
289 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
290 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
291 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
294 #define CTRL_V3_TS_BITS \
295 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
296 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
297 TS_LTYPE1_EN | VLAN_LTYPE1_EN)
299 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
300 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
301 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
303 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
304 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
305 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
306 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
307 #define TS_MSG_TYPE_EN_MASK (0xffff)
309 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
310 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
312 /* Bit definitions for the CPSW1_TS_CTL register */
313 #define CPSW_V1_TS_RX_EN BIT(0)
314 #define CPSW_V1_TS_TX_EN BIT(4)
315 #define CPSW_V1_MSG_TYPE_OFS 16
317 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
318 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
320 #define CPSW_MAX_BLKS_TX 15
321 #define CPSW_MAX_BLKS_TX_SHIFT 4
322 #define CPSW_MAX_BLKS_RX 5
324 struct cpsw_host_regs {
330 u32 cpdma_tx_pri_map;
331 u32 cpdma_rx_chan_map;
334 struct cpsw_sliver_regs {
347 struct cpsw_hw_stats {
349 u32 rxbroadcastframes;
350 u32 rxmulticastframes;
353 u32 rxaligncodeerrors;
354 u32 rxoversizedframes;
356 u32 rxundersizedframes;
361 u32 txbroadcastframes;
362 u32 txmulticastframes;
364 u32 txdeferredframes;
365 u32 txcollisionframes;
366 u32 txsinglecollframes;
367 u32 txmultcollframes;
368 u32 txexcessivecollisions;
369 u32 txlatecollisions;
371 u32 txcarriersenseerrors;
374 u32 octetframes65t127;
375 u32 octetframes128t255;
376 u32 octetframes256t511;
377 u32 octetframes512t1023;
378 u32 octetframes1024tup;
385 struct cpsw_slave_data {
386 struct device_node *phy_node;
387 char phy_id[MII_BUS_ID_SIZE];
389 u8 mac_addr[ETH_ALEN];
390 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
394 struct cpsw_platform_data {
395 struct cpsw_slave_data *slave_data;
396 u32 ss_reg_ofs; /* Subsystem control register offset */
397 u32 channels; /* number of cpdma channels (symmetric) */
398 u32 slaves; /* number of slave cpgmac ports */
399 u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
400 u32 ale_entries; /* ale table size */
401 u32 bd_ram_size; /*buffer descriptor ram size */
402 u32 mac_control; /* Mac control register */
403 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
404 bool dual_emac; /* Enable Dual EMAC mode */
409 struct cpsw_sliver_regs __iomem *sliver;
412 struct cpsw_slave_data *data;
413 struct phy_device *phy;
414 struct net_device *ndev;
418 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
420 return readl_relaxed(slave->regs + offset);
423 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
425 writel_relaxed(val, slave->regs + offset);
429 struct cpdma_chan *ch;
435 struct cpsw_platform_data data;
436 struct napi_struct napi_rx;
437 struct napi_struct napi_tx;
438 struct cpsw_ss_regs __iomem *regs;
439 struct cpsw_wr_regs __iomem *wr_regs;
440 u8 __iomem *hw_stats;
441 struct cpsw_host_regs __iomem *host_port_regs;
446 struct cpsw_slave *slaves;
447 struct cpdma_ctlr *dma;
448 struct cpsw_vector txv[CPSW_MAX_QUEUES];
449 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
450 struct cpsw_ale *ale;
452 bool rx_irq_disabled;
453 bool tx_irq_disabled;
454 u32 irqs_table[IRQ_NUM];
456 int rx_ch_num, tx_ch_num;
462 struct net_device *ndev;
465 u8 mac_addr[ETH_ALEN];
469 int fifo_bw[CPSW_TC_NUM];
474 struct cpsw_common *cpsw;
478 char stat_string[ETH_GSTRING_LEN];
490 #define CPSW_STAT(m) CPSW_STATS, \
491 FIELD_SIZEOF(struct cpsw_hw_stats, m), \
492 offsetof(struct cpsw_hw_stats, m)
493 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
494 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
495 offsetof(struct cpdma_chan_stats, m)
496 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
497 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
498 offsetof(struct cpdma_chan_stats, m)
500 static const struct cpsw_stats cpsw_gstrings_stats[] = {
501 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
502 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
503 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
504 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
505 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
506 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
507 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
508 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
509 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
510 { "Rx Fragments", CPSW_STAT(rxfragments) },
511 { "Rx Octets", CPSW_STAT(rxoctets) },
512 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
513 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
514 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
515 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
516 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
517 { "Collisions", CPSW_STAT(txcollisionframes) },
518 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
519 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
520 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
521 { "Late Collisions", CPSW_STAT(txlatecollisions) },
522 { "Tx Underrun", CPSW_STAT(txunderrun) },
523 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
524 { "Tx Octets", CPSW_STAT(txoctets) },
525 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
526 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
527 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
528 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
529 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
530 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
531 { "Net Octets", CPSW_STAT(netoctets) },
532 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
533 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
534 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
537 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
538 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
539 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
540 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
541 { "misqueued", CPDMA_RX_STAT(misqueued) },
542 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
543 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
544 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
545 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
546 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
547 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
548 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
549 { "requeue", CPDMA_RX_STAT(requeue) },
550 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
553 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
554 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
556 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
557 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
558 #define for_each_slave(priv, func, arg...) \
560 struct cpsw_slave *slave; \
561 struct cpsw_common *cpsw = (priv)->cpsw; \
563 if (cpsw->data.dual_emac) \
564 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
566 for (n = cpsw->data.slaves, \
567 slave = cpsw->slaves; \
569 (func)(slave++, ##arg); \
572 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
573 __be16 proto, u16 vid);
575 static inline int cpsw_get_slave_port(u32 slave_num)
577 return slave_num + 1;
580 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
582 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
583 struct cpsw_ale *ale = cpsw->ale;
586 if (cpsw->data.dual_emac) {
589 /* Enabling promiscuous mode for one interface will be
590 * common for both the interface as the interface shares
591 * the same hardware resource.
593 for (i = 0; i < cpsw->data.slaves; i++)
594 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
597 if (!enable && flag) {
599 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
604 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
606 dev_dbg(&ndev->dev, "promiscuity enabled\n");
609 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
610 dev_dbg(&ndev->dev, "promiscuity disabled\n");
614 unsigned long timeout = jiffies + HZ;
616 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
617 for (i = 0; i <= cpsw->data.slaves; i++) {
618 cpsw_ale_control_set(ale, i,
619 ALE_PORT_NOLEARN, 1);
620 cpsw_ale_control_set(ale, i,
621 ALE_PORT_NO_SA_UPDATE, 1);
624 /* Clear All Untouched entries */
625 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
628 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
630 } while (time_after(timeout, jiffies));
631 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
633 /* Clear all mcast from ALE */
634 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
635 __hw_addr_ref_unsync_dev(&ndev->mc, ndev, NULL);
637 /* Flood All Unicast Packets to Host port */
638 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
639 dev_dbg(&ndev->dev, "promiscuity enabled\n");
641 /* Don't Flood All Unicast Packets to Host port */
642 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
644 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
645 for (i = 0; i <= cpsw->data.slaves; i++) {
646 cpsw_ale_control_set(ale, i,
647 ALE_PORT_NOLEARN, 0);
648 cpsw_ale_control_set(ale, i,
649 ALE_PORT_NO_SA_UPDATE, 0);
651 dev_dbg(&ndev->dev, "promiscuity disabled\n");
656 struct addr_sync_ctx {
657 struct net_device *ndev;
658 const u8 *addr; /* address to be synched */
659 int consumed; /* number of address instances */
660 int flush; /* flush flag */
664 * cpsw_set_mc - adds multicast entry to the table if it's not added or deletes
665 * if it's not deleted
666 * @ndev: device to sync
667 * @addr: address to be added or deleted
668 * @vid: vlan id, if vid < 0 set/unset address for real device
669 * @add: add address if the flag is set or remove otherwise
671 static int cpsw_set_mc(struct net_device *ndev, const u8 *addr,
674 struct cpsw_priv *priv = netdev_priv(ndev);
675 struct cpsw_common *cpsw = priv->cpsw;
676 int mask, flags, ret;
679 if (cpsw->data.dual_emac)
680 vid = cpsw->slaves[priv->emac_port].port_vlan;
685 mask = cpsw->data.dual_emac ? ALE_PORT_HOST : ALE_ALL_PORTS;
686 flags = vid ? ALE_VLAN : 0;
689 ret = cpsw_ale_add_mcast(cpsw->ale, addr, mask, flags, vid, 0);
691 ret = cpsw_ale_del_mcast(cpsw->ale, addr, 0, flags, vid);
696 static int cpsw_update_vlan_mc(struct net_device *vdev, int vid, void *ctx)
698 struct addr_sync_ctx *sync_ctx = ctx;
699 struct netdev_hw_addr *ha;
700 int found = 0, ret = 0;
702 if (!vdev || !(vdev->flags & IFF_UP))
705 /* vlan address is relevant if its sync_cnt != 0 */
706 netdev_for_each_mc_addr(ha, vdev) {
707 if (ether_addr_equal(ha->addr, sync_ctx->addr)) {
708 found = ha->sync_cnt;
714 sync_ctx->consumed++;
716 if (sync_ctx->flush) {
718 cpsw_set_mc(sync_ctx->ndev, sync_ctx->addr, vid, 0);
723 ret = cpsw_set_mc(sync_ctx->ndev, sync_ctx->addr, vid, 1);
728 static int cpsw_add_mc_addr(struct net_device *ndev, const u8 *addr, int num)
730 struct addr_sync_ctx sync_ctx;
733 sync_ctx.consumed = 0;
734 sync_ctx.addr = addr;
735 sync_ctx.ndev = ndev;
738 ret = vlan_for_each(ndev, cpsw_update_vlan_mc, &sync_ctx);
739 if (sync_ctx.consumed < num && !ret)
740 ret = cpsw_set_mc(ndev, addr, -1, 1);
745 static int cpsw_del_mc_addr(struct net_device *ndev, const u8 *addr, int num)
747 struct addr_sync_ctx sync_ctx;
749 sync_ctx.consumed = 0;
750 sync_ctx.addr = addr;
751 sync_ctx.ndev = ndev;
754 vlan_for_each(ndev, cpsw_update_vlan_mc, &sync_ctx);
755 if (sync_ctx.consumed == num)
756 cpsw_set_mc(ndev, addr, -1, 0);
761 static int cpsw_purge_vlan_mc(struct net_device *vdev, int vid, void *ctx)
763 struct addr_sync_ctx *sync_ctx = ctx;
764 struct netdev_hw_addr *ha;
767 if (!vdev || !(vdev->flags & IFF_UP))
770 /* vlan address is relevant if its sync_cnt != 0 */
771 netdev_for_each_mc_addr(ha, vdev) {
772 if (ether_addr_equal(ha->addr, sync_ctx->addr)) {
773 found = ha->sync_cnt;
781 sync_ctx->consumed++;
782 cpsw_set_mc(sync_ctx->ndev, sync_ctx->addr, vid, 0);
786 static int cpsw_purge_all_mc(struct net_device *ndev, const u8 *addr, int num)
788 struct addr_sync_ctx sync_ctx;
790 sync_ctx.addr = addr;
791 sync_ctx.ndev = ndev;
792 sync_ctx.consumed = 0;
794 vlan_for_each(ndev, cpsw_purge_vlan_mc, &sync_ctx);
795 if (sync_ctx.consumed < num)
796 cpsw_set_mc(ndev, addr, -1, 0);
801 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
803 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
805 if (ndev->flags & IFF_PROMISC) {
806 /* Enable promiscuous mode */
807 cpsw_set_promiscious(ndev, true);
808 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
811 /* Disable promiscuous mode */
812 cpsw_set_promiscious(ndev, false);
815 /* Restore allmulti on vlans if necessary */
816 cpsw_ale_set_allmulti(cpsw->ale, ndev->flags & IFF_ALLMULTI);
818 /* add/remove mcast address either for real netdev or for vlan */
819 __hw_addr_ref_sync_dev(&ndev->mc, ndev, cpsw_add_mc_addr,
823 static void cpsw_intr_enable(struct cpsw_common *cpsw)
825 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
826 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
828 cpdma_ctlr_int_ctrl(cpsw->dma, true);
832 static void cpsw_intr_disable(struct cpsw_common *cpsw)
834 writel_relaxed(0, &cpsw->wr_regs->tx_en);
835 writel_relaxed(0, &cpsw->wr_regs->rx_en);
837 cpdma_ctlr_int_ctrl(cpsw->dma, false);
841 static void cpsw_tx_handler(void *token, int len, int status)
843 struct netdev_queue *txq;
844 struct sk_buff *skb = token;
845 struct net_device *ndev = skb->dev;
846 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
848 /* Check whether the queue is stopped due to stalled tx dma, if the
849 * queue is stopped then start the queue as we have free desc for tx
851 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
852 if (unlikely(netif_tx_queue_stopped(txq)))
853 netif_tx_wake_queue(txq);
855 cpts_tx_timestamp(cpsw->cpts, skb);
856 ndev->stats.tx_packets++;
857 ndev->stats.tx_bytes += len;
858 dev_kfree_skb_any(skb);
861 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
863 struct cpsw_priv *priv = netdev_priv(skb->dev);
864 struct cpsw_common *cpsw = priv->cpsw;
865 u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
866 u16 vtag, vid, prio, pkt_type;
868 /* Remove VLAN header encapsulation word */
869 skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
871 pkt_type = (rx_vlan_encap_hdr >>
872 CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
873 CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
874 /* Ignore unknown & Priority-tagged packets*/
875 if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
876 pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
879 vid = (rx_vlan_encap_hdr >>
880 CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
882 /* Ignore vid 0 and pass packet as is */
885 /* Ignore default vlans in dual mac mode */
886 if (cpsw->data.dual_emac &&
887 vid == cpsw->slaves[priv->emac_port].port_vlan)
890 prio = (rx_vlan_encap_hdr >>
891 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
892 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
894 vtag = (prio << VLAN_PRIO_SHIFT) | vid;
895 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
897 /* strip vlan tag for VLAN-tagged packet */
898 if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
899 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
900 skb_pull(skb, VLAN_HLEN);
904 static void cpsw_rx_handler(void *token, int len, int status)
906 struct cpdma_chan *ch;
907 struct sk_buff *skb = token;
908 struct sk_buff *new_skb;
909 struct net_device *ndev = skb->dev;
911 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
912 struct cpsw_priv *priv;
914 if (cpsw->data.dual_emac) {
915 port = CPDMA_RX_SOURCE_PORT(status);
917 ndev = cpsw->slaves[--port].ndev;
922 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
923 /* In dual emac mode check for all interfaces */
924 if (cpsw->data.dual_emac && cpsw->usage_count &&
926 /* The packet received is for the interface which
927 * is already down and the other interface is up
928 * and running, instead of freeing which results
929 * in reducing of the number of rx descriptor in
930 * DMA engine, requeue skb back to cpdma.
936 /* the interface is going down, skbs are purged */
937 dev_kfree_skb_any(skb);
941 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
943 skb_copy_queue_mapping(new_skb, skb);
945 if (status & CPDMA_RX_VLAN_ENCAP)
946 cpsw_rx_vlan_encap(skb);
947 priv = netdev_priv(ndev);
948 if (priv->rx_ts_enabled)
949 cpts_rx_timestamp(cpsw->cpts, skb);
950 skb->protocol = eth_type_trans(skb, ndev);
951 netif_receive_skb(skb);
952 ndev->stats.rx_bytes += len;
953 ndev->stats.rx_packets++;
954 kmemleak_not_leak(new_skb);
956 ndev->stats.rx_dropped++;
961 if (netif_dormant(ndev)) {
962 dev_kfree_skb_any(new_skb);
966 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
967 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
968 skb_tailroom(new_skb), 0);
969 if (WARN_ON(ret < 0))
970 dev_kfree_skb_any(new_skb);
973 static void cpsw_split_res(struct net_device *ndev)
975 struct cpsw_priv *priv = netdev_priv(ndev);
976 u32 consumed_rate = 0, bigest_rate = 0;
977 struct cpsw_common *cpsw = priv->cpsw;
978 struct cpsw_vector *txv = cpsw->txv;
979 int i, ch_weight, rlim_ch_num = 0;
980 int budget, bigest_rate_ch = 0;
981 u32 ch_rate, max_rate;
984 for (i = 0; i < cpsw->tx_ch_num; i++) {
985 ch_rate = cpdma_chan_get_rate(txv[i].ch);
990 consumed_rate += ch_rate;
993 if (cpsw->tx_ch_num == rlim_ch_num) {
994 max_rate = consumed_rate;
995 } else if (!rlim_ch_num) {
996 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
998 max_rate = consumed_rate;
1000 max_rate = cpsw->speed * 1000;
1002 /* if max_rate is less then expected due to reduced link speed,
1003 * split proportionally according next potential max speed
1005 if (max_rate < consumed_rate)
1008 if (max_rate < consumed_rate)
1011 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
1012 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
1013 (cpsw->tx_ch_num - rlim_ch_num);
1014 bigest_rate = (max_rate - consumed_rate) /
1015 (cpsw->tx_ch_num - rlim_ch_num);
1018 /* split tx weight/budget */
1019 budget = CPSW_POLL_WEIGHT;
1020 for (i = 0; i < cpsw->tx_ch_num; i++) {
1021 ch_rate = cpdma_chan_get_rate(txv[i].ch);
1023 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
1026 if (ch_rate > bigest_rate) {
1028 bigest_rate = ch_rate;
1031 ch_weight = (ch_rate * 100) / max_rate;
1034 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
1036 txv[i].budget = ch_budget;
1037 if (!bigest_rate_ch)
1039 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
1042 budget -= txv[i].budget;
1046 txv[bigest_rate_ch].budget += budget;
1048 /* split rx budget */
1049 budget = CPSW_POLL_WEIGHT;
1050 ch_budget = budget / cpsw->rx_ch_num;
1051 for (i = 0; i < cpsw->rx_ch_num; i++) {
1052 cpsw->rxv[i].budget = ch_budget;
1053 budget -= ch_budget;
1057 cpsw->rxv[0].budget += budget;
1060 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
1062 struct cpsw_common *cpsw = dev_id;
1064 writel(0, &cpsw->wr_regs->tx_en);
1065 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
1067 if (cpsw->quirk_irq) {
1068 disable_irq_nosync(cpsw->irqs_table[1]);
1069 cpsw->tx_irq_disabled = true;
1072 napi_schedule(&cpsw->napi_tx);
1076 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
1078 struct cpsw_common *cpsw = dev_id;
1080 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
1081 writel(0, &cpsw->wr_regs->rx_en);
1083 if (cpsw->quirk_irq) {
1084 disable_irq_nosync(cpsw->irqs_table[0]);
1085 cpsw->rx_irq_disabled = true;
1088 napi_schedule(&cpsw->napi_rx);
1092 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
1095 int num_tx, cur_budget, ch;
1096 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
1097 struct cpsw_vector *txv;
1099 /* process every unprocessed channel */
1100 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
1101 for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) {
1102 if (!(ch_map & 0x80))
1105 txv = &cpsw->txv[ch];
1106 if (unlikely(txv->budget > budget - num_tx))
1107 cur_budget = budget - num_tx;
1109 cur_budget = txv->budget;
1111 num_tx += cpdma_chan_process(txv->ch, cur_budget);
1112 if (num_tx >= budget)
1116 if (num_tx < budget) {
1117 napi_complete(napi_tx);
1118 writel(0xff, &cpsw->wr_regs->tx_en);
1124 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
1126 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
1129 num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
1130 if (num_tx < budget) {
1131 napi_complete(napi_tx);
1132 writel(0xff, &cpsw->wr_regs->tx_en);
1133 if (cpsw->tx_irq_disabled) {
1134 cpsw->tx_irq_disabled = false;
1135 enable_irq(cpsw->irqs_table[1]);
1142 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1145 int num_rx, cur_budget, ch;
1146 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1147 struct cpsw_vector *rxv;
1149 /* process every unprocessed channel */
1150 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1151 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1152 if (!(ch_map & 0x01))
1155 rxv = &cpsw->rxv[ch];
1156 if (unlikely(rxv->budget > budget - num_rx))
1157 cur_budget = budget - num_rx;
1159 cur_budget = rxv->budget;
1161 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1162 if (num_rx >= budget)
1166 if (num_rx < budget) {
1167 napi_complete_done(napi_rx, num_rx);
1168 writel(0xff, &cpsw->wr_regs->rx_en);
1174 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1176 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1179 num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1180 if (num_rx < budget) {
1181 napi_complete_done(napi_rx, num_rx);
1182 writel(0xff, &cpsw->wr_regs->rx_en);
1183 if (cpsw->rx_irq_disabled) {
1184 cpsw->rx_irq_disabled = false;
1185 enable_irq(cpsw->irqs_table[0]);
1192 static inline void soft_reset(const char *module, void __iomem *reg)
1194 unsigned long timeout = jiffies + HZ;
1196 writel_relaxed(1, reg);
1199 } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1201 WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1204 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1205 struct cpsw_priv *priv)
1207 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1208 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1211 static bool cpsw_shp_is_off(struct cpsw_priv *priv)
1213 struct cpsw_common *cpsw = priv->cpsw;
1214 struct cpsw_slave *slave;
1215 u32 shift, mask, val;
1217 val = readl_relaxed(&cpsw->regs->ptype);
1219 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1220 shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1227 static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on)
1229 struct cpsw_common *cpsw = priv->cpsw;
1230 struct cpsw_slave *slave;
1231 u32 shift, mask, val;
1233 val = readl_relaxed(&cpsw->regs->ptype);
1235 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1236 shift = CPSW_FIFO_SHAPE_EN_SHIFT + 3 * slave->slave_num;
1237 mask = (1 << --fifo) << shift;
1238 val = on ? val | mask : val & ~mask;
1240 writel_relaxed(val, &cpsw->regs->ptype);
1243 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1244 struct cpsw_priv *priv, bool *link)
1246 struct phy_device *phy = slave->phy;
1247 u32 mac_control = 0;
1249 struct cpsw_common *cpsw = priv->cpsw;
1254 slave_port = cpsw_get_slave_port(slave->slave_num);
1257 mac_control = cpsw->data.mac_control;
1259 /* enable forwarding */
1260 cpsw_ale_control_set(cpsw->ale, slave_port,
1261 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1263 if (phy->speed == 1000)
1264 mac_control |= BIT(7); /* GIGABITEN */
1266 mac_control |= BIT(0); /* FULLDUPLEXEN */
1268 /* set speed_in input in case RMII mode is used in 100Mbps */
1269 if (phy->speed == 100)
1270 mac_control |= BIT(15);
1271 /* in band mode only works in 10Mbps RGMII mode */
1272 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1273 mac_control |= BIT(18); /* In Band mode */
1276 mac_control |= BIT(3);
1279 mac_control |= BIT(4);
1283 if (priv->shp_cfg_speed &&
1284 priv->shp_cfg_speed != slave->phy->speed &&
1285 !cpsw_shp_is_off(priv))
1287 "Speed was changed, CBS shaper speeds are changed!");
1290 /* disable forwarding */
1291 cpsw_ale_control_set(cpsw->ale, slave_port,
1292 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1295 if (mac_control != slave->mac_control) {
1296 phy_print_status(phy);
1297 writel_relaxed(mac_control, &slave->sliver->mac_control);
1300 slave->mac_control = mac_control;
1303 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1307 for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1308 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1309 speed += cpsw->slaves[i].phy->speed;
1314 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1319 /* re-split resources only in case speed was changed */
1320 speed = cpsw_get_common_speed(cpsw);
1321 if (speed == cpsw->speed || !speed)
1324 cpsw->speed = speed;
1326 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1327 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1334 /* cases not dependent on speed */
1335 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1341 static void cpsw_adjust_link(struct net_device *ndev)
1343 struct cpsw_priv *priv = netdev_priv(ndev);
1344 struct cpsw_common *cpsw = priv->cpsw;
1347 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1350 if (cpsw_need_resplit(cpsw))
1351 cpsw_split_res(ndev);
1353 netif_carrier_on(ndev);
1354 if (netif_running(ndev))
1355 netif_tx_wake_all_queues(ndev);
1357 netif_carrier_off(ndev);
1358 netif_tx_stop_all_queues(ndev);
1362 static int cpsw_get_coalesce(struct net_device *ndev,
1363 struct ethtool_coalesce *coal)
1365 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1367 coal->rx_coalesce_usecs = cpsw->coal_intvl;
1371 static int cpsw_set_coalesce(struct net_device *ndev,
1372 struct ethtool_coalesce *coal)
1374 struct cpsw_priv *priv = netdev_priv(ndev);
1376 u32 num_interrupts = 0;
1380 struct cpsw_common *cpsw = priv->cpsw;
1382 coal_intvl = coal->rx_coalesce_usecs;
1384 int_ctrl = readl(&cpsw->wr_regs->int_control);
1385 prescale = cpsw->bus_freq_mhz * 4;
1387 if (!coal->rx_coalesce_usecs) {
1388 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1392 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1393 coal_intvl = CPSW_CMINTMIN_INTVL;
1395 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1396 /* Interrupt pacer works with 4us Pulse, we can
1397 * throttle further by dilating the 4us pulse.
1399 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1401 if (addnl_dvdr > 1) {
1402 prescale *= addnl_dvdr;
1403 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1404 coal_intvl = (CPSW_CMINTMAX_INTVL
1408 coal_intvl = CPSW_CMINTMAX_INTVL;
1412 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1413 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1414 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1416 int_ctrl |= CPSW_INTPACEEN;
1417 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1418 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1421 writel(int_ctrl, &cpsw->wr_regs->int_control);
1423 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1424 cpsw->coal_intvl = coal_intvl;
1429 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1431 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1435 return (CPSW_STATS_COMMON_LEN +
1436 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1443 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1449 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1450 for (i = 0; i < ch_stats_len; i++) {
1451 line = i % CPSW_STATS_CH_LEN;
1452 snprintf(*p, ETH_GSTRING_LEN,
1453 "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1454 (long)(i / CPSW_STATS_CH_LEN),
1455 cpsw_gstrings_ch_stats[line].stat_string);
1456 *p += ETH_GSTRING_LEN;
1460 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1462 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1466 switch (stringset) {
1468 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1469 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1471 p += ETH_GSTRING_LEN;
1474 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1475 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1480 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1481 struct ethtool_stats *stats, u64 *data)
1484 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1485 struct cpdma_chan_stats ch_stats;
1488 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1489 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1490 data[l] = readl(cpsw->hw_stats +
1491 cpsw_gstrings_stats[l].stat_offset);
1493 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1494 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1495 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1496 p = (u8 *)&ch_stats +
1497 cpsw_gstrings_ch_stats[i].stat_offset;
1498 data[l] = *(u32 *)p;
1502 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1503 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1504 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1505 p = (u8 *)&ch_stats +
1506 cpsw_gstrings_ch_stats[i].stat_offset;
1507 data[l] = *(u32 *)p;
1512 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1513 struct sk_buff *skb,
1514 struct cpdma_chan *txch)
1516 struct cpsw_common *cpsw = priv->cpsw;
1518 skb_tx_timestamp(skb);
1519 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1520 priv->emac_port + cpsw->data.dual_emac);
1523 static inline void cpsw_add_dual_emac_def_ale_entries(
1524 struct cpsw_priv *priv, struct cpsw_slave *slave,
1527 struct cpsw_common *cpsw = priv->cpsw;
1528 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1530 if (cpsw->version == CPSW_VERSION_1)
1531 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1533 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1534 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1535 port_mask, port_mask, 0);
1536 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1537 ALE_PORT_HOST, ALE_VLAN, slave->port_vlan, 0);
1538 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1539 HOST_PORT_NUM, ALE_VLAN |
1540 ALE_SECURE, slave->port_vlan);
1541 cpsw_ale_control_set(cpsw->ale, slave_port,
1542 ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1545 static void soft_reset_slave(struct cpsw_slave *slave)
1549 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1550 soft_reset(name, &slave->sliver->soft_reset);
1553 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1556 struct phy_device *phy;
1557 struct cpsw_common *cpsw = priv->cpsw;
1559 soft_reset_slave(slave);
1561 /* setup priority mapping */
1562 writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1564 switch (cpsw->version) {
1565 case CPSW_VERSION_1:
1566 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1567 /* Increase RX FIFO size to 5 for supporting fullduplex
1571 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1572 CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1574 case CPSW_VERSION_2:
1575 case CPSW_VERSION_3:
1576 case CPSW_VERSION_4:
1577 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1578 /* Increase RX FIFO size to 5 for supporting fullduplex
1582 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1583 CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1587 /* setup max packet size, and mac address */
1588 writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1589 cpsw_set_slave_mac(slave, priv);
1591 slave->mac_control = 0; /* no link yet */
1593 slave_port = cpsw_get_slave_port(slave->slave_num);
1595 if (cpsw->data.dual_emac)
1596 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1598 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1599 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1601 if (slave->data->phy_node) {
1602 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1603 &cpsw_adjust_link, 0, slave->data->phy_if);
1605 dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1606 slave->data->phy_node,
1611 phy = phy_connect(priv->ndev, slave->data->phy_id,
1612 &cpsw_adjust_link, slave->data->phy_if);
1615 "phy \"%s\" not found on slave %d, err %ld\n",
1616 slave->data->phy_id, slave->slave_num,
1624 phy_attached_info(slave->phy);
1626 phy_start(slave->phy);
1628 /* Configure GMII_SEL register */
1629 if (!IS_ERR(slave->data->ifphy))
1630 phy_set_mode_ext(slave->data->ifphy, PHY_MODE_ETHERNET,
1631 slave->data->phy_if);
1633 cpsw_phy_sel(cpsw->dev, slave->phy->interface,
1637 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1639 struct cpsw_common *cpsw = priv->cpsw;
1640 const int vlan = cpsw->data.default_vlan;
1643 int unreg_mcast_mask;
1645 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1648 writel(vlan, &cpsw->host_port_regs->port_vlan);
1650 for (i = 0; i < cpsw->data.slaves; i++)
1651 slave_write(cpsw->slaves + i, vlan, reg);
1653 if (priv->ndev->flags & IFF_ALLMULTI)
1654 unreg_mcast_mask = ALE_ALL_PORTS;
1656 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1658 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1659 ALE_ALL_PORTS, ALE_ALL_PORTS,
1663 static void cpsw_init_host_port(struct cpsw_priv *priv)
1667 struct cpsw_common *cpsw = priv->cpsw;
1669 /* soft reset the controller and initialize ale */
1670 soft_reset("cpsw", &cpsw->regs->soft_reset);
1671 cpsw_ale_start(cpsw->ale);
1673 /* switch to vlan unaware mode */
1674 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1675 CPSW_ALE_VLAN_AWARE);
1676 control_reg = readl(&cpsw->regs->control);
1677 control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1678 writel(control_reg, &cpsw->regs->control);
1679 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1680 CPSW_FIFO_NORMAL_MODE;
1681 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1683 /* setup host port priority mapping */
1684 writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1685 &cpsw->host_port_regs->cpdma_tx_pri_map);
1686 writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1688 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1689 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1691 if (!cpsw->data.dual_emac) {
1692 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1694 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1695 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1699 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1701 struct cpsw_common *cpsw = priv->cpsw;
1702 struct sk_buff *skb;
1706 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1707 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1708 for (i = 0; i < ch_buf_num; i++) {
1709 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1710 cpsw->rx_packet_max,
1713 cpsw_err(priv, ifup, "cannot allocate skb\n");
1717 skb_set_queue_mapping(skb, ch);
1718 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1719 skb->data, skb_tailroom(skb),
1722 cpsw_err(priv, ifup,
1723 "cannot submit skb to channel %d rx, error %d\n",
1728 kmemleak_not_leak(skb);
1731 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1738 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1742 slave_port = cpsw_get_slave_port(slave->slave_num);
1746 phy_stop(slave->phy);
1747 phy_disconnect(slave->phy);
1749 cpsw_ale_control_set(cpsw->ale, slave_port,
1750 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1751 soft_reset_slave(slave);
1754 static int cpsw_tc_to_fifo(int tc, int num_tc)
1756 if (tc == num_tc - 1)
1759 return CPSW_FIFO_SHAPERS_NUM - tc;
1762 static int cpsw_set_fifo_bw(struct cpsw_priv *priv, int fifo, int bw)
1764 struct cpsw_common *cpsw = priv->cpsw;
1765 u32 val = 0, send_pct, shift;
1766 struct cpsw_slave *slave;
1769 if (bw > priv->shp_cfg_speed * 1000)
1772 /* shaping has to stay enabled for highest fifos linearly
1773 * and fifo bw no more then interface can allow
1775 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1776 send_pct = slave_read(slave, SEND_PERCENT);
1777 for (i = CPSW_FIFO_SHAPERS_NUM; i > 0; i--) {
1779 if (i >= fifo || !priv->fifo_bw[i])
1782 dev_warn(priv->dev, "Prev FIFO%d is shaped", i);
1786 if (!priv->fifo_bw[i] && i > fifo) {
1787 dev_err(priv->dev, "Upper FIFO%d is not shaped", i);
1791 shift = (i - 1) * 8;
1793 send_pct &= ~(CPSW_PCT_MASK << shift);
1794 val = DIV_ROUND_UP(bw, priv->shp_cfg_speed * 10);
1798 send_pct |= val << shift;
1803 if (priv->fifo_bw[i])
1804 pct += (send_pct >> shift) & CPSW_PCT_MASK;
1810 slave_write(slave, send_pct, SEND_PERCENT);
1811 priv->fifo_bw[fifo] = bw;
1813 dev_warn(priv->dev, "set FIFO%d bw = %d\n", fifo,
1814 DIV_ROUND_CLOSEST(val * priv->shp_cfg_speed, 100));
1818 dev_err(priv->dev, "Bandwidth doesn't fit in tc configuration");
1822 static int cpsw_set_fifo_rlimit(struct cpsw_priv *priv, int fifo, int bw)
1824 struct cpsw_common *cpsw = priv->cpsw;
1825 struct cpsw_slave *slave;
1826 u32 tx_in_ctl_rg, val;
1829 ret = cpsw_set_fifo_bw(priv, fifo, bw);
1833 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1834 tx_in_ctl_rg = cpsw->version == CPSW_VERSION_1 ?
1835 CPSW1_TX_IN_CTL : CPSW2_TX_IN_CTL;
1838 cpsw_fifo_shp_on(priv, fifo, bw);
1840 val = slave_read(slave, tx_in_ctl_rg);
1841 if (cpsw_shp_is_off(priv)) {
1842 /* disable FIFOs rate limited queues */
1843 val &= ~(0xf << CPSW_FIFO_RATE_EN_SHIFT);
1845 /* set type of FIFO queues to normal priority mode */
1846 val &= ~(3 << CPSW_FIFO_QUEUE_TYPE_SHIFT);
1848 /* set type of FIFO queues to be rate limited */
1850 val |= 2 << CPSW_FIFO_QUEUE_TYPE_SHIFT;
1852 priv->shp_cfg_speed = 0;
1855 /* toggle a FIFO rate limited queue */
1857 val |= BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1859 val &= ~BIT(fifo + CPSW_FIFO_RATE_EN_SHIFT);
1860 slave_write(slave, val, tx_in_ctl_rg);
1862 /* FIFO transmit shape enable */
1863 cpsw_fifo_shp_on(priv, fifo, bw);
1870 * shaping for class A should be set first
1872 static int cpsw_set_cbs(struct net_device *ndev,
1873 struct tc_cbs_qopt_offload *qopt)
1875 struct cpsw_priv *priv = netdev_priv(ndev);
1876 struct cpsw_common *cpsw = priv->cpsw;
1877 struct cpsw_slave *slave;
1882 tc = netdev_txq_to_tc(priv->ndev, qopt->queue);
1884 /* enable channels in backward order, as highest FIFOs must be rate
1885 * limited first and for compliance with CPDMA rate limited channels
1886 * that also used in bacward order. FIFO0 cannot be rate limited.
1888 fifo = cpsw_tc_to_fifo(tc, ndev->num_tc);
1890 dev_err(priv->dev, "Last tc%d can't be rate limited", tc);
1894 /* do nothing, it's disabled anyway */
1895 if (!qopt->enable && !priv->fifo_bw[fifo])
1898 /* shapers can be set if link speed is known */
1899 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1900 if (slave->phy && slave->phy->link) {
1901 if (priv->shp_cfg_speed &&
1902 priv->shp_cfg_speed != slave->phy->speed)
1903 prev_speed = priv->shp_cfg_speed;
1905 priv->shp_cfg_speed = slave->phy->speed;
1908 if (!priv->shp_cfg_speed) {
1909 dev_err(priv->dev, "Link speed is not known");
1913 ret = pm_runtime_get_sync(cpsw->dev);
1915 pm_runtime_put_noidle(cpsw->dev);
1919 bw = qopt->enable ? qopt->idleslope : 0;
1920 ret = cpsw_set_fifo_rlimit(priv, fifo, bw);
1922 priv->shp_cfg_speed = prev_speed;
1926 if (bw && prev_speed)
1928 "Speed was changed, CBS shaper speeds are changed!");
1930 pm_runtime_put_sync(cpsw->dev);
1934 static void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1938 for (fifo = CPSW_FIFO_SHAPERS_NUM; fifo > 0; fifo--) {
1939 bw = priv->fifo_bw[fifo];
1943 cpsw_set_fifo_rlimit(priv, fifo, bw);
1947 static void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv)
1949 struct cpsw_common *cpsw = priv->cpsw;
1950 u32 tx_prio_map = 0;
1954 if (!priv->mqprio_hw)
1957 for (i = 0; i < 8; i++) {
1958 tc = netdev_get_prio_tc_map(priv->ndev, i);
1959 fifo = CPSW_FIFO_SHAPERS_NUM - tc;
1960 tx_prio_map |= fifo << (4 * i);
1963 tx_prio_rg = cpsw->version == CPSW_VERSION_1 ?
1964 CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
1966 slave_write(slave, tx_prio_map, tx_prio_rg);
1969 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg)
1971 struct cpsw_priv *priv = arg;
1976 cpsw_ndo_vlan_rx_add_vid(priv->ndev, 0, vid);
1980 /* restore resources after port reset */
1981 static void cpsw_restore(struct cpsw_priv *priv)
1983 /* restore vlan configurations */
1984 vlan_for_each(priv->ndev, cpsw_restore_vlans, priv);
1986 /* restore MQPRIO offload */
1987 for_each_slave(priv, cpsw_mqprio_resume, priv);
1989 /* restore CBS offload */
1990 for_each_slave(priv, cpsw_cbs_resume, priv);
1993 static int cpsw_ndo_open(struct net_device *ndev)
1995 struct cpsw_priv *priv = netdev_priv(ndev);
1996 struct cpsw_common *cpsw = priv->cpsw;
2000 ret = pm_runtime_get_sync(cpsw->dev);
2002 pm_runtime_put_noidle(cpsw->dev);
2006 netif_carrier_off(ndev);
2008 /* Notify the stack of the actual queue counts. */
2009 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
2011 dev_err(priv->dev, "cannot set real number of tx queues\n");
2015 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
2017 dev_err(priv->dev, "cannot set real number of rx queues\n");
2021 reg = cpsw->version;
2023 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
2024 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
2025 CPSW_RTL_VERSION(reg));
2027 /* Initialize host and slave ports */
2028 if (!cpsw->usage_count)
2029 cpsw_init_host_port(priv);
2030 for_each_slave(priv, cpsw_slave_open, priv);
2032 /* Add default VLAN */
2033 if (!cpsw->data.dual_emac)
2034 cpsw_add_default_vlan(priv);
2036 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
2037 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
2039 /* initialize shared resources for every ndev */
2040 if (!cpsw->usage_count) {
2041 /* disable priority elevation */
2042 writel_relaxed(0, &cpsw->regs->ptype);
2044 /* enable statistics collection only on all ports */
2045 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
2047 /* Enable internal fifo flow control */
2048 writel(0x7, &cpsw->regs->flow_control);
2050 napi_enable(&cpsw->napi_rx);
2051 napi_enable(&cpsw->napi_tx);
2053 if (cpsw->tx_irq_disabled) {
2054 cpsw->tx_irq_disabled = false;
2055 enable_irq(cpsw->irqs_table[1]);
2058 if (cpsw->rx_irq_disabled) {
2059 cpsw->rx_irq_disabled = false;
2060 enable_irq(cpsw->irqs_table[0]);
2063 ret = cpsw_fill_rx_channels(priv);
2067 if (cpts_register(cpsw->cpts))
2068 dev_err(priv->dev, "error registering cpts device\n");
2074 /* Enable Interrupt pacing if configured */
2075 if (cpsw->coal_intvl != 0) {
2076 struct ethtool_coalesce coal;
2078 coal.rx_coalesce_usecs = cpsw->coal_intvl;
2079 cpsw_set_coalesce(ndev, &coal);
2082 cpdma_ctlr_start(cpsw->dma);
2083 cpsw_intr_enable(cpsw);
2084 cpsw->usage_count++;
2089 cpdma_ctlr_stop(cpsw->dma);
2090 for_each_slave(priv, cpsw_slave_stop, cpsw);
2091 pm_runtime_put_sync(cpsw->dev);
2092 netif_carrier_off(priv->ndev);
2096 static int cpsw_ndo_stop(struct net_device *ndev)
2098 struct cpsw_priv *priv = netdev_priv(ndev);
2099 struct cpsw_common *cpsw = priv->cpsw;
2101 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
2102 __hw_addr_ref_unsync_dev(&ndev->mc, ndev, cpsw_purge_all_mc);
2103 netif_tx_stop_all_queues(priv->ndev);
2104 netif_carrier_off(priv->ndev);
2106 if (cpsw->usage_count <= 1) {
2107 napi_disable(&cpsw->napi_rx);
2108 napi_disable(&cpsw->napi_tx);
2109 cpts_unregister(cpsw->cpts);
2110 cpsw_intr_disable(cpsw);
2111 cpdma_ctlr_stop(cpsw->dma);
2112 cpsw_ale_stop(cpsw->ale);
2114 for_each_slave(priv, cpsw_slave_stop, cpsw);
2116 if (cpsw_need_resplit(cpsw))
2117 cpsw_split_res(ndev);
2119 cpsw->usage_count--;
2120 pm_runtime_put_sync(cpsw->dev);
2124 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
2125 struct net_device *ndev)
2127 struct cpsw_priv *priv = netdev_priv(ndev);
2128 struct cpsw_common *cpsw = priv->cpsw;
2129 struct cpts *cpts = cpsw->cpts;
2130 struct netdev_queue *txq;
2131 struct cpdma_chan *txch;
2134 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
2135 cpsw_err(priv, tx_err, "packet pad failed\n");
2136 ndev->stats.tx_dropped++;
2137 return NET_XMIT_DROP;
2140 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2141 priv->tx_ts_enabled && cpts_can_timestamp(cpts, skb))
2142 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2144 q_idx = skb_get_queue_mapping(skb);
2145 if (q_idx >= cpsw->tx_ch_num)
2146 q_idx = q_idx % cpsw->tx_ch_num;
2148 txch = cpsw->txv[q_idx].ch;
2149 txq = netdev_get_tx_queue(ndev, q_idx);
2150 ret = cpsw_tx_packet_submit(priv, skb, txch);
2151 if (unlikely(ret != 0)) {
2152 cpsw_err(priv, tx_err, "desc submit failed\n");
2156 /* If there is no more tx desc left free then we need to
2157 * tell the kernel to stop sending us tx frames.
2159 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
2160 netif_tx_stop_queue(txq);
2162 /* Barrier, so that stop_queue visible to other cpus */
2163 smp_mb__after_atomic();
2165 if (cpdma_check_free_tx_desc(txch))
2166 netif_tx_wake_queue(txq);
2169 return NETDEV_TX_OK;
2171 ndev->stats.tx_dropped++;
2172 netif_tx_stop_queue(txq);
2174 /* Barrier, so that stop_queue visible to other cpus */
2175 smp_mb__after_atomic();
2177 if (cpdma_check_free_tx_desc(txch))
2178 netif_tx_wake_queue(txq);
2180 return NETDEV_TX_BUSY;
2183 #if IS_ENABLED(CONFIG_TI_CPTS)
2185 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
2187 struct cpsw_common *cpsw = priv->cpsw;
2188 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2191 if (!priv->tx_ts_enabled && !priv->rx_ts_enabled) {
2192 slave_write(slave, 0, CPSW1_TS_CTL);
2196 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
2197 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
2199 if (priv->tx_ts_enabled)
2200 ts_en |= CPSW_V1_TS_TX_EN;
2202 if (priv->rx_ts_enabled)
2203 ts_en |= CPSW_V1_TS_RX_EN;
2205 slave_write(slave, ts_en, CPSW1_TS_CTL);
2206 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
2209 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
2211 struct cpsw_slave *slave;
2212 struct cpsw_common *cpsw = priv->cpsw;
2215 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2217 ctrl = slave_read(slave, CPSW2_CONTROL);
2218 switch (cpsw->version) {
2219 case CPSW_VERSION_2:
2220 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2222 if (priv->tx_ts_enabled)
2223 ctrl |= CTRL_V2_TX_TS_BITS;
2225 if (priv->rx_ts_enabled)
2226 ctrl |= CTRL_V2_RX_TS_BITS;
2228 case CPSW_VERSION_3:
2230 ctrl &= ~CTRL_V3_ALL_TS_MASK;
2232 if (priv->tx_ts_enabled)
2233 ctrl |= CTRL_V3_TX_TS_BITS;
2235 if (priv->rx_ts_enabled)
2236 ctrl |= CTRL_V3_RX_TS_BITS;
2240 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
2242 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
2243 slave_write(slave, ctrl, CPSW2_CONTROL);
2244 writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
2245 writel_relaxed(ETH_P_8021Q, &cpsw->regs->vlan_ltype);
2248 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2250 struct cpsw_priv *priv = netdev_priv(dev);
2251 struct hwtstamp_config cfg;
2252 struct cpsw_common *cpsw = priv->cpsw;
2254 if (cpsw->version != CPSW_VERSION_1 &&
2255 cpsw->version != CPSW_VERSION_2 &&
2256 cpsw->version != CPSW_VERSION_3)
2259 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
2262 /* reserved for future extensions */
2266 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2269 switch (cfg.rx_filter) {
2270 case HWTSTAMP_FILTER_NONE:
2271 priv->rx_ts_enabled = 0;
2273 case HWTSTAMP_FILTER_ALL:
2274 case HWTSTAMP_FILTER_NTP_ALL:
2276 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2277 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2278 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2279 priv->rx_ts_enabled = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2280 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
2282 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2283 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2284 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2285 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2286 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2287 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2288 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2289 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2290 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2291 priv->rx_ts_enabled = HWTSTAMP_FILTER_PTP_V2_EVENT;
2292 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2298 priv->tx_ts_enabled = cfg.tx_type == HWTSTAMP_TX_ON;
2300 switch (cpsw->version) {
2301 case CPSW_VERSION_1:
2302 cpsw_hwtstamp_v1(priv);
2304 case CPSW_VERSION_2:
2305 case CPSW_VERSION_3:
2306 cpsw_hwtstamp_v2(priv);
2312 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2315 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2317 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
2318 struct cpsw_priv *priv = netdev_priv(dev);
2319 struct hwtstamp_config cfg;
2321 if (cpsw->version != CPSW_VERSION_1 &&
2322 cpsw->version != CPSW_VERSION_2 &&
2323 cpsw->version != CPSW_VERSION_3)
2327 cfg.tx_type = priv->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2328 cfg.rx_filter = priv->rx_ts_enabled;
2330 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
2333 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2338 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2342 #endif /*CONFIG_TI_CPTS*/
2344 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2346 struct cpsw_priv *priv = netdev_priv(dev);
2347 struct cpsw_common *cpsw = priv->cpsw;
2348 int slave_no = cpsw_slave_index(cpsw, priv);
2350 if (!netif_running(dev))
2355 return cpsw_hwtstamp_set(dev, req);
2357 return cpsw_hwtstamp_get(dev, req);
2360 if (!cpsw->slaves[slave_no].phy)
2362 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2365 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
2367 struct cpsw_priv *priv = netdev_priv(ndev);
2368 struct cpsw_common *cpsw = priv->cpsw;
2371 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
2372 ndev->stats.tx_errors++;
2373 cpsw_intr_disable(cpsw);
2374 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
2375 cpdma_chan_stop(cpsw->txv[ch].ch);
2376 cpdma_chan_start(cpsw->txv[ch].ch);
2379 cpsw_intr_enable(cpsw);
2380 netif_trans_update(ndev);
2381 netif_tx_wake_all_queues(ndev);
2384 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
2386 struct cpsw_priv *priv = netdev_priv(ndev);
2387 struct sockaddr *addr = (struct sockaddr *)p;
2388 struct cpsw_common *cpsw = priv->cpsw;
2393 if (!is_valid_ether_addr(addr->sa_data))
2394 return -EADDRNOTAVAIL;
2396 ret = pm_runtime_get_sync(cpsw->dev);
2398 pm_runtime_put_noidle(cpsw->dev);
2402 if (cpsw->data.dual_emac) {
2403 vid = cpsw->slaves[priv->emac_port].port_vlan;
2407 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
2409 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
2412 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
2413 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2414 for_each_slave(priv, cpsw_set_slave_mac, priv);
2416 pm_runtime_put(cpsw->dev);
2421 #ifdef CONFIG_NET_POLL_CONTROLLER
2422 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2424 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2426 cpsw_intr_disable(cpsw);
2427 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2428 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2429 cpsw_intr_enable(cpsw);
2433 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2437 int unreg_mcast_mask = 0;
2440 struct cpsw_common *cpsw = priv->cpsw;
2442 if (cpsw->data.dual_emac) {
2443 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2445 mcast_mask = ALE_PORT_HOST;
2446 if (priv->ndev->flags & IFF_ALLMULTI)
2447 unreg_mcast_mask = mcast_mask;
2449 port_mask = ALE_ALL_PORTS;
2450 mcast_mask = port_mask;
2452 if (priv->ndev->flags & IFF_ALLMULTI)
2453 unreg_mcast_mask = ALE_ALL_PORTS;
2455 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2458 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2463 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2464 HOST_PORT_NUM, ALE_VLAN, vid);
2468 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2469 mcast_mask, ALE_VLAN, vid, 0);
2471 goto clean_vlan_ucast;
2475 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2476 HOST_PORT_NUM, ALE_VLAN, vid);
2478 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2482 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2483 __be16 proto, u16 vid)
2485 struct cpsw_priv *priv = netdev_priv(ndev);
2486 struct cpsw_common *cpsw = priv->cpsw;
2489 if (vid == cpsw->data.default_vlan)
2492 ret = pm_runtime_get_sync(cpsw->dev);
2494 pm_runtime_put_noidle(cpsw->dev);
2498 if (cpsw->data.dual_emac) {
2499 /* In dual EMAC, reserved VLAN id should not be used for
2500 * creating VLAN interfaces as this can break the dual
2501 * EMAC port separation
2505 for (i = 0; i < cpsw->data.slaves; i++) {
2506 if (vid == cpsw->slaves[i].port_vlan) {
2513 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2514 ret = cpsw_add_vlan_ale_entry(priv, vid);
2516 pm_runtime_put(cpsw->dev);
2520 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2521 __be16 proto, u16 vid)
2523 struct cpsw_priv *priv = netdev_priv(ndev);
2524 struct cpsw_common *cpsw = priv->cpsw;
2527 if (vid == cpsw->data.default_vlan)
2530 ret = pm_runtime_get_sync(cpsw->dev);
2532 pm_runtime_put_noidle(cpsw->dev);
2536 if (cpsw->data.dual_emac) {
2539 for (i = 0; i < cpsw->data.slaves; i++) {
2540 if (vid == cpsw->slaves[i].port_vlan)
2545 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2546 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2547 ret |= cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2548 HOST_PORT_NUM, ALE_VLAN, vid);
2549 ret |= cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2551 ret |= cpsw_ale_flush_multicast(cpsw->ale, 0, vid);
2553 pm_runtime_put(cpsw->dev);
2557 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2559 struct cpsw_priv *priv = netdev_priv(ndev);
2560 struct cpsw_common *cpsw = priv->cpsw;
2561 struct cpsw_slave *slave;
2566 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2567 if (ch_rate == rate)
2570 ch_rate = rate * 1000;
2571 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2572 if ((ch_rate < min_rate && ch_rate)) {
2573 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2578 if (rate > cpsw->speed) {
2579 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2583 ret = pm_runtime_get_sync(cpsw->dev);
2585 pm_runtime_put_noidle(cpsw->dev);
2589 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2590 pm_runtime_put(cpsw->dev);
2595 /* update rates for slaves tx queues */
2596 for (i = 0; i < cpsw->data.slaves; i++) {
2597 slave = &cpsw->slaves[i];
2601 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2604 cpsw_split_res(ndev);
2608 static int cpsw_set_mqprio(struct net_device *ndev, void *type_data)
2610 struct tc_mqprio_qopt_offload *mqprio = type_data;
2611 struct cpsw_priv *priv = netdev_priv(ndev);
2612 struct cpsw_common *cpsw = priv->cpsw;
2613 int fifo, num_tc, count, offset;
2614 struct cpsw_slave *slave;
2615 u32 tx_prio_map = 0;
2618 num_tc = mqprio->qopt.num_tc;
2619 if (num_tc > CPSW_TC_NUM)
2622 if (mqprio->mode != TC_MQPRIO_MODE_DCB)
2625 ret = pm_runtime_get_sync(cpsw->dev);
2627 pm_runtime_put_noidle(cpsw->dev);
2632 for (i = 0; i < 8; i++) {
2633 tc = mqprio->qopt.prio_tc_map[i];
2634 fifo = cpsw_tc_to_fifo(tc, num_tc);
2635 tx_prio_map |= fifo << (4 * i);
2638 netdev_set_num_tc(ndev, num_tc);
2639 for (i = 0; i < num_tc; i++) {
2640 count = mqprio->qopt.count[i];
2641 offset = mqprio->qopt.offset[i];
2642 netdev_set_tc_queue(ndev, i, count, offset);
2646 if (!mqprio->qopt.hw) {
2647 /* restore default configuration */
2648 netdev_reset_tc(ndev);
2649 tx_prio_map = TX_PRIORITY_MAPPING;
2652 priv->mqprio_hw = mqprio->qopt.hw;
2654 offset = cpsw->version == CPSW_VERSION_1 ?
2655 CPSW1_TX_PRI_MAP : CPSW2_TX_PRI_MAP;
2657 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
2658 slave_write(slave, tx_prio_map, offset);
2660 pm_runtime_put_sync(cpsw->dev);
2665 static int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
2669 case TC_SETUP_QDISC_CBS:
2670 return cpsw_set_cbs(ndev, type_data);
2672 case TC_SETUP_QDISC_MQPRIO:
2673 return cpsw_set_mqprio(ndev, type_data);
2680 static const struct net_device_ops cpsw_netdev_ops = {
2681 .ndo_open = cpsw_ndo_open,
2682 .ndo_stop = cpsw_ndo_stop,
2683 .ndo_start_xmit = cpsw_ndo_start_xmit,
2684 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2685 .ndo_do_ioctl = cpsw_ndo_ioctl,
2686 .ndo_validate_addr = eth_validate_addr,
2687 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
2688 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
2689 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
2690 #ifdef CONFIG_NET_POLL_CONTROLLER
2691 .ndo_poll_controller = cpsw_ndo_poll_controller,
2693 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2694 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
2695 .ndo_setup_tc = cpsw_ndo_setup_tc,
2698 static int cpsw_get_regs_len(struct net_device *ndev)
2700 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2702 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2705 static void cpsw_get_regs(struct net_device *ndev,
2706 struct ethtool_regs *regs, void *p)
2709 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2711 /* update CPSW IP version */
2712 regs->version = cpsw->version;
2714 cpsw_ale_dump(cpsw->ale, reg);
2717 static void cpsw_get_drvinfo(struct net_device *ndev,
2718 struct ethtool_drvinfo *info)
2720 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2721 struct platform_device *pdev = to_platform_device(cpsw->dev);
2723 strlcpy(info->driver, "cpsw", sizeof(info->driver));
2724 strlcpy(info->version, "1.0", sizeof(info->version));
2725 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2728 static u32 cpsw_get_msglevel(struct net_device *ndev)
2730 struct cpsw_priv *priv = netdev_priv(ndev);
2731 return priv->msg_enable;
2734 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2736 struct cpsw_priv *priv = netdev_priv(ndev);
2737 priv->msg_enable = value;
2740 #if IS_ENABLED(CONFIG_TI_CPTS)
2741 static int cpsw_get_ts_info(struct net_device *ndev,
2742 struct ethtool_ts_info *info)
2744 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2746 info->so_timestamping =
2747 SOF_TIMESTAMPING_TX_HARDWARE |
2748 SOF_TIMESTAMPING_TX_SOFTWARE |
2749 SOF_TIMESTAMPING_RX_HARDWARE |
2750 SOF_TIMESTAMPING_RX_SOFTWARE |
2751 SOF_TIMESTAMPING_SOFTWARE |
2752 SOF_TIMESTAMPING_RAW_HARDWARE;
2753 info->phc_index = cpsw->cpts->phc_index;
2755 (1 << HWTSTAMP_TX_OFF) |
2756 (1 << HWTSTAMP_TX_ON);
2758 (1 << HWTSTAMP_FILTER_NONE) |
2759 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2760 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2764 static int cpsw_get_ts_info(struct net_device *ndev,
2765 struct ethtool_ts_info *info)
2767 info->so_timestamping =
2768 SOF_TIMESTAMPING_TX_SOFTWARE |
2769 SOF_TIMESTAMPING_RX_SOFTWARE |
2770 SOF_TIMESTAMPING_SOFTWARE;
2771 info->phc_index = -1;
2773 info->rx_filters = 0;
2778 static int cpsw_get_link_ksettings(struct net_device *ndev,
2779 struct ethtool_link_ksettings *ecmd)
2781 struct cpsw_priv *priv = netdev_priv(ndev);
2782 struct cpsw_common *cpsw = priv->cpsw;
2783 int slave_no = cpsw_slave_index(cpsw, priv);
2785 if (!cpsw->slaves[slave_no].phy)
2788 phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2792 static int cpsw_set_link_ksettings(struct net_device *ndev,
2793 const struct ethtool_link_ksettings *ecmd)
2795 struct cpsw_priv *priv = netdev_priv(ndev);
2796 struct cpsw_common *cpsw = priv->cpsw;
2797 int slave_no = cpsw_slave_index(cpsw, priv);
2799 if (cpsw->slaves[slave_no].phy)
2800 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2806 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2808 struct cpsw_priv *priv = netdev_priv(ndev);
2809 struct cpsw_common *cpsw = priv->cpsw;
2810 int slave_no = cpsw_slave_index(cpsw, priv);
2815 if (cpsw->slaves[slave_no].phy)
2816 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2819 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2821 struct cpsw_priv *priv = netdev_priv(ndev);
2822 struct cpsw_common *cpsw = priv->cpsw;
2823 int slave_no = cpsw_slave_index(cpsw, priv);
2825 if (cpsw->slaves[slave_no].phy)
2826 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2831 static void cpsw_get_pauseparam(struct net_device *ndev,
2832 struct ethtool_pauseparam *pause)
2834 struct cpsw_priv *priv = netdev_priv(ndev);
2836 pause->autoneg = AUTONEG_DISABLE;
2837 pause->rx_pause = priv->rx_pause ? true : false;
2838 pause->tx_pause = priv->tx_pause ? true : false;
2841 static int cpsw_set_pauseparam(struct net_device *ndev,
2842 struct ethtool_pauseparam *pause)
2844 struct cpsw_priv *priv = netdev_priv(ndev);
2847 priv->rx_pause = pause->rx_pause ? true : false;
2848 priv->tx_pause = pause->tx_pause ? true : false;
2850 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2854 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2856 struct cpsw_priv *priv = netdev_priv(ndev);
2857 struct cpsw_common *cpsw = priv->cpsw;
2860 ret = pm_runtime_get_sync(cpsw->dev);
2862 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2863 pm_runtime_put_noidle(cpsw->dev);
2869 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2871 struct cpsw_priv *priv = netdev_priv(ndev);
2874 ret = pm_runtime_put(priv->cpsw->dev);
2876 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2879 static void cpsw_get_channels(struct net_device *ndev,
2880 struct ethtool_channels *ch)
2882 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2884 ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2885 ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2886 ch->max_combined = 0;
2888 ch->other_count = 0;
2889 ch->rx_count = cpsw->rx_ch_num;
2890 ch->tx_count = cpsw->tx_ch_num;
2891 ch->combined_count = 0;
2894 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2895 struct ethtool_channels *ch)
2897 if (cpsw->quirk_irq) {
2898 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2902 if (ch->combined_count)
2905 /* verify we have at least one channel in each direction */
2906 if (!ch->rx_count || !ch->tx_count)
2909 if (ch->rx_count > cpsw->data.channels ||
2910 ch->tx_count > cpsw->data.channels)
2916 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2918 struct cpsw_common *cpsw = priv->cpsw;
2919 void (*handler)(void *, int, int);
2920 struct netdev_queue *queue;
2921 struct cpsw_vector *vec;
2925 ch = &cpsw->rx_ch_num;
2927 handler = cpsw_rx_handler;
2929 ch = &cpsw->tx_ch_num;
2931 handler = cpsw_tx_handler;
2934 while (*ch < ch_num) {
2935 vch = rx ? *ch : 7 - *ch;
2936 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
2937 queue = netdev_get_tx_queue(priv->ndev, *ch);
2938 queue->tx_maxrate = 0;
2940 if (IS_ERR(vec[*ch].ch))
2941 return PTR_ERR(vec[*ch].ch);
2946 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2947 (rx ? "rx" : "tx"));
2951 while (*ch > ch_num) {
2954 ret = cpdma_chan_destroy(vec[*ch].ch);
2958 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2959 (rx ? "rx" : "tx"));
2965 static int cpsw_update_channels(struct cpsw_priv *priv,
2966 struct ethtool_channels *ch)
2970 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2974 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2981 static void cpsw_suspend_data_pass(struct net_device *ndev)
2983 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2984 struct cpsw_slave *slave;
2987 /* Disable NAPI scheduling */
2988 cpsw_intr_disable(cpsw);
2990 /* Stop all transmit queues for every network device.
2991 * Disable re-using rx descriptors with dormant_on.
2993 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2994 if (!(slave->ndev && netif_running(slave->ndev)))
2997 netif_tx_stop_all_queues(slave->ndev);
2998 netif_dormant_on(slave->ndev);
3001 /* Handle rest of tx packets and stop cpdma channels */
3002 cpdma_ctlr_stop(cpsw->dma);
3005 static int cpsw_resume_data_pass(struct net_device *ndev)
3007 struct cpsw_priv *priv = netdev_priv(ndev);
3008 struct cpsw_common *cpsw = priv->cpsw;
3009 struct cpsw_slave *slave;
3012 /* Allow rx packets handling */
3013 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
3014 if (slave->ndev && netif_running(slave->ndev))
3015 netif_dormant_off(slave->ndev);
3017 /* After this receive is started */
3018 if (cpsw->usage_count) {
3019 ret = cpsw_fill_rx_channels(priv);
3023 cpdma_ctlr_start(cpsw->dma);
3024 cpsw_intr_enable(cpsw);
3027 /* Resume transmit for every affected interface */
3028 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
3029 if (slave->ndev && netif_running(slave->ndev))
3030 netif_tx_start_all_queues(slave->ndev);
3035 static int cpsw_set_channels(struct net_device *ndev,
3036 struct ethtool_channels *chs)
3038 struct cpsw_priv *priv = netdev_priv(ndev);
3039 struct cpsw_common *cpsw = priv->cpsw;
3040 struct cpsw_slave *slave;
3043 ret = cpsw_check_ch_settings(cpsw, chs);
3047 cpsw_suspend_data_pass(ndev);
3048 ret = cpsw_update_channels(priv, chs);
3052 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
3053 if (!(slave->ndev && netif_running(slave->ndev)))
3056 /* Inform stack about new count of queues */
3057 ret = netif_set_real_num_tx_queues(slave->ndev,
3060 dev_err(priv->dev, "cannot set real number of tx queues\n");
3064 ret = netif_set_real_num_rx_queues(slave->ndev,
3067 dev_err(priv->dev, "cannot set real number of rx queues\n");
3072 if (cpsw->usage_count)
3073 cpsw_split_res(ndev);
3075 ret = cpsw_resume_data_pass(ndev);
3079 dev_err(priv->dev, "cannot update channels number, closing device\n");
3084 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3086 struct cpsw_priv *priv = netdev_priv(ndev);
3087 struct cpsw_common *cpsw = priv->cpsw;
3088 int slave_no = cpsw_slave_index(cpsw, priv);
3090 if (cpsw->slaves[slave_no].phy)
3091 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
3096 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3098 struct cpsw_priv *priv = netdev_priv(ndev);
3099 struct cpsw_common *cpsw = priv->cpsw;
3100 int slave_no = cpsw_slave_index(cpsw, priv);
3102 if (cpsw->slaves[slave_no].phy)
3103 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
3108 static int cpsw_nway_reset(struct net_device *ndev)
3110 struct cpsw_priv *priv = netdev_priv(ndev);
3111 struct cpsw_common *cpsw = priv->cpsw;
3112 int slave_no = cpsw_slave_index(cpsw, priv);
3114 if (cpsw->slaves[slave_no].phy)
3115 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
3120 static void cpsw_get_ringparam(struct net_device *ndev,
3121 struct ethtool_ringparam *ering)
3123 struct cpsw_priv *priv = netdev_priv(ndev);
3124 struct cpsw_common *cpsw = priv->cpsw;
3127 ering->tx_max_pending = 0;
3128 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
3129 ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
3130 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
3133 static int cpsw_set_ringparam(struct net_device *ndev,
3134 struct ethtool_ringparam *ering)
3136 struct cpsw_priv *priv = netdev_priv(ndev);
3137 struct cpsw_common *cpsw = priv->cpsw;
3140 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
3142 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
3143 ering->rx_pending < CPSW_MAX_QUEUES ||
3144 ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
3147 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
3150 cpsw_suspend_data_pass(ndev);
3152 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
3154 if (cpsw->usage_count)
3155 cpdma_chan_split_pool(cpsw->dma);
3157 ret = cpsw_resume_data_pass(ndev);
3161 dev_err(&ndev->dev, "cannot set ring params, closing device\n");
3166 static const struct ethtool_ops cpsw_ethtool_ops = {
3167 .get_drvinfo = cpsw_get_drvinfo,
3168 .get_msglevel = cpsw_get_msglevel,
3169 .set_msglevel = cpsw_set_msglevel,
3170 .get_link = ethtool_op_get_link,
3171 .get_ts_info = cpsw_get_ts_info,
3172 .get_coalesce = cpsw_get_coalesce,
3173 .set_coalesce = cpsw_set_coalesce,
3174 .get_sset_count = cpsw_get_sset_count,
3175 .get_strings = cpsw_get_strings,
3176 .get_ethtool_stats = cpsw_get_ethtool_stats,
3177 .get_pauseparam = cpsw_get_pauseparam,
3178 .set_pauseparam = cpsw_set_pauseparam,
3179 .get_wol = cpsw_get_wol,
3180 .set_wol = cpsw_set_wol,
3181 .get_regs_len = cpsw_get_regs_len,
3182 .get_regs = cpsw_get_regs,
3183 .begin = cpsw_ethtool_op_begin,
3184 .complete = cpsw_ethtool_op_complete,
3185 .get_channels = cpsw_get_channels,
3186 .set_channels = cpsw_set_channels,
3187 .get_link_ksettings = cpsw_get_link_ksettings,
3188 .set_link_ksettings = cpsw_set_link_ksettings,
3189 .get_eee = cpsw_get_eee,
3190 .set_eee = cpsw_set_eee,
3191 .nway_reset = cpsw_nway_reset,
3192 .get_ringparam = cpsw_get_ringparam,
3193 .set_ringparam = cpsw_set_ringparam,
3196 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
3197 u32 slave_reg_ofs, u32 sliver_reg_ofs)
3199 void __iomem *regs = cpsw->regs;
3200 int slave_num = slave->slave_num;
3201 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
3204 slave->regs = regs + slave_reg_ofs;
3205 slave->sliver = regs + sliver_reg_ofs;
3206 slave->port_vlan = data->dual_emac_res_vlan;
3209 static int cpsw_probe_dt(struct cpsw_platform_data *data,
3210 struct platform_device *pdev)
3212 struct device_node *node = pdev->dev.of_node;
3213 struct device_node *slave_node;
3220 if (of_property_read_u32(node, "slaves", &prop)) {
3221 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
3224 data->slaves = prop;
3226 if (of_property_read_u32(node, "active_slave", &prop)) {
3227 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
3230 data->active_slave = prop;
3232 data->slave_data = devm_kcalloc(&pdev->dev,
3234 sizeof(struct cpsw_slave_data),
3236 if (!data->slave_data)
3239 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
3240 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
3243 data->channels = prop;
3245 if (of_property_read_u32(node, "ale_entries", &prop)) {
3246 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
3249 data->ale_entries = prop;
3251 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
3252 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
3255 data->bd_ram_size = prop;
3257 if (of_property_read_u32(node, "mac_control", &prop)) {
3258 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
3261 data->mac_control = prop;
3263 if (of_property_read_bool(node, "dual_emac"))
3264 data->dual_emac = 1;
3267 * Populate all the child nodes here...
3269 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
3270 /* We do not want to force this, as in some cases may not have child */
3272 dev_warn(&pdev->dev, "Doesn't have any child node\n");
3274 for_each_available_child_of_node(node, slave_node) {
3275 struct cpsw_slave_data *slave_data = data->slave_data + i;
3276 const void *mac_addr = NULL;
3280 /* This is no slave child node, continue */
3281 if (!of_node_name_eq(slave_node, "slave"))
3284 slave_data->ifphy = devm_of_phy_get(&pdev->dev, slave_node,
3286 if (!IS_ENABLED(CONFIG_TI_CPSW_PHY_SEL) &&
3287 IS_ERR(slave_data->ifphy)) {
3288 ret = PTR_ERR(slave_data->ifphy);
3290 "%d: Error retrieving port phy: %d\n", i, ret);
3294 slave_data->phy_node = of_parse_phandle(slave_node,
3296 parp = of_get_property(slave_node, "phy_id", &lenp);
3297 if (slave_data->phy_node) {
3299 "slave[%d] using phy-handle=\"%pOF\"\n",
3300 i, slave_data->phy_node);
3301 } else if (of_phy_is_fixed_link(slave_node)) {
3302 /* In the case of a fixed PHY, the DT node associated
3303 * to the PHY is the Ethernet MAC DT node.
3305 ret = of_phy_register_fixed_link(slave_node);
3307 if (ret != -EPROBE_DEFER)
3308 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
3311 slave_data->phy_node = of_node_get(slave_node);
3314 struct device_node *mdio_node;
3315 struct platform_device *mdio;
3317 if (lenp != (sizeof(__be32) * 2)) {
3318 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
3321 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
3322 phyid = be32_to_cpup(parp+1);
3323 mdio = of_find_device_by_node(mdio_node);
3324 of_node_put(mdio_node);
3326 dev_err(&pdev->dev, "Missing mdio platform device\n");
3329 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
3330 PHY_ID_FMT, mdio->name, phyid);
3331 put_device(&mdio->dev);
3334 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
3338 slave_data->phy_if = of_get_phy_mode(slave_node);
3339 if (slave_data->phy_if < 0) {
3340 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
3342 return slave_data->phy_if;
3346 mac_addr = of_get_mac_address(slave_node);
3348 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
3350 ret = ti_cm_get_macid(&pdev->dev, i,
3351 slave_data->mac_addr);
3355 if (data->dual_emac) {
3356 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
3358 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
3359 slave_data->dual_emac_res_vlan = i+1;
3360 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
3361 slave_data->dual_emac_res_vlan, i);
3363 slave_data->dual_emac_res_vlan = prop;
3368 if (i == data->slaves)
3375 static void cpsw_remove_dt(struct platform_device *pdev)
3377 struct net_device *ndev = platform_get_drvdata(pdev);
3378 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3379 struct cpsw_platform_data *data = &cpsw->data;
3380 struct device_node *node = pdev->dev.of_node;
3381 struct device_node *slave_node;
3384 for_each_available_child_of_node(node, slave_node) {
3385 struct cpsw_slave_data *slave_data = &data->slave_data[i];
3387 if (!of_node_name_eq(slave_node, "slave"))
3390 if (of_phy_is_fixed_link(slave_node))
3391 of_phy_deregister_fixed_link(slave_node);
3393 of_node_put(slave_data->phy_node);
3396 if (i == data->slaves)
3400 of_platform_depopulate(&pdev->dev);
3403 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3405 struct cpsw_common *cpsw = priv->cpsw;
3406 struct cpsw_platform_data *data = &cpsw->data;
3407 struct net_device *ndev;
3408 struct cpsw_priv *priv_sl2;
3411 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3413 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
3417 priv_sl2 = netdev_priv(ndev);
3418 priv_sl2->cpsw = cpsw;
3419 priv_sl2->ndev = ndev;
3420 priv_sl2->dev = &ndev->dev;
3421 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3423 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
3424 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
3426 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
3427 priv_sl2->mac_addr);
3429 eth_random_addr(priv_sl2->mac_addr);
3430 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
3431 priv_sl2->mac_addr);
3433 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
3435 priv_sl2->emac_port = 1;
3436 cpsw->slaves[1].ndev = ndev;
3437 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3439 ndev->netdev_ops = &cpsw_netdev_ops;
3440 ndev->ethtool_ops = &cpsw_ethtool_ops;
3442 /* register the network device */
3443 SET_NETDEV_DEV(ndev, cpsw->dev);
3444 ret = register_netdev(ndev);
3446 dev_err(cpsw->dev, "cpsw: error registering net device\n");
3454 static const struct of_device_id cpsw_of_mtable[] = {
3455 { .compatible = "ti,cpsw"},
3456 { .compatible = "ti,am335x-cpsw"},
3457 { .compatible = "ti,am4372-cpsw"},
3458 { .compatible = "ti,dra7-cpsw"},
3461 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
3463 static const struct soc_device_attribute cpsw_soc_devices[] = {
3464 { .family = "AM33xx", .revision = "ES1.0"},
3468 static int cpsw_probe(struct platform_device *pdev)
3471 struct cpsw_platform_data *data;
3472 struct net_device *ndev;
3473 struct cpsw_priv *priv;
3474 struct cpdma_params dma_params;
3475 struct cpsw_ale_params ale_params;
3476 void __iomem *ss_regs;
3477 void __iomem *cpts_regs;
3478 struct resource *res, *ss_res;
3479 struct gpio_descs *mode;
3480 u32 slave_offset, sliver_offset, slave_size;
3481 const struct soc_device_attribute *soc;
3482 struct cpsw_common *cpsw;
3486 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
3490 cpsw->dev = &pdev->dev;
3492 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
3494 dev_err(&pdev->dev, "error allocating net_device\n");
3498 platform_set_drvdata(pdev, ndev);
3499 priv = netdev_priv(ndev);
3502 priv->dev = &ndev->dev;
3503 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3504 cpsw->rx_packet_max = max(rx_packet_max, 128);
3506 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
3508 ret = PTR_ERR(mode);
3509 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
3510 goto clean_ndev_ret;
3514 * This may be required here for child devices.
3516 pm_runtime_enable(&pdev->dev);
3518 /* Select default pin state */
3519 pinctrl_pm_select_default_state(&pdev->dev);
3521 /* Need to enable clocks with runtime PM api to access module
3524 ret = pm_runtime_get_sync(&pdev->dev);
3526 pm_runtime_put_noidle(&pdev->dev);
3527 goto clean_runtime_disable_ret;
3530 ret = cpsw_probe_dt(&cpsw->data, pdev);
3535 cpsw->rx_ch_num = 1;
3536 cpsw->tx_ch_num = 1;
3538 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3539 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3540 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
3542 eth_random_addr(priv->mac_addr);
3543 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
3546 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
3548 cpsw->slaves = devm_kcalloc(&pdev->dev,
3549 data->slaves, sizeof(struct cpsw_slave),
3551 if (!cpsw->slaves) {
3555 for (i = 0; i < data->slaves; i++)
3556 cpsw->slaves[i].slave_num = i;
3558 cpsw->slaves[0].ndev = ndev;
3559 priv->emac_port = 0;
3561 clk = devm_clk_get(&pdev->dev, "fck");
3563 dev_err(priv->dev, "fck is not found\n");
3567 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
3569 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3570 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
3571 if (IS_ERR(ss_regs)) {
3572 ret = PTR_ERR(ss_regs);
3575 cpsw->regs = ss_regs;
3577 cpsw->version = readl(&cpsw->regs->id_ver);
3579 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3580 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3581 if (IS_ERR(cpsw->wr_regs)) {
3582 ret = PTR_ERR(cpsw->wr_regs);
3586 memset(&dma_params, 0, sizeof(dma_params));
3587 memset(&ale_params, 0, sizeof(ale_params));
3589 switch (cpsw->version) {
3590 case CPSW_VERSION_1:
3591 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3592 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
3593 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
3594 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
3595 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
3596 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
3597 slave_offset = CPSW1_SLAVE_OFFSET;
3598 slave_size = CPSW1_SLAVE_SIZE;
3599 sliver_offset = CPSW1_SLIVER_OFFSET;
3600 dma_params.desc_mem_phys = 0;
3602 case CPSW_VERSION_2:
3603 case CPSW_VERSION_3:
3604 case CPSW_VERSION_4:
3605 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3606 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
3607 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
3608 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
3609 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
3610 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
3611 slave_offset = CPSW2_SLAVE_OFFSET;
3612 slave_size = CPSW2_SLAVE_SIZE;
3613 sliver_offset = CPSW2_SLIVER_OFFSET;
3614 dma_params.desc_mem_phys =
3615 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3618 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3622 for (i = 0; i < cpsw->data.slaves; i++) {
3623 struct cpsw_slave *slave = &cpsw->slaves[i];
3625 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3626 slave_offset += slave_size;
3627 sliver_offset += SLIVER_SIZE;
3630 dma_params.dev = &pdev->dev;
3631 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
3632 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
3633 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
3634 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
3635 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
3637 dma_params.num_chan = data->channels;
3638 dma_params.has_soft_reset = true;
3639 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
3640 dma_params.desc_mem_size = data->bd_ram_size;
3641 dma_params.desc_align = 16;
3642 dma_params.has_ext_regs = true;
3643 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
3644 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
3645 dma_params.descs_pool_size = descs_pool_size;
3647 cpsw->dma = cpdma_ctlr_create(&dma_params);
3649 dev_err(priv->dev, "error initializing dma\n");
3654 soc = soc_device_match(cpsw_soc_devices);
3656 cpsw->quirk_irq = 1;
3658 ch = cpsw->quirk_irq ? 0 : 7;
3659 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0);
3660 if (IS_ERR(cpsw->txv[0].ch)) {
3661 dev_err(priv->dev, "error initializing tx dma channel\n");
3662 ret = PTR_ERR(cpsw->txv[0].ch);
3666 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3667 if (IS_ERR(cpsw->rxv[0].ch)) {
3668 dev_err(priv->dev, "error initializing rx dma channel\n");
3669 ret = PTR_ERR(cpsw->rxv[0].ch);
3673 ale_params.dev = &pdev->dev;
3674 ale_params.ale_ageout = ale_ageout;
3675 ale_params.ale_entries = data->ale_entries;
3676 ale_params.ale_ports = CPSW_ALE_PORTS_NUM;
3678 cpsw->ale = cpsw_ale_create(&ale_params);
3680 dev_err(priv->dev, "error initializing ale engine\n");
3685 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3686 if (IS_ERR(cpsw->cpts)) {
3687 ret = PTR_ERR(cpsw->cpts);
3691 ndev->irq = platform_get_irq(pdev, 1);
3692 if (ndev->irq < 0) {
3693 dev_err(priv->dev, "error getting irq resource\n");
3698 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3700 ndev->netdev_ops = &cpsw_netdev_ops;
3701 ndev->ethtool_ops = &cpsw_ethtool_ops;
3702 netif_napi_add(ndev, &cpsw->napi_rx,
3703 cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll,
3705 netif_tx_napi_add(ndev, &cpsw->napi_tx,
3706 cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll,
3708 cpsw_split_res(ndev);
3710 /* register the network device */
3711 SET_NETDEV_DEV(ndev, &pdev->dev);
3712 ret = register_netdev(ndev);
3714 dev_err(priv->dev, "error registering net device\n");
3719 if (cpsw->data.dual_emac) {
3720 ret = cpsw_probe_dual_emac(priv);
3722 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3723 goto clean_unregister_netdev_ret;
3727 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3728 * MISC IRQs which are always kept disabled with this driver so
3729 * we will not request them.
3731 * If anyone wants to implement support for those, make sure to
3732 * first request and append them to irqs_table array.
3736 irq = platform_get_irq(pdev, 1);
3742 cpsw->irqs_table[0] = irq;
3743 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3744 0, dev_name(&pdev->dev), cpsw);
3746 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3751 irq = platform_get_irq(pdev, 2);
3757 cpsw->irqs_table[1] = irq;
3758 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3759 0, dev_name(&pdev->dev), cpsw);
3761 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3765 cpsw_notice(priv, probe,
3766 "initialized device (regs %pa, irq %d, pool size %d)\n",
3767 &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3769 pm_runtime_put(&pdev->dev);
3773 clean_unregister_netdev_ret:
3774 unregister_netdev(ndev);
3776 cpdma_ctlr_destroy(cpsw->dma);
3778 cpsw_remove_dt(pdev);
3779 pm_runtime_put_sync(&pdev->dev);
3780 clean_runtime_disable_ret:
3781 pm_runtime_disable(&pdev->dev);
3783 free_netdev(priv->ndev);
3787 static int cpsw_remove(struct platform_device *pdev)
3789 struct net_device *ndev = platform_get_drvdata(pdev);
3790 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3793 ret = pm_runtime_get_sync(&pdev->dev);
3795 pm_runtime_put_noidle(&pdev->dev);
3799 if (cpsw->data.dual_emac)
3800 unregister_netdev(cpsw->slaves[1].ndev);
3801 unregister_netdev(ndev);
3803 cpts_release(cpsw->cpts);
3804 cpdma_ctlr_destroy(cpsw->dma);
3805 cpsw_remove_dt(pdev);
3806 pm_runtime_put_sync(&pdev->dev);
3807 pm_runtime_disable(&pdev->dev);
3808 if (cpsw->data.dual_emac)
3809 free_netdev(cpsw->slaves[1].ndev);
3814 #ifdef CONFIG_PM_SLEEP
3815 static int cpsw_suspend(struct device *dev)
3817 struct net_device *ndev = dev_get_drvdata(dev);
3818 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3820 if (cpsw->data.dual_emac) {
3823 for (i = 0; i < cpsw->data.slaves; i++) {
3824 if (netif_running(cpsw->slaves[i].ndev))
3825 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3828 if (netif_running(ndev))
3829 cpsw_ndo_stop(ndev);
3832 /* Select sleep pin state */
3833 pinctrl_pm_select_sleep_state(dev);
3838 static int cpsw_resume(struct device *dev)
3840 struct net_device *ndev = dev_get_drvdata(dev);
3841 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3843 /* Select default pin state */
3844 pinctrl_pm_select_default_state(dev);
3846 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3848 if (cpsw->data.dual_emac) {
3851 for (i = 0; i < cpsw->data.slaves; i++) {
3852 if (netif_running(cpsw->slaves[i].ndev))
3853 cpsw_ndo_open(cpsw->slaves[i].ndev);
3856 if (netif_running(ndev))
3857 cpsw_ndo_open(ndev);
3865 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3867 static struct platform_driver cpsw_driver = {
3871 .of_match_table = cpsw_of_mtable,
3873 .probe = cpsw_probe,
3874 .remove = cpsw_remove,
3877 module_platform_driver(cpsw_driver);
3879 MODULE_LICENSE("GPL");
3880 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3881 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3882 MODULE_DESCRIPTION("TI CPSW Ethernet driver");