2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio/consumer.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38 #include <linux/kmemleak.h>
39 #include <linux/sys_soc.h>
41 #include <linux/pinctrl/consumer.h>
46 #include "davinci_cpdma.h"
48 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
49 NETIF_MSG_DRV | NETIF_MSG_LINK | \
50 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
51 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
52 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
53 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
54 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
57 #define cpsw_info(priv, type, format, ...) \
59 if (netif_msg_##type(priv) && net_ratelimit()) \
60 dev_info(priv->dev, format, ## __VA_ARGS__); \
63 #define cpsw_err(priv, type, format, ...) \
65 if (netif_msg_##type(priv) && net_ratelimit()) \
66 dev_err(priv->dev, format, ## __VA_ARGS__); \
69 #define cpsw_dbg(priv, type, format, ...) \
71 if (netif_msg_##type(priv) && net_ratelimit()) \
72 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
75 #define cpsw_notice(priv, type, format, ...) \
77 if (netif_msg_##type(priv) && net_ratelimit()) \
78 dev_notice(priv->dev, format, ## __VA_ARGS__); \
81 #define ALE_ALL_PORTS 0x7
83 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
84 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
85 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
87 #define CPSW_VERSION_1 0x19010a
88 #define CPSW_VERSION_2 0x19010c
89 #define CPSW_VERSION_3 0x19010f
90 #define CPSW_VERSION_4 0x190112
92 #define HOST_PORT_NUM 0
93 #define CPSW_ALE_PORTS_NUM 3
94 #define SLIVER_SIZE 0x40
96 #define CPSW1_HOST_PORT_OFFSET 0x028
97 #define CPSW1_SLAVE_OFFSET 0x050
98 #define CPSW1_SLAVE_SIZE 0x040
99 #define CPSW1_CPDMA_OFFSET 0x100
100 #define CPSW1_STATERAM_OFFSET 0x200
101 #define CPSW1_HW_STATS 0x400
102 #define CPSW1_CPTS_OFFSET 0x500
103 #define CPSW1_ALE_OFFSET 0x600
104 #define CPSW1_SLIVER_OFFSET 0x700
106 #define CPSW2_HOST_PORT_OFFSET 0x108
107 #define CPSW2_SLAVE_OFFSET 0x200
108 #define CPSW2_SLAVE_SIZE 0x100
109 #define CPSW2_CPDMA_OFFSET 0x800
110 #define CPSW2_HW_STATS 0x900
111 #define CPSW2_STATERAM_OFFSET 0xa00
112 #define CPSW2_CPTS_OFFSET 0xc00
113 #define CPSW2_ALE_OFFSET 0xd00
114 #define CPSW2_SLIVER_OFFSET 0xd80
115 #define CPSW2_BD_OFFSET 0x2000
117 #define CPDMA_RXTHRESH 0x0c0
118 #define CPDMA_RXFREE 0x0e0
119 #define CPDMA_TXHDP 0x00
120 #define CPDMA_RXHDP 0x20
121 #define CPDMA_TXCP 0x40
122 #define CPDMA_RXCP 0x60
124 #define CPSW_POLL_WEIGHT 64
125 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4
126 #define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN)
127 #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\
129 CPSW_RX_VLAN_ENCAP_HDR_SIZE)
131 #define RX_PRIORITY_MAPPING 0x76543210
132 #define TX_PRIORITY_MAPPING 0x33221100
133 #define CPDMA_TX_PRIORITY_MAP 0x76543210
135 #define CPSW_VLAN_AWARE BIT(1)
136 #define CPSW_RX_VLAN_ENCAP BIT(2)
137 #define CPSW_ALE_VLAN_AWARE 1
139 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
140 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
141 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
143 #define CPSW_INTPACEEN (0x3f << 16)
144 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
145 #define CPSW_CMINTMAX_CNT 63
146 #define CPSW_CMINTMIN_CNT 2
147 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
148 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
150 #define cpsw_slave_index(cpsw, priv) \
151 ((cpsw->data.dual_emac) ? priv->emac_port : \
152 cpsw->data.active_slave)
154 #define CPSW_MAX_QUEUES 8
155 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
157 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
158 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
159 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16
160 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8
161 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
163 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
164 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
165 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
166 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
169 static int debug_level;
170 module_param(debug_level, int, 0);
171 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
173 static int ale_ageout = 10;
174 module_param(ale_ageout, int, 0);
175 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
177 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
178 module_param(rx_packet_max, int, 0);
179 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
181 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
182 module_param(descs_pool_size, int, 0444);
183 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
185 struct cpsw_wr_regs {
205 struct cpsw_ss_regs {
222 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
223 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
224 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
225 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
226 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
227 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
228 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
229 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
232 #define CPSW2_CONTROL 0x00 /* Control Register */
233 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
234 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
235 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
236 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
237 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
238 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
240 /* CPSW_PORT_V1 and V2 */
241 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
242 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
243 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
245 /* CPSW_PORT_V2 only */
246 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
247 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
248 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
249 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
250 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
251 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
252 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
253 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
255 /* Bit definitions for the CPSW2_CONTROL register */
256 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
257 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
258 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
259 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
260 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
261 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
262 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
263 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
264 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
265 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
266 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
267 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
268 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
269 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
270 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
271 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
272 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
274 #define CTRL_V2_TS_BITS \
275 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
276 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
278 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
279 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
280 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
283 #define CTRL_V3_TS_BITS \
284 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
285 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
288 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
289 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
290 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
292 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
293 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
294 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
295 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
296 #define TS_MSG_TYPE_EN_MASK (0xffff)
298 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
299 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
301 /* Bit definitions for the CPSW1_TS_CTL register */
302 #define CPSW_V1_TS_RX_EN BIT(0)
303 #define CPSW_V1_TS_TX_EN BIT(4)
304 #define CPSW_V1_MSG_TYPE_OFS 16
306 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
307 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
309 #define CPSW_MAX_BLKS_TX 15
310 #define CPSW_MAX_BLKS_TX_SHIFT 4
311 #define CPSW_MAX_BLKS_RX 5
313 struct cpsw_host_regs {
319 u32 cpdma_tx_pri_map;
320 u32 cpdma_rx_chan_map;
323 struct cpsw_sliver_regs {
336 struct cpsw_hw_stats {
338 u32 rxbroadcastframes;
339 u32 rxmulticastframes;
342 u32 rxaligncodeerrors;
343 u32 rxoversizedframes;
345 u32 rxundersizedframes;
350 u32 txbroadcastframes;
351 u32 txmulticastframes;
353 u32 txdeferredframes;
354 u32 txcollisionframes;
355 u32 txsinglecollframes;
356 u32 txmultcollframes;
357 u32 txexcessivecollisions;
358 u32 txlatecollisions;
360 u32 txcarriersenseerrors;
363 u32 octetframes65t127;
364 u32 octetframes128t255;
365 u32 octetframes256t511;
366 u32 octetframes512t1023;
367 u32 octetframes1024tup;
374 struct cpsw_slave_data {
375 struct device_node *phy_node;
376 char phy_id[MII_BUS_ID_SIZE];
378 u8 mac_addr[ETH_ALEN];
379 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
382 struct cpsw_platform_data {
383 struct cpsw_slave_data *slave_data;
384 u32 ss_reg_ofs; /* Subsystem control register offset */
385 u32 channels; /* number of cpdma channels (symmetric) */
386 u32 slaves; /* number of slave cpgmac ports */
387 u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
388 u32 ale_entries; /* ale table size */
389 u32 bd_ram_size; /*buffer descriptor ram size */
390 u32 mac_control; /* Mac control register */
391 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
392 bool dual_emac; /* Enable Dual EMAC mode */
397 struct cpsw_sliver_regs __iomem *sliver;
400 struct cpsw_slave_data *data;
401 struct phy_device *phy;
402 struct net_device *ndev;
406 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
408 return readl_relaxed(slave->regs + offset);
411 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
413 writel_relaxed(val, slave->regs + offset);
417 struct cpdma_chan *ch;
423 struct cpsw_platform_data data;
424 struct napi_struct napi_rx;
425 struct napi_struct napi_tx;
426 struct cpsw_ss_regs __iomem *regs;
427 struct cpsw_wr_regs __iomem *wr_regs;
428 u8 __iomem *hw_stats;
429 struct cpsw_host_regs __iomem *host_port_regs;
434 struct cpsw_slave *slaves;
435 struct cpdma_ctlr *dma;
436 struct cpsw_vector txv[CPSW_MAX_QUEUES];
437 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
438 struct cpsw_ale *ale;
440 bool rx_irq_disabled;
441 bool tx_irq_disabled;
442 u32 irqs_table[IRQ_NUM];
444 int rx_ch_num, tx_ch_num;
450 struct net_device *ndev;
453 u8 mac_addr[ETH_ALEN];
457 struct cpsw_common *cpsw;
461 char stat_string[ETH_GSTRING_LEN];
473 #define CPSW_STAT(m) CPSW_STATS, \
474 sizeof(((struct cpsw_hw_stats *)0)->m), \
475 offsetof(struct cpsw_hw_stats, m)
476 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
477 sizeof(((struct cpdma_chan_stats *)0)->m), \
478 offsetof(struct cpdma_chan_stats, m)
479 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
480 sizeof(((struct cpdma_chan_stats *)0)->m), \
481 offsetof(struct cpdma_chan_stats, m)
483 static const struct cpsw_stats cpsw_gstrings_stats[] = {
484 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
485 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
486 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
487 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
488 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
489 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
490 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
491 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
492 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
493 { "Rx Fragments", CPSW_STAT(rxfragments) },
494 { "Rx Octets", CPSW_STAT(rxoctets) },
495 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
496 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
497 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
498 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
499 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
500 { "Collisions", CPSW_STAT(txcollisionframes) },
501 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
502 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
503 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
504 { "Late Collisions", CPSW_STAT(txlatecollisions) },
505 { "Tx Underrun", CPSW_STAT(txunderrun) },
506 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
507 { "Tx Octets", CPSW_STAT(txoctets) },
508 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
509 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
510 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
511 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
512 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
513 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
514 { "Net Octets", CPSW_STAT(netoctets) },
515 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
516 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
517 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
520 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
521 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
522 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
523 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
524 { "misqueued", CPDMA_RX_STAT(misqueued) },
525 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
526 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
527 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
528 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
529 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
530 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
531 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
532 { "requeue", CPDMA_RX_STAT(requeue) },
533 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
536 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
537 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
539 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
540 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
541 #define for_each_slave(priv, func, arg...) \
543 struct cpsw_slave *slave; \
544 struct cpsw_common *cpsw = (priv)->cpsw; \
546 if (cpsw->data.dual_emac) \
547 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
549 for (n = cpsw->data.slaves, \
550 slave = cpsw->slaves; \
552 (func)(slave++, ##arg); \
555 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
557 if (!cpsw->data.dual_emac) \
559 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
560 ndev = cpsw->slaves[0].ndev; \
562 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
563 ndev = cpsw->slaves[1].ndev; \
567 #define cpsw_add_mcast(cpsw, priv, addr) \
569 if (cpsw->data.dual_emac) { \
570 struct cpsw_slave *slave = cpsw->slaves + \
572 int slave_port = cpsw_get_slave_port( \
574 cpsw_ale_add_mcast(cpsw->ale, addr, \
575 1 << slave_port | ALE_PORT_HOST, \
576 ALE_VLAN, slave->port_vlan, 0); \
578 cpsw_ale_add_mcast(cpsw->ale, addr, \
584 static inline int cpsw_get_slave_port(u32 slave_num)
586 return slave_num + 1;
589 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
591 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
592 struct cpsw_ale *ale = cpsw->ale;
595 if (cpsw->data.dual_emac) {
598 /* Enabling promiscuous mode for one interface will be
599 * common for both the interface as the interface shares
600 * the same hardware resource.
602 for (i = 0; i < cpsw->data.slaves; i++)
603 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
606 if (!enable && flag) {
608 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
613 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
615 dev_dbg(&ndev->dev, "promiscuity enabled\n");
618 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
619 dev_dbg(&ndev->dev, "promiscuity disabled\n");
623 unsigned long timeout = jiffies + HZ;
625 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
626 for (i = 0; i <= cpsw->data.slaves; i++) {
627 cpsw_ale_control_set(ale, i,
628 ALE_PORT_NOLEARN, 1);
629 cpsw_ale_control_set(ale, i,
630 ALE_PORT_NO_SA_UPDATE, 1);
633 /* Clear All Untouched entries */
634 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
637 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
639 } while (time_after(timeout, jiffies));
640 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
642 /* Clear all mcast from ALE */
643 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
645 /* Flood All Unicast Packets to Host port */
646 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
647 dev_dbg(&ndev->dev, "promiscuity enabled\n");
649 /* Don't Flood All Unicast Packets to Host port */
650 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
652 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
653 for (i = 0; i <= cpsw->data.slaves; i++) {
654 cpsw_ale_control_set(ale, i,
655 ALE_PORT_NOLEARN, 0);
656 cpsw_ale_control_set(ale, i,
657 ALE_PORT_NO_SA_UPDATE, 0);
659 dev_dbg(&ndev->dev, "promiscuity disabled\n");
664 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
666 struct cpsw_priv *priv = netdev_priv(ndev);
667 struct cpsw_common *cpsw = priv->cpsw;
670 if (cpsw->data.dual_emac)
671 vid = cpsw->slaves[priv->emac_port].port_vlan;
673 vid = cpsw->data.default_vlan;
675 if (ndev->flags & IFF_PROMISC) {
676 /* Enable promiscuous mode */
677 cpsw_set_promiscious(ndev, true);
678 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
681 /* Disable promiscuous mode */
682 cpsw_set_promiscious(ndev, false);
685 /* Restore allmulti on vlans if necessary */
686 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
688 /* Clear all mcast from ALE */
689 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
691 if (!netdev_mc_empty(ndev)) {
692 struct netdev_hw_addr *ha;
694 /* program multicast address list into ALE register */
695 netdev_for_each_mc_addr(ha, ndev) {
696 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
701 static void cpsw_intr_enable(struct cpsw_common *cpsw)
703 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
704 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
706 cpdma_ctlr_int_ctrl(cpsw->dma, true);
710 static void cpsw_intr_disable(struct cpsw_common *cpsw)
712 writel_relaxed(0, &cpsw->wr_regs->tx_en);
713 writel_relaxed(0, &cpsw->wr_regs->rx_en);
715 cpdma_ctlr_int_ctrl(cpsw->dma, false);
719 static void cpsw_tx_handler(void *token, int len, int status)
721 struct netdev_queue *txq;
722 struct sk_buff *skb = token;
723 struct net_device *ndev = skb->dev;
724 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
726 /* Check whether the queue is stopped due to stalled tx dma, if the
727 * queue is stopped then start the queue as we have free desc for tx
729 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
730 if (unlikely(netif_tx_queue_stopped(txq)))
731 netif_tx_wake_queue(txq);
733 cpts_tx_timestamp(cpsw->cpts, skb);
734 ndev->stats.tx_packets++;
735 ndev->stats.tx_bytes += len;
736 dev_kfree_skb_any(skb);
739 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
741 struct cpsw_priv *priv = netdev_priv(skb->dev);
742 struct cpsw_common *cpsw = priv->cpsw;
743 u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
744 u16 vtag, vid, prio, pkt_type;
746 /* Remove VLAN header encapsulation word */
747 skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
749 pkt_type = (rx_vlan_encap_hdr >>
750 CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
751 CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
752 /* Ignore unknown & Priority-tagged packets*/
753 if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
754 pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
757 vid = (rx_vlan_encap_hdr >>
758 CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
760 /* Ignore vid 0 and pass packet as is */
763 /* Ignore default vlans in dual mac mode */
764 if (cpsw->data.dual_emac &&
765 vid == cpsw->slaves[priv->emac_port].port_vlan)
768 prio = (rx_vlan_encap_hdr >>
769 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
770 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
772 vtag = (prio << VLAN_PRIO_SHIFT) | vid;
773 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
775 /* strip vlan tag for VLAN-tagged packet */
776 if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
777 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
778 skb_pull(skb, VLAN_HLEN);
782 static void cpsw_rx_handler(void *token, int len, int status)
784 struct cpdma_chan *ch;
785 struct sk_buff *skb = token;
786 struct sk_buff *new_skb;
787 struct net_device *ndev = skb->dev;
789 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
791 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
793 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
794 /* In dual emac mode check for all interfaces */
795 if (cpsw->data.dual_emac && cpsw->usage_count &&
797 /* The packet received is for the interface which
798 * is already down and the other interface is up
799 * and running, instead of freeing which results
800 * in reducing of the number of rx descriptor in
801 * DMA engine, requeue skb back to cpdma.
807 /* the interface is going down, skbs are purged */
808 dev_kfree_skb_any(skb);
812 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
814 skb_copy_queue_mapping(new_skb, skb);
816 if (status & CPDMA_RX_VLAN_ENCAP)
817 cpsw_rx_vlan_encap(skb);
818 cpts_rx_timestamp(cpsw->cpts, skb);
819 skb->protocol = eth_type_trans(skb, ndev);
820 netif_receive_skb(skb);
821 ndev->stats.rx_bytes += len;
822 ndev->stats.rx_packets++;
823 kmemleak_not_leak(new_skb);
825 ndev->stats.rx_dropped++;
830 if (netif_dormant(ndev)) {
831 dev_kfree_skb_any(new_skb);
835 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
836 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
837 skb_tailroom(new_skb), 0);
838 if (WARN_ON(ret < 0))
839 dev_kfree_skb_any(new_skb);
842 static void cpsw_split_res(struct net_device *ndev)
844 struct cpsw_priv *priv = netdev_priv(ndev);
845 u32 consumed_rate = 0, bigest_rate = 0;
846 struct cpsw_common *cpsw = priv->cpsw;
847 struct cpsw_vector *txv = cpsw->txv;
848 int i, ch_weight, rlim_ch_num = 0;
849 int budget, bigest_rate_ch = 0;
850 u32 ch_rate, max_rate;
853 for (i = 0; i < cpsw->tx_ch_num; i++) {
854 ch_rate = cpdma_chan_get_rate(txv[i].ch);
859 consumed_rate += ch_rate;
862 if (cpsw->tx_ch_num == rlim_ch_num) {
863 max_rate = consumed_rate;
864 } else if (!rlim_ch_num) {
865 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
867 max_rate = consumed_rate;
869 max_rate = cpsw->speed * 1000;
871 /* if max_rate is less then expected due to reduced link speed,
872 * split proportionally according next potential max speed
874 if (max_rate < consumed_rate)
877 if (max_rate < consumed_rate)
880 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
881 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
882 (cpsw->tx_ch_num - rlim_ch_num);
883 bigest_rate = (max_rate - consumed_rate) /
884 (cpsw->tx_ch_num - rlim_ch_num);
887 /* split tx weight/budget */
888 budget = CPSW_POLL_WEIGHT;
889 for (i = 0; i < cpsw->tx_ch_num; i++) {
890 ch_rate = cpdma_chan_get_rate(txv[i].ch);
892 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
895 if (ch_rate > bigest_rate) {
897 bigest_rate = ch_rate;
900 ch_weight = (ch_rate * 100) / max_rate;
903 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
905 txv[i].budget = ch_budget;
908 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
911 budget -= txv[i].budget;
915 txv[bigest_rate_ch].budget += budget;
917 /* split rx budget */
918 budget = CPSW_POLL_WEIGHT;
919 ch_budget = budget / cpsw->rx_ch_num;
920 for (i = 0; i < cpsw->rx_ch_num; i++) {
921 cpsw->rxv[i].budget = ch_budget;
926 cpsw->rxv[0].budget += budget;
929 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
931 struct cpsw_common *cpsw = dev_id;
933 writel(0, &cpsw->wr_regs->tx_en);
934 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
936 if (cpsw->quirk_irq) {
937 disable_irq_nosync(cpsw->irqs_table[1]);
938 cpsw->tx_irq_disabled = true;
941 napi_schedule(&cpsw->napi_tx);
945 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
947 struct cpsw_common *cpsw = dev_id;
949 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
950 writel(0, &cpsw->wr_regs->rx_en);
952 if (cpsw->quirk_irq) {
953 disable_irq_nosync(cpsw->irqs_table[0]);
954 cpsw->rx_irq_disabled = true;
957 napi_schedule(&cpsw->napi_rx);
961 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
964 int num_tx, cur_budget, ch;
965 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
966 struct cpsw_vector *txv;
968 /* process every unprocessed channel */
969 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
970 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
971 if (!(ch_map & 0x01))
974 txv = &cpsw->txv[ch];
975 if (unlikely(txv->budget > budget - num_tx))
976 cur_budget = budget - num_tx;
978 cur_budget = txv->budget;
980 num_tx += cpdma_chan_process(txv->ch, cur_budget);
981 if (num_tx >= budget)
985 if (num_tx < budget) {
986 napi_complete(napi_tx);
987 writel(0xff, &cpsw->wr_regs->tx_en);
993 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
995 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
998 num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
999 if (num_tx < budget) {
1000 napi_complete(napi_tx);
1001 writel(0xff, &cpsw->wr_regs->tx_en);
1002 if (cpsw->tx_irq_disabled) {
1003 cpsw->tx_irq_disabled = false;
1004 enable_irq(cpsw->irqs_table[1]);
1011 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1014 int num_rx, cur_budget, ch;
1015 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1016 struct cpsw_vector *rxv;
1018 /* process every unprocessed channel */
1019 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1020 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1021 if (!(ch_map & 0x01))
1024 rxv = &cpsw->rxv[ch];
1025 if (unlikely(rxv->budget > budget - num_rx))
1026 cur_budget = budget - num_rx;
1028 cur_budget = rxv->budget;
1030 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1031 if (num_rx >= budget)
1035 if (num_rx < budget) {
1036 napi_complete_done(napi_rx, num_rx);
1037 writel(0xff, &cpsw->wr_regs->rx_en);
1043 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1045 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1048 num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1049 if (num_rx < budget) {
1050 napi_complete_done(napi_rx, num_rx);
1051 writel(0xff, &cpsw->wr_regs->rx_en);
1052 if (cpsw->rx_irq_disabled) {
1053 cpsw->rx_irq_disabled = false;
1054 enable_irq(cpsw->irqs_table[0]);
1061 static inline void soft_reset(const char *module, void __iomem *reg)
1063 unsigned long timeout = jiffies + HZ;
1065 writel_relaxed(1, reg);
1068 } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1070 WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1073 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1074 struct cpsw_priv *priv)
1076 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1077 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1080 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1081 struct cpsw_priv *priv, bool *link)
1083 struct phy_device *phy = slave->phy;
1084 u32 mac_control = 0;
1086 struct cpsw_common *cpsw = priv->cpsw;
1091 slave_port = cpsw_get_slave_port(slave->slave_num);
1094 mac_control = cpsw->data.mac_control;
1096 /* enable forwarding */
1097 cpsw_ale_control_set(cpsw->ale, slave_port,
1098 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1100 if (phy->speed == 1000)
1101 mac_control |= BIT(7); /* GIGABITEN */
1103 mac_control |= BIT(0); /* FULLDUPLEXEN */
1105 /* set speed_in input in case RMII mode is used in 100Mbps */
1106 if (phy->speed == 100)
1107 mac_control |= BIT(15);
1108 /* in band mode only works in 10Mbps RGMII mode */
1109 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1110 mac_control |= BIT(18); /* In Band mode */
1113 mac_control |= BIT(3);
1116 mac_control |= BIT(4);
1121 /* disable forwarding */
1122 cpsw_ale_control_set(cpsw->ale, slave_port,
1123 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1126 if (mac_control != slave->mac_control) {
1127 phy_print_status(phy);
1128 writel_relaxed(mac_control, &slave->sliver->mac_control);
1131 slave->mac_control = mac_control;
1134 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1138 for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1139 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1140 speed += cpsw->slaves[i].phy->speed;
1145 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1150 /* re-split resources only in case speed was changed */
1151 speed = cpsw_get_common_speed(cpsw);
1152 if (speed == cpsw->speed || !speed)
1155 cpsw->speed = speed;
1157 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1158 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1165 /* cases not dependent on speed */
1166 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1172 static void cpsw_adjust_link(struct net_device *ndev)
1174 struct cpsw_priv *priv = netdev_priv(ndev);
1175 struct cpsw_common *cpsw = priv->cpsw;
1178 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1181 if (cpsw_need_resplit(cpsw))
1182 cpsw_split_res(ndev);
1184 netif_carrier_on(ndev);
1185 if (netif_running(ndev))
1186 netif_tx_wake_all_queues(ndev);
1188 netif_carrier_off(ndev);
1189 netif_tx_stop_all_queues(ndev);
1193 static int cpsw_get_coalesce(struct net_device *ndev,
1194 struct ethtool_coalesce *coal)
1196 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1198 coal->rx_coalesce_usecs = cpsw->coal_intvl;
1202 static int cpsw_set_coalesce(struct net_device *ndev,
1203 struct ethtool_coalesce *coal)
1205 struct cpsw_priv *priv = netdev_priv(ndev);
1207 u32 num_interrupts = 0;
1211 struct cpsw_common *cpsw = priv->cpsw;
1213 coal_intvl = coal->rx_coalesce_usecs;
1215 int_ctrl = readl(&cpsw->wr_regs->int_control);
1216 prescale = cpsw->bus_freq_mhz * 4;
1218 if (!coal->rx_coalesce_usecs) {
1219 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1223 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1224 coal_intvl = CPSW_CMINTMIN_INTVL;
1226 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1227 /* Interrupt pacer works with 4us Pulse, we can
1228 * throttle further by dilating the 4us pulse.
1230 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1232 if (addnl_dvdr > 1) {
1233 prescale *= addnl_dvdr;
1234 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1235 coal_intvl = (CPSW_CMINTMAX_INTVL
1239 coal_intvl = CPSW_CMINTMAX_INTVL;
1243 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1244 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1245 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1247 int_ctrl |= CPSW_INTPACEEN;
1248 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1249 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1252 writel(int_ctrl, &cpsw->wr_regs->int_control);
1254 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1255 cpsw->coal_intvl = coal_intvl;
1260 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1262 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1266 return (CPSW_STATS_COMMON_LEN +
1267 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1274 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1280 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1281 for (i = 0; i < ch_stats_len; i++) {
1282 line = i % CPSW_STATS_CH_LEN;
1283 snprintf(*p, ETH_GSTRING_LEN,
1284 "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1285 (long)(i / CPSW_STATS_CH_LEN),
1286 cpsw_gstrings_ch_stats[line].stat_string);
1287 *p += ETH_GSTRING_LEN;
1291 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1293 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1297 switch (stringset) {
1299 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1300 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1302 p += ETH_GSTRING_LEN;
1305 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1306 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1311 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1312 struct ethtool_stats *stats, u64 *data)
1315 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1316 struct cpdma_chan_stats ch_stats;
1319 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1320 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1321 data[l] = readl(cpsw->hw_stats +
1322 cpsw_gstrings_stats[l].stat_offset);
1324 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1325 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1326 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1327 p = (u8 *)&ch_stats +
1328 cpsw_gstrings_ch_stats[i].stat_offset;
1329 data[l] = *(u32 *)p;
1333 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1334 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1335 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1336 p = (u8 *)&ch_stats +
1337 cpsw_gstrings_ch_stats[i].stat_offset;
1338 data[l] = *(u32 *)p;
1343 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1344 struct sk_buff *skb,
1345 struct cpdma_chan *txch)
1347 struct cpsw_common *cpsw = priv->cpsw;
1349 skb_tx_timestamp(skb);
1350 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1351 priv->emac_port + cpsw->data.dual_emac);
1354 static inline void cpsw_add_dual_emac_def_ale_entries(
1355 struct cpsw_priv *priv, struct cpsw_slave *slave,
1358 struct cpsw_common *cpsw = priv->cpsw;
1359 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1361 if (cpsw->version == CPSW_VERSION_1)
1362 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1364 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1365 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1366 port_mask, port_mask, 0);
1367 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1368 port_mask, ALE_VLAN, slave->port_vlan, 0);
1369 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1370 HOST_PORT_NUM, ALE_VLAN |
1371 ALE_SECURE, slave->port_vlan);
1372 cpsw_ale_control_set(cpsw->ale, slave_port,
1373 ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1376 static void soft_reset_slave(struct cpsw_slave *slave)
1380 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1381 soft_reset(name, &slave->sliver->soft_reset);
1384 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1387 struct phy_device *phy;
1388 struct cpsw_common *cpsw = priv->cpsw;
1390 soft_reset_slave(slave);
1392 /* setup priority mapping */
1393 writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1395 switch (cpsw->version) {
1396 case CPSW_VERSION_1:
1397 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1398 /* Increase RX FIFO size to 5 for supporting fullduplex
1402 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1403 CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1405 case CPSW_VERSION_2:
1406 case CPSW_VERSION_3:
1407 case CPSW_VERSION_4:
1408 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1409 /* Increase RX FIFO size to 5 for supporting fullduplex
1413 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1414 CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1418 /* setup max packet size, and mac address */
1419 writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1420 cpsw_set_slave_mac(slave, priv);
1422 slave->mac_control = 0; /* no link yet */
1424 slave_port = cpsw_get_slave_port(slave->slave_num);
1426 if (cpsw->data.dual_emac)
1427 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1429 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1430 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1432 if (slave->data->phy_node) {
1433 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1434 &cpsw_adjust_link, 0, slave->data->phy_if);
1436 dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1437 slave->data->phy_node,
1442 phy = phy_connect(priv->ndev, slave->data->phy_id,
1443 &cpsw_adjust_link, slave->data->phy_if);
1446 "phy \"%s\" not found on slave %d, err %ld\n",
1447 slave->data->phy_id, slave->slave_num,
1455 phy_attached_info(slave->phy);
1457 phy_start(slave->phy);
1459 /* Configure GMII_SEL register */
1460 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1463 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1465 struct cpsw_common *cpsw = priv->cpsw;
1466 const int vlan = cpsw->data.default_vlan;
1469 int unreg_mcast_mask;
1471 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1474 writel(vlan, &cpsw->host_port_regs->port_vlan);
1476 for (i = 0; i < cpsw->data.slaves; i++)
1477 slave_write(cpsw->slaves + i, vlan, reg);
1479 if (priv->ndev->flags & IFF_ALLMULTI)
1480 unreg_mcast_mask = ALE_ALL_PORTS;
1482 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1484 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1485 ALE_ALL_PORTS, ALE_ALL_PORTS,
1489 static void cpsw_init_host_port(struct cpsw_priv *priv)
1493 struct cpsw_common *cpsw = priv->cpsw;
1495 /* soft reset the controller and initialize ale */
1496 soft_reset("cpsw", &cpsw->regs->soft_reset);
1497 cpsw_ale_start(cpsw->ale);
1499 /* switch to vlan unaware mode */
1500 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1501 CPSW_ALE_VLAN_AWARE);
1502 control_reg = readl(&cpsw->regs->control);
1503 control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1504 writel(control_reg, &cpsw->regs->control);
1505 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1506 CPSW_FIFO_NORMAL_MODE;
1507 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1509 /* setup host port priority mapping */
1510 writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1511 &cpsw->host_port_regs->cpdma_tx_pri_map);
1512 writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1514 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1515 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1517 if (!cpsw->data.dual_emac) {
1518 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1520 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1521 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1525 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1527 struct cpsw_common *cpsw = priv->cpsw;
1528 struct sk_buff *skb;
1532 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1533 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1534 for (i = 0; i < ch_buf_num; i++) {
1535 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1536 cpsw->rx_packet_max,
1539 cpsw_err(priv, ifup, "cannot allocate skb\n");
1543 skb_set_queue_mapping(skb, ch);
1544 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1545 skb->data, skb_tailroom(skb),
1548 cpsw_err(priv, ifup,
1549 "cannot submit skb to channel %d rx, error %d\n",
1554 kmemleak_not_leak(skb);
1557 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1564 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1568 slave_port = cpsw_get_slave_port(slave->slave_num);
1572 phy_stop(slave->phy);
1573 phy_disconnect(slave->phy);
1575 cpsw_ale_control_set(cpsw->ale, slave_port,
1576 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1577 soft_reset_slave(slave);
1580 static int cpsw_ndo_open(struct net_device *ndev)
1582 struct cpsw_priv *priv = netdev_priv(ndev);
1583 struct cpsw_common *cpsw = priv->cpsw;
1587 ret = pm_runtime_get_sync(cpsw->dev);
1589 pm_runtime_put_noidle(cpsw->dev);
1593 netif_carrier_off(ndev);
1595 /* Notify the stack of the actual queue counts. */
1596 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1598 dev_err(priv->dev, "cannot set real number of tx queues\n");
1602 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1604 dev_err(priv->dev, "cannot set real number of rx queues\n");
1608 reg = cpsw->version;
1610 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1611 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1612 CPSW_RTL_VERSION(reg));
1614 /* Initialize host and slave ports */
1615 if (!cpsw->usage_count)
1616 cpsw_init_host_port(priv);
1617 for_each_slave(priv, cpsw_slave_open, priv);
1619 /* Add default VLAN */
1620 if (!cpsw->data.dual_emac)
1621 cpsw_add_default_vlan(priv);
1623 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1624 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1626 /* initialize shared resources for every ndev */
1627 if (!cpsw->usage_count) {
1628 /* disable priority elevation */
1629 writel_relaxed(0, &cpsw->regs->ptype);
1631 /* enable statistics collection only on all ports */
1632 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1634 /* Enable internal fifo flow control */
1635 writel(0x7, &cpsw->regs->flow_control);
1637 napi_enable(&cpsw->napi_rx);
1638 napi_enable(&cpsw->napi_tx);
1640 if (cpsw->tx_irq_disabled) {
1641 cpsw->tx_irq_disabled = false;
1642 enable_irq(cpsw->irqs_table[1]);
1645 if (cpsw->rx_irq_disabled) {
1646 cpsw->rx_irq_disabled = false;
1647 enable_irq(cpsw->irqs_table[0]);
1650 ret = cpsw_fill_rx_channels(priv);
1654 if (cpts_register(cpsw->cpts))
1655 dev_err(priv->dev, "error registering cpts device\n");
1659 /* Enable Interrupt pacing if configured */
1660 if (cpsw->coal_intvl != 0) {
1661 struct ethtool_coalesce coal;
1663 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1664 cpsw_set_coalesce(ndev, &coal);
1667 cpdma_ctlr_start(cpsw->dma);
1668 cpsw_intr_enable(cpsw);
1669 cpsw->usage_count++;
1674 cpdma_ctlr_stop(cpsw->dma);
1675 for_each_slave(priv, cpsw_slave_stop, cpsw);
1676 pm_runtime_put_sync(cpsw->dev);
1677 netif_carrier_off(priv->ndev);
1681 static int cpsw_ndo_stop(struct net_device *ndev)
1683 struct cpsw_priv *priv = netdev_priv(ndev);
1684 struct cpsw_common *cpsw = priv->cpsw;
1686 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1687 netif_tx_stop_all_queues(priv->ndev);
1688 netif_carrier_off(priv->ndev);
1690 if (cpsw->usage_count <= 1) {
1691 napi_disable(&cpsw->napi_rx);
1692 napi_disable(&cpsw->napi_tx);
1693 cpts_unregister(cpsw->cpts);
1694 cpsw_intr_disable(cpsw);
1695 cpdma_ctlr_stop(cpsw->dma);
1696 cpsw_ale_stop(cpsw->ale);
1698 for_each_slave(priv, cpsw_slave_stop, cpsw);
1700 if (cpsw_need_resplit(cpsw))
1701 cpsw_split_res(ndev);
1703 cpsw->usage_count--;
1704 pm_runtime_put_sync(cpsw->dev);
1708 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1709 struct net_device *ndev)
1711 struct cpsw_priv *priv = netdev_priv(ndev);
1712 struct cpsw_common *cpsw = priv->cpsw;
1713 struct cpts *cpts = cpsw->cpts;
1714 struct netdev_queue *txq;
1715 struct cpdma_chan *txch;
1718 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1719 cpsw_err(priv, tx_err, "packet pad failed\n");
1720 ndev->stats.tx_dropped++;
1721 return NET_XMIT_DROP;
1724 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1725 cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1726 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1728 q_idx = skb_get_queue_mapping(skb);
1729 if (q_idx >= cpsw->tx_ch_num)
1730 q_idx = q_idx % cpsw->tx_ch_num;
1732 txch = cpsw->txv[q_idx].ch;
1733 txq = netdev_get_tx_queue(ndev, q_idx);
1734 ret = cpsw_tx_packet_submit(priv, skb, txch);
1735 if (unlikely(ret != 0)) {
1736 cpsw_err(priv, tx_err, "desc submit failed\n");
1740 /* If there is no more tx desc left free then we need to
1741 * tell the kernel to stop sending us tx frames.
1743 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1744 netif_tx_stop_queue(txq);
1746 /* Barrier, so that stop_queue visible to other cpus */
1747 smp_mb__after_atomic();
1749 if (cpdma_check_free_tx_desc(txch))
1750 netif_tx_wake_queue(txq);
1753 return NETDEV_TX_OK;
1755 ndev->stats.tx_dropped++;
1756 netif_tx_stop_queue(txq);
1758 /* Barrier, so that stop_queue visible to other cpus */
1759 smp_mb__after_atomic();
1761 if (cpdma_check_free_tx_desc(txch))
1762 netif_tx_wake_queue(txq);
1764 return NETDEV_TX_BUSY;
1767 #if IS_ENABLED(CONFIG_TI_CPTS)
1769 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1771 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1774 if (!cpts_is_tx_enabled(cpsw->cpts) &&
1775 !cpts_is_rx_enabled(cpsw->cpts)) {
1776 slave_write(slave, 0, CPSW1_TS_CTL);
1780 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1781 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1783 if (cpts_is_tx_enabled(cpsw->cpts))
1784 ts_en |= CPSW_V1_TS_TX_EN;
1786 if (cpts_is_rx_enabled(cpsw->cpts))
1787 ts_en |= CPSW_V1_TS_RX_EN;
1789 slave_write(slave, ts_en, CPSW1_TS_CTL);
1790 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1793 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1795 struct cpsw_slave *slave;
1796 struct cpsw_common *cpsw = priv->cpsw;
1799 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1801 ctrl = slave_read(slave, CPSW2_CONTROL);
1802 switch (cpsw->version) {
1803 case CPSW_VERSION_2:
1804 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1806 if (cpts_is_tx_enabled(cpsw->cpts))
1807 ctrl |= CTRL_V2_TX_TS_BITS;
1809 if (cpts_is_rx_enabled(cpsw->cpts))
1810 ctrl |= CTRL_V2_RX_TS_BITS;
1812 case CPSW_VERSION_3:
1814 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1816 if (cpts_is_tx_enabled(cpsw->cpts))
1817 ctrl |= CTRL_V3_TX_TS_BITS;
1819 if (cpts_is_rx_enabled(cpsw->cpts))
1820 ctrl |= CTRL_V3_RX_TS_BITS;
1824 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1826 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1827 slave_write(slave, ctrl, CPSW2_CONTROL);
1828 writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
1831 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1833 struct cpsw_priv *priv = netdev_priv(dev);
1834 struct hwtstamp_config cfg;
1835 struct cpsw_common *cpsw = priv->cpsw;
1836 struct cpts *cpts = cpsw->cpts;
1838 if (cpsw->version != CPSW_VERSION_1 &&
1839 cpsw->version != CPSW_VERSION_2 &&
1840 cpsw->version != CPSW_VERSION_3)
1843 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1846 /* reserved for future extensions */
1850 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1853 switch (cfg.rx_filter) {
1854 case HWTSTAMP_FILTER_NONE:
1855 cpts_rx_enable(cpts, 0);
1857 case HWTSTAMP_FILTER_ALL:
1858 case HWTSTAMP_FILTER_NTP_ALL:
1860 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1861 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1862 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1863 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1864 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1866 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1867 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1868 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1869 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1870 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1871 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1872 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1873 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1874 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1875 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1876 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1882 cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1884 switch (cpsw->version) {
1885 case CPSW_VERSION_1:
1886 cpsw_hwtstamp_v1(cpsw);
1888 case CPSW_VERSION_2:
1889 case CPSW_VERSION_3:
1890 cpsw_hwtstamp_v2(priv);
1896 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1899 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1901 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1902 struct cpts *cpts = cpsw->cpts;
1903 struct hwtstamp_config cfg;
1905 if (cpsw->version != CPSW_VERSION_1 &&
1906 cpsw->version != CPSW_VERSION_2 &&
1907 cpsw->version != CPSW_VERSION_3)
1911 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1912 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1913 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1914 cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1916 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1919 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1924 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1928 #endif /*CONFIG_TI_CPTS*/
1930 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1932 struct cpsw_priv *priv = netdev_priv(dev);
1933 struct cpsw_common *cpsw = priv->cpsw;
1934 int slave_no = cpsw_slave_index(cpsw, priv);
1936 if (!netif_running(dev))
1941 return cpsw_hwtstamp_set(dev, req);
1943 return cpsw_hwtstamp_get(dev, req);
1946 if (!cpsw->slaves[slave_no].phy)
1948 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1951 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1953 struct cpsw_priv *priv = netdev_priv(ndev);
1954 struct cpsw_common *cpsw = priv->cpsw;
1957 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1958 ndev->stats.tx_errors++;
1959 cpsw_intr_disable(cpsw);
1960 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1961 cpdma_chan_stop(cpsw->txv[ch].ch);
1962 cpdma_chan_start(cpsw->txv[ch].ch);
1965 cpsw_intr_enable(cpsw);
1966 netif_trans_update(ndev);
1967 netif_tx_wake_all_queues(ndev);
1970 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1972 struct cpsw_priv *priv = netdev_priv(ndev);
1973 struct sockaddr *addr = (struct sockaddr *)p;
1974 struct cpsw_common *cpsw = priv->cpsw;
1979 if (!is_valid_ether_addr(addr->sa_data))
1980 return -EADDRNOTAVAIL;
1982 ret = pm_runtime_get_sync(cpsw->dev);
1984 pm_runtime_put_noidle(cpsw->dev);
1988 if (cpsw->data.dual_emac) {
1989 vid = cpsw->slaves[priv->emac_port].port_vlan;
1993 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1995 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1998 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1999 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2000 for_each_slave(priv, cpsw_set_slave_mac, priv);
2002 pm_runtime_put(cpsw->dev);
2007 #ifdef CONFIG_NET_POLL_CONTROLLER
2008 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2010 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2012 cpsw_intr_disable(cpsw);
2013 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2014 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2015 cpsw_intr_enable(cpsw);
2019 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2023 int unreg_mcast_mask = 0;
2025 struct cpsw_common *cpsw = priv->cpsw;
2027 if (cpsw->data.dual_emac) {
2028 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2030 if (priv->ndev->flags & IFF_ALLMULTI)
2031 unreg_mcast_mask = port_mask;
2033 port_mask = ALE_ALL_PORTS;
2035 if (priv->ndev->flags & IFF_ALLMULTI)
2036 unreg_mcast_mask = ALE_ALL_PORTS;
2038 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2041 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2046 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2047 HOST_PORT_NUM, ALE_VLAN, vid);
2051 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2052 port_mask, ALE_VLAN, vid, 0);
2054 goto clean_vlan_ucast;
2058 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2059 HOST_PORT_NUM, ALE_VLAN, vid);
2061 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2065 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2066 __be16 proto, u16 vid)
2068 struct cpsw_priv *priv = netdev_priv(ndev);
2069 struct cpsw_common *cpsw = priv->cpsw;
2072 if (vid == cpsw->data.default_vlan)
2075 ret = pm_runtime_get_sync(cpsw->dev);
2077 pm_runtime_put_noidle(cpsw->dev);
2081 if (cpsw->data.dual_emac) {
2082 /* In dual EMAC, reserved VLAN id should not be used for
2083 * creating VLAN interfaces as this can break the dual
2084 * EMAC port separation
2088 for (i = 0; i < cpsw->data.slaves; i++) {
2089 if (vid == cpsw->slaves[i].port_vlan)
2094 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2095 ret = cpsw_add_vlan_ale_entry(priv, vid);
2097 pm_runtime_put(cpsw->dev);
2101 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2102 __be16 proto, u16 vid)
2104 struct cpsw_priv *priv = netdev_priv(ndev);
2105 struct cpsw_common *cpsw = priv->cpsw;
2108 if (vid == cpsw->data.default_vlan)
2111 ret = pm_runtime_get_sync(cpsw->dev);
2113 pm_runtime_put_noidle(cpsw->dev);
2117 if (cpsw->data.dual_emac) {
2120 for (i = 0; i < cpsw->data.slaves; i++) {
2121 if (vid == cpsw->slaves[i].port_vlan)
2126 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2127 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2131 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2132 HOST_PORT_NUM, ALE_VLAN, vid);
2136 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2138 pm_runtime_put(cpsw->dev);
2142 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2144 struct cpsw_priv *priv = netdev_priv(ndev);
2145 struct cpsw_common *cpsw = priv->cpsw;
2146 struct cpsw_slave *slave;
2151 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2152 if (ch_rate == rate)
2155 ch_rate = rate * 1000;
2156 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2157 if ((ch_rate < min_rate && ch_rate)) {
2158 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2163 if (rate > cpsw->speed) {
2164 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2168 ret = pm_runtime_get_sync(cpsw->dev);
2170 pm_runtime_put_noidle(cpsw->dev);
2174 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2175 pm_runtime_put(cpsw->dev);
2180 /* update rates for slaves tx queues */
2181 for (i = 0; i < cpsw->data.slaves; i++) {
2182 slave = &cpsw->slaves[i];
2186 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2189 cpsw_split_res(ndev);
2193 static const struct net_device_ops cpsw_netdev_ops = {
2194 .ndo_open = cpsw_ndo_open,
2195 .ndo_stop = cpsw_ndo_stop,
2196 .ndo_start_xmit = cpsw_ndo_start_xmit,
2197 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2198 .ndo_do_ioctl = cpsw_ndo_ioctl,
2199 .ndo_validate_addr = eth_validate_addr,
2200 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
2201 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
2202 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
2203 #ifdef CONFIG_NET_POLL_CONTROLLER
2204 .ndo_poll_controller = cpsw_ndo_poll_controller,
2206 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2207 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
2210 static int cpsw_get_regs_len(struct net_device *ndev)
2212 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2214 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2217 static void cpsw_get_regs(struct net_device *ndev,
2218 struct ethtool_regs *regs, void *p)
2221 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2223 /* update CPSW IP version */
2224 regs->version = cpsw->version;
2226 cpsw_ale_dump(cpsw->ale, reg);
2229 static void cpsw_get_drvinfo(struct net_device *ndev,
2230 struct ethtool_drvinfo *info)
2232 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2233 struct platform_device *pdev = to_platform_device(cpsw->dev);
2235 strlcpy(info->driver, "cpsw", sizeof(info->driver));
2236 strlcpy(info->version, "1.0", sizeof(info->version));
2237 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2240 static u32 cpsw_get_msglevel(struct net_device *ndev)
2242 struct cpsw_priv *priv = netdev_priv(ndev);
2243 return priv->msg_enable;
2246 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2248 struct cpsw_priv *priv = netdev_priv(ndev);
2249 priv->msg_enable = value;
2252 #if IS_ENABLED(CONFIG_TI_CPTS)
2253 static int cpsw_get_ts_info(struct net_device *ndev,
2254 struct ethtool_ts_info *info)
2256 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2258 info->so_timestamping =
2259 SOF_TIMESTAMPING_TX_HARDWARE |
2260 SOF_TIMESTAMPING_TX_SOFTWARE |
2261 SOF_TIMESTAMPING_RX_HARDWARE |
2262 SOF_TIMESTAMPING_RX_SOFTWARE |
2263 SOF_TIMESTAMPING_SOFTWARE |
2264 SOF_TIMESTAMPING_RAW_HARDWARE;
2265 info->phc_index = cpsw->cpts->phc_index;
2267 (1 << HWTSTAMP_TX_OFF) |
2268 (1 << HWTSTAMP_TX_ON);
2270 (1 << HWTSTAMP_FILTER_NONE) |
2271 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2272 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2276 static int cpsw_get_ts_info(struct net_device *ndev,
2277 struct ethtool_ts_info *info)
2279 info->so_timestamping =
2280 SOF_TIMESTAMPING_TX_SOFTWARE |
2281 SOF_TIMESTAMPING_RX_SOFTWARE |
2282 SOF_TIMESTAMPING_SOFTWARE;
2283 info->phc_index = -1;
2285 info->rx_filters = 0;
2290 static int cpsw_get_link_ksettings(struct net_device *ndev,
2291 struct ethtool_link_ksettings *ecmd)
2293 struct cpsw_priv *priv = netdev_priv(ndev);
2294 struct cpsw_common *cpsw = priv->cpsw;
2295 int slave_no = cpsw_slave_index(cpsw, priv);
2297 if (!cpsw->slaves[slave_no].phy)
2300 phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2304 static int cpsw_set_link_ksettings(struct net_device *ndev,
2305 const struct ethtool_link_ksettings *ecmd)
2307 struct cpsw_priv *priv = netdev_priv(ndev);
2308 struct cpsw_common *cpsw = priv->cpsw;
2309 int slave_no = cpsw_slave_index(cpsw, priv);
2311 if (cpsw->slaves[slave_no].phy)
2312 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2318 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2320 struct cpsw_priv *priv = netdev_priv(ndev);
2321 struct cpsw_common *cpsw = priv->cpsw;
2322 int slave_no = cpsw_slave_index(cpsw, priv);
2327 if (cpsw->slaves[slave_no].phy)
2328 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2331 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2333 struct cpsw_priv *priv = netdev_priv(ndev);
2334 struct cpsw_common *cpsw = priv->cpsw;
2335 int slave_no = cpsw_slave_index(cpsw, priv);
2337 if (cpsw->slaves[slave_no].phy)
2338 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2343 static void cpsw_get_pauseparam(struct net_device *ndev,
2344 struct ethtool_pauseparam *pause)
2346 struct cpsw_priv *priv = netdev_priv(ndev);
2348 pause->autoneg = AUTONEG_DISABLE;
2349 pause->rx_pause = priv->rx_pause ? true : false;
2350 pause->tx_pause = priv->tx_pause ? true : false;
2353 static int cpsw_set_pauseparam(struct net_device *ndev,
2354 struct ethtool_pauseparam *pause)
2356 struct cpsw_priv *priv = netdev_priv(ndev);
2359 priv->rx_pause = pause->rx_pause ? true : false;
2360 priv->tx_pause = pause->tx_pause ? true : false;
2362 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2366 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2368 struct cpsw_priv *priv = netdev_priv(ndev);
2369 struct cpsw_common *cpsw = priv->cpsw;
2372 ret = pm_runtime_get_sync(cpsw->dev);
2374 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2375 pm_runtime_put_noidle(cpsw->dev);
2381 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2383 struct cpsw_priv *priv = netdev_priv(ndev);
2386 ret = pm_runtime_put(priv->cpsw->dev);
2388 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2391 static void cpsw_get_channels(struct net_device *ndev,
2392 struct ethtool_channels *ch)
2394 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2396 ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2397 ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2398 ch->max_combined = 0;
2400 ch->other_count = 0;
2401 ch->rx_count = cpsw->rx_ch_num;
2402 ch->tx_count = cpsw->tx_ch_num;
2403 ch->combined_count = 0;
2406 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2407 struct ethtool_channels *ch)
2409 if (cpsw->quirk_irq) {
2410 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2414 if (ch->combined_count)
2417 /* verify we have at least one channel in each direction */
2418 if (!ch->rx_count || !ch->tx_count)
2421 if (ch->rx_count > cpsw->data.channels ||
2422 ch->tx_count > cpsw->data.channels)
2428 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2430 struct cpsw_common *cpsw = priv->cpsw;
2431 void (*handler)(void *, int, int);
2432 struct netdev_queue *queue;
2433 struct cpsw_vector *vec;
2437 ch = &cpsw->rx_ch_num;
2439 handler = cpsw_rx_handler;
2441 ch = &cpsw->tx_ch_num;
2443 handler = cpsw_tx_handler;
2446 while (*ch < ch_num) {
2447 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2448 queue = netdev_get_tx_queue(priv->ndev, *ch);
2449 queue->tx_maxrate = 0;
2451 if (IS_ERR(vec[*ch].ch))
2452 return PTR_ERR(vec[*ch].ch);
2457 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2458 (rx ? "rx" : "tx"));
2462 while (*ch > ch_num) {
2465 ret = cpdma_chan_destroy(vec[*ch].ch);
2469 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2470 (rx ? "rx" : "tx"));
2476 static int cpsw_update_channels(struct cpsw_priv *priv,
2477 struct ethtool_channels *ch)
2481 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2485 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2492 static void cpsw_suspend_data_pass(struct net_device *ndev)
2494 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2495 struct cpsw_slave *slave;
2498 /* Disable NAPI scheduling */
2499 cpsw_intr_disable(cpsw);
2501 /* Stop all transmit queues for every network device.
2502 * Disable re-using rx descriptors with dormant_on.
2504 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2505 if (!(slave->ndev && netif_running(slave->ndev)))
2508 netif_tx_stop_all_queues(slave->ndev);
2509 netif_dormant_on(slave->ndev);
2512 /* Handle rest of tx packets and stop cpdma channels */
2513 cpdma_ctlr_stop(cpsw->dma);
2516 static int cpsw_resume_data_pass(struct net_device *ndev)
2518 struct cpsw_priv *priv = netdev_priv(ndev);
2519 struct cpsw_common *cpsw = priv->cpsw;
2520 struct cpsw_slave *slave;
2523 /* Allow rx packets handling */
2524 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2525 if (slave->ndev && netif_running(slave->ndev))
2526 netif_dormant_off(slave->ndev);
2528 /* After this receive is started */
2529 if (cpsw->usage_count) {
2530 ret = cpsw_fill_rx_channels(priv);
2534 cpdma_ctlr_start(cpsw->dma);
2535 cpsw_intr_enable(cpsw);
2538 /* Resume transmit for every affected interface */
2539 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2540 if (slave->ndev && netif_running(slave->ndev))
2541 netif_tx_start_all_queues(slave->ndev);
2546 static int cpsw_set_channels(struct net_device *ndev,
2547 struct ethtool_channels *chs)
2549 struct cpsw_priv *priv = netdev_priv(ndev);
2550 struct cpsw_common *cpsw = priv->cpsw;
2551 struct cpsw_slave *slave;
2554 ret = cpsw_check_ch_settings(cpsw, chs);
2558 cpsw_suspend_data_pass(ndev);
2559 ret = cpsw_update_channels(priv, chs);
2563 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2564 if (!(slave->ndev && netif_running(slave->ndev)))
2567 /* Inform stack about new count of queues */
2568 ret = netif_set_real_num_tx_queues(slave->ndev,
2571 dev_err(priv->dev, "cannot set real number of tx queues\n");
2575 ret = netif_set_real_num_rx_queues(slave->ndev,
2578 dev_err(priv->dev, "cannot set real number of rx queues\n");
2583 if (cpsw->usage_count)
2584 cpsw_split_res(ndev);
2586 ret = cpsw_resume_data_pass(ndev);
2590 dev_err(priv->dev, "cannot update channels number, closing device\n");
2595 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2597 struct cpsw_priv *priv = netdev_priv(ndev);
2598 struct cpsw_common *cpsw = priv->cpsw;
2599 int slave_no = cpsw_slave_index(cpsw, priv);
2601 if (cpsw->slaves[slave_no].phy)
2602 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2607 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2609 struct cpsw_priv *priv = netdev_priv(ndev);
2610 struct cpsw_common *cpsw = priv->cpsw;
2611 int slave_no = cpsw_slave_index(cpsw, priv);
2613 if (cpsw->slaves[slave_no].phy)
2614 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2619 static int cpsw_nway_reset(struct net_device *ndev)
2621 struct cpsw_priv *priv = netdev_priv(ndev);
2622 struct cpsw_common *cpsw = priv->cpsw;
2623 int slave_no = cpsw_slave_index(cpsw, priv);
2625 if (cpsw->slaves[slave_no].phy)
2626 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2631 static void cpsw_get_ringparam(struct net_device *ndev,
2632 struct ethtool_ringparam *ering)
2634 struct cpsw_priv *priv = netdev_priv(ndev);
2635 struct cpsw_common *cpsw = priv->cpsw;
2638 ering->tx_max_pending = 0;
2639 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2640 ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2641 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2644 static int cpsw_set_ringparam(struct net_device *ndev,
2645 struct ethtool_ringparam *ering)
2647 struct cpsw_priv *priv = netdev_priv(ndev);
2648 struct cpsw_common *cpsw = priv->cpsw;
2651 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2653 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2654 ering->rx_pending < CPSW_MAX_QUEUES ||
2655 ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2658 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2661 cpsw_suspend_data_pass(ndev);
2663 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2665 if (cpsw->usage_count)
2666 cpdma_chan_split_pool(cpsw->dma);
2668 ret = cpsw_resume_data_pass(ndev);
2672 dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2677 static const struct ethtool_ops cpsw_ethtool_ops = {
2678 .get_drvinfo = cpsw_get_drvinfo,
2679 .get_msglevel = cpsw_get_msglevel,
2680 .set_msglevel = cpsw_set_msglevel,
2681 .get_link = ethtool_op_get_link,
2682 .get_ts_info = cpsw_get_ts_info,
2683 .get_coalesce = cpsw_get_coalesce,
2684 .set_coalesce = cpsw_set_coalesce,
2685 .get_sset_count = cpsw_get_sset_count,
2686 .get_strings = cpsw_get_strings,
2687 .get_ethtool_stats = cpsw_get_ethtool_stats,
2688 .get_pauseparam = cpsw_get_pauseparam,
2689 .set_pauseparam = cpsw_set_pauseparam,
2690 .get_wol = cpsw_get_wol,
2691 .set_wol = cpsw_set_wol,
2692 .get_regs_len = cpsw_get_regs_len,
2693 .get_regs = cpsw_get_regs,
2694 .begin = cpsw_ethtool_op_begin,
2695 .complete = cpsw_ethtool_op_complete,
2696 .get_channels = cpsw_get_channels,
2697 .set_channels = cpsw_set_channels,
2698 .get_link_ksettings = cpsw_get_link_ksettings,
2699 .set_link_ksettings = cpsw_set_link_ksettings,
2700 .get_eee = cpsw_get_eee,
2701 .set_eee = cpsw_set_eee,
2702 .nway_reset = cpsw_nway_reset,
2703 .get_ringparam = cpsw_get_ringparam,
2704 .set_ringparam = cpsw_set_ringparam,
2707 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2708 u32 slave_reg_ofs, u32 sliver_reg_ofs)
2710 void __iomem *regs = cpsw->regs;
2711 int slave_num = slave->slave_num;
2712 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
2715 slave->regs = regs + slave_reg_ofs;
2716 slave->sliver = regs + sliver_reg_ofs;
2717 slave->port_vlan = data->dual_emac_res_vlan;
2720 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2721 struct platform_device *pdev)
2723 struct device_node *node = pdev->dev.of_node;
2724 struct device_node *slave_node;
2731 if (of_property_read_u32(node, "slaves", &prop)) {
2732 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2735 data->slaves = prop;
2737 if (of_property_read_u32(node, "active_slave", &prop)) {
2738 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2741 data->active_slave = prop;
2743 data->slave_data = devm_kcalloc(&pdev->dev,
2745 sizeof(struct cpsw_slave_data),
2747 if (!data->slave_data)
2750 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2751 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2754 data->channels = prop;
2756 if (of_property_read_u32(node, "ale_entries", &prop)) {
2757 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2760 data->ale_entries = prop;
2762 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2763 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2766 data->bd_ram_size = prop;
2768 if (of_property_read_u32(node, "mac_control", &prop)) {
2769 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2772 data->mac_control = prop;
2774 if (of_property_read_bool(node, "dual_emac"))
2775 data->dual_emac = 1;
2778 * Populate all the child nodes here...
2780 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2781 /* We do not want to force this, as in some cases may not have child */
2783 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2785 for_each_available_child_of_node(node, slave_node) {
2786 struct cpsw_slave_data *slave_data = data->slave_data + i;
2787 const void *mac_addr = NULL;
2791 /* This is no slave child node, continue */
2792 if (strcmp(slave_node->name, "slave"))
2795 slave_data->phy_node = of_parse_phandle(slave_node,
2797 parp = of_get_property(slave_node, "phy_id", &lenp);
2798 if (slave_data->phy_node) {
2800 "slave[%d] using phy-handle=\"%pOF\"\n",
2801 i, slave_data->phy_node);
2802 } else if (of_phy_is_fixed_link(slave_node)) {
2803 /* In the case of a fixed PHY, the DT node associated
2804 * to the PHY is the Ethernet MAC DT node.
2806 ret = of_phy_register_fixed_link(slave_node);
2808 if (ret != -EPROBE_DEFER)
2809 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2812 slave_data->phy_node = of_node_get(slave_node);
2815 struct device_node *mdio_node;
2816 struct platform_device *mdio;
2818 if (lenp != (sizeof(__be32) * 2)) {
2819 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2822 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2823 phyid = be32_to_cpup(parp+1);
2824 mdio = of_find_device_by_node(mdio_node);
2825 of_node_put(mdio_node);
2827 dev_err(&pdev->dev, "Missing mdio platform device\n");
2830 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2831 PHY_ID_FMT, mdio->name, phyid);
2832 put_device(&mdio->dev);
2835 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2839 slave_data->phy_if = of_get_phy_mode(slave_node);
2840 if (slave_data->phy_if < 0) {
2841 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2843 return slave_data->phy_if;
2847 mac_addr = of_get_mac_address(slave_node);
2849 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2851 ret = ti_cm_get_macid(&pdev->dev, i,
2852 slave_data->mac_addr);
2856 if (data->dual_emac) {
2857 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2859 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2860 slave_data->dual_emac_res_vlan = i+1;
2861 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2862 slave_data->dual_emac_res_vlan, i);
2864 slave_data->dual_emac_res_vlan = prop;
2869 if (i == data->slaves)
2876 static void cpsw_remove_dt(struct platform_device *pdev)
2878 struct net_device *ndev = platform_get_drvdata(pdev);
2879 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2880 struct cpsw_platform_data *data = &cpsw->data;
2881 struct device_node *node = pdev->dev.of_node;
2882 struct device_node *slave_node;
2885 for_each_available_child_of_node(node, slave_node) {
2886 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2888 if (strcmp(slave_node->name, "slave"))
2891 if (of_phy_is_fixed_link(slave_node))
2892 of_phy_deregister_fixed_link(slave_node);
2894 of_node_put(slave_data->phy_node);
2897 if (i == data->slaves)
2901 of_platform_depopulate(&pdev->dev);
2904 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2906 struct cpsw_common *cpsw = priv->cpsw;
2907 struct cpsw_platform_data *data = &cpsw->data;
2908 struct net_device *ndev;
2909 struct cpsw_priv *priv_sl2;
2912 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2914 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2918 priv_sl2 = netdev_priv(ndev);
2919 priv_sl2->cpsw = cpsw;
2920 priv_sl2->ndev = ndev;
2921 priv_sl2->dev = &ndev->dev;
2922 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2924 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2925 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2927 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2928 priv_sl2->mac_addr);
2930 random_ether_addr(priv_sl2->mac_addr);
2931 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2932 priv_sl2->mac_addr);
2934 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2936 priv_sl2->emac_port = 1;
2937 cpsw->slaves[1].ndev = ndev;
2938 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2940 ndev->netdev_ops = &cpsw_netdev_ops;
2941 ndev->ethtool_ops = &cpsw_ethtool_ops;
2943 /* register the network device */
2944 SET_NETDEV_DEV(ndev, cpsw->dev);
2945 ret = register_netdev(ndev);
2947 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2955 static const struct of_device_id cpsw_of_mtable[] = {
2956 { .compatible = "ti,cpsw"},
2957 { .compatible = "ti,am335x-cpsw"},
2958 { .compatible = "ti,am4372-cpsw"},
2959 { .compatible = "ti,dra7-cpsw"},
2962 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2964 static const struct soc_device_attribute cpsw_soc_devices[] = {
2965 { .family = "AM33xx", .revision = "ES1.0"},
2969 static int cpsw_probe(struct platform_device *pdev)
2972 struct cpsw_platform_data *data;
2973 struct net_device *ndev;
2974 struct cpsw_priv *priv;
2975 struct cpdma_params dma_params;
2976 struct cpsw_ale_params ale_params;
2977 void __iomem *ss_regs;
2978 void __iomem *cpts_regs;
2979 struct resource *res, *ss_res;
2980 struct gpio_descs *mode;
2981 u32 slave_offset, sliver_offset, slave_size;
2982 const struct soc_device_attribute *soc;
2983 struct cpsw_common *cpsw;
2987 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2991 cpsw->dev = &pdev->dev;
2993 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2995 dev_err(&pdev->dev, "error allocating net_device\n");
2999 platform_set_drvdata(pdev, ndev);
3000 priv = netdev_priv(ndev);
3003 priv->dev = &ndev->dev;
3004 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3005 cpsw->rx_packet_max = max(rx_packet_max, 128);
3007 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
3009 ret = PTR_ERR(mode);
3010 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
3011 goto clean_ndev_ret;
3015 * This may be required here for child devices.
3017 pm_runtime_enable(&pdev->dev);
3019 /* Select default pin state */
3020 pinctrl_pm_select_default_state(&pdev->dev);
3022 /* Need to enable clocks with runtime PM api to access module
3025 ret = pm_runtime_get_sync(&pdev->dev);
3027 pm_runtime_put_noidle(&pdev->dev);
3028 goto clean_runtime_disable_ret;
3031 ret = cpsw_probe_dt(&cpsw->data, pdev);
3036 cpsw->rx_ch_num = 1;
3037 cpsw->tx_ch_num = 1;
3039 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3040 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3041 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
3043 eth_random_addr(priv->mac_addr);
3044 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
3047 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
3049 cpsw->slaves = devm_kcalloc(&pdev->dev,
3050 data->slaves, sizeof(struct cpsw_slave),
3052 if (!cpsw->slaves) {
3056 for (i = 0; i < data->slaves; i++)
3057 cpsw->slaves[i].slave_num = i;
3059 cpsw->slaves[0].ndev = ndev;
3060 priv->emac_port = 0;
3062 clk = devm_clk_get(&pdev->dev, "fck");
3064 dev_err(priv->dev, "fck is not found\n");
3068 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
3070 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3071 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
3072 if (IS_ERR(ss_regs)) {
3073 ret = PTR_ERR(ss_regs);
3076 cpsw->regs = ss_regs;
3078 cpsw->version = readl(&cpsw->regs->id_ver);
3080 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3081 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3082 if (IS_ERR(cpsw->wr_regs)) {
3083 ret = PTR_ERR(cpsw->wr_regs);
3087 memset(&dma_params, 0, sizeof(dma_params));
3088 memset(&ale_params, 0, sizeof(ale_params));
3090 switch (cpsw->version) {
3091 case CPSW_VERSION_1:
3092 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3093 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
3094 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
3095 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
3096 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
3097 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
3098 slave_offset = CPSW1_SLAVE_OFFSET;
3099 slave_size = CPSW1_SLAVE_SIZE;
3100 sliver_offset = CPSW1_SLIVER_OFFSET;
3101 dma_params.desc_mem_phys = 0;
3103 case CPSW_VERSION_2:
3104 case CPSW_VERSION_3:
3105 case CPSW_VERSION_4:
3106 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3107 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
3108 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
3109 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
3110 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
3111 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
3112 slave_offset = CPSW2_SLAVE_OFFSET;
3113 slave_size = CPSW2_SLAVE_SIZE;
3114 sliver_offset = CPSW2_SLIVER_OFFSET;
3115 dma_params.desc_mem_phys =
3116 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3119 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3123 for (i = 0; i < cpsw->data.slaves; i++) {
3124 struct cpsw_slave *slave = &cpsw->slaves[i];
3126 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3127 slave_offset += slave_size;
3128 sliver_offset += SLIVER_SIZE;
3131 dma_params.dev = &pdev->dev;
3132 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
3133 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
3134 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
3135 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
3136 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
3138 dma_params.num_chan = data->channels;
3139 dma_params.has_soft_reset = true;
3140 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
3141 dma_params.desc_mem_size = data->bd_ram_size;
3142 dma_params.desc_align = 16;
3143 dma_params.has_ext_regs = true;
3144 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
3145 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
3146 dma_params.descs_pool_size = descs_pool_size;
3148 cpsw->dma = cpdma_ctlr_create(&dma_params);
3150 dev_err(priv->dev, "error initializing dma\n");
3155 soc = soc_device_match(cpsw_soc_devices);
3157 cpsw->quirk_irq = 1;
3159 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3160 if (IS_ERR(cpsw->txv[0].ch)) {
3161 dev_err(priv->dev, "error initializing tx dma channel\n");
3162 ret = PTR_ERR(cpsw->txv[0].ch);
3166 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3167 if (IS_ERR(cpsw->rxv[0].ch)) {
3168 dev_err(priv->dev, "error initializing rx dma channel\n");
3169 ret = PTR_ERR(cpsw->rxv[0].ch);
3173 ale_params.dev = &pdev->dev;
3174 ale_params.ale_ageout = ale_ageout;
3175 ale_params.ale_entries = data->ale_entries;
3176 ale_params.ale_ports = CPSW_ALE_PORTS_NUM;
3178 cpsw->ale = cpsw_ale_create(&ale_params);
3180 dev_err(priv->dev, "error initializing ale engine\n");
3185 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3186 if (IS_ERR(cpsw->cpts)) {
3187 ret = PTR_ERR(cpsw->cpts);
3191 ndev->irq = platform_get_irq(pdev, 1);
3192 if (ndev->irq < 0) {
3193 dev_err(priv->dev, "error getting irq resource\n");
3198 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3200 ndev->netdev_ops = &cpsw_netdev_ops;
3201 ndev->ethtool_ops = &cpsw_ethtool_ops;
3202 netif_napi_add(ndev, &cpsw->napi_rx,
3203 cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll,
3205 netif_tx_napi_add(ndev, &cpsw->napi_tx,
3206 cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll,
3208 cpsw_split_res(ndev);
3210 /* register the network device */
3211 SET_NETDEV_DEV(ndev, &pdev->dev);
3212 ret = register_netdev(ndev);
3214 dev_err(priv->dev, "error registering net device\n");
3219 if (cpsw->data.dual_emac) {
3220 ret = cpsw_probe_dual_emac(priv);
3222 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3223 goto clean_unregister_netdev_ret;
3227 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3228 * MISC IRQs which are always kept disabled with this driver so
3229 * we will not request them.
3231 * If anyone wants to implement support for those, make sure to
3232 * first request and append them to irqs_table array.
3236 irq = platform_get_irq(pdev, 1);
3242 cpsw->irqs_table[0] = irq;
3243 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3244 0, dev_name(&pdev->dev), cpsw);
3246 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3251 irq = platform_get_irq(pdev, 2);
3257 cpsw->irqs_table[1] = irq;
3258 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3259 0, dev_name(&pdev->dev), cpsw);
3261 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3265 cpsw_notice(priv, probe,
3266 "initialized device (regs %pa, irq %d, pool size %d)\n",
3267 &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3269 pm_runtime_put(&pdev->dev);
3273 clean_unregister_netdev_ret:
3274 unregister_netdev(ndev);
3276 cpdma_ctlr_destroy(cpsw->dma);
3278 cpsw_remove_dt(pdev);
3279 pm_runtime_put_sync(&pdev->dev);
3280 clean_runtime_disable_ret:
3281 pm_runtime_disable(&pdev->dev);
3283 free_netdev(priv->ndev);
3287 static int cpsw_remove(struct platform_device *pdev)
3289 struct net_device *ndev = platform_get_drvdata(pdev);
3290 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3293 ret = pm_runtime_get_sync(&pdev->dev);
3295 pm_runtime_put_noidle(&pdev->dev);
3299 if (cpsw->data.dual_emac)
3300 unregister_netdev(cpsw->slaves[1].ndev);
3301 unregister_netdev(ndev);
3303 cpts_release(cpsw->cpts);
3304 cpdma_ctlr_destroy(cpsw->dma);
3305 cpsw_remove_dt(pdev);
3306 pm_runtime_put_sync(&pdev->dev);
3307 pm_runtime_disable(&pdev->dev);
3308 if (cpsw->data.dual_emac)
3309 free_netdev(cpsw->slaves[1].ndev);
3314 #ifdef CONFIG_PM_SLEEP
3315 static int cpsw_suspend(struct device *dev)
3317 struct platform_device *pdev = to_platform_device(dev);
3318 struct net_device *ndev = platform_get_drvdata(pdev);
3319 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3321 if (cpsw->data.dual_emac) {
3324 for (i = 0; i < cpsw->data.slaves; i++) {
3325 if (netif_running(cpsw->slaves[i].ndev))
3326 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3329 if (netif_running(ndev))
3330 cpsw_ndo_stop(ndev);
3333 /* Select sleep pin state */
3334 pinctrl_pm_select_sleep_state(dev);
3339 static int cpsw_resume(struct device *dev)
3341 struct platform_device *pdev = to_platform_device(dev);
3342 struct net_device *ndev = platform_get_drvdata(pdev);
3343 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3345 /* Select default pin state */
3346 pinctrl_pm_select_default_state(dev);
3348 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3350 if (cpsw->data.dual_emac) {
3353 for (i = 0; i < cpsw->data.slaves; i++) {
3354 if (netif_running(cpsw->slaves[i].ndev))
3355 cpsw_ndo_open(cpsw->slaves[i].ndev);
3358 if (netif_running(ndev))
3359 cpsw_ndo_open(ndev);
3367 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3369 static struct platform_driver cpsw_driver = {
3373 .of_match_table = cpsw_of_mtable,
3375 .probe = cpsw_probe,
3376 .remove = cpsw_remove,
3379 module_platform_driver(cpsw_driver);
3381 MODULE_LICENSE("GPL");
3382 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3383 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3384 MODULE_DESCRIPTION("TI CPSW Ethernet driver");