1 /* Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
3 * This is a driver for the Synopsys DWC Ethernet QoS IP version 4.10a (GMAC).
4 * This version introduced a lot of changes which breaks backwards
5 * compatibility the non-QoS IP from Synopsys (used in the ST Micro drivers).
6 * Some fields differ between version 4.00a and 4.10a, mainly the interrupt
7 * bit fields. The driver could be made compatible with 4.00, if all relevant
8 * HW erratas are handled.
10 * The GMAC is highly configurable at synthesis time. This driver has been
11 * developed for a subset of the total available feature set. Currently
14 * - Checksum offload for RX and TX.
15 * - Energy efficient ethernet.
16 * - GMII phy interface.
17 * - The statistics module.
18 * - Single RX and TX queue.
20 * Copyright (C) 2015 Axis Communications AB.
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms and conditions of the GNU General Public License,
24 * version 2, as published by the Free Software Foundation.
27 #include <linux/clk.h>
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/init.h>
32 #include <linux/ethtool.h>
33 #include <linux/stat.h>
34 #include <linux/types.h>
36 #include <linux/types.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/platform_device.h>
44 #include <linux/phy.h>
45 #include <linux/mii.h>
46 #include <linux/delay.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/vmalloc.h>
49 #include <linux/version.h>
51 #include <linux/device.h>
52 #include <linux/bitrev.h>
53 #include <linux/crc32.h>
56 #include <linux/interrupt.h>
57 #include <linux/clocksource.h>
58 #include <linux/net_tstamp.h>
59 #include <linux/pm_runtime.h>
60 #include <linux/of_net.h>
61 #include <linux/of_address.h>
62 #include <linux/of_mdio.h>
63 #include <linux/timer.h>
64 #include <linux/tcp.h>
66 #define DRIVER_NAME "dwceqos"
67 #define DRIVER_DESCRIPTION "Synopsys DWC Ethernet QoS driver"
68 #define DRIVER_VERSION "0.9"
70 #define DWCEQOS_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
71 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
73 #define DWCEQOS_TX_TIMEOUT 5 /* Seconds */
75 #define DWCEQOS_LPI_TIMER_MIN 8
76 #define DWCEQOS_LPI_TIMER_MAX ((1 << 20) - 1)
78 #define DWCEQOS_RX_BUF_SIZE 2048
80 #define DWCEQOS_RX_DCNT 256
81 #define DWCEQOS_TX_DCNT 256
83 #define DWCEQOS_HASH_TABLE_SIZE 64
85 /* The size field in the DMA descriptor is 14 bits */
86 #define BYTES_PER_DMA_DESC 16376
88 /* Hardware registers */
89 #define START_MAC_REG_OFFSET 0x0000
90 #define MAX_MAC_REG_OFFSET 0x0bd0
91 #define START_MTL_REG_OFFSET 0x0c00
92 #define MAX_MTL_REG_OFFSET 0x0d7c
93 #define START_DMA_REG_OFFSET 0x1000
94 #define MAX_DMA_REG_OFFSET 0x117C
96 #define REG_SPACE_SIZE 0x1800
99 #define REG_DWCEQOS_DMA_MODE 0x1000
100 #define REG_DWCEQOS_DMA_SYSBUS_MODE 0x1004
101 #define REG_DWCEQOS_DMA_IS 0x1008
102 #define REG_DWCEQOS_DMA_DEBUG_ST0 0x100c
104 /* DMA channel registers */
105 #define REG_DWCEQOS_DMA_CH0_CTRL 0x1100
106 #define REG_DWCEQOS_DMA_CH0_TX_CTRL 0x1104
107 #define REG_DWCEQOS_DMA_CH0_RX_CTRL 0x1108
108 #define REG_DWCEQOS_DMA_CH0_TXDESC_LIST 0x1114
109 #define REG_DWCEQOS_DMA_CH0_RXDESC_LIST 0x111c
110 #define REG_DWCEQOS_DMA_CH0_TXDESC_TAIL 0x1120
111 #define REG_DWCEQOS_DMA_CH0_RXDESC_TAIL 0x1128
112 #define REG_DWCEQOS_DMA_CH0_TXDESC_LEN 0x112c
113 #define REG_DWCEQOS_DMA_CH0_RXDESC_LEN 0x1130
114 #define REG_DWCEQOS_DMA_CH0_IE 0x1134
115 #define REG_DWCEQOS_DMA_CH0_CUR_TXDESC 0x1144
116 #define REG_DWCEQOS_DMA_CH0_CUR_RXDESC 0x114c
117 #define REG_DWCEQOS_DMA_CH0_CUR_TXBUF 0x1154
118 #define REG_DWCEQOS_DMA_CH0_CUR_RXBUG 0x115c
119 #define REG_DWCEQOS_DMA_CH0_STA 0x1160
121 #define DWCEQOS_DMA_MODE_TXPR BIT(11)
122 #define DWCEQOS_DMA_MODE_DA BIT(1)
124 #define DWCEQOS_DMA_SYSBUS_MODE_EN_LPI BIT(31)
125 #define DWCEQOS_DMA_SYSBUS_MODE_FB BIT(0)
126 #define DWCEQOS_DMA_SYSBUS_MODE_AAL BIT(12)
128 #define DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT(x) \
129 (((x) << 16) & 0x000F0000)
130 #define DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT_DEFAULT 3
131 #define DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT_MASK GENMASK(19, 16)
133 #define DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT(x) \
134 (((x) << 24) & 0x0F000000)
135 #define DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT_DEFAULT 3
136 #define DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT_MASK GENMASK(27, 24)
138 #define DWCEQOS_DMA_SYSBUS_MODE_BURST_MASK GENMASK(7, 1)
139 #define DWCEQOS_DMA_SYSBUS_MODE_BURST(x) \
140 (((x) << 1) & DWCEQOS_DMA_SYSBUS_MODE_BURST_MASK)
141 #define DWCEQOS_DMA_SYSBUS_MODE_BURST_DEFAULT GENMASK(3, 1)
143 #define DWCEQOS_DMA_CH_CTRL_PBLX8 BIT(16)
144 #define DWCEQOS_DMA_CH_CTRL_DSL(x) ((x) << 18)
146 #define DWCEQOS_DMA_CH_CTRL_PBL(x) ((x) << 16)
147 #define DWCEQOS_DMA_CH_CTRL_START BIT(0)
148 #define DWCEQOS_DMA_CH_RX_CTRL_BUFSIZE(x) ((x) << 1)
149 #define DWCEQOS_DMA_CH_TX_OSP BIT(4)
150 #define DWCEQOS_DMA_CH_TX_TSE BIT(12)
152 #define DWCEQOS_DMA_CH0_IE_NIE BIT(15)
153 #define DWCEQOS_DMA_CH0_IE_AIE BIT(14)
154 #define DWCEQOS_DMA_CH0_IE_RIE BIT(6)
155 #define DWCEQOS_DMA_CH0_IE_TIE BIT(0)
156 #define DWCEQOS_DMA_CH0_IE_FBEE BIT(12)
157 #define DWCEQOS_DMA_CH0_IE_RBUE BIT(7)
159 #define DWCEQOS_DMA_IS_DC0IS BIT(0)
160 #define DWCEQOS_DMA_IS_MTLIS BIT(16)
161 #define DWCEQOS_DMA_IS_MACIS BIT(17)
163 #define DWCEQOS_DMA_CH0_IS_TI BIT(0)
164 #define DWCEQOS_DMA_CH0_IS_RI BIT(6)
165 #define DWCEQOS_DMA_CH0_IS_RBU BIT(7)
166 #define DWCEQOS_DMA_CH0_IS_FBE BIT(12)
167 #define DWCEQOS_DMA_CH0_IS_CDE BIT(13)
168 #define DWCEQOS_DMA_CH0_IS_AIS BIT(14)
170 #define DWCEQOS_DMA_CH0_IS_TEB GENMASK(18, 16)
171 #define DWCEQOS_DMA_CH0_IS_TX_ERR_READ BIT(16)
172 #define DWCEQOS_DMA_CH0_IS_TX_ERR_DESCR BIT(17)
174 #define DWCEQOS_DMA_CH0_IS_REB GENMASK(21, 19)
175 #define DWCEQOS_DMA_CH0_IS_RX_ERR_READ BIT(19)
176 #define DWCEQOS_DMA_CH0_IS_RX_ERR_DESCR BIT(20)
178 /* DMA descriptor bits for RX normal descriptor (read format) */
179 #define DWCEQOS_DMA_RDES3_OWN BIT(31)
180 #define DWCEQOS_DMA_RDES3_INTE BIT(30)
181 #define DWCEQOS_DMA_RDES3_BUF2V BIT(25)
182 #define DWCEQOS_DMA_RDES3_BUF1V BIT(24)
184 /* DMA descriptor bits for RX normal descriptor (write back format) */
185 #define DWCEQOS_DMA_RDES1_IPCE BIT(7)
186 #define DWCEQOS_DMA_RDES3_ES BIT(15)
187 #define DWCEQOS_DMA_RDES3_E_JT BIT(14)
188 #define DWCEQOS_DMA_RDES3_PL(x) ((x) & 0x7fff)
189 #define DWCEQOS_DMA_RDES1_PT 0x00000007
190 #define DWCEQOS_DMA_RDES1_PT_UDP BIT(0)
191 #define DWCEQOS_DMA_RDES1_PT_TCP BIT(1)
192 #define DWCEQOS_DMA_RDES1_PT_ICMP 0x00000003
194 /* DMA descriptor bits for TX normal descriptor (read format) */
195 #define DWCEQOS_DMA_TDES2_IOC BIT(31)
196 #define DWCEQOS_DMA_TDES3_OWN BIT(31)
197 #define DWCEQOS_DMA_TDES3_CTXT BIT(30)
198 #define DWCEQOS_DMA_TDES3_FD BIT(29)
199 #define DWCEQOS_DMA_TDES3_LD BIT(28)
200 #define DWCEQOS_DMA_TDES3_CIPH BIT(16)
201 #define DWCEQOS_DMA_TDES3_CIPP BIT(17)
202 #define DWCEQOS_DMA_TDES3_CA 0x00030000
203 #define DWCEQOS_DMA_TDES3_TSE BIT(18)
204 #define DWCEQOS_DMA_DES3_THL(x) ((x) << 19)
205 #define DWCEQOS_DMA_DES2_B2L(x) ((x) << 16)
207 #define DWCEQOS_DMA_TDES3_TCMSSV BIT(26)
209 /* DMA channel states */
210 #define DMA_TX_CH_STOPPED 0
211 #define DMA_TX_CH_SUSPENDED 6
213 #define DMA_GET_TX_STATE_CH0(status0) ((status0 & 0xF000) >> 12)
216 #define REG_DWCEQOS_MTL_OPER 0x0c00
217 #define REG_DWCEQOS_MTL_DEBUG_ST 0x0c0c
218 #define REG_DWCEQOS_MTL_TXQ0_DEBUG_ST 0x0d08
219 #define REG_DWCEQOS_MTL_RXQ0_DEBUG_ST 0x0d38
221 #define REG_DWCEQOS_MTL_IS 0x0c20
222 #define REG_DWCEQOS_MTL_TXQ0_OPER 0x0d00
223 #define REG_DWCEQOS_MTL_RXQ0_OPER 0x0d30
224 #define REG_DWCEQOS_MTL_RXQ0_MIS_CNT 0x0d34
225 #define REG_DWCEQOS_MTL_RXQ0_CTRL 0x0d3c
227 #define REG_DWCEQOS_MTL_Q0_ISCTRL 0x0d2c
229 #define DWCEQOS_MTL_SCHALG_STRICT 0x00000060
231 #define DWCEQOS_MTL_TXQ_TXQEN BIT(3)
232 #define DWCEQOS_MTL_TXQ_TSF BIT(1)
233 #define DWCEQOS_MTL_TXQ_FTQ BIT(0)
234 #define DWCEQOS_MTL_TXQ_TTC512 0x00000070
236 #define DWCEQOS_MTL_TXQ_SIZE(x) ((((x) - 256) & 0xff00) << 8)
238 #define DWCEQOS_MTL_RXQ_SIZE(x) ((((x) - 256) & 0xff00) << 12)
239 #define DWCEQOS_MTL_RXQ_EHFC BIT(7)
240 #define DWCEQOS_MTL_RXQ_DIS_TCP_EF BIT(6)
241 #define DWCEQOS_MTL_RXQ_FEP BIT(4)
242 #define DWCEQOS_MTL_RXQ_FUP BIT(3)
243 #define DWCEQOS_MTL_RXQ_RSF BIT(5)
244 #define DWCEQOS_MTL_RXQ_RTC32 BIT(0)
247 #define REG_DWCEQOS_MAC_CFG 0x0000
248 #define REG_DWCEQOS_MAC_EXT_CFG 0x0004
249 #define REG_DWCEQOS_MAC_PKT_FILT 0x0008
250 #define REG_DWCEQOS_MAC_WD_TO 0x000c
251 #define REG_DWCEQOS_HASTABLE_LO 0x0010
252 #define REG_DWCEQOS_HASTABLE_HI 0x0014
253 #define REG_DWCEQOS_MAC_IS 0x00b0
254 #define REG_DWCEQOS_MAC_IE 0x00b4
255 #define REG_DWCEQOS_MAC_STAT 0x00b8
256 #define REG_DWCEQOS_MAC_MDIO_ADDR 0x0200
257 #define REG_DWCEQOS_MAC_MDIO_DATA 0x0204
258 #define REG_DWCEQOS_MAC_MAC_ADDR0_HI 0x0300
259 #define REG_DWCEQOS_MAC_MAC_ADDR0_LO 0x0304
260 #define REG_DWCEQOS_MAC_RXQ0_CTRL0 0x00a0
261 #define REG_DWCEQOS_MAC_HW_FEATURE0 0x011c
262 #define REG_DWCEQOS_MAC_HW_FEATURE1 0x0120
263 #define REG_DWCEQOS_MAC_HW_FEATURE2 0x0124
264 #define REG_DWCEQOS_MAC_HASHTABLE_LO 0x0010
265 #define REG_DWCEQOS_MAC_HASHTABLE_HI 0x0014
266 #define REG_DWCEQOS_MAC_LPI_CTRL_STATUS 0x00d0
267 #define REG_DWCEQOS_MAC_LPI_TIMERS_CTRL 0x00d4
268 #define REG_DWCEQOS_MAC_LPI_ENTRY_TIMER 0x00d8
269 #define REG_DWCEQOS_MAC_1US_TIC_COUNTER 0x00dc
270 #define REG_DWCEQOS_MAC_RX_FLOW_CTRL 0x0090
271 #define REG_DWCEQOS_MAC_Q0_TX_FLOW 0x0070
273 #define DWCEQOS_MAC_CFG_ACS BIT(20)
274 #define DWCEQOS_MAC_CFG_JD BIT(17)
275 #define DWCEQOS_MAC_CFG_JE BIT(16)
276 #define DWCEQOS_MAC_CFG_PS BIT(15)
277 #define DWCEQOS_MAC_CFG_FES BIT(14)
278 #define DWCEQOS_MAC_CFG_DM BIT(13)
279 #define DWCEQOS_MAC_CFG_DO BIT(10)
280 #define DWCEQOS_MAC_CFG_TE BIT(1)
281 #define DWCEQOS_MAC_CFG_IPC BIT(27)
282 #define DWCEQOS_MAC_CFG_RE BIT(0)
284 #define DWCEQOS_ADDR_HIGH(reg) (0x00000300 + (reg * 8))
285 #define DWCEQOS_ADDR_LOW(reg) (0x00000304 + (reg * 8))
287 #define DWCEQOS_MAC_IS_LPI_INT BIT(5)
288 #define DWCEQOS_MAC_IS_MMC_INT BIT(8)
290 #define DWCEQOS_MAC_RXQ_EN BIT(1)
291 #define DWCEQOS_MAC_MAC_ADDR_HI_EN BIT(31)
292 #define DWCEQOS_MAC_PKT_FILT_RA BIT(31)
293 #define DWCEQOS_MAC_PKT_FILT_HPF BIT(10)
294 #define DWCEQOS_MAC_PKT_FILT_SAF BIT(9)
295 #define DWCEQOS_MAC_PKT_FILT_SAIF BIT(8)
296 #define DWCEQOS_MAC_PKT_FILT_DBF BIT(5)
297 #define DWCEQOS_MAC_PKT_FILT_PM BIT(4)
298 #define DWCEQOS_MAC_PKT_FILT_DAIF BIT(3)
299 #define DWCEQOS_MAC_PKT_FILT_HMC BIT(2)
300 #define DWCEQOS_MAC_PKT_FILT_HUC BIT(1)
301 #define DWCEQOS_MAC_PKT_FILT_PR BIT(0)
303 #define DWCEQOS_MAC_MDIO_ADDR_CR(x) (((x & 15)) << 8)
304 #define DWCEQOS_MAC_MDIO_ADDR_CR_20 2
305 #define DWCEQOS_MAC_MDIO_ADDR_CR_35 3
306 #define DWCEQOS_MAC_MDIO_ADDR_CR_60 0
307 #define DWCEQOS_MAC_MDIO_ADDR_CR_100 1
308 #define DWCEQOS_MAC_MDIO_ADDR_CR_150 4
309 #define DWCEQOS_MAC_MDIO_ADDR_CR_250 5
310 #define DWCEQOS_MAC_MDIO_ADDR_GOC_READ 0x0000000c
311 #define DWCEQOS_MAC_MDIO_ADDR_GOC_WRITE BIT(2)
312 #define DWCEQOS_MAC_MDIO_ADDR_GB BIT(0)
314 #define DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIEN BIT(0)
315 #define DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIEX BIT(1)
316 #define DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIEN BIT(2)
317 #define DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIEX BIT(3)
318 #define DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIST BIT(8)
319 #define DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIST BIT(9)
320 #define DWCEQOS_MAC_LPI_CTRL_STATUS_LPIEN BIT(16)
321 #define DWCEQOS_MAC_LPI_CTRL_STATUS_PLS BIT(17)
322 #define DWCEQOS_MAC_LPI_CTRL_STATUS_PLSEN BIT(18)
323 #define DWCEQOS_MAC_LPI_CTRL_STATUS_LIPTXA BIT(19)
324 #define DWCEQOS_MAC_LPI_CTRL_STATUS_LPITE BIT(20)
325 #define DWCEQOS_MAC_LPI_CTRL_STATUS_LPITCSE BIT(21)
327 #define DWCEQOS_MAC_1US_TIC_COUNTER_VAL(x) ((x) & GENMASK(11, 0))
329 #define DWCEQOS_LPI_CTRL_ENABLE_EEE (DWCEQOS_MAC_LPI_CTRL_STATUS_LPITE | \
330 DWCEQOS_MAC_LPI_CTRL_STATUS_LIPTXA | \
331 DWCEQOS_MAC_LPI_CTRL_STATUS_LPIEN)
333 #define DWCEQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
335 #define DWCEQOS_MAC_Q0_TX_FLOW_TFE BIT(1)
336 #define DWCEQOS_MAC_Q0_TX_FLOW_PT(time) ((time) << 16)
337 #define DWCEQOS_MAC_Q0_TX_FLOW_PLT_4_SLOTS (0 << 4)
340 #define DWCEQOS_MAC_HW_FEATURE0_RXCOESEL BIT(16)
341 #define DWCEQOS_MAC_HW_FEATURE0_TXCOESEL BIT(14)
342 #define DWCEQOS_MAC_HW_FEATURE0_HDSEL BIT(2)
343 #define DWCEQOS_MAC_HW_FEATURE0_EEESEL BIT(13)
344 #define DWCEQOS_MAC_HW_FEATURE0_GMIISEL BIT(1)
345 #define DWCEQOS_MAC_HW_FEATURE0_MIISEL BIT(0)
347 #define DWCEQOS_MAC_HW_FEATURE1_TSOEN BIT(18)
348 #define DWCEQOS_MAC_HW_FEATURE1_TXFIFOSIZE(x) ((128 << ((x) & 0x7c0)) >> 6)
349 #define DWCEQOS_MAC_HW_FEATURE1_RXFIFOSIZE(x) (128 << ((x) & 0x1f))
351 #define DWCEQOS_MAX_PERFECT_ADDRESSES(feature1) \
352 (1 + (((feature1) & 0x1fc0000) >> 18))
354 #define DWCEQOS_MDIO_PHYADDR(x) (((x) & 0x1f) << 21)
355 #define DWCEQOS_MDIO_PHYREG(x) (((x) & 0x1f) << 16)
357 #define DWCEQOS_DMA_MODE_SWR BIT(0)
359 #define DWCEQOS_DWCEQOS_RX_BUF_SIZE 2048
361 /* Mac Management Counters */
362 #define REG_DWCEQOS_MMC_CTRL 0x0700
363 #define REG_DWCEQOS_MMC_RXIRQ 0x0704
364 #define REG_DWCEQOS_MMC_TXIRQ 0x0708
365 #define REG_DWCEQOS_MMC_RXIRQMASK 0x070c
366 #define REG_DWCEQOS_MMC_TXIRQMASK 0x0710
368 #define DWCEQOS_MMC_CTRL_CNTRST BIT(0)
369 #define DWCEQOS_MMC_CTRL_RSTONRD BIT(2)
371 #define DWC_MMC_TXLPITRANSCNTR 0x07F0
372 #define DWC_MMC_TXLPIUSCNTR 0x07EC
373 #define DWC_MMC_TXOVERSIZE_G 0x0778
374 #define DWC_MMC_TXVLANPACKETS_G 0x0774
375 #define DWC_MMC_TXPAUSEPACKETS 0x0770
376 #define DWC_MMC_TXEXCESSDEF 0x076C
377 #define DWC_MMC_TXPACKETCOUNT_G 0x0768
378 #define DWC_MMC_TXOCTETCOUNT_G 0x0764
379 #define DWC_MMC_TXCARRIERERROR 0x0760
380 #define DWC_MMC_TXEXCESSCOL 0x075C
381 #define DWC_MMC_TXLATECOL 0x0758
382 #define DWC_MMC_TXDEFERRED 0x0754
383 #define DWC_MMC_TXMULTICOL_G 0x0750
384 #define DWC_MMC_TXSINGLECOL_G 0x074C
385 #define DWC_MMC_TXUNDERFLOWERROR 0x0748
386 #define DWC_MMC_TXBROADCASTPACKETS_GB 0x0744
387 #define DWC_MMC_TXMULTICASTPACKETS_GB 0x0740
388 #define DWC_MMC_TXUNICASTPACKETS_GB 0x073C
389 #define DWC_MMC_TX1024TOMAXOCTETS_GB 0x0738
390 #define DWC_MMC_TX512TO1023OCTETS_GB 0x0734
391 #define DWC_MMC_TX256TO511OCTETS_GB 0x0730
392 #define DWC_MMC_TX128TO255OCTETS_GB 0x072C
393 #define DWC_MMC_TX65TO127OCTETS_GB 0x0728
394 #define DWC_MMC_TX64OCTETS_GB 0x0724
395 #define DWC_MMC_TXMULTICASTPACKETS_G 0x0720
396 #define DWC_MMC_TXBROADCASTPACKETS_G 0x071C
397 #define DWC_MMC_TXPACKETCOUNT_GB 0x0718
398 #define DWC_MMC_TXOCTETCOUNT_GB 0x0714
400 #define DWC_MMC_RXLPITRANSCNTR 0x07F8
401 #define DWC_MMC_RXLPIUSCNTR 0x07F4
402 #define DWC_MMC_RXCTRLPACKETS_G 0x07E4
403 #define DWC_MMC_RXRCVERROR 0x07E0
404 #define DWC_MMC_RXWATCHDOG 0x07DC
405 #define DWC_MMC_RXVLANPACKETS_GB 0x07D8
406 #define DWC_MMC_RXFIFOOVERFLOW 0x07D4
407 #define DWC_MMC_RXPAUSEPACKETS 0x07D0
408 #define DWC_MMC_RXOUTOFRANGETYPE 0x07CC
409 #define DWC_MMC_RXLENGTHERROR 0x07C8
410 #define DWC_MMC_RXUNICASTPACKETS_G 0x07C4
411 #define DWC_MMC_RX1024TOMAXOCTETS_GB 0x07C0
412 #define DWC_MMC_RX512TO1023OCTETS_GB 0x07BC
413 #define DWC_MMC_RX256TO511OCTETS_GB 0x07B8
414 #define DWC_MMC_RX128TO255OCTETS_GB 0x07B4
415 #define DWC_MMC_RX65TO127OCTETS_GB 0x07B0
416 #define DWC_MMC_RX64OCTETS_GB 0x07AC
417 #define DWC_MMC_RXOVERSIZE_G 0x07A8
418 #define DWC_MMC_RXUNDERSIZE_G 0x07A4
419 #define DWC_MMC_RXJABBERERROR 0x07A0
420 #define DWC_MMC_RXRUNTERROR 0x079C
421 #define DWC_MMC_RXALIGNMENTERROR 0x0798
422 #define DWC_MMC_RXCRCERROR 0x0794
423 #define DWC_MMC_RXMULTICASTPACKETS_G 0x0790
424 #define DWC_MMC_RXBROADCASTPACKETS_G 0x078C
425 #define DWC_MMC_RXOCTETCOUNT_G 0x0788
426 #define DWC_MMC_RXOCTETCOUNT_GB 0x0784
427 #define DWC_MMC_RXPACKETCOUNT_GB 0x0780
429 static int debug = 3;
430 module_param(debug, int, 0);
431 MODULE_PARM_DESC(debug, "DWC_eth_qos debug level (0=none,...,16=all)");
433 /* DMA ring descriptor. These are used as support descriptors for the HW DMA */
440 /* DMA hardware descriptor */
441 struct dwceqos_dma_desc {
446 } ____cacheline_aligned;
448 struct dwceqos_mmc_counters {
449 __u64 txlpitranscntr;
452 __u64 txvlanpackets_g;
453 __u64 txpausepackets;
455 __u64 txpacketcount_g;
456 __u64 txoctetcount_g;
457 __u64 txcarriererror;
463 __u64 txunderflowerror;
464 __u64 txbroadcastpackets_gb;
465 __u64 txmulticastpackets_gb;
466 __u64 txunicastpackets_gb;
467 __u64 tx1024tomaxoctets_gb;
468 __u64 tx512to1023octets_gb;
469 __u64 tx256to511octets_gb;
470 __u64 tx128to255octets_gb;
471 __u64 tx65to127octets_gb;
473 __u64 txmulticastpackets_g;
474 __u64 txbroadcastpackets_g;
475 __u64 txpacketcount_gb;
476 __u64 txoctetcount_gb;
478 __u64 rxlpitranscntr;
480 __u64 rxctrlpackets_g;
483 __u64 rxvlanpackets_gb;
484 __u64 rxfifooverflow;
485 __u64 rxpausepackets;
486 __u64 rxoutofrangetype;
488 __u64 rxunicastpackets_g;
489 __u64 rx1024tomaxoctets_gb;
490 __u64 rx512to1023octets_gb;
491 __u64 rx256to511octets_gb;
492 __u64 rx128to255octets_gb;
493 __u64 rx65to127octets_gb;
499 __u64 rxalignmenterror;
501 __u64 rxmulticastpackets_g;
502 __u64 rxbroadcastpackets_g;
503 __u64 rxoctetcount_g;
504 __u64 rxoctetcount_gb;
505 __u64 rxpacketcount_gb;
508 /* Ethtool statistics */
510 struct dwceqos_stat {
511 const char stat_name[ETH_GSTRING_LEN];
515 #define STAT_ITEM(name, var) \
518 offsetof(struct dwceqos_mmc_counters, var),\
521 static const struct dwceqos_stat dwceqos_ethtool_stats[] = {
522 STAT_ITEM("tx_bytes", txoctetcount_gb),
523 STAT_ITEM("tx_packets", txpacketcount_gb),
524 STAT_ITEM("tx_unicst_packets", txunicastpackets_gb),
525 STAT_ITEM("tx_broadcast_packets", txbroadcastpackets_gb),
526 STAT_ITEM("tx_multicast_packets", txmulticastpackets_gb),
527 STAT_ITEM("tx_pause_packets", txpausepackets),
528 STAT_ITEM("tx_up_to_64_byte_packets", tx64octets_gb),
529 STAT_ITEM("tx_65_to_127_byte_packets", tx65to127octets_gb),
530 STAT_ITEM("tx_128_to_255_byte_packets", tx128to255octets_gb),
531 STAT_ITEM("tx_256_to_511_byte_packets", tx256to511octets_gb),
532 STAT_ITEM("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
533 STAT_ITEM("tx_1024_to_maxsize_packets", tx1024tomaxoctets_gb),
534 STAT_ITEM("tx_underflow_errors", txunderflowerror),
535 STAT_ITEM("tx_lpi_count", txlpitranscntr),
537 STAT_ITEM("rx_bytes", rxoctetcount_gb),
538 STAT_ITEM("rx_packets", rxpacketcount_gb),
539 STAT_ITEM("rx_unicast_packets", rxunicastpackets_g),
540 STAT_ITEM("rx_broadcast_packets", rxbroadcastpackets_g),
541 STAT_ITEM("rx_multicast_packets", rxmulticastpackets_g),
542 STAT_ITEM("rx_vlan_packets", rxvlanpackets_gb),
543 STAT_ITEM("rx_pause_packets", rxpausepackets),
544 STAT_ITEM("rx_up_to_64_byte_packets", rx64octets_gb),
545 STAT_ITEM("rx_65_to_127_byte_packets", rx65to127octets_gb),
546 STAT_ITEM("rx_128_to_255_byte_packets", rx128to255octets_gb),
547 STAT_ITEM("rx_256_to_511_byte_packets", rx256to511octets_gb),
548 STAT_ITEM("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
549 STAT_ITEM("rx_1024_to_maxsize_packets", rx1024tomaxoctets_gb),
550 STAT_ITEM("rx_fifo_overflow_errors", rxfifooverflow),
551 STAT_ITEM("rx_oversize_packets", rxoversize_g),
552 STAT_ITEM("rx_undersize_packets", rxundersize_g),
553 STAT_ITEM("rx_jabbers", rxjabbererror),
554 STAT_ITEM("rx_align_errors", rxalignmenterror),
555 STAT_ITEM("rx_crc_errors", rxcrcerror),
556 STAT_ITEM("rx_lpi_count", rxlpitranscntr),
559 /* Configuration of AXI bus parameters.
560 * These values depend on the parameters set on the MAC core as well
561 * as the AXI interconnect.
563 struct dwceqos_bus_cfg {
564 /* Enable AXI low-power interface. */
566 /* Limit on number of outstanding AXI write requests. */
568 /* Limit on number of outstanding AXI read requests. */
570 /* Bitmap of allowed AXI burst lengths, 4-256 beats. */
572 /* DMA Programmable burst length*/
577 struct dwceqos_flowcontrol {
586 void __iomem *baseaddr;
587 struct clk *phy_ref_clk;
588 struct clk *apb_pclk;
590 struct device_node *phy_node;
591 struct net_device *ndev;
592 struct platform_device *pdev;
596 struct tasklet_struct tx_bdreclaim_tasklet;
597 struct workqueue_struct *txtimeout_handler_wq;
598 struct work_struct txtimeout_reinit;
600 phy_interface_t phy_interface;
601 struct phy_device *phy_dev;
602 struct mii_bus *mii_bus;
608 struct napi_struct napi;
610 /* DMA Descriptor Areas */
611 struct ring_desc *rx_skb;
612 struct ring_desc *tx_skb;
614 struct dwceqos_dma_desc *tx_descs;
615 struct dwceqos_dma_desc *rx_descs;
617 /* DMA Mapped Descriptor areas*/
618 dma_addr_t tx_descs_addr;
619 dma_addr_t rx_descs_addr;
620 dma_addr_t tx_descs_tail_addr;
621 dma_addr_t rx_descs_tail_addr;
628 /* Spinlocks for accessing DMA Descriptors */
631 /* Spinlock for register read-modify-writes. */
638 struct dwceqos_bus_cfg bus_cfg;
639 bool en_tx_lpi_clockgating;
646 struct dwceqos_mmc_counters mmc_counters;
647 /* Protect the mmc_counter updates. */
648 spinlock_t stats_lock;
649 u32 mmc_rx_counters_mask;
650 u32 mmc_tx_counters_mask;
652 struct dwceqos_flowcontrol flowcontrol;
655 static void dwceqos_read_mmc_counters(struct net_local *lp, u32 rx_mask,
658 static void dwceqos_set_umac_addr(struct net_local *lp, unsigned char *addr,
660 static int dwceqos_stop(struct net_device *ndev);
661 static int dwceqos_open(struct net_device *ndev);
662 static void dwceqos_tx_poll_demand(struct net_local *lp);
664 static void dwceqos_set_rx_flowcontrol(struct net_local *lp, bool enable);
665 static void dwceqos_set_tx_flowcontrol(struct net_local *lp, bool enable);
667 static void dwceqos_reset_state(struct net_local *lp);
669 #define dwceqos_read(lp, reg) \
670 readl_relaxed(((void __iomem *)((lp)->baseaddr)) + (reg))
671 #define dwceqos_write(lp, reg, val) \
672 writel_relaxed((val), ((void __iomem *)((lp)->baseaddr)) + (reg))
674 static void dwceqos_reset_state(struct net_local *lp)
678 lp->duplex = DUPLEX_UNKNOWN;
679 lp->flowcontrol.rx_current = 0;
680 lp->flowcontrol.tx_current = 0;
685 static void print_descriptor(struct net_local *lp, int index, int tx)
687 struct dwceqos_dma_desc *dd;
690 dd = (struct dwceqos_dma_desc *)&lp->tx_descs[index];
692 dd = (struct dwceqos_dma_desc *)&lp->rx_descs[index];
694 pr_info("%s DMA Descriptor #%d@%p Contents:\n", tx ? "TX" : "RX",
696 pr_info("0x%08x 0x%08x 0x%08x 0x%08x\n", dd->des0, dd->des1, dd->des2,
700 static void print_status(struct net_local *lp)
704 pr_info("tx_free %zu, tx_cur %zu, tx_next %zu\n", lp->tx_free,
705 lp->tx_cur, lp->tx_next);
707 print_descriptor(lp, lp->rx_cur, 0);
709 for (desci = (lp->tx_cur - 10) % DWCEQOS_TX_DCNT, i = 0;
712 print_descriptor(lp, desci, 1);
713 desci = (desci + 1) % DWCEQOS_TX_DCNT;
716 pr_info("DMA_Debug_Status0: 0x%08x\n",
717 dwceqos_read(lp, REG_DWCEQOS_DMA_DEBUG_ST0));
718 pr_info("DMA_CH0_Status: 0x%08x\n",
719 dwceqos_read(lp, REG_DWCEQOS_DMA_IS));
720 pr_info("DMA_CH0_Current_App_TxDesc: 0x%08x\n",
721 dwceqos_read(lp, 0x1144));
722 pr_info("DMA_CH0_Current_App_TxBuff: 0x%08x\n",
723 dwceqos_read(lp, 0x1154));
724 pr_info("MTL_Debug_Status: 0x%08x\n",
725 dwceqos_read(lp, REG_DWCEQOS_MTL_DEBUG_ST));
726 pr_info("MTL_TXQ0_Debug_Status: 0x%08x\n",
727 dwceqos_read(lp, REG_DWCEQOS_MTL_TXQ0_DEBUG_ST));
728 pr_info("MTL_RXQ0_Debug_Status: 0x%08x\n",
729 dwceqos_read(lp, REG_DWCEQOS_MTL_RXQ0_DEBUG_ST));
730 pr_info("Current TX DMA: 0x%08x, RX DMA: 0x%08x\n",
731 dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_CUR_TXDESC),
732 dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_CUR_RXDESC));
735 static void dwceqos_mdio_set_csr(struct net_local *lp)
737 int rate = clk_get_rate(lp->apb_pclk);
739 if (rate <= 20000000)
740 lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_20;
741 else if (rate <= 35000000)
742 lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_35;
743 else if (rate <= 60000000)
744 lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_60;
745 else if (rate <= 100000000)
746 lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_100;
747 else if (rate <= 150000000)
748 lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_150;
749 else if (rate <= 250000000)
750 lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_250;
753 /* Simple MDIO functions implementing mii_bus */
754 static int dwceqos_mdio_read(struct mii_bus *bus, int mii_id, int phyreg)
756 struct net_local *lp = bus->priv;
761 regval = DWCEQOS_MDIO_PHYADDR(mii_id) |
762 DWCEQOS_MDIO_PHYREG(phyreg) |
763 DWCEQOS_MAC_MDIO_ADDR_CR(lp->csr_val) |
764 DWCEQOS_MAC_MDIO_ADDR_GB |
765 DWCEQOS_MAC_MDIO_ADDR_GOC_READ;
766 dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_ADDR, regval);
768 for (i = 0; i < 5; ++i) {
769 usleep_range(64, 128);
770 if (!(dwceqos_read(lp, REG_DWCEQOS_MAC_MDIO_ADDR) &
771 DWCEQOS_MAC_MDIO_ADDR_GB))
775 data = dwceqos_read(lp, REG_DWCEQOS_MAC_MDIO_DATA);
777 netdev_warn(lp->ndev, "MDIO read timed out\n");
781 return data & 0xffff;
784 static int dwceqos_mdio_write(struct mii_bus *bus, int mii_id, int phyreg,
787 struct net_local *lp = bus->priv;
791 dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_DATA, value);
793 regval = DWCEQOS_MDIO_PHYADDR(mii_id) |
794 DWCEQOS_MDIO_PHYREG(phyreg) |
795 DWCEQOS_MAC_MDIO_ADDR_CR(lp->csr_val) |
796 DWCEQOS_MAC_MDIO_ADDR_GB |
797 DWCEQOS_MAC_MDIO_ADDR_GOC_WRITE;
798 dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_ADDR, regval);
800 for (i = 0; i < 5; ++i) {
801 usleep_range(64, 128);
802 if (!(dwceqos_read(lp, REG_DWCEQOS_MAC_MDIO_ADDR) &
803 DWCEQOS_MAC_MDIO_ADDR_GB))
807 netdev_warn(lp->ndev, "MDIO write timed out\n");
811 static int dwceqos_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
813 struct net_local *lp = netdev_priv(ndev);
814 struct phy_device *phydev = lp->phy_dev;
816 if (!netif_running(ndev))
826 return phy_mii_ioctl(phydev, rq, cmd);
828 dev_info(&lp->pdev->dev, "ioctl %X not implemented.\n", cmd);
833 static void dwceqos_link_down(struct net_local *lp)
838 /* Indicate link down to the LPI state machine */
839 spin_lock_irqsave(&lp->hw_lock, flags);
840 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
841 regval &= ~DWCEQOS_MAC_LPI_CTRL_STATUS_PLS;
842 dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
843 spin_unlock_irqrestore(&lp->hw_lock, flags);
846 static void dwceqos_link_up(struct net_local *lp)
851 /* Indicate link up to the LPI state machine */
852 spin_lock_irqsave(&lp->hw_lock, flags);
853 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
854 regval |= DWCEQOS_MAC_LPI_CTRL_STATUS_PLS;
855 dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
856 spin_unlock_irqrestore(&lp->hw_lock, flags);
858 lp->eee_active = !phy_init_eee(lp->phy_dev, 0);
860 /* Check for changed EEE capability */
861 if (!lp->eee_active && lp->eee_enabled) {
864 spin_lock_irqsave(&lp->hw_lock, flags);
865 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
866 regval &= ~DWCEQOS_LPI_CTRL_ENABLE_EEE;
867 dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
868 spin_unlock_irqrestore(&lp->hw_lock, flags);
872 static void dwceqos_set_speed(struct net_local *lp)
874 struct phy_device *phydev = lp->phy_dev;
877 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_CFG);
878 regval &= ~(DWCEQOS_MAC_CFG_PS | DWCEQOS_MAC_CFG_FES |
882 regval |= DWCEQOS_MAC_CFG_DM;
883 if (phydev->speed == SPEED_10) {
884 regval |= DWCEQOS_MAC_CFG_PS;
885 } else if (phydev->speed == SPEED_100) {
886 regval |= DWCEQOS_MAC_CFG_PS |
888 } else if (phydev->speed != SPEED_1000) {
890 "unknown PHY speed %d\n",
895 dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, regval);
898 static void dwceqos_adjust_link(struct net_device *ndev)
900 struct net_local *lp = netdev_priv(ndev);
901 struct phy_device *phydev = lp->phy_dev;
902 int status_change = 0;
905 if ((lp->speed != phydev->speed) ||
906 (lp->duplex != phydev->duplex)) {
907 dwceqos_set_speed(lp);
909 lp->speed = phydev->speed;
910 lp->duplex = phydev->duplex;
914 if (lp->flowcontrol.autoneg) {
915 lp->flowcontrol.rx = phydev->pause ||
917 lp->flowcontrol.tx = phydev->pause ||
921 if (lp->flowcontrol.rx != lp->flowcontrol.rx_current) {
922 if (netif_msg_link(lp))
923 netdev_dbg(ndev, "set rx flow to %d\n",
925 dwceqos_set_rx_flowcontrol(lp, lp->flowcontrol.rx);
926 lp->flowcontrol.rx_current = lp->flowcontrol.rx;
928 if (lp->flowcontrol.tx != lp->flowcontrol.tx_current) {
929 if (netif_msg_link(lp))
930 netdev_dbg(ndev, "set tx flow to %d\n",
932 dwceqos_set_tx_flowcontrol(lp, lp->flowcontrol.tx);
933 lp->flowcontrol.tx_current = lp->flowcontrol.tx;
937 if (phydev->link != lp->link) {
938 lp->link = phydev->link;
944 lp->ndev->trans_start = jiffies;
947 dwceqos_link_down(lp);
949 phy_print_status(phydev);
953 static int dwceqos_mii_probe(struct net_device *ndev)
955 struct net_local *lp = netdev_priv(ndev);
956 struct phy_device *phydev = NULL;
959 phydev = of_phy_connect(lp->ndev,
961 &dwceqos_adjust_link,
966 netdev_err(ndev, "no PHY found\n");
970 netdev_err(ndev, "no PHY configured\n");
974 if (netif_msg_probe(lp))
976 "phydev %p, phydev->phy_id 0xa%x, phydev->addr 0x%x\n",
977 phydev, phydev->phy_id, phydev->addr);
979 phydev->supported &= PHY_GBIT_FEATURES;
983 lp->duplex = DUPLEX_UNKNOWN;
984 lp->phy_dev = phydev;
986 if (netif_msg_probe(lp)) {
987 netdev_dbg(lp->ndev, "phy_addr 0x%x, phy_id 0x%08x\n",
988 lp->phy_dev->addr, lp->phy_dev->phy_id);
990 netdev_dbg(lp->ndev, "attach [%s] phy driver\n",
991 lp->phy_dev->drv->name);
997 static void dwceqos_alloc_rxring_desc(struct net_local *lp, int index)
999 struct sk_buff *new_skb;
1000 dma_addr_t new_skb_baddr = 0;
1002 new_skb = netdev_alloc_skb(lp->ndev, DWCEQOS_RX_BUF_SIZE);
1004 netdev_err(lp->ndev, "alloc_skb error for desc %d\n", index);
1008 new_skb_baddr = dma_map_single(lp->ndev->dev.parent,
1009 new_skb->data, DWCEQOS_RX_BUF_SIZE,
1011 if (dma_mapping_error(lp->ndev->dev.parent, new_skb_baddr)) {
1012 netdev_err(lp->ndev, "DMA map error\n");
1013 dev_kfree_skb(new_skb);
1018 lp->rx_descs[index].des0 = new_skb_baddr;
1019 lp->rx_descs[index].des1 = 0;
1020 lp->rx_descs[index].des2 = 0;
1021 lp->rx_descs[index].des3 = DWCEQOS_DMA_RDES3_INTE |
1022 DWCEQOS_DMA_RDES3_BUF1V |
1023 DWCEQOS_DMA_RDES3_OWN;
1025 lp->rx_skb[index].mapping = new_skb_baddr;
1026 lp->rx_skb[index].len = DWCEQOS_RX_BUF_SIZE;
1029 lp->rx_skb[index].skb = new_skb;
1032 static void dwceqos_clean_rings(struct net_local *lp)
1037 for (i = 0; i < DWCEQOS_RX_DCNT; i++) {
1038 if (lp->rx_skb[i].skb) {
1039 dma_unmap_single(lp->ndev->dev.parent,
1040 lp->rx_skb[i].mapping,
1044 dev_kfree_skb(lp->rx_skb[i].skb);
1045 lp->rx_skb[i].skb = NULL;
1046 lp->rx_skb[i].mapping = 0;
1052 for (i = 0; i < DWCEQOS_TX_DCNT; i++) {
1053 if (lp->tx_skb[i].skb) {
1054 dev_kfree_skb(lp->tx_skb[i].skb);
1055 lp->tx_skb[i].skb = NULL;
1057 if (lp->tx_skb[i].mapping) {
1058 dma_unmap_single(lp->ndev->dev.parent,
1059 lp->tx_skb[i].mapping,
1062 lp->tx_skb[i].mapping = 0;
1068 static void dwceqos_descriptor_free(struct net_local *lp)
1072 dwceqos_clean_rings(lp);
1079 size = DWCEQOS_RX_DCNT * sizeof(struct dwceqos_dma_desc);
1081 dma_free_coherent(lp->ndev->dev.parent, size,
1082 (void *)(lp->rx_descs), lp->rx_descs_addr);
1083 lp->rx_descs = NULL;
1086 size = DWCEQOS_TX_DCNT * sizeof(struct dwceqos_dma_desc);
1088 dma_free_coherent(lp->ndev->dev.parent, size,
1089 (void *)(lp->tx_descs), lp->tx_descs_addr);
1090 lp->tx_descs = NULL;
1094 static int dwceqos_descriptor_init(struct net_local *lp)
1103 lp->rx_descs = NULL;
1104 lp->tx_descs = NULL;
1106 /* Reset the DMA indexes */
1110 lp->tx_free = DWCEQOS_TX_DCNT;
1112 /* Allocate Ring descriptors */
1113 size = DWCEQOS_RX_DCNT * sizeof(struct ring_desc);
1114 lp->rx_skb = kzalloc(size, GFP_KERNEL);
1118 size = DWCEQOS_TX_DCNT * sizeof(struct ring_desc);
1119 lp->tx_skb = kzalloc(size, GFP_KERNEL);
1123 /* Allocate DMA descriptors */
1124 size = DWCEQOS_RX_DCNT * sizeof(struct dwceqos_dma_desc);
1125 lp->rx_descs = dma_alloc_coherent(lp->ndev->dev.parent, size,
1126 &lp->rx_descs_addr, 0);
1129 lp->rx_descs_tail_addr = lp->rx_descs_addr +
1130 sizeof(struct dwceqos_dma_desc) * DWCEQOS_RX_DCNT;
1132 size = DWCEQOS_TX_DCNT * sizeof(struct dwceqos_dma_desc);
1133 lp->tx_descs = dma_alloc_coherent(lp->ndev->dev.parent, size,
1134 &lp->tx_descs_addr, 0);
1137 lp->tx_descs_tail_addr = lp->tx_descs_addr +
1138 sizeof(struct dwceqos_dma_desc) * DWCEQOS_TX_DCNT;
1140 /* Initialize RX Ring Descriptors and buffers */
1141 for (i = 0; i < DWCEQOS_RX_DCNT; ++i) {
1142 dwceqos_alloc_rxring_desc(lp, i);
1143 if (!(lp->rx_skb[lp->rx_cur].skb))
1147 /* Initialize TX Descriptors */
1148 for (i = 0; i < DWCEQOS_TX_DCNT; ++i) {
1149 lp->tx_descs[i].des0 = 0;
1150 lp->tx_descs[i].des1 = 0;
1151 lp->tx_descs[i].des2 = 0;
1152 lp->tx_descs[i].des3 = 0;
1155 /* Make descriptor writes visible to the DMA. */
1161 dwceqos_descriptor_free(lp);
1165 static int dwceqos_packet_avail(struct net_local *lp)
1167 return !(lp->rx_descs[lp->rx_cur].des3 & DWCEQOS_DMA_RDES3_OWN);
1170 static void dwceqos_get_hwfeatures(struct net_local *lp)
1172 lp->feature0 = dwceqos_read(lp, REG_DWCEQOS_MAC_HW_FEATURE0);
1173 lp->feature1 = dwceqos_read(lp, REG_DWCEQOS_MAC_HW_FEATURE1);
1174 lp->feature2 = dwceqos_read(lp, REG_DWCEQOS_MAC_HW_FEATURE2);
1177 static void dwceqos_dma_enable_txirq(struct net_local *lp)
1180 unsigned long flags;
1182 spin_lock_irqsave(&lp->hw_lock, flags);
1183 regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
1184 regval |= DWCEQOS_DMA_CH0_IE_TIE;
1185 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
1186 spin_unlock_irqrestore(&lp->hw_lock, flags);
1189 static void dwceqos_dma_disable_txirq(struct net_local *lp)
1192 unsigned long flags;
1194 spin_lock_irqsave(&lp->hw_lock, flags);
1195 regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
1196 regval &= ~DWCEQOS_DMA_CH0_IE_TIE;
1197 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
1198 spin_unlock_irqrestore(&lp->hw_lock, flags);
1201 static void dwceqos_dma_enable_rxirq(struct net_local *lp)
1204 unsigned long flags;
1206 spin_lock_irqsave(&lp->hw_lock, flags);
1207 regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
1208 regval |= DWCEQOS_DMA_CH0_IE_RIE;
1209 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
1210 spin_unlock_irqrestore(&lp->hw_lock, flags);
1213 static void dwceqos_dma_disable_rxirq(struct net_local *lp)
1216 unsigned long flags;
1218 spin_lock_irqsave(&lp->hw_lock, flags);
1219 regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
1220 regval &= ~DWCEQOS_DMA_CH0_IE_RIE;
1221 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
1222 spin_unlock_irqrestore(&lp->hw_lock, flags);
1225 static void dwceqos_enable_mmc_interrupt(struct net_local *lp)
1227 dwceqos_write(lp, REG_DWCEQOS_MMC_RXIRQMASK, 0);
1228 dwceqos_write(lp, REG_DWCEQOS_MMC_TXIRQMASK, 0);
1231 static int dwceqos_mii_init(struct net_local *lp)
1233 int ret = -ENXIO, i;
1234 struct resource res;
1235 struct device_node *mdionode;
1237 mdionode = of_get_child_by_name(lp->pdev->dev.of_node, "mdio");
1242 lp->mii_bus = mdiobus_alloc();
1248 lp->mii_bus->name = "DWCEQOS MII bus";
1249 lp->mii_bus->read = &dwceqos_mdio_read;
1250 lp->mii_bus->write = &dwceqos_mdio_write;
1251 lp->mii_bus->priv = lp;
1252 lp->mii_bus->parent = &lp->ndev->dev;
1254 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1255 if (!lp->mii_bus->irq) {
1257 goto err_out_free_mdiobus;
1260 for (i = 0; i < PHY_MAX_ADDR; i++)
1261 lp->mii_bus->irq[i] = PHY_POLL;
1262 of_address_to_resource(lp->pdev->dev.of_node, 0, &res);
1263 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%.8llx",
1264 (unsigned long long)res.start);
1265 if (of_mdiobus_register(lp->mii_bus, mdionode))
1266 goto err_out_free_mdio_irq;
1270 err_out_free_mdio_irq:
1271 kfree(lp->mii_bus->irq);
1272 err_out_free_mdiobus:
1273 mdiobus_free(lp->mii_bus);
1275 of_node_put(mdionode);
1279 /* DMA reset. When issued also resets all MTL and MAC registers as well */
1280 static void dwceqos_reset_hw(struct net_local *lp)
1282 /* Wait (at most) 0.5 seconds for DMA reset*/
1286 /* Force gigabit to guarantee a TX clock for GMII. */
1287 reg = dwceqos_read(lp, REG_DWCEQOS_MAC_CFG);
1288 reg &= ~(DWCEQOS_MAC_CFG_PS | DWCEQOS_MAC_CFG_FES);
1289 reg |= DWCEQOS_MAC_CFG_DM;
1290 dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, reg);
1292 dwceqos_write(lp, REG_DWCEQOS_DMA_MODE, DWCEQOS_DMA_MODE_SWR);
1297 reg = dwceqos_read(lp, REG_DWCEQOS_DMA_MODE);
1298 } while ((reg & DWCEQOS_DMA_MODE_SWR) && i);
1299 /* We might experience a timeout if the chip clock mux is broken */
1301 netdev_err(lp->ndev, "DMA reset timed out!\n");
1304 static void dwceqos_fatal_bus_error(struct net_local *lp, u32 dma_status)
1306 if (dma_status & DWCEQOS_DMA_CH0_IS_TEB) {
1307 netdev_err(lp->ndev, "txdma bus error %s %s (status=%08x)\n",
1308 dma_status & DWCEQOS_DMA_CH0_IS_TX_ERR_READ ?
1310 dma_status & DWCEQOS_DMA_CH0_IS_TX_ERR_DESCR ?
1316 if (dma_status & DWCEQOS_DMA_CH0_IS_REB) {
1317 netdev_err(lp->ndev, "rxdma bus error %s %s (status=%08x)\n",
1318 dma_status & DWCEQOS_DMA_CH0_IS_RX_ERR_READ ?
1320 dma_status & DWCEQOS_DMA_CH0_IS_RX_ERR_DESCR ?
1328 static void dwceqos_mmc_interrupt(struct net_local *lp)
1330 unsigned long flags;
1332 spin_lock_irqsave(&lp->stats_lock, flags);
1334 /* A latched mmc interrupt can not be masked, we must read
1335 * all the counters with an interrupt pending.
1337 dwceqos_read_mmc_counters(lp,
1338 dwceqos_read(lp, REG_DWCEQOS_MMC_RXIRQ),
1339 dwceqos_read(lp, REG_DWCEQOS_MMC_TXIRQ));
1341 spin_unlock_irqrestore(&lp->stats_lock, flags);
1344 static void dwceqos_mac_interrupt(struct net_local *lp)
1348 cause = dwceqos_read(lp, REG_DWCEQOS_MAC_IS);
1350 if (cause & DWCEQOS_MAC_IS_MMC_INT)
1351 dwceqos_mmc_interrupt(lp);
1354 static irqreturn_t dwceqos_interrupt(int irq, void *dev_id)
1356 struct net_device *ndev = dev_id;
1357 struct net_local *lp = netdev_priv(ndev);
1361 irqreturn_t ret = IRQ_NONE;
1363 cause = dwceqos_read(lp, REG_DWCEQOS_DMA_IS);
1364 /* DMA Channel 0 Interrupt */
1365 if (cause & DWCEQOS_DMA_IS_DC0IS) {
1366 dma_status = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_STA);
1368 /* Transmit Interrupt */
1369 if (dma_status & DWCEQOS_DMA_CH0_IS_TI) {
1370 tasklet_schedule(&lp->tx_bdreclaim_tasklet);
1371 dwceqos_dma_disable_txirq(lp);
1374 /* Receive Interrupt */
1375 if (dma_status & DWCEQOS_DMA_CH0_IS_RI) {
1376 /* Disable RX IRQs */
1377 dwceqos_dma_disable_rxirq(lp);
1378 napi_schedule(&lp->napi);
1381 /* Fatal Bus Error interrupt */
1382 if (unlikely(dma_status & DWCEQOS_DMA_CH0_IS_FBE)) {
1383 dwceqos_fatal_bus_error(lp, dma_status);
1385 /* errata 9000831707 */
1386 dma_status |= DWCEQOS_DMA_CH0_IS_TEB |
1387 DWCEQOS_DMA_CH0_IS_REB;
1390 /* Ack all DMA Channel 0 IRQs */
1391 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_STA, dma_status);
1395 if (cause & DWCEQOS_DMA_IS_MTLIS) {
1396 u32 val = dwceqos_read(lp, REG_DWCEQOS_MTL_Q0_ISCTRL);
1398 dwceqos_write(lp, REG_DWCEQOS_MTL_Q0_ISCTRL, val);
1402 if (cause & DWCEQOS_DMA_IS_MACIS) {
1403 dwceqos_mac_interrupt(lp);
1409 static void dwceqos_set_rx_flowcontrol(struct net_local *lp, bool enable)
1412 unsigned long flags;
1414 spin_lock_irqsave(&lp->hw_lock, flags);
1416 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_RX_FLOW_CTRL);
1418 regval |= DWCEQOS_MAC_RX_FLOW_CTRL_RFE;
1420 regval &= ~DWCEQOS_MAC_RX_FLOW_CTRL_RFE;
1421 dwceqos_write(lp, REG_DWCEQOS_MAC_RX_FLOW_CTRL, regval);
1423 spin_unlock_irqrestore(&lp->hw_lock, flags);
1426 static void dwceqos_set_tx_flowcontrol(struct net_local *lp, bool enable)
1429 unsigned long flags;
1431 spin_lock_irqsave(&lp->hw_lock, flags);
1433 /* MTL flow control */
1434 regval = dwceqos_read(lp, REG_DWCEQOS_MTL_RXQ0_OPER);
1436 regval |= DWCEQOS_MTL_RXQ_EHFC;
1438 regval &= ~DWCEQOS_MTL_RXQ_EHFC;
1440 dwceqos_write(lp, REG_DWCEQOS_MTL_RXQ0_OPER, regval);
1442 /* MAC flow control */
1443 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_Q0_TX_FLOW);
1445 regval |= DWCEQOS_MAC_Q0_TX_FLOW_TFE;
1447 regval &= ~DWCEQOS_MAC_Q0_TX_FLOW_TFE;
1448 dwceqos_write(lp, REG_DWCEQOS_MAC_Q0_TX_FLOW, regval);
1450 spin_unlock_irqrestore(&lp->hw_lock, flags);
1453 static void dwceqos_configure_flow_control(struct net_local *lp)
1456 unsigned long flags;
1459 spin_lock_irqsave(&lp->hw_lock, flags);
1461 regval = dwceqos_read(lp, REG_DWCEQOS_MTL_RXQ0_OPER);
1463 /* The queue size is in units of 256 bytes. We want 512 bytes units for
1464 * the threshold fields.
1466 RQS = ((regval >> 20) & 0x3FF) + 1;
1469 /* The thresholds are relative to a full queue, with a bias
1470 * of 1 KiByte below full.
1475 regval = (regval & 0xFFF000FF) | (RFD << 14) | (RFA << 8);
1477 if (RFD >= 0 && RFA >= 0) {
1478 dwceqos_write(lp, REG_DWCEQOS_MTL_RXQ0_OPER, regval);
1480 netdev_warn(lp->ndev,
1481 "FIFO too small for flow control.");
1484 regval = DWCEQOS_MAC_Q0_TX_FLOW_PT(256) |
1485 DWCEQOS_MAC_Q0_TX_FLOW_PLT_4_SLOTS;
1487 dwceqos_write(lp, REG_DWCEQOS_MAC_Q0_TX_FLOW, regval);
1489 spin_unlock_irqrestore(&lp->hw_lock, flags);
1492 static void dwceqos_configure_clock(struct net_local *lp)
1494 unsigned long rate_mhz = clk_get_rate(lp->apb_pclk) / 1000000;
1499 REG_DWCEQOS_MAC_1US_TIC_COUNTER,
1500 DWCEQOS_MAC_1US_TIC_COUNTER_VAL(rate_mhz - 1));
1503 static void dwceqos_configure_bus(struct net_local *lp)
1507 /* N.B. We do not support the Fixed Burst mode because it
1508 * opens a race window by making HW access to DMA descriptors
1512 sysbus_reg = DWCEQOS_DMA_SYSBUS_MODE_AAL;
1514 if (lp->bus_cfg.en_lpi)
1515 sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_EN_LPI;
1517 if (lp->bus_cfg.burst_map)
1518 sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_BURST(
1519 lp->bus_cfg.burst_map);
1521 sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_BURST(
1522 DWCEQOS_DMA_SYSBUS_MODE_BURST_DEFAULT);
1524 if (lp->bus_cfg.read_requests)
1525 sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT(
1526 lp->bus_cfg.read_requests - 1);
1528 sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT(
1529 DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT_DEFAULT);
1531 if (lp->bus_cfg.write_requests)
1532 sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT(
1533 lp->bus_cfg.write_requests - 1);
1535 sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT(
1536 DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT_DEFAULT);
1538 if (netif_msg_hw(lp))
1539 netdev_dbg(lp->ndev, "SysbusMode %#X\n", sysbus_reg);
1541 dwceqos_write(lp, REG_DWCEQOS_DMA_SYSBUS_MODE, sysbus_reg);
1544 static void dwceqos_init_hw(struct net_local *lp)
1550 /* Software reset */
1551 dwceqos_reset_hw(lp);
1553 dwceqos_configure_bus(lp);
1555 /* Probe data bus width, 32/64/128 bits. */
1556 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL, 0xF);
1557 regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL);
1558 buswidth = (regval ^ 0xF) + 1;
1560 /* Cache-align dma descriptors. */
1561 dma_skip = (sizeof(struct dwceqos_dma_desc) - 16) / buswidth;
1562 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_CTRL,
1563 DWCEQOS_DMA_CH_CTRL_DSL(dma_skip) |
1564 DWCEQOS_DMA_CH_CTRL_PBLX8);
1566 /* Initialize DMA Channel 0 */
1567 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_LEN, DWCEQOS_TX_DCNT - 1);
1568 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_LEN, DWCEQOS_RX_DCNT - 1);
1569 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_LIST,
1570 (u32)lp->tx_descs_addr);
1571 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_LIST,
1572 (u32)lp->rx_descs_addr);
1574 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL,
1575 lp->tx_descs_tail_addr);
1576 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_TAIL,
1577 lp->rx_descs_tail_addr);
1579 if (lp->bus_cfg.tx_pbl)
1580 regval = DWCEQOS_DMA_CH_CTRL_PBL(lp->bus_cfg.tx_pbl);
1582 regval = DWCEQOS_DMA_CH_CTRL_PBL(2);
1584 /* Enable TSO if the HW support it */
1585 if (lp->feature1 & DWCEQOS_MAC_HW_FEATURE1_TSOEN)
1586 regval |= DWCEQOS_DMA_CH_TX_TSE;
1588 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TX_CTRL, regval);
1590 if (lp->bus_cfg.rx_pbl)
1591 regval = DWCEQOS_DMA_CH_CTRL_PBL(lp->bus_cfg.rx_pbl);
1593 regval = DWCEQOS_DMA_CH_CTRL_PBL(2);
1595 regval |= DWCEQOS_DMA_CH_RX_CTRL_BUFSIZE(DWCEQOS_DWCEQOS_RX_BUF_SIZE);
1596 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RX_CTRL, regval);
1598 regval |= DWCEQOS_DMA_CH_CTRL_START;
1599 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RX_CTRL, regval);
1601 /* Initialize MTL Queues */
1602 regval = DWCEQOS_MTL_SCHALG_STRICT;
1603 dwceqos_write(lp, REG_DWCEQOS_MTL_OPER, regval);
1605 regval = DWCEQOS_MTL_TXQ_SIZE(
1606 DWCEQOS_MAC_HW_FEATURE1_TXFIFOSIZE(lp->feature1)) |
1607 DWCEQOS_MTL_TXQ_TXQEN | DWCEQOS_MTL_TXQ_TSF |
1608 DWCEQOS_MTL_TXQ_TTC512;
1609 dwceqos_write(lp, REG_DWCEQOS_MTL_TXQ0_OPER, regval);
1611 regval = DWCEQOS_MTL_RXQ_SIZE(
1612 DWCEQOS_MAC_HW_FEATURE1_RXFIFOSIZE(lp->feature1)) |
1613 DWCEQOS_MTL_RXQ_FUP | DWCEQOS_MTL_RXQ_FEP | DWCEQOS_MTL_RXQ_RSF;
1614 dwceqos_write(lp, REG_DWCEQOS_MTL_RXQ0_OPER, regval);
1616 dwceqos_configure_flow_control(lp);
1618 /* Initialize MAC */
1619 dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
1621 lp->eee_enabled = 0;
1623 dwceqos_configure_clock(lp);
1627 /* probe implemented counters */
1628 dwceqos_write(lp, REG_DWCEQOS_MMC_RXIRQMASK, ~0u);
1629 dwceqos_write(lp, REG_DWCEQOS_MMC_TXIRQMASK, ~0u);
1630 lp->mmc_rx_counters_mask = dwceqos_read(lp, REG_DWCEQOS_MMC_RXIRQMASK);
1631 lp->mmc_tx_counters_mask = dwceqos_read(lp, REG_DWCEQOS_MMC_TXIRQMASK);
1633 dwceqos_write(lp, REG_DWCEQOS_MMC_CTRL, DWCEQOS_MMC_CTRL_CNTRST |
1634 DWCEQOS_MMC_CTRL_RSTONRD);
1635 dwceqos_enable_mmc_interrupt(lp);
1637 /* Enable Interrupts */
1638 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE,
1639 DWCEQOS_DMA_CH0_IE_NIE |
1640 DWCEQOS_DMA_CH0_IE_RIE | DWCEQOS_DMA_CH0_IE_TIE |
1641 DWCEQOS_DMA_CH0_IE_AIE |
1642 DWCEQOS_DMA_CH0_IE_FBEE);
1644 dwceqos_write(lp, REG_DWCEQOS_MAC_IE, 0);
1646 dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, DWCEQOS_MAC_CFG_IPC |
1647 DWCEQOS_MAC_CFG_DM | DWCEQOS_MAC_CFG_TE | DWCEQOS_MAC_CFG_RE);
1650 regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_TX_CTRL);
1651 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TX_CTRL,
1652 regval | DWCEQOS_DMA_CH_CTRL_START);
1654 /* Enable MAC TX/RX */
1655 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_CFG);
1656 dwceqos_write(lp, REG_DWCEQOS_MAC_CFG,
1657 regval | DWCEQOS_MAC_CFG_TE | DWCEQOS_MAC_CFG_RE);
1660 static void dwceqos_tx_reclaim(unsigned long data)
1662 struct net_device *ndev = (struct net_device *)data;
1663 struct net_local *lp = netdev_priv(ndev);
1664 unsigned int tx_bytes = 0;
1665 unsigned int tx_packets = 0;
1667 spin_lock(&lp->tx_lock);
1669 while (lp->tx_free < DWCEQOS_TX_DCNT) {
1670 struct dwceqos_dma_desc *dd = &lp->tx_descs[lp->tx_cur];
1671 struct ring_desc *rd = &lp->tx_skb[lp->tx_cur];
1673 /* Descriptor still being held by DMA ? */
1674 if (dd->des3 & DWCEQOS_DMA_TDES3_OWN)
1678 dma_unmap_single(ndev->dev.parent, rd->mapping, rd->len,
1681 if (unlikely(rd->skb)) {
1683 tx_bytes += rd->skb->len;
1684 dev_consume_skb_any(rd->skb);
1690 lp->tx_cur = (lp->tx_cur + 1) % DWCEQOS_TX_DCNT;
1692 if ((dd->des3 & DWCEQOS_DMA_TDES3_LD) &&
1693 (dd->des3 & DWCEQOS_DMA_RDES3_ES)) {
1694 if (netif_msg_tx_err(lp))
1695 netdev_err(ndev, "TX Error, TDES3 = 0x%x\n",
1697 if (netif_msg_hw(lp))
1701 spin_unlock(&lp->tx_lock);
1703 netdev_completed_queue(ndev, tx_packets, tx_bytes);
1705 dwceqos_dma_enable_txirq(lp);
1706 netif_wake_queue(ndev);
1709 static int dwceqos_rx(struct net_local *lp, int budget)
1711 struct sk_buff *skb;
1713 unsigned int n_packets = 0;
1714 unsigned int n_descs = 0;
1717 struct dwceqos_dma_desc *dd;
1718 struct sk_buff *new_skb;
1719 dma_addr_t new_skb_baddr = 0;
1721 while (n_descs < budget) {
1722 if (!dwceqos_packet_avail(lp))
1725 new_skb = netdev_alloc_skb(lp->ndev, DWCEQOS_RX_BUF_SIZE);
1727 netdev_err(lp->ndev, "no memory for new sk_buff\n");
1731 /* Get dma handle of skb->data */
1732 new_skb_baddr = (u32)dma_map_single(lp->ndev->dev.parent,
1734 DWCEQOS_RX_BUF_SIZE,
1736 if (dma_mapping_error(lp->ndev->dev.parent, new_skb_baddr)) {
1737 netdev_err(lp->ndev, "DMA map error\n");
1738 dev_kfree_skb(new_skb);
1742 /* Read descriptor data after reading owner bit. */
1745 dd = &lp->rx_descs[lp->rx_cur];
1746 len = DWCEQOS_DMA_RDES3_PL(dd->des3);
1747 skb = lp->rx_skb[lp->rx_cur].skb;
1749 /* Unmap old buffer */
1750 dma_unmap_single(lp->ndev->dev.parent,
1751 lp->rx_skb[lp->rx_cur].mapping,
1752 lp->rx_skb[lp->rx_cur].len, DMA_FROM_DEVICE);
1754 /* Discard packet on reception error or bad checksum */
1755 if ((dd->des3 & DWCEQOS_DMA_RDES3_ES) ||
1756 (dd->des1 & DWCEQOS_DMA_RDES1_IPCE)) {
1761 skb->protocol = eth_type_trans(skb, lp->ndev);
1762 switch (dd->des1 & DWCEQOS_DMA_RDES1_PT) {
1763 case DWCEQOS_DMA_RDES1_PT_UDP:
1764 case DWCEQOS_DMA_RDES1_PT_TCP:
1765 case DWCEQOS_DMA_RDES1_PT_ICMP:
1766 skb->ip_summed = CHECKSUM_UNNECESSARY;
1769 skb->ip_summed = CHECKSUM_NONE;
1774 if (unlikely(!skb)) {
1775 if (netif_msg_rx_err(lp))
1776 netdev_dbg(lp->ndev, "rx error: des3=%X\n",
1777 lp->rx_descs[lp->rx_cur].des3);
1779 tot_size += skb->len;
1782 netif_receive_skb(skb);
1785 lp->rx_descs[lp->rx_cur].des0 = new_skb_baddr;
1786 lp->rx_descs[lp->rx_cur].des1 = 0;
1787 lp->rx_descs[lp->rx_cur].des2 = 0;
1788 /* The DMA must observe des0/1/2 written before des3. */
1790 lp->rx_descs[lp->rx_cur].des3 = DWCEQOS_DMA_RDES3_INTE |
1791 DWCEQOS_DMA_RDES3_OWN |
1792 DWCEQOS_DMA_RDES3_BUF1V;
1794 lp->rx_skb[lp->rx_cur].mapping = new_skb_baddr;
1795 lp->rx_skb[lp->rx_cur].len = DWCEQOS_RX_BUF_SIZE;
1796 lp->rx_skb[lp->rx_cur].skb = new_skb;
1799 lp->rx_cur = (lp->rx_cur + 1) % DWCEQOS_RX_DCNT;
1802 /* Make sure any ownership update is written to the descriptors before
1807 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_STA, DWCEQOS_DMA_CH0_IS_RI);
1808 /* Wake up RX by writing tail pointer */
1809 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_TAIL,
1810 lp->rx_descs_tail_addr);
1815 static int dwceqos_rx_poll(struct napi_struct *napi, int budget)
1817 struct net_local *lp = container_of(napi, struct net_local, napi);
1820 work_done = dwceqos_rx(lp, budget - work_done);
1822 if (!dwceqos_packet_avail(lp) && work_done < budget) {
1823 napi_complete(napi);
1824 dwceqos_dma_enable_rxirq(lp);
1832 /* Reinitialize function if a TX timed out */
1833 static void dwceqos_reinit_for_txtimeout(struct work_struct *data)
1835 struct net_local *lp = container_of(data, struct net_local,
1838 netdev_err(lp->ndev, "transmit timeout %d s, resetting...\n",
1839 DWCEQOS_TX_TIMEOUT);
1841 if (netif_msg_hw(lp))
1845 dwceqos_stop(lp->ndev);
1846 dwceqos_open(lp->ndev);
1850 /* DT Probing function called by main probe */
1851 static inline int dwceqos_probe_config_dt(struct platform_device *pdev)
1853 struct net_device *ndev;
1854 struct net_local *lp;
1855 const void *mac_address;
1856 struct dwceqos_bus_cfg *bus_cfg;
1857 struct device_node *np = pdev->dev.of_node;
1859 ndev = platform_get_drvdata(pdev);
1860 lp = netdev_priv(ndev);
1861 bus_cfg = &lp->bus_cfg;
1863 /* Set the MAC address. */
1864 mac_address = of_get_mac_address(pdev->dev.of_node);
1866 ether_addr_copy(ndev->dev_addr, mac_address);
1868 /* These are all optional parameters */
1869 lp->en_tx_lpi_clockgating = of_property_read_bool(np,
1870 "snps,en-tx-lpi-clockgating");
1871 bus_cfg->en_lpi = of_property_read_bool(np, "snps,en-lpi");
1872 of_property_read_u32(np, "snps,write-requests",
1873 &bus_cfg->write_requests);
1874 of_property_read_u32(np, "snps,read-requests", &bus_cfg->read_requests);
1875 of_property_read_u32(np, "snps,burst-map", &bus_cfg->burst_map);
1876 of_property_read_u32(np, "snps,txpbl", &bus_cfg->tx_pbl);
1877 of_property_read_u32(np, "snps,rxpbl", &bus_cfg->rx_pbl);
1879 netdev_dbg(ndev, "BusCfg: lpi:%u wr:%u rr:%u bm:%X rxpbl:%u txpbl:%d\n",
1881 bus_cfg->write_requests,
1882 bus_cfg->read_requests,
1890 static int dwceqos_open(struct net_device *ndev)
1892 struct net_local *lp = netdev_priv(ndev);
1895 dwceqos_reset_state(lp);
1896 res = dwceqos_descriptor_init(lp);
1898 netdev_err(ndev, "Unable to allocate DMA memory, rc %d\n", res);
1901 netdev_reset_queue(ndev);
1903 napi_enable(&lp->napi);
1904 phy_start(lp->phy_dev);
1905 dwceqos_init_hw(lp);
1907 netif_start_queue(ndev);
1908 tasklet_enable(&lp->tx_bdreclaim_tasklet);
1913 static bool dweqos_is_tx_dma_suspended(struct net_local *lp)
1917 reg = dwceqos_read(lp, REG_DWCEQOS_DMA_DEBUG_ST0);
1918 reg = DMA_GET_TX_STATE_CH0(reg);
1920 return reg == DMA_TX_CH_SUSPENDED;
1923 static void dwceqos_drain_dma(struct net_local *lp)
1925 /* Wait for all pending TX buffers to be sent. Upper limit based
1926 * on max frame size on a 10 Mbit link.
1928 size_t limit = (DWCEQOS_TX_DCNT * 1250) / 100;
1930 while (!dweqos_is_tx_dma_suspended(lp) && limit--)
1931 usleep_range(100, 200);
1934 static int dwceqos_stop(struct net_device *ndev)
1936 struct net_local *lp = netdev_priv(ndev);
1938 phy_stop(lp->phy_dev);
1940 tasklet_disable(&lp->tx_bdreclaim_tasklet);
1941 netif_stop_queue(ndev);
1942 napi_disable(&lp->napi);
1944 dwceqos_drain_dma(lp);
1946 netif_tx_lock(lp->ndev);
1947 dwceqos_reset_hw(lp);
1948 dwceqos_descriptor_free(lp);
1949 netif_tx_unlock(lp->ndev);
1954 static void dwceqos_dmadesc_set_ctx(struct net_local *lp,
1955 unsigned short gso_size)
1957 struct dwceqos_dma_desc *dd = &lp->tx_descs[lp->tx_next];
1961 dd->des2 = gso_size;
1962 dd->des3 = DWCEQOS_DMA_TDES3_CTXT | DWCEQOS_DMA_TDES3_TCMSSV;
1964 lp->tx_next = (lp->tx_next + 1) % DWCEQOS_TX_DCNT;
1967 static void dwceqos_tx_poll_demand(struct net_local *lp)
1969 dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL,
1970 lp->tx_descs_tail_addr);
1974 size_t nr_descriptors;
1975 size_t initial_descriptor;
1976 size_t last_descriptor;
1977 size_t prev_gso_size;
1978 size_t network_header_len;
1981 static void dwceqos_tx_prepare(struct sk_buff *skb, struct net_local *lp,
1982 struct dwceqos_tx *tx)
1987 if (skb_is_gso(skb) && skb_shinfo(skb)->gso_size != lp->gso_size)
1990 for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
1991 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1993 n += (skb_frag_size(frag) + BYTES_PER_DMA_DESC - 1) /
1997 tx->nr_descriptors = n;
1998 tx->initial_descriptor = lp->tx_next;
1999 tx->last_descriptor = lp->tx_next;
2000 tx->prev_gso_size = lp->gso_size;
2002 tx->network_header_len = skb_transport_offset(skb);
2003 if (skb_is_gso(skb))
2004 tx->network_header_len += tcp_hdrlen(skb);
2007 static int dwceqos_tx_linear(struct sk_buff *skb, struct net_local *lp,
2008 struct dwceqos_tx *tx)
2010 struct ring_desc *rd;
2011 struct dwceqos_dma_desc *dd;
2013 dma_addr_t dma_handle;
2015 if (skb_is_gso(skb) && skb_shinfo(skb)->gso_size != lp->gso_size) {
2016 dwceqos_dmadesc_set_ctx(lp, skb_shinfo(skb)->gso_size);
2017 lp->gso_size = skb_shinfo(skb)->gso_size;
2020 dma_handle = dma_map_single(lp->ndev->dev.parent, skb->data,
2021 skb_headlen(skb), DMA_TO_DEVICE);
2023 if (dma_mapping_error(lp->ndev->dev.parent, dma_handle)) {
2024 netdev_err(lp->ndev, "TX DMA Mapping error\n");
2028 rd = &lp->tx_skb[lp->tx_next];
2029 dd = &lp->tx_descs[lp->tx_next];
2032 rd->len = skb_headlen(skb);
2033 rd->mapping = dma_handle;
2035 /* Set up DMA Descriptor */
2036 dd->des0 = dma_handle;
2038 if (skb_is_gso(skb)) {
2039 payload_len = skb_headlen(skb) - tx->network_header_len;
2042 dd->des1 = dma_handle + tx->network_header_len;
2043 dd->des2 = tx->network_header_len |
2044 DWCEQOS_DMA_DES2_B2L(payload_len);
2045 dd->des3 = DWCEQOS_DMA_TDES3_TSE |
2046 DWCEQOS_DMA_DES3_THL((tcp_hdrlen(skb) / 4)) |
2047 (skb->len - tx->network_header_len);
2050 dd->des2 = skb_headlen(skb);
2051 dd->des3 = skb->len;
2053 switch (skb->ip_summed) {
2054 case CHECKSUM_PARTIAL:
2055 dd->des3 |= DWCEQOS_DMA_TDES3_CA;
2057 case CHECKSUM_UNNECESSARY:
2058 case CHECKSUM_COMPLETE:
2064 dd->des3 |= DWCEQOS_DMA_TDES3_FD;
2065 if (lp->tx_next != tx->initial_descriptor)
2066 dd->des3 |= DWCEQOS_DMA_TDES3_OWN;
2068 tx->last_descriptor = lp->tx_next;
2069 lp->tx_next = (lp->tx_next + 1) % DWCEQOS_TX_DCNT;
2074 static int dwceqos_tx_frags(struct sk_buff *skb, struct net_local *lp,
2075 struct dwceqos_tx *tx)
2077 struct ring_desc *rd = NULL;
2078 struct dwceqos_dma_desc *dd;
2079 dma_addr_t dma_handle;
2082 /* Setup more ring and DMA descriptor if the packet is fragmented */
2083 for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
2084 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2086 size_t consumed_size;
2089 dma_handle = skb_frag_dma_map(lp->ndev->dev.parent, frag, 0,
2090 skb_frag_size(frag),
2092 if (dma_mapping_error(lp->ndev->dev.parent, dma_handle)) {
2093 netdev_err(lp->ndev, "DMA Mapping error\n");
2097 /* order-3 fragments span more than one descriptor. */
2098 frag_size = skb_frag_size(frag);
2100 while (consumed_size < frag_size) {
2101 size_t dma_size = min_t(size_t, 16376,
2102 frag_size - consumed_size);
2104 rd = &lp->tx_skb[lp->tx_next];
2105 memset(rd, 0, sizeof(*rd));
2107 dd = &lp->tx_descs[lp->tx_next];
2109 /* Set DMA Descriptor fields */
2110 dd->des0 = dma_handle;
2112 dd->des2 = dma_size;
2114 if (skb_is_gso(skb))
2115 dd->des3 = (skb->len - tx->network_header_len);
2117 dd->des3 = skb->len;
2119 dd->des3 |= DWCEQOS_DMA_TDES3_OWN;
2121 tx->last_descriptor = lp->tx_next;
2122 lp->tx_next = (lp->tx_next + 1) % DWCEQOS_TX_DCNT;
2123 consumed_size += dma_size;
2126 rd->len = skb_frag_size(frag);
2127 rd->mapping = dma_handle;
2133 static void dwceqos_tx_finalize(struct sk_buff *skb, struct net_local *lp,
2134 struct dwceqos_tx *tx)
2136 lp->tx_descs[tx->last_descriptor].des3 |= DWCEQOS_DMA_TDES3_LD;
2137 lp->tx_descs[tx->last_descriptor].des2 |= DWCEQOS_DMA_TDES2_IOC;
2139 lp->tx_skb[tx->last_descriptor].skb = skb;
2141 /* Make all descriptor updates visible to the DMA before setting the
2146 lp->tx_descs[tx->initial_descriptor].des3 |= DWCEQOS_DMA_TDES3_OWN;
2148 /* Make the owner bit visible before TX wakeup. */
2151 dwceqos_tx_poll_demand(lp);
2154 static void dwceqos_tx_rollback(struct net_local *lp, struct dwceqos_tx *tx)
2156 size_t i = tx->initial_descriptor;
2158 while (i != lp->tx_next) {
2159 if (lp->tx_skb[i].mapping)
2160 dma_unmap_single(lp->ndev->dev.parent,
2161 lp->tx_skb[i].mapping,
2165 lp->tx_skb[i].mapping = 0;
2166 lp->tx_skb[i].skb = NULL;
2168 memset(&lp->tx_descs[i], 0, sizeof(lp->tx_descs[i]));
2170 i = (i + 1) % DWCEQOS_TX_DCNT;
2173 lp->tx_next = tx->initial_descriptor;
2174 lp->gso_size = tx->prev_gso_size;
2177 static int dwceqos_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2179 struct net_local *lp = netdev_priv(ndev);
2180 struct dwceqos_tx trans;
2183 dwceqos_tx_prepare(skb, lp, &trans);
2184 if (lp->tx_free < trans.nr_descriptors) {
2185 netif_stop_queue(ndev);
2186 return NETDEV_TX_BUSY;
2189 err = dwceqos_tx_linear(skb, lp, &trans);
2193 err = dwceqos_tx_frags(skb, lp, &trans);
2197 WARN_ON(lp->tx_next !=
2198 ((trans.initial_descriptor + trans.nr_descriptors) %
2201 dwceqos_tx_finalize(skb, lp, &trans);
2203 netdev_sent_queue(ndev, skb->len);
2205 spin_lock_bh(&lp->tx_lock);
2206 lp->tx_free -= trans.nr_descriptors;
2207 spin_unlock_bh(&lp->tx_lock);
2209 ndev->trans_start = jiffies;
2213 dwceqos_tx_rollback(lp, &trans);
2218 /* Set MAC address and then update HW accordingly */
2219 static int dwceqos_set_mac_address(struct net_device *ndev, void *addr)
2221 struct net_local *lp = netdev_priv(ndev);
2222 struct sockaddr *hwaddr = (struct sockaddr *)addr;
2224 if (netif_running(ndev))
2227 if (!is_valid_ether_addr(hwaddr->sa_data))
2228 return -EADDRNOTAVAIL;
2230 memcpy(ndev->dev_addr, hwaddr->sa_data, ndev->addr_len);
2232 dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
2236 static void dwceqos_tx_timeout(struct net_device *ndev)
2238 struct net_local *lp = netdev_priv(ndev);
2240 queue_work(lp->txtimeout_handler_wq, &lp->txtimeout_reinit);
2243 static void dwceqos_set_umac_addr(struct net_local *lp, unsigned char *addr,
2248 data = (addr[5] << 8) | addr[4];
2249 dwceqos_write(lp, DWCEQOS_ADDR_HIGH(reg_n),
2250 data | DWCEQOS_MAC_MAC_ADDR_HI_EN);
2251 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
2252 dwceqos_write(lp, DWCEQOS_ADDR_LOW(reg_n), data);
2255 static void dwceqos_disable_umac_addr(struct net_local *lp, unsigned int reg_n)
2257 /* Do not disable MAC address 0 */
2259 dwceqos_write(lp, DWCEQOS_ADDR_HIGH(reg_n), 0);
2262 static void dwceqos_set_rx_mode(struct net_device *ndev)
2264 struct net_local *lp = netdev_priv(ndev);
2268 struct netdev_hw_addr *ha;
2269 unsigned int max_mac_addr;
2271 max_mac_addr = DWCEQOS_MAX_PERFECT_ADDRESSES(lp->feature1);
2273 if (ndev->flags & IFF_PROMISC) {
2274 regval = DWCEQOS_MAC_PKT_FILT_PR;
2275 } else if (((netdev_mc_count(ndev) > DWCEQOS_HASH_TABLE_SIZE) ||
2276 (ndev->flags & IFF_ALLMULTI))) {
2277 regval = DWCEQOS_MAC_PKT_FILT_PM;
2278 dwceqos_write(lp, REG_DWCEQOS_HASTABLE_LO, 0xffffffff);
2279 dwceqos_write(lp, REG_DWCEQOS_HASTABLE_HI, 0xffffffff);
2280 } else if (!netdev_mc_empty(ndev)) {
2281 regval = DWCEQOS_MAC_PKT_FILT_HMC;
2282 memset(mc_filter, 0, sizeof(mc_filter));
2283 netdev_for_each_mc_addr(ha, ndev) {
2284 /* The upper 6 bits of the calculated CRC are used to
2285 * index the contens of the hash table
2287 int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
2288 /* The most significant bit determines the register
2289 * to use (H/L) while the other 5 bits determine
2290 * the bit within the register.
2292 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2294 dwceqos_write(lp, REG_DWCEQOS_HASTABLE_LO, mc_filter[0]);
2295 dwceqos_write(lp, REG_DWCEQOS_HASTABLE_HI, mc_filter[1]);
2297 if (netdev_uc_count(ndev) > max_mac_addr) {
2298 regval |= DWCEQOS_MAC_PKT_FILT_PR;
2300 netdev_for_each_uc_addr(ha, ndev) {
2301 dwceqos_set_umac_addr(lp, ha->addr, reg);
2304 for (; reg < DWCEQOS_MAX_PERFECT_ADDRESSES(lp->feature1); reg++)
2305 dwceqos_disable_umac_addr(lp, reg);
2307 dwceqos_write(lp, REG_DWCEQOS_MAC_PKT_FILT, regval);
2310 #ifdef CONFIG_NET_POLL_CONTROLLER
2311 static void dwceqos_poll_controller(struct net_device *ndev)
2313 disable_irq(ndev->irq);
2314 dwceqos_interrupt(ndev->irq, ndev);
2315 enable_irq(ndev->irq);
2319 static void dwceqos_read_mmc_counters(struct net_local *lp, u32 rx_mask,
2322 if (tx_mask & BIT(27))
2323 lp->mmc_counters.txlpitranscntr +=
2324 dwceqos_read(lp, DWC_MMC_TXLPITRANSCNTR);
2325 if (tx_mask & BIT(26))
2326 lp->mmc_counters.txpiuscntr +=
2327 dwceqos_read(lp, DWC_MMC_TXLPIUSCNTR);
2328 if (tx_mask & BIT(25))
2329 lp->mmc_counters.txoversize_g +=
2330 dwceqos_read(lp, DWC_MMC_TXOVERSIZE_G);
2331 if (tx_mask & BIT(24))
2332 lp->mmc_counters.txvlanpackets_g +=
2333 dwceqos_read(lp, DWC_MMC_TXVLANPACKETS_G);
2334 if (tx_mask & BIT(23))
2335 lp->mmc_counters.txpausepackets +=
2336 dwceqos_read(lp, DWC_MMC_TXPAUSEPACKETS);
2337 if (tx_mask & BIT(22))
2338 lp->mmc_counters.txexcessdef +=
2339 dwceqos_read(lp, DWC_MMC_TXEXCESSDEF);
2340 if (tx_mask & BIT(21))
2341 lp->mmc_counters.txpacketcount_g +=
2342 dwceqos_read(lp, DWC_MMC_TXPACKETCOUNT_G);
2343 if (tx_mask & BIT(20))
2344 lp->mmc_counters.txoctetcount_g +=
2345 dwceqos_read(lp, DWC_MMC_TXOCTETCOUNT_G);
2346 if (tx_mask & BIT(19))
2347 lp->mmc_counters.txcarriererror +=
2348 dwceqos_read(lp, DWC_MMC_TXCARRIERERROR);
2349 if (tx_mask & BIT(18))
2350 lp->mmc_counters.txexcesscol +=
2351 dwceqos_read(lp, DWC_MMC_TXEXCESSCOL);
2352 if (tx_mask & BIT(17))
2353 lp->mmc_counters.txlatecol +=
2354 dwceqos_read(lp, DWC_MMC_TXLATECOL);
2355 if (tx_mask & BIT(16))
2356 lp->mmc_counters.txdeferred +=
2357 dwceqos_read(lp, DWC_MMC_TXDEFERRED);
2358 if (tx_mask & BIT(15))
2359 lp->mmc_counters.txmulticol_g +=
2360 dwceqos_read(lp, DWC_MMC_TXMULTICOL_G);
2361 if (tx_mask & BIT(14))
2362 lp->mmc_counters.txsinglecol_g +=
2363 dwceqos_read(lp, DWC_MMC_TXSINGLECOL_G);
2364 if (tx_mask & BIT(13))
2365 lp->mmc_counters.txunderflowerror +=
2366 dwceqos_read(lp, DWC_MMC_TXUNDERFLOWERROR);
2367 if (tx_mask & BIT(12))
2368 lp->mmc_counters.txbroadcastpackets_gb +=
2369 dwceqos_read(lp, DWC_MMC_TXBROADCASTPACKETS_GB);
2370 if (tx_mask & BIT(11))
2371 lp->mmc_counters.txmulticastpackets_gb +=
2372 dwceqos_read(lp, DWC_MMC_TXMULTICASTPACKETS_GB);
2373 if (tx_mask & BIT(10))
2374 lp->mmc_counters.txunicastpackets_gb +=
2375 dwceqos_read(lp, DWC_MMC_TXUNICASTPACKETS_GB);
2376 if (tx_mask & BIT(9))
2377 lp->mmc_counters.tx1024tomaxoctets_gb +=
2378 dwceqos_read(lp, DWC_MMC_TX1024TOMAXOCTETS_GB);
2379 if (tx_mask & BIT(8))
2380 lp->mmc_counters.tx512to1023octets_gb +=
2381 dwceqos_read(lp, DWC_MMC_TX512TO1023OCTETS_GB);
2382 if (tx_mask & BIT(7))
2383 lp->mmc_counters.tx256to511octets_gb +=
2384 dwceqos_read(lp, DWC_MMC_TX256TO511OCTETS_GB);
2385 if (tx_mask & BIT(6))
2386 lp->mmc_counters.tx128to255octets_gb +=
2387 dwceqos_read(lp, DWC_MMC_TX128TO255OCTETS_GB);
2388 if (tx_mask & BIT(5))
2389 lp->mmc_counters.tx65to127octets_gb +=
2390 dwceqos_read(lp, DWC_MMC_TX65TO127OCTETS_GB);
2391 if (tx_mask & BIT(4))
2392 lp->mmc_counters.tx64octets_gb +=
2393 dwceqos_read(lp, DWC_MMC_TX64OCTETS_GB);
2394 if (tx_mask & BIT(3))
2395 lp->mmc_counters.txmulticastpackets_g +=
2396 dwceqos_read(lp, DWC_MMC_TXMULTICASTPACKETS_G);
2397 if (tx_mask & BIT(2))
2398 lp->mmc_counters.txbroadcastpackets_g +=
2399 dwceqos_read(lp, DWC_MMC_TXBROADCASTPACKETS_G);
2400 if (tx_mask & BIT(1))
2401 lp->mmc_counters.txpacketcount_gb +=
2402 dwceqos_read(lp, DWC_MMC_TXPACKETCOUNT_GB);
2403 if (tx_mask & BIT(0))
2404 lp->mmc_counters.txoctetcount_gb +=
2405 dwceqos_read(lp, DWC_MMC_TXOCTETCOUNT_GB);
2407 if (rx_mask & BIT(27))
2408 lp->mmc_counters.rxlpitranscntr +=
2409 dwceqos_read(lp, DWC_MMC_RXLPITRANSCNTR);
2410 if (rx_mask & BIT(26))
2411 lp->mmc_counters.rxlpiuscntr +=
2412 dwceqos_read(lp, DWC_MMC_RXLPIUSCNTR);
2413 if (rx_mask & BIT(25))
2414 lp->mmc_counters.rxctrlpackets_g +=
2415 dwceqos_read(lp, DWC_MMC_RXCTRLPACKETS_G);
2416 if (rx_mask & BIT(24))
2417 lp->mmc_counters.rxrcverror +=
2418 dwceqos_read(lp, DWC_MMC_RXRCVERROR);
2419 if (rx_mask & BIT(23))
2420 lp->mmc_counters.rxwatchdog +=
2421 dwceqos_read(lp, DWC_MMC_RXWATCHDOG);
2422 if (rx_mask & BIT(22))
2423 lp->mmc_counters.rxvlanpackets_gb +=
2424 dwceqos_read(lp, DWC_MMC_RXVLANPACKETS_GB);
2425 if (rx_mask & BIT(21))
2426 lp->mmc_counters.rxfifooverflow +=
2427 dwceqos_read(lp, DWC_MMC_RXFIFOOVERFLOW);
2428 if (rx_mask & BIT(20))
2429 lp->mmc_counters.rxpausepackets +=
2430 dwceqos_read(lp, DWC_MMC_RXPAUSEPACKETS);
2431 if (rx_mask & BIT(19))
2432 lp->mmc_counters.rxoutofrangetype +=
2433 dwceqos_read(lp, DWC_MMC_RXOUTOFRANGETYPE);
2434 if (rx_mask & BIT(18))
2435 lp->mmc_counters.rxlengtherror +=
2436 dwceqos_read(lp, DWC_MMC_RXLENGTHERROR);
2437 if (rx_mask & BIT(17))
2438 lp->mmc_counters.rxunicastpackets_g +=
2439 dwceqos_read(lp, DWC_MMC_RXUNICASTPACKETS_G);
2440 if (rx_mask & BIT(16))
2441 lp->mmc_counters.rx1024tomaxoctets_gb +=
2442 dwceqos_read(lp, DWC_MMC_RX1024TOMAXOCTETS_GB);
2443 if (rx_mask & BIT(15))
2444 lp->mmc_counters.rx512to1023octets_gb +=
2445 dwceqos_read(lp, DWC_MMC_RX512TO1023OCTETS_GB);
2446 if (rx_mask & BIT(14))
2447 lp->mmc_counters.rx256to511octets_gb +=
2448 dwceqos_read(lp, DWC_MMC_RX256TO511OCTETS_GB);
2449 if (rx_mask & BIT(13))
2450 lp->mmc_counters.rx128to255octets_gb +=
2451 dwceqos_read(lp, DWC_MMC_RX128TO255OCTETS_GB);
2452 if (rx_mask & BIT(12))
2453 lp->mmc_counters.rx65to127octets_gb +=
2454 dwceqos_read(lp, DWC_MMC_RX65TO127OCTETS_GB);
2455 if (rx_mask & BIT(11))
2456 lp->mmc_counters.rx64octets_gb +=
2457 dwceqos_read(lp, DWC_MMC_RX64OCTETS_GB);
2458 if (rx_mask & BIT(10))
2459 lp->mmc_counters.rxoversize_g +=
2460 dwceqos_read(lp, DWC_MMC_RXOVERSIZE_G);
2461 if (rx_mask & BIT(9))
2462 lp->mmc_counters.rxundersize_g +=
2463 dwceqos_read(lp, DWC_MMC_RXUNDERSIZE_G);
2464 if (rx_mask & BIT(8))
2465 lp->mmc_counters.rxjabbererror +=
2466 dwceqos_read(lp, DWC_MMC_RXJABBERERROR);
2467 if (rx_mask & BIT(7))
2468 lp->mmc_counters.rxrunterror +=
2469 dwceqos_read(lp, DWC_MMC_RXRUNTERROR);
2470 if (rx_mask & BIT(6))
2471 lp->mmc_counters.rxalignmenterror +=
2472 dwceqos_read(lp, DWC_MMC_RXALIGNMENTERROR);
2473 if (rx_mask & BIT(5))
2474 lp->mmc_counters.rxcrcerror +=
2475 dwceqos_read(lp, DWC_MMC_RXCRCERROR);
2476 if (rx_mask & BIT(4))
2477 lp->mmc_counters.rxmulticastpackets_g +=
2478 dwceqos_read(lp, DWC_MMC_RXMULTICASTPACKETS_G);
2479 if (rx_mask & BIT(3))
2480 lp->mmc_counters.rxbroadcastpackets_g +=
2481 dwceqos_read(lp, DWC_MMC_RXBROADCASTPACKETS_G);
2482 if (rx_mask & BIT(2))
2483 lp->mmc_counters.rxoctetcount_g +=
2484 dwceqos_read(lp, DWC_MMC_RXOCTETCOUNT_G);
2485 if (rx_mask & BIT(1))
2486 lp->mmc_counters.rxoctetcount_gb +=
2487 dwceqos_read(lp, DWC_MMC_RXOCTETCOUNT_GB);
2488 if (rx_mask & BIT(0))
2489 lp->mmc_counters.rxpacketcount_gb +=
2490 dwceqos_read(lp, DWC_MMC_RXPACKETCOUNT_GB);
2493 static struct rtnl_link_stats64*
2494 dwceqos_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *s)
2496 unsigned long flags;
2497 struct net_local *lp = netdev_priv(ndev);
2498 struct dwceqos_mmc_counters *hwstats = &lp->mmc_counters;
2500 spin_lock_irqsave(&lp->stats_lock, flags);
2501 dwceqos_read_mmc_counters(lp, lp->mmc_rx_counters_mask,
2502 lp->mmc_tx_counters_mask);
2503 spin_unlock_irqrestore(&lp->stats_lock, flags);
2505 s->rx_packets = hwstats->rxpacketcount_gb;
2506 s->rx_bytes = hwstats->rxoctetcount_gb;
2507 s->rx_errors = hwstats->rxpacketcount_gb -
2508 hwstats->rxbroadcastpackets_g -
2509 hwstats->rxmulticastpackets_g -
2510 hwstats->rxunicastpackets_g;
2511 s->multicast = hwstats->rxmulticastpackets_g;
2512 s->rx_length_errors = hwstats->rxlengtherror;
2513 s->rx_crc_errors = hwstats->rxcrcerror;
2514 s->rx_fifo_errors = hwstats->rxfifooverflow;
2516 s->tx_packets = hwstats->txpacketcount_gb;
2517 s->tx_bytes = hwstats->txoctetcount_gb;
2519 if (lp->mmc_tx_counters_mask & BIT(21))
2520 s->tx_errors = hwstats->txpacketcount_gb -
2521 hwstats->txpacketcount_g;
2523 s->tx_errors = hwstats->txunderflowerror +
2524 hwstats->txcarriererror;
2530 dwceqos_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
2532 struct net_local *lp = netdev_priv(ndev);
2533 struct phy_device *phydev = lp->phy_dev;
2538 return phy_ethtool_gset(phydev, ecmd);
2542 dwceqos_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
2544 struct net_local *lp = netdev_priv(ndev);
2545 struct phy_device *phydev = lp->phy_dev;
2550 return phy_ethtool_sset(phydev, ecmd);
2554 dwceqos_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *ed)
2556 const struct net_local *lp = netdev_priv(ndev);
2558 strcpy(ed->driver, lp->pdev->dev.driver->name);
2559 strcpy(ed->version, DRIVER_VERSION);
2562 static void dwceqos_get_pauseparam(struct net_device *ndev,
2563 struct ethtool_pauseparam *pp)
2565 const struct net_local *lp = netdev_priv(ndev);
2567 pp->autoneg = lp->flowcontrol.autoneg;
2568 pp->tx_pause = lp->flowcontrol.tx;
2569 pp->rx_pause = lp->flowcontrol.rx;
2572 static int dwceqos_set_pauseparam(struct net_device *ndev,
2573 struct ethtool_pauseparam *pp)
2575 struct net_local *lp = netdev_priv(ndev);
2578 lp->flowcontrol.autoneg = pp->autoneg;
2580 lp->phy_dev->advertising |= ADVERTISED_Pause;
2581 lp->phy_dev->advertising |= ADVERTISED_Asym_Pause;
2583 lp->phy_dev->advertising &= ~ADVERTISED_Pause;
2584 lp->phy_dev->advertising &= ~ADVERTISED_Asym_Pause;
2585 lp->flowcontrol.rx = pp->rx_pause;
2586 lp->flowcontrol.tx = pp->tx_pause;
2589 if (netif_running(ndev))
2590 ret = phy_start_aneg(lp->phy_dev);
2595 static void dwceqos_get_strings(struct net_device *ndev, u32 stringset,
2600 if (stringset != ETH_SS_STATS)
2603 for (i = 0; i < ARRAY_SIZE(dwceqos_ethtool_stats); ++i) {
2604 memcpy(data, dwceqos_ethtool_stats[i].stat_name,
2606 data += ETH_GSTRING_LEN;
2610 static void dwceqos_get_ethtool_stats(struct net_device *ndev,
2611 struct ethtool_stats *stats, u64 *data)
2613 struct net_local *lp = netdev_priv(ndev);
2614 unsigned long flags;
2616 u8 *mmcstat = (u8 *)&lp->mmc_counters;
2618 spin_lock_irqsave(&lp->stats_lock, flags);
2619 dwceqos_read_mmc_counters(lp, lp->mmc_rx_counters_mask,
2620 lp->mmc_tx_counters_mask);
2621 spin_unlock_irqrestore(&lp->stats_lock, flags);
2623 for (i = 0; i < ARRAY_SIZE(dwceqos_ethtool_stats); ++i) {
2625 mmcstat + dwceqos_ethtool_stats[i].offset,
2631 static int dwceqos_get_sset_count(struct net_device *ndev, int sset)
2633 if (sset == ETH_SS_STATS)
2634 return ARRAY_SIZE(dwceqos_ethtool_stats);
2639 static void dwceqos_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2642 const struct net_local *lp = netdev_priv(dev);
2643 u32 *reg_space = (u32 *)space;
2648 for (reg_offset = START_MAC_REG_OFFSET;
2649 reg_offset <= MAX_DMA_REG_OFFSET; reg_offset += 4) {
2650 reg_space[reg_ix] = dwceqos_read(lp, reg_offset);
2654 for (reg_offset = START_MTL_REG_OFFSET;
2655 reg_offset <= MAX_MTL_REG_OFFSET; reg_offset += 4) {
2656 reg_space[reg_ix] = dwceqos_read(lp, reg_offset);
2661 for (reg_offset = START_DMA_REG_OFFSET;
2662 reg_offset <= MAX_DMA_REG_OFFSET; reg_offset += 4) {
2663 reg_space[reg_ix] = dwceqos_read(lp, reg_offset);
2667 BUG_ON(4 * reg_ix > REG_SPACE_SIZE);
2670 static int dwceqos_get_regs_len(struct net_device *dev)
2672 return REG_SPACE_SIZE;
2675 static inline const char *dwceqos_get_rx_lpi_state(u32 lpi_ctrl)
2677 return (lpi_ctrl & DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIST) ? "on" : "off";
2680 static inline const char *dwceqos_get_tx_lpi_state(u32 lpi_ctrl)
2682 return (lpi_ctrl & DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIST) ? "on" : "off";
2685 static int dwceqos_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2687 struct net_local *lp = netdev_priv(ndev);
2691 if (!(lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_EEESEL))
2694 edata->eee_active = lp->eee_active;
2695 edata->eee_enabled = lp->eee_enabled;
2696 edata->tx_lpi_timer = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_ENTRY_TIMER);
2697 lpi_status = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
2698 lpi_enabled = !!(lpi_status & DWCEQOS_MAC_LPI_CTRL_STATUS_LIPTXA);
2699 edata->tx_lpi_enabled = lpi_enabled;
2701 if (netif_msg_hw(lp)) {
2704 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
2706 netdev_info(lp->ndev, "MAC LPI State: RX:%s TX:%s\n",
2707 dwceqos_get_rx_lpi_state(regval),
2708 dwceqos_get_tx_lpi_state(regval));
2711 return phy_ethtool_get_eee(lp->phy_dev, edata);
2714 static int dwceqos_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2716 struct net_local *lp = netdev_priv(ndev);
2718 unsigned long flags;
2720 if (!(lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_EEESEL))
2723 if (edata->eee_enabled && !lp->eee_active)
2726 if (edata->tx_lpi_enabled) {
2727 if (edata->tx_lpi_timer < DWCEQOS_LPI_TIMER_MIN ||
2728 edata->tx_lpi_timer > DWCEQOS_LPI_TIMER_MAX)
2732 lp->eee_enabled = edata->eee_enabled;
2734 if (edata->eee_enabled && edata->tx_lpi_enabled) {
2735 dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_ENTRY_TIMER,
2736 edata->tx_lpi_timer);
2738 spin_lock_irqsave(&lp->hw_lock, flags);
2739 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
2740 regval |= DWCEQOS_LPI_CTRL_ENABLE_EEE;
2741 if (lp->en_tx_lpi_clockgating)
2742 regval |= DWCEQOS_MAC_LPI_CTRL_STATUS_LPITCSE;
2743 dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
2744 spin_unlock_irqrestore(&lp->hw_lock, flags);
2746 spin_lock_irqsave(&lp->hw_lock, flags);
2747 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
2748 regval &= ~DWCEQOS_LPI_CTRL_ENABLE_EEE;
2749 dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
2750 spin_unlock_irqrestore(&lp->hw_lock, flags);
2753 return phy_ethtool_set_eee(lp->phy_dev, edata);
2756 static u32 dwceqos_get_msglevel(struct net_device *ndev)
2758 const struct net_local *lp = netdev_priv(ndev);
2760 return lp->msg_enable;
2763 static void dwceqos_set_msglevel(struct net_device *ndev, u32 msglevel)
2765 struct net_local *lp = netdev_priv(ndev);
2767 lp->msg_enable = msglevel;
2770 static struct ethtool_ops dwceqos_ethtool_ops = {
2771 .get_settings = dwceqos_get_settings,
2772 .set_settings = dwceqos_set_settings,
2773 .get_drvinfo = dwceqos_get_drvinfo,
2774 .get_link = ethtool_op_get_link,
2775 .get_pauseparam = dwceqos_get_pauseparam,
2776 .set_pauseparam = dwceqos_set_pauseparam,
2777 .get_strings = dwceqos_get_strings,
2778 .get_ethtool_stats = dwceqos_get_ethtool_stats,
2779 .get_sset_count = dwceqos_get_sset_count,
2780 .get_regs = dwceqos_get_regs,
2781 .get_regs_len = dwceqos_get_regs_len,
2782 .get_eee = dwceqos_get_eee,
2783 .set_eee = dwceqos_set_eee,
2784 .get_msglevel = dwceqos_get_msglevel,
2785 .set_msglevel = dwceqos_set_msglevel,
2788 static struct net_device_ops netdev_ops = {
2789 .ndo_open = dwceqos_open,
2790 .ndo_stop = dwceqos_stop,
2791 .ndo_start_xmit = dwceqos_start_xmit,
2792 .ndo_set_rx_mode = dwceqos_set_rx_mode,
2793 .ndo_set_mac_address = dwceqos_set_mac_address,
2794 #ifdef CONFIG_NET_POLL_CONTROLLER
2795 .ndo_poll_controller = dwceqos_poll_controller,
2797 .ndo_do_ioctl = dwceqos_ioctl,
2798 .ndo_tx_timeout = dwceqos_tx_timeout,
2799 .ndo_get_stats64 = dwceqos_get_stats64,
2802 static const struct of_device_id dwceq_of_match[] = {
2803 { .compatible = "snps,dwc-qos-ethernet-4.10", },
2806 MODULE_DEVICE_TABLE(of, dwceq_of_match);
2808 static int dwceqos_probe(struct platform_device *pdev)
2810 struct resource *r_mem = NULL;
2811 struct net_device *ndev;
2812 struct net_local *lp;
2815 r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2817 dev_err(&pdev->dev, "no IO resource defined.\n");
2821 ndev = alloc_etherdev(sizeof(*lp));
2823 dev_err(&pdev->dev, "etherdev allocation failed.\n");
2827 SET_NETDEV_DEV(ndev, &pdev->dev);
2829 lp = netdev_priv(ndev);
2832 lp->msg_enable = netif_msg_init(debug, DWCEQOS_MSG_DEFAULT);
2834 spin_lock_init(&lp->tx_lock);
2835 spin_lock_init(&lp->hw_lock);
2836 spin_lock_init(&lp->stats_lock);
2838 lp->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
2839 if (IS_ERR(lp->apb_pclk)) {
2840 dev_err(&pdev->dev, "apb_pclk clock not found.\n");
2841 ret = PTR_ERR(lp->apb_pclk);
2842 goto err_out_free_netdev;
2845 ret = clk_prepare_enable(lp->apb_pclk);
2847 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
2848 goto err_out_free_netdev;
2851 lp->baseaddr = devm_ioremap_resource(&pdev->dev, r_mem);
2852 if (IS_ERR(lp->baseaddr)) {
2853 dev_err(&pdev->dev, "failed to map baseaddress.\n");
2854 ret = PTR_ERR(lp->baseaddr);
2855 goto err_out_clk_dis_aper;
2858 ndev->irq = platform_get_irq(pdev, 0);
2859 ndev->watchdog_timeo = DWCEQOS_TX_TIMEOUT * HZ;
2860 ndev->netdev_ops = &netdev_ops;
2861 ndev->ethtool_ops = &dwceqos_ethtool_ops;
2862 ndev->base_addr = r_mem->start;
2864 dwceqos_get_hwfeatures(lp);
2865 dwceqos_mdio_set_csr(lp);
2867 ndev->hw_features = NETIF_F_SG;
2869 if (lp->feature1 & DWCEQOS_MAC_HW_FEATURE1_TSOEN)
2870 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2872 if (lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_TXCOESEL)
2873 ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2875 if (lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_RXCOESEL)
2876 ndev->hw_features |= NETIF_F_RXCSUM;
2878 ndev->features = ndev->hw_features;
2880 netif_napi_add(ndev, &lp->napi, dwceqos_rx_poll, NAPI_POLL_WEIGHT);
2882 ret = register_netdev(ndev);
2884 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2885 goto err_out_clk_dis_aper;
2888 lp->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref_clk");
2889 if (IS_ERR(lp->phy_ref_clk)) {
2890 dev_err(&pdev->dev, "phy_ref_clk clock not found.\n");
2891 ret = PTR_ERR(lp->phy_ref_clk);
2892 goto err_out_unregister_netdev;
2895 ret = clk_prepare_enable(lp->phy_ref_clk);
2897 dev_err(&pdev->dev, "Unable to enable device clock.\n");
2898 goto err_out_unregister_netdev;
2901 lp->phy_node = of_parse_phandle(lp->pdev->dev.of_node,
2903 if (!lp->phy_node && of_phy_is_fixed_link(lp->pdev->dev.of_node)) {
2904 ret = of_phy_register_fixed_link(lp->pdev->dev.of_node);
2906 dev_err(&pdev->dev, "invalid fixed-link");
2907 goto err_out_unregister_netdev;
2910 lp->phy_node = of_node_get(lp->pdev->dev.of_node);
2913 ret = of_get_phy_mode(lp->pdev->dev.of_node);
2915 dev_err(&lp->pdev->dev, "error in getting phy i/f\n");
2916 goto err_out_unregister_clk_notifier;
2919 lp->phy_interface = ret;
2921 ret = dwceqos_mii_init(lp);
2923 dev_err(&lp->pdev->dev, "error in dwceqos_mii_init\n");
2924 goto err_out_unregister_clk_notifier;
2927 ret = dwceqos_mii_probe(ndev);
2929 netdev_err(ndev, "mii_probe fail.\n");
2931 goto err_out_unregister_clk_notifier;
2934 dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
2936 tasklet_init(&lp->tx_bdreclaim_tasklet, dwceqos_tx_reclaim,
2937 (unsigned long)ndev);
2938 tasklet_disable(&lp->tx_bdreclaim_tasklet);
2940 lp->txtimeout_handler_wq = create_singlethread_workqueue(DRIVER_NAME);
2941 INIT_WORK(&lp->txtimeout_reinit, dwceqos_reinit_for_txtimeout);
2943 platform_set_drvdata(pdev, ndev);
2944 ret = dwceqos_probe_config_dt(pdev);
2946 dev_err(&lp->pdev->dev, "Unable to retrieve DT, error %d\n",
2948 goto err_out_unregister_clk_notifier;
2950 dev_info(&lp->pdev->dev, "pdev->id %d, baseaddr 0x%08lx, irq %d\n",
2951 pdev->id, ndev->base_addr, ndev->irq);
2953 ret = devm_request_irq(&pdev->dev, ndev->irq, &dwceqos_interrupt, 0,
2956 dev_err(&lp->pdev->dev, "Unable to request IRQ %d, error %d\n",
2958 goto err_out_unregister_clk_notifier;
2961 if (netif_msg_probe(lp))
2962 netdev_dbg(ndev, "net_local@%p\n", lp);
2966 err_out_unregister_clk_notifier:
2967 clk_disable_unprepare(lp->phy_ref_clk);
2968 err_out_unregister_netdev:
2969 unregister_netdev(ndev);
2970 err_out_clk_dis_aper:
2971 clk_disable_unprepare(lp->apb_pclk);
2972 err_out_free_netdev:
2974 of_node_put(lp->phy_node);
2976 platform_set_drvdata(pdev, NULL);
2980 static int dwceqos_remove(struct platform_device *pdev)
2982 struct net_device *ndev = platform_get_drvdata(pdev);
2983 struct net_local *lp;
2986 lp = netdev_priv(ndev);
2989 phy_disconnect(lp->phy_dev);
2990 mdiobus_unregister(lp->mii_bus);
2991 kfree(lp->mii_bus->irq);
2992 mdiobus_free(lp->mii_bus);
2994 unregister_netdev(ndev);
2996 clk_disable_unprepare(lp->phy_ref_clk);
2997 clk_disable_unprepare(lp->apb_pclk);
3005 static struct platform_driver dwceqos_driver = {
3006 .probe = dwceqos_probe,
3007 .remove = dwceqos_remove,
3009 .name = DRIVER_NAME,
3010 .of_match_table = dwceq_of_match,
3014 module_platform_driver(dwceqos_driver);
3016 MODULE_DESCRIPTION("DWC Ethernet QoS v4.10a driver");
3017 MODULE_LICENSE("GPL v2");
3018 MODULE_AUTHOR("Andreas Irestaal <andreas.irestal@axis.com>");
3019 MODULE_AUTHOR("Lars Persson <lars.persson@axis.com>");