drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/prefetch.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #ifdef CONFIG_DEBUG_FS
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #endif /* CONFIG_DEBUG_FS */
  38 #include <linux/net_tstamp.h>
  39 #include <linux/phylink.h>
  40 #include <linux/udp.h>
  41 #include <linux/bpf_trace.h>
  42 #include <net/pkt_cls.h>
  43 #include <net/xdp_sock_drv.h>
  44 #include "stmmac_ptp.h"
  45 #include "stmmac.h"
  46 #include "stmmac_xdp.h"
  47 #include <linux/reset.h>
  48 #include <linux/of_mdio.h>
  49 #include "dwmac1000.h"
  50 #include "dwxgmac2.h"
  51 #include "hwif.h"
  52
  53 /* As long as the interface is active, we keep the timestamping counter enabled
  54  * with fine resolution and binary rollover. This avoid non-monotonic behavior
  55  * (clock jumps) when changing timestamping settings at runtime.
  56  */
  57 #define STMMAC_HWTS_ACTIVE      (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
  58                                  PTP_TCR_TSCTRLSSR)
  59
  60 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  61 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  62
  63 /* Module parameters */
  64 #define TX_TIMEO        5000
  65 static int watchdog = TX_TIMEO;
  66 module_param(watchdog, int, 0644);
  67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  68
  69 static int debug = -1;
  70 module_param(debug, int, 0644);
  71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  72
  73 static int phyaddr = -1;
  74 module_param(phyaddr, int, 0444);
  75 MODULE_PARM_DESC(phyaddr, "Physical device address");
  76
  77 #define STMMAC_TX_THRESH(x)     ((x)->dma_tx_size / 4)
  78 #define STMMAC_RX_THRESH(x)     ((x)->dma_rx_size / 4)
  79
  80 /* Limit to make sure XDP TX and slow path can coexist */
  81 #define STMMAC_XSK_TX_BUDGET_MAX        256
  82 #define STMMAC_TX_XSK_AVAIL             16
  83 #define STMMAC_RX_FILL_BATCH            16
  84
  85 #define STMMAC_XDP_PASS         0
  86 #define STMMAC_XDP_CONSUMED     BIT(0)
  87 #define STMMAC_XDP_TX           BIT(1)
  88 #define STMMAC_XDP_REDIRECT     BIT(2)
  89
  90 static int flow_ctrl = FLOW_AUTO;
  91 module_param(flow_ctrl, int, 0644);
  92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  93
  94 static int pause = PAUSE_TIME;
  95 module_param(pause, int, 0644);
  96 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  97
  98 #define TC_DEFAULT 64
  99 static int tc = TC_DEFAULT;
 100 module_param(tc, int, 0644);
 101 MODULE_PARM_DESC(tc, "DMA threshold control value");
 102
 103 #define DEFAULT_BUFSIZE 1536
 104 static int buf_sz = DEFAULT_BUFSIZE;
 105 module_param(buf_sz, int, 0644);
 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 107
 108 #define STMMAC_RX_COPYBREAK     256
 109
 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 111                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 112                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 113
 114 #define STMMAC_DEFAULT_LPI_TIMER        1000
 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 116 module_param(eee_timer, int, 0644);
 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
 119
 120 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 121  * but allow user to force to use the chain instead of the ring
 122  */
 123 static unsigned int chain_mode;
 124 module_param(chain_mode, int, 0444);
 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 126
 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 128 /* For MSI interrupts handling */
 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
 133 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
 134 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
 135 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
 136                                           u32 rxmode, u32 chan);
 137
 138 #ifdef CONFIG_DEBUG_FS
 139 static const struct net_device_ops stmmac_netdev_ops;
 140 static void stmmac_init_fs(struct net_device *dev);
 141 static void stmmac_exit_fs(struct net_device *dev);
 142 #endif
 143
 144 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
 145
 146 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
 147 {
 148         int ret = 0;
 149
 150         if (enabled) {
 151                 ret = clk_prepare_enable(priv->plat->stmmac_clk);
 152                 if (ret)
 153                         return ret;
 154                 ret = clk_prepare_enable(priv->plat->pclk);
 155                 if (ret) {
 156                         clk_disable_unprepare(priv->plat->stmmac_clk);
 157                         return ret;
 158                 }
 159                 if (priv->plat->clks_config) {
 160                         ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 161                         if (ret) {
 162                                 clk_disable_unprepare(priv->plat->stmmac_clk);
 163                                 clk_disable_unprepare(priv->plat->pclk);
 164                                 return ret;
 165                         }
 166                 }
 167         } else {
 168                 clk_disable_unprepare(priv->plat->stmmac_clk);
 169                 clk_disable_unprepare(priv->plat->pclk);
 170                 if (priv->plat->clks_config)
 171                         priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 172         }
 173
 174         return ret;
 175 }
 176 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
 177
 178 /**
 179  * stmmac_verify_args - verify the driver parameters.
 180  * Description: it checks the driver parameters and set a default in case of
 181  * errors.
 182  */
 183 static void stmmac_verify_args(void)
 184 {
 185         if (unlikely(watchdog < 0))
 186                 watchdog = TX_TIMEO;
 187         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 188                 buf_sz = DEFAULT_BUFSIZE;
 189         if (unlikely(flow_ctrl > 1))
 190                 flow_ctrl = FLOW_AUTO;
 191         else if (likely(flow_ctrl < 0))
 192                 flow_ctrl = FLOW_OFF;
 193         if (unlikely((pause < 0) || (pause > 0xffff)))
 194                 pause = PAUSE_TIME;
 195         if (eee_timer < 0)
 196                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 197 }
 198
 199 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
 200 {
 201         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 202         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 203         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 204         u32 queue;
 205
 206         for (queue = 0; queue < maxq; queue++) {
 207                 struct stmmac_channel *ch = &priv->channel[queue];
 208
 209                 if (stmmac_xdp_is_enabled(priv) &&
 210                     test_bit(queue, priv->af_xdp_zc_qps)) {
 211                         napi_disable(&ch->rxtx_napi);
 212                         continue;
 213                 }
 214
 215                 if (queue < rx_queues_cnt)
 216                         napi_disable(&ch->rx_napi);
 217                 if (queue < tx_queues_cnt)
 218                         napi_disable(&ch->tx_napi);
 219         }
 220 }
 221
 222 /**
 223  * stmmac_disable_all_queues - Disable all queues
 224  * @priv: driver private structure
 225  */
 226 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 227 {
 228         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 229         struct stmmac_rx_queue *rx_q;
 230         u32 queue;
 231
 232         /* synchronize_rcu() needed for pending XDP buffers to drain */
 233         for (queue = 0; queue < rx_queues_cnt; queue++) {
 234                 rx_q = &priv->rx_queue[queue];
 235                 if (rx_q->xsk_pool) {
 236                         synchronize_rcu();
 237                         break;
 238                 }
 239         }
 240
 241         __stmmac_disable_all_queues(priv);
 242 }
 243
 244 /**
 245  * stmmac_enable_all_queues - Enable all queues
 246  * @priv: driver private structure
 247  */
 248 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 249 {
 250         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 251         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 252         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 253         u32 queue;
 254
 255         for (queue = 0; queue < maxq; queue++) {
 256                 struct stmmac_channel *ch = &priv->channel[queue];
 257
 258                 if (stmmac_xdp_is_enabled(priv) &&
 259                     test_bit(queue, priv->af_xdp_zc_qps)) {
 260                         napi_enable(&ch->rxtx_napi);
 261                         continue;
 262                 }
 263
 264                 if (queue < rx_queues_cnt)
 265                         napi_enable(&ch->rx_napi);
 266                 if (queue < tx_queues_cnt)
 267                         napi_enable(&ch->tx_napi);
 268         }
 269 }
 270
 271 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 272 {
 273         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 274             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 275                 queue_work(priv->wq, &priv->service_task);
 276 }
 277
 278 static void stmmac_global_err(struct stmmac_priv *priv)
 279 {
 280         netif_carrier_off(priv->dev);
 281         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 282         stmmac_service_event_schedule(priv);
 283 }
 284
 285 /**
 286  * stmmac_clk_csr_set - dynamically set the MDC clock
 287  * @priv: driver private structure
 288  * Description: this is to dynamically set the MDC clock according to the csr
 289  * clock input.
 290  * Note:
 291  *      If a specific clk_csr value is passed from the platform
 292  *      this means that the CSR Clock Range selection cannot be
 293  *      changed at run-time and it is fixed (as reported in the driver
 294  *      documentation). Viceversa the driver will try to set the MDC
 295  *      clock dynamically according to the actual clock input.
 296  */
 297 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 298 {
 299         u32 clk_rate;
 300
 301         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 302
 303         /* Platform provided default clk_csr would be assumed valid
 304          * for all other cases except for the below mentioned ones.
 305          * For values higher than the IEEE 802.3 specified frequency
 306          * we can not estimate the proper divider as it is not known
 307          * the frequency of clk_csr_i. So we do not change the default
 308          * divider.
 309          */
 310         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 311                 if (clk_rate < CSR_F_35M)
 312                         priv->clk_csr = STMMAC_CSR_20_35M;
 313                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 314                         priv->clk_csr = STMMAC_CSR_35_60M;
 315                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 316                         priv->clk_csr = STMMAC_CSR_60_100M;
 317                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 318                         priv->clk_csr = STMMAC_CSR_100_150M;
 319                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 320                         priv->clk_csr = STMMAC_CSR_150_250M;
 321                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 322                         priv->clk_csr = STMMAC_CSR_250_300M;
 323         }
 324
 325         if (priv->plat->has_sun8i) {
 326                 if (clk_rate > 160000000)
 327                         priv->clk_csr = 0x03;
 328                 else if (clk_rate > 80000000)
 329                         priv->clk_csr = 0x02;
 330                 else if (clk_rate > 40000000)
 331                         priv->clk_csr = 0x01;
 332                 else
 333                         priv->clk_csr = 0;
 334         }
 335
 336         if (priv->plat->has_xgmac) {
 337                 if (clk_rate > 400000000)
 338                         priv->clk_csr = 0x5;
 339                 else if (clk_rate > 350000000)
 340                         priv->clk_csr = 0x4;
 341                 else if (clk_rate > 300000000)
 342                         priv->clk_csr = 0x3;
 343                 else if (clk_rate > 250000000)
 344                         priv->clk_csr = 0x2;
 345                 else if (clk_rate > 150000000)
 346                         priv->clk_csr = 0x1;
 347                 else
 348                         priv->clk_csr = 0x0;
 349         }
 350 }
 351
 352 static void print_pkt(unsigned char *buf, int len)
 353 {
 354         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 355         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 356 }
 357
 358 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 359 {
 360         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 361         u32 avail;
 362
 363         if (tx_q->dirty_tx > tx_q->cur_tx)
 364                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 365         else
 366                 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
 367
 368         return avail;
 369 }
 370
 371 /**
 372  * stmmac_rx_dirty - Get RX queue dirty
 373  * @priv: driver private structure
 374  * @queue: RX queue index
 375  */
 376 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 377 {
 378         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 379         u32 dirty;
 380
 381         if (rx_q->dirty_rx <= rx_q->cur_rx)
 382                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 383         else
 384                 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
 385
 386         return dirty;
 387 }
 388
 389 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
 390 {
 391         int tx_lpi_timer;
 392
 393         /* Clear/set the SW EEE timer flag based on LPI ET enablement */
 394         priv->eee_sw_timer_en = en ? 0 : 1;
 395         tx_lpi_timer  = en ? priv->tx_lpi_timer : 0;
 396         stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
 397 }
 398
 399 /**
 400  * stmmac_enable_eee_mode - check and enter in LPI mode
 401  * @priv: driver private structure
 402  * Description: this function is to verify and enter in LPI mode in case of
 403  * EEE.
 404  */
 405 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 406 {
 407         u32 tx_cnt = priv->plat->tx_queues_to_use;
 408         u32 queue;
 409
 410         /* check if all TX queues have the work finished */
 411         for (queue = 0; queue < tx_cnt; queue++) {
 412                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 413
 414                 if (tx_q->dirty_tx != tx_q->cur_tx)
 415                         return; /* still unfinished work */
 416         }
 417
 418         /* Check and enter in LPI mode */
 419         if (!priv->tx_path_in_lpi_mode)
 420                 stmmac_set_eee_mode(priv, priv->hw,
 421                                 priv->plat->en_tx_lpi_clockgating);
 422 }
 423
 424 /**
 425  * stmmac_disable_eee_mode - disable and exit from LPI mode
 426  * @priv: driver private structure
 427  * Description: this function is to exit and disable EEE in case of
 428  * LPI state is true. This is called by the xmit.
 429  */
 430 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 431 {
 432         if (!priv->eee_sw_timer_en) {
 433                 stmmac_lpi_entry_timer_config(priv, 0);
 434                 return;
 435         }
 436
 437         stmmac_reset_eee_mode(priv, priv->hw);
 438         del_timer_sync(&priv->eee_ctrl_timer);
 439         priv->tx_path_in_lpi_mode = false;
 440 }
 441
 442 /**
 443  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 444  * @t:  timer_list struct containing private info
 445  * Description:
 446  *  if there is no data transfer and if we are not in LPI state,
 447  *  then MAC Transmitter can be moved to LPI state.
 448  */
 449 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 450 {
 451         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 452
 453         stmmac_enable_eee_mode(priv);
 454         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
 455 }
 456
 457 /**
 458  * stmmac_eee_init - init EEE
 459  * @priv: driver private structure
 460  * Description:
 461  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 462  *  can also manage EEE, this function enable the LPI state and start related
 463  *  timer.
 464  */
 465 bool stmmac_eee_init(struct stmmac_priv *priv)
 466 {
 467         int eee_tw_timer = priv->eee_tw_timer;
 468
 469         /* Using PCS we cannot dial with the phy registers at this stage
 470          * so we do not support extra feature like EEE.
 471          */
 472         if (priv->hw->pcs == STMMAC_PCS_TBI ||
 473             priv->hw->pcs == STMMAC_PCS_RTBI)
 474                 return false;
 475
 476         /* Check if MAC core supports the EEE feature. */
 477         if (!priv->dma_cap.eee)
 478                 return false;
 479
 480         mutex_lock(&priv->lock);
 481
 482         /* Check if it needs to be deactivated */
 483         if (!priv->eee_active) {
 484                 if (priv->eee_enabled) {
 485                         netdev_dbg(priv->dev, "disable EEE\n");
 486                         stmmac_lpi_entry_timer_config(priv, 0);
 487                         del_timer_sync(&priv->eee_ctrl_timer);
 488                         stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
 489                         if (priv->hw->xpcs)
 490                                 xpcs_config_eee(priv->hw->xpcs,
 491                                                 priv->plat->mult_fact_100ns,
 492                                                 false);
 493                 }
 494                 mutex_unlock(&priv->lock);
 495                 return false;
 496         }
 497
 498         if (priv->eee_active && !priv->eee_enabled) {
 499                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 500                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 501                                      eee_tw_timer);
 502                 if (priv->hw->xpcs)
 503                         xpcs_config_eee(priv->hw->xpcs,
 504                                         priv->plat->mult_fact_100ns,
 505                                         true);
 506         }
 507
 508         if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
 509                 del_timer_sync(&priv->eee_ctrl_timer);
 510                 priv->tx_path_in_lpi_mode = false;
 511                 stmmac_lpi_entry_timer_config(priv, 1);
 512         } else {
 513                 stmmac_lpi_entry_timer_config(priv, 0);
 514                 mod_timer(&priv->eee_ctrl_timer,
 515                           STMMAC_LPI_T(priv->tx_lpi_timer));
 516         }
 517
 518         mutex_unlock(&priv->lock);
 519         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 520         return true;
 521 }
 522
 523 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 524  * @priv: driver private structure
 525  * @p : descriptor pointer
 526  * @skb : the socket buffer
 527  * Description :
 528  * This function will read timestamp from the descriptor & pass it to stack.
 529  * and also perform some sanity checks.
 530  */
 531 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 532                                    struct dma_desc *p, struct sk_buff *skb)
 533 {
 534         struct skb_shared_hwtstamps shhwtstamp;
 535         bool found = false;
 536         u64 ns = 0;
 537
 538         if (!priv->hwts_tx_en)
 539                 return;
 540
 541         /* exit if skb doesn't support hw tstamp */
 542         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 543                 return;
 544
 545         /* check tx tstamp status */
 546         if (stmmac_get_tx_timestamp_status(priv, p)) {
 547                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 548                 found = true;
 549         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 550                 found = true;
 551         }
 552
 553         if (found) {
 554                 ns -= priv->plat->cdc_error_adj;
 555
 556                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 557                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 558
 559                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 560                 /* pass tstamp to stack */
 561                 skb_tstamp_tx(skb, &shhwtstamp);
 562         }
 563 }
 564
 565 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 566  * @priv: driver private structure
 567  * @p : descriptor pointer
 568  * @np : next descriptor pointer
 569  * @skb : the socket buffer
 570  * Description :
 571  * This function will read received packet's timestamp from the descriptor
 572  * and pass it to stack. It also perform some sanity checks.
 573  */
 574 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 575                                    struct dma_desc *np, struct sk_buff *skb)
 576 {
 577         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 578         struct dma_desc *desc = p;
 579         u64 ns = 0;
 580
 581         if (!priv->hwts_rx_en)
 582                 return;
 583         /* For GMAC4, the valid timestamp is from CTX next desc. */
 584         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 585                 desc = np;
 586
 587         /* Check if timestamp is available */
 588         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 589                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 590
 591                 ns -= priv->plat->cdc_error_adj;
 592
 593                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 594                 shhwtstamp = skb_hwtstamps(skb);
 595                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 596                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 597         } else  {
 598                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 599         }
 600 }
 601
 602 /**
 603  *  stmmac_hwtstamp_set - control hardware timestamping.
 604  *  @dev: device pointer.
 605  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 606  *  a proprietary structure used to pass information to the driver.
 607  *  Description:
 608  *  This function configures the MAC to enable/disable both outgoing(TX)
 609  *  and incoming(RX) packets time stamping based on user input.
 610  *  Return Value:
 611  *  0 on success and an appropriate -ve integer on failure.
 612  */
 613 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 614 {
 615         struct stmmac_priv *priv = netdev_priv(dev);
 616         struct hwtstamp_config config;
 617         u32 ptp_v2 = 0;
 618         u32 tstamp_all = 0;
 619         u32 ptp_over_ipv4_udp = 0;
 620         u32 ptp_over_ipv6_udp = 0;
 621         u32 ptp_over_ethernet = 0;
 622         u32 snap_type_sel = 0;
 623         u32 ts_master_en = 0;
 624         u32 ts_event_en = 0;
 625
 626         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 627                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 628                 priv->hwts_tx_en = 0;
 629                 priv->hwts_rx_en = 0;
 630
 631                 return -EOPNOTSUPP;
 632         }
 633
 634         if (copy_from_user(&config, ifr->ifr_data,
 635                            sizeof(config)))
 636                 return -EFAULT;
 637
 638         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 639                    __func__, config.flags, config.tx_type, config.rx_filter);
 640
 641         if (config.tx_type != HWTSTAMP_TX_OFF &&
 642             config.tx_type != HWTSTAMP_TX_ON)
 643                 return -ERANGE;
 644
 645         if (priv->adv_ts) {
 646                 switch (config.rx_filter) {
 647                 case HWTSTAMP_FILTER_NONE:
 648                         /* time stamp no incoming packet at all */
 649                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 650                         break;
 651
 652                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 653                         /* PTP v1, UDP, any kind of event packet */
 654                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 655                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 656                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 657                          * This leaves Delay_Req timestamps out.
 658                          * Enable all events *and* general purpose message
 659                          * timestamping
 660                          */
 661                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 662                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 663                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 664                         break;
 665
 666                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 667                         /* PTP v1, UDP, Sync packet */
 668                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 669                         /* take time stamp for SYNC messages only */
 670                         ts_event_en = PTP_TCR_TSEVNTENA;
 671
 672                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 673                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 674                         break;
 675
 676                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 677                         /* PTP v1, UDP, Delay_req packet */
 678                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 679                         /* take time stamp for Delay_Req messages only */
 680                         ts_master_en = PTP_TCR_TSMSTRENA;
 681                         ts_event_en = PTP_TCR_TSEVNTENA;
 682
 683                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 684                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 685                         break;
 686
 687                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 688                         /* PTP v2, UDP, any kind of event packet */
 689                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 690                         ptp_v2 = PTP_TCR_TSVER2ENA;
 691                         /* take time stamp for all event messages */
 692                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 693
 694                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 695                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 696                         break;
 697
 698                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 699                         /* PTP v2, UDP, Sync packet */
 700                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 701                         ptp_v2 = PTP_TCR_TSVER2ENA;
 702                         /* take time stamp for SYNC messages only */
 703                         ts_event_en = PTP_TCR_TSEVNTENA;
 704
 705                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 706                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 707                         break;
 708
 709                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 710                         /* PTP v2, UDP, Delay_req packet */
 711                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 712                         ptp_v2 = PTP_TCR_TSVER2ENA;
 713                         /* take time stamp for Delay_Req messages only */
 714                         ts_master_en = PTP_TCR_TSMSTRENA;
 715                         ts_event_en = PTP_TCR_TSEVNTENA;
 716
 717                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 718                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 719                         break;
 720
 721                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 722                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 723                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 724                         ptp_v2 = PTP_TCR_TSVER2ENA;
 725                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 726                         if (priv->synopsys_id < DWMAC_CORE_4_10)
 727                                 ts_event_en = PTP_TCR_TSEVNTENA;
 728                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 729                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 730                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 731                         break;
 732
 733                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 734                         /* PTP v2/802.AS1, any layer, Sync packet */
 735                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 736                         ptp_v2 = PTP_TCR_TSVER2ENA;
 737                         /* take time stamp for SYNC messages only */
 738                         ts_event_en = PTP_TCR_TSEVNTENA;
 739
 740                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 741                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 742                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 743                         break;
 744
 745                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 746                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 747                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 748                         ptp_v2 = PTP_TCR_TSVER2ENA;
 749                         /* take time stamp for Delay_Req messages only */
 750                         ts_master_en = PTP_TCR_TSMSTRENA;
 751                         ts_event_en = PTP_TCR_TSEVNTENA;
 752
 753                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 754                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 755                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 756                         break;
 757
 758                 case HWTSTAMP_FILTER_NTP_ALL:
 759                 case HWTSTAMP_FILTER_ALL:
 760                         /* time stamp any incoming packet */
 761                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 762                         tstamp_all = PTP_TCR_TSENALL;
 763                         break;
 764
 765                 default:
 766                         return -ERANGE;
 767                 }
 768         } else {
 769                 switch (config.rx_filter) {
 770                 case HWTSTAMP_FILTER_NONE:
 771                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 772                         break;
 773                 default:
 774                         /* PTP v1, UDP, any kind of event packet */
 775                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 776                         break;
 777                 }
 778         }
 779         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 780         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 781
 782         priv->systime_flags = STMMAC_HWTS_ACTIVE;
 783
 784         if (priv->hwts_tx_en || priv->hwts_rx_en) {
 785                 priv->systime_flags |= tstamp_all | ptp_v2 |
 786                                        ptp_over_ethernet | ptp_over_ipv6_udp |
 787                                        ptp_over_ipv4_udp | ts_event_en |
 788                                        ts_master_en | snap_type_sel;
 789         }
 790
 791         stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags);
 792
 793         memcpy(&priv->tstamp_config, &config, sizeof(config));
 794
 795         return copy_to_user(ifr->ifr_data, &config,
 796                             sizeof(config)) ? -EFAULT : 0;
 797 }
 798
 799 /**
 800  *  stmmac_hwtstamp_get - read hardware timestamping.
 801  *  @dev: device pointer.
 802  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 803  *  a proprietary structure used to pass information to the driver.
 804  *  Description:
 805  *  This function obtain the current hardware timestamping settings
 806  *  as requested.
 807  */
 808 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 809 {
 810         struct stmmac_priv *priv = netdev_priv(dev);
 811         struct hwtstamp_config *config = &priv->tstamp_config;
 812
 813         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 814                 return -EOPNOTSUPP;
 815
 816         return copy_to_user(ifr->ifr_data, config,
 817                             sizeof(*config)) ? -EFAULT : 0;
 818 }
 819
 820 /**
 821  * stmmac_init_tstamp_counter - init hardware timestamping counter
 822  * @priv: driver private structure
 823  * @systime_flags: timestamping flags
 824  * Description:
 825  * Initialize hardware counter for packet timestamping.
 826  * This is valid as long as the interface is open and not suspended.
 827  * Will be rerun after resuming from suspend, case in which the timestamping
 828  * flags updated by stmmac_hwtstamp_set() also need to be restored.
 829  */
 830 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)
 831 {
 832         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 833         struct timespec64 now;
 834         u32 sec_inc = 0;
 835         u64 temp = 0;
 836         int ret;
 837
 838         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 839                 return -EOPNOTSUPP;
 840
 841         ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
 842         if (ret < 0) {
 843                 netdev_warn(priv->dev,
 844                             "failed to enable PTP reference clock: %pe\n",
 845                             ERR_PTR(ret));
 846                 return ret;
 847         }
 848
 849         stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags);
 850         priv->systime_flags = systime_flags;
 851
 852         /* program Sub Second Increment reg */
 853         stmmac_config_sub_second_increment(priv, priv->ptpaddr,
 854                                            priv->plat->clk_ptp_rate,
 855                                            xmac, &sec_inc);
 856         temp = div_u64(1000000000ULL, sec_inc);
 857
 858         /* Store sub second increment for later use */
 859         priv->sub_second_inc = sec_inc;
 860
 861         /* calculate default added value:
 862          * formula is :
 863          * addend = (2^32)/freq_div_ratio;
 864          * where, freq_div_ratio = 1e9ns/sec_inc
 865          */
 866         temp = (u64)(temp << 32);
 867         priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 868         stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 869
 870         /* initialize system time */
 871         ktime_get_real_ts64(&now);
 872
 873         /* lower 32 bits of tv_sec are safe until y2106 */
 874         stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec);
 875
 876         return 0;
 877 }
 878 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter);
 879
 880 /**
 881  * stmmac_init_ptp - init PTP
 882  * @priv: driver private structure
 883  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 884  * This is done by looking at the HW cap. register.
 885  * This function also registers the ptp driver.
 886  */
 887 static int stmmac_init_ptp(struct stmmac_priv *priv)
 888 {
 889         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 890         int ret;
 891
 892         ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
 893         if (ret)
 894                 return ret;
 895
 896         priv->adv_ts = 0;
 897         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 898         if (xmac && priv->dma_cap.atime_stamp)
 899                 priv->adv_ts = 1;
 900         /* Dwmac 3.x core with extend_desc can support adv_ts */
 901         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 902                 priv->adv_ts = 1;
 903
 904         if (priv->dma_cap.time_stamp)
 905                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 906
 907         if (priv->adv_ts)
 908                 netdev_info(priv->dev,
 909                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 910
 911         priv->hwts_tx_en = 0;
 912         priv->hwts_rx_en = 0;
 913
 914         stmmac_ptp_register(priv);
 915
 916         return 0;
 917 }
 918
 919 static void stmmac_release_ptp(struct stmmac_priv *priv)
 920 {
 921         clk_disable_unprepare(priv->plat->clk_ptp_ref);
 922         stmmac_ptp_unregister(priv);
 923 }
 924
 925 /**
 926  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 927  *  @priv: driver private structure
 928  *  @duplex: duplex passed to the next function
 929  *  Description: It is used for configuring the flow control in all queues
 930  */
 931 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 932 {
 933         u32 tx_cnt = priv->plat->tx_queues_to_use;
 934
 935         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 936                         priv->pause, tx_cnt);
 937 }
 938
 939 static void stmmac_validate(struct phylink_config *config,
 940                             unsigned long *supported,
 941                             struct phylink_link_state *state)
 942 {
 943         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 944
 945         /* This is very similar to phylink_generic_validate() except that
 946          * we always use PHY_INTERFACE_MODE_INTERNAL to get all capabilities.
 947          * This is because we don't always have config->supported_interfaces
 948          * populated (only when we have the XPCS.)
 949          *
 950          * When we do have an XPCS, we could pass state->interface, as XPCS
 951          * limits to a subset of the ethtool link modes allowed here.
 952          */
 953         phylink_set(mac_supported, Autoneg);
 954         phylink_set_port_modes(mac_supported);
 955         phylink_get_linkmodes(mac_supported, PHY_INTERFACE_MODE_INTERNAL,
 956                               config->mac_capabilities);
 957
 958         linkmode_and(supported, supported, mac_supported);
 959         linkmode_and(state->advertising, state->advertising, mac_supported);
 960 }
 961
 962 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 963                               const struct phylink_link_state *state)
 964 {
 965         /* Nothing to do, xpcs_config() handles everything */
 966 }
 967
 968 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
 969 {
 970         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
 971         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
 972         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
 973         bool *hs_enable = &fpe_cfg->hs_enable;
 974
 975         if (is_up && *hs_enable) {
 976                 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
 977         } else {
 978                 *lo_state = FPE_STATE_OFF;
 979                 *lp_state = FPE_STATE_OFF;
 980         }
 981 }
 982
 983 static void stmmac_mac_link_down(struct phylink_config *config,
 984                                  unsigned int mode, phy_interface_t interface)
 985 {
 986         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 987
 988         stmmac_mac_set(priv, priv->ioaddr, false);
 989         priv->eee_active = false;
 990         priv->tx_lpi_enabled = false;
 991         priv->eee_enabled = stmmac_eee_init(priv);
 992         stmmac_set_eee_pls(priv, priv->hw, false);
 993
 994         if (priv->dma_cap.fpesel)
 995                 stmmac_fpe_link_state_handle(priv, false);
 996 }
 997
 998 static void stmmac_mac_link_up(struct phylink_config *config,
 999                                struct phy_device *phy,
1000                                unsigned int mode, phy_interface_t interface,
1001                                int speed, int duplex,
1002                                bool tx_pause, bool rx_pause)
1003 {
1004         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1005         u32 ctrl;
1006
1007         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
1008         ctrl &= ~priv->hw->link.speed_mask;
1009
1010         if (interface == PHY_INTERFACE_MODE_USXGMII) {
1011                 switch (speed) {
1012                 case SPEED_10000:
1013                         ctrl |= priv->hw->link.xgmii.speed10000;
1014                         break;
1015                 case SPEED_5000:
1016                         ctrl |= priv->hw->link.xgmii.speed5000;
1017                         break;
1018                 case SPEED_2500:
1019                         ctrl |= priv->hw->link.xgmii.speed2500;
1020                         break;
1021                 default:
1022                         return;
1023                 }
1024         } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1025                 switch (speed) {
1026                 case SPEED_100000:
1027                         ctrl |= priv->hw->link.xlgmii.speed100000;
1028                         break;
1029                 case SPEED_50000:
1030                         ctrl |= priv->hw->link.xlgmii.speed50000;
1031                         break;
1032                 case SPEED_40000:
1033                         ctrl |= priv->hw->link.xlgmii.speed40000;
1034                         break;
1035                 case SPEED_25000:
1036                         ctrl |= priv->hw->link.xlgmii.speed25000;
1037                         break;
1038                 case SPEED_10000:
1039                         ctrl |= priv->hw->link.xgmii.speed10000;
1040                         break;
1041                 case SPEED_2500:
1042                         ctrl |= priv->hw->link.speed2500;
1043                         break;
1044                 case SPEED_1000:
1045                         ctrl |= priv->hw->link.speed1000;
1046                         break;
1047                 default:
1048                         return;
1049                 }
1050         } else {
1051                 switch (speed) {
1052                 case SPEED_2500:
1053                         ctrl |= priv->hw->link.speed2500;
1054                         break;
1055                 case SPEED_1000:
1056                         ctrl |= priv->hw->link.speed1000;
1057                         break;
1058                 case SPEED_100:
1059                         ctrl |= priv->hw->link.speed100;
1060                         break;
1061                 case SPEED_10:
1062                         ctrl |= priv->hw->link.speed10;
1063                         break;
1064                 default:
1065                         return;
1066                 }
1067         }
1068
1069         priv->speed = speed;
1070
1071         if (priv->plat->fix_mac_speed)
1072                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1073
1074         if (!duplex)
1075                 ctrl &= ~priv->hw->link.duplex;
1076         else
1077                 ctrl |= priv->hw->link.duplex;
1078
1079         /* Flow Control operation */
1080         if (tx_pause && rx_pause)
1081                 stmmac_mac_flow_ctrl(priv, duplex);
1082
1083         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1084
1085         stmmac_mac_set(priv, priv->ioaddr, true);
1086         if (phy && priv->dma_cap.eee) {
1087                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1088                 priv->eee_enabled = stmmac_eee_init(priv);
1089                 priv->tx_lpi_enabled = priv->eee_enabled;
1090                 stmmac_set_eee_pls(priv, priv->hw, true);
1091         }
1092
1093         if (priv->dma_cap.fpesel)
1094                 stmmac_fpe_link_state_handle(priv, true);
1095 }
1096
1097 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1098         .validate = stmmac_validate,
1099         .mac_config = stmmac_mac_config,
1100         .mac_link_down = stmmac_mac_link_down,
1101         .mac_link_up = stmmac_mac_link_up,
1102 };
1103
1104 /**
1105  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1106  * @priv: driver private structure
1107  * Description: this is to verify if the HW supports the PCS.
1108  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1109  * configured for the TBI, RTBI, or SGMII PHY interface.
1110  */
1111 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1112 {
1113         int interface = priv->plat->interface;
1114
1115         if (priv->dma_cap.pcs) {
1116                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1117                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1118                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1119                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1120                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1121                         priv->hw->pcs = STMMAC_PCS_RGMII;
1122                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1123                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1124                         priv->hw->pcs = STMMAC_PCS_SGMII;
1125                 }
1126         }
1127 }
1128
1129 /**
1130  * stmmac_init_phy - PHY initialization
1131  * @dev: net device structure
1132  * Description: it initializes the driver's PHY state, and attaches the PHY
1133  * to the mac driver.
1134  *  Return value:
1135  *  0 on success
1136  */
1137 static int stmmac_init_phy(struct net_device *dev)
1138 {
1139         struct stmmac_priv *priv = netdev_priv(dev);
1140         struct device_node *node;
1141         int ret;
1142
1143         node = priv->plat->phylink_node;
1144
1145         if (node)
1146                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1147
1148         /* Some DT bindings do not set-up the PHY handle. Let's try to
1149          * manually parse it
1150          */
1151         if (!node || ret) {
1152                 int addr = priv->plat->phy_addr;
1153                 struct phy_device *phydev;
1154
1155                 phydev = mdiobus_get_phy(priv->mii, addr);
1156                 if (!phydev) {
1157                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1158                         return -ENODEV;
1159                 }
1160
1161                 ret = phylink_connect_phy(priv->phylink, phydev);
1162         }
1163
1164         if (!priv->plat->pmt) {
1165                 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1166
1167                 phylink_ethtool_get_wol(priv->phylink, &wol);
1168                 device_set_wakeup_capable(priv->device, !!wol.supported);
1169         }
1170
1171         return ret;
1172 }
1173
1174 static int stmmac_phy_setup(struct stmmac_priv *priv)
1175 {
1176         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1177         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1178         int max_speed = priv->plat->max_speed;
1179         int mode = priv->plat->phy_interface;
1180         struct phylink *phylink;
1181
1182         priv->phylink_config.dev = &priv->dev->dev;
1183         priv->phylink_config.type = PHYLINK_NETDEV;
1184         priv->phylink_config.pcs_poll = true;
1185         if (priv->plat->mdio_bus_data)
1186                 priv->phylink_config.ovr_an_inband =
1187                         mdio_bus_data->xpcs_an_inband;
1188
1189         if (!fwnode)
1190                 fwnode = dev_fwnode(priv->device);
1191
1192         /* Set the platform/firmware specified interface mode */
1193         __set_bit(mode, priv->phylink_config.supported_interfaces);
1194
1195         /* If we have an xpcs, it defines which PHY interfaces are supported. */
1196         if (priv->hw->xpcs)
1197                 xpcs_get_interfaces(priv->hw->xpcs,
1198                                     priv->phylink_config.supported_interfaces);
1199
1200         priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1201                 MAC_10 | MAC_100;
1202
1203         if (!max_speed || max_speed >= 1000)
1204                 priv->phylink_config.mac_capabilities |= MAC_1000;
1205
1206         if (priv->plat->has_gmac4) {
1207                 if (!max_speed || max_speed >= 2500)
1208                         priv->phylink_config.mac_capabilities |= MAC_2500FD;
1209         } else if (priv->plat->has_xgmac) {
1210                 if (!max_speed || max_speed >= 2500)
1211                         priv->phylink_config.mac_capabilities |= MAC_2500FD;
1212                 if (!max_speed || max_speed >= 5000)
1213                         priv->phylink_config.mac_capabilities |= MAC_5000FD;
1214                 if (!max_speed || max_speed >= 10000)
1215                         priv->phylink_config.mac_capabilities |= MAC_10000FD;
1216                 if (!max_speed || max_speed >= 25000)
1217                         priv->phylink_config.mac_capabilities |= MAC_25000FD;
1218                 if (!max_speed || max_speed >= 40000)
1219                         priv->phylink_config.mac_capabilities |= MAC_40000FD;
1220                 if (!max_speed || max_speed >= 50000)
1221                         priv->phylink_config.mac_capabilities |= MAC_50000FD;
1222                 if (!max_speed || max_speed >= 100000)
1223                         priv->phylink_config.mac_capabilities |= MAC_100000FD;
1224         }
1225
1226         /* Half-Duplex can only work with single queue */
1227         if (priv->plat->tx_queues_to_use > 1)
1228                 priv->phylink_config.mac_capabilities &=
1229                         ~(MAC_10HD | MAC_100HD | MAC_1000HD);
1230
1231         phylink = phylink_create(&priv->phylink_config, fwnode,
1232                                  mode, &stmmac_phylink_mac_ops);
1233         if (IS_ERR(phylink))
1234                 return PTR_ERR(phylink);
1235
1236         if (priv->hw->xpcs)
1237                 phylink_set_pcs(phylink, &priv->hw->xpcs->pcs);
1238
1239         priv->phylink = phylink;
1240         return 0;
1241 }
1242
1243 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1244 {
1245         u32 rx_cnt = priv->plat->rx_queues_to_use;
1246         unsigned int desc_size;
1247         void *head_rx;
1248         u32 queue;
1249
1250         /* Display RX rings */
1251         for (queue = 0; queue < rx_cnt; queue++) {
1252                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1253
1254                 pr_info("\tRX Queue %u rings\n", queue);
1255
1256                 if (priv->extend_desc) {
1257                         head_rx = (void *)rx_q->dma_erx;
1258                         desc_size = sizeof(struct dma_extended_desc);
1259                 } else {
1260                         head_rx = (void *)rx_q->dma_rx;
1261                         desc_size = sizeof(struct dma_desc);
1262                 }
1263
1264                 /* Display RX ring */
1265                 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
1266                                     rx_q->dma_rx_phy, desc_size);
1267         }
1268 }
1269
1270 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1271 {
1272         u32 tx_cnt = priv->plat->tx_queues_to_use;
1273         unsigned int desc_size;
1274         void *head_tx;
1275         u32 queue;
1276
1277         /* Display TX rings */
1278         for (queue = 0; queue < tx_cnt; queue++) {
1279                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1280
1281                 pr_info("\tTX Queue %d rings\n", queue);
1282
1283                 if (priv->extend_desc) {
1284                         head_tx = (void *)tx_q->dma_etx;
1285                         desc_size = sizeof(struct dma_extended_desc);
1286                 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1287                         head_tx = (void *)tx_q->dma_entx;
1288                         desc_size = sizeof(struct dma_edesc);
1289                 } else {
1290                         head_tx = (void *)tx_q->dma_tx;
1291                         desc_size = sizeof(struct dma_desc);
1292                 }
1293
1294                 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
1295                                     tx_q->dma_tx_phy, desc_size);
1296         }
1297 }
1298
1299 static void stmmac_display_rings(struct stmmac_priv *priv)
1300 {
1301         /* Display RX ring */
1302         stmmac_display_rx_rings(priv);
1303
1304         /* Display TX ring */
1305         stmmac_display_tx_rings(priv);
1306 }
1307
1308 static int stmmac_set_bfsize(int mtu, int bufsize)
1309 {
1310         int ret = bufsize;
1311
1312         if (mtu >= BUF_SIZE_8KiB)
1313                 ret = BUF_SIZE_16KiB;
1314         else if (mtu >= BUF_SIZE_4KiB)
1315                 ret = BUF_SIZE_8KiB;
1316         else if (mtu >= BUF_SIZE_2KiB)
1317                 ret = BUF_SIZE_4KiB;
1318         else if (mtu > DEFAULT_BUFSIZE)
1319                 ret = BUF_SIZE_2KiB;
1320         else
1321                 ret = DEFAULT_BUFSIZE;
1322
1323         return ret;
1324 }
1325
1326 /**
1327  * stmmac_clear_rx_descriptors - clear RX descriptors
1328  * @priv: driver private structure
1329  * @queue: RX queue index
1330  * Description: this function is called to clear the RX descriptors
1331  * in case of both basic and extended descriptors are used.
1332  */
1333 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1334 {
1335         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1336         int i;
1337
1338         /* Clear the RX descriptors */
1339         for (i = 0; i < priv->dma_rx_size; i++)
1340                 if (priv->extend_desc)
1341                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1342                                         priv->use_riwt, priv->mode,
1343                                         (i == priv->dma_rx_size - 1),
1344                                         priv->dma_buf_sz);
1345                 else
1346                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1347                                         priv->use_riwt, priv->mode,
1348                                         (i == priv->dma_rx_size - 1),
1349                                         priv->dma_buf_sz);
1350 }
1351
1352 /**
1353  * stmmac_clear_tx_descriptors - clear tx descriptors
1354  * @priv: driver private structure
1355  * @queue: TX queue index.
1356  * Description: this function is called to clear the TX descriptors
1357  * in case of both basic and extended descriptors are used.
1358  */
1359 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1360 {
1361         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1362         int i;
1363
1364         /* Clear the TX descriptors */
1365         for (i = 0; i < priv->dma_tx_size; i++) {
1366                 int last = (i == (priv->dma_tx_size - 1));
1367                 struct dma_desc *p;
1368
1369                 if (priv->extend_desc)
1370                         p = &tx_q->dma_etx[i].basic;
1371                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1372                         p = &tx_q->dma_entx[i].basic;
1373                 else
1374                         p = &tx_q->dma_tx[i];
1375
1376                 stmmac_init_tx_desc(priv, p, priv->mode, last);
1377         }
1378 }
1379
1380 /**
1381  * stmmac_clear_descriptors - clear descriptors
1382  * @priv: driver private structure
1383  * Description: this function is called to clear the TX and RX descriptors
1384  * in case of both basic and extended descriptors are used.
1385  */
1386 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1387 {
1388         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1389         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1390         u32 queue;
1391
1392         /* Clear the RX descriptors */
1393         for (queue = 0; queue < rx_queue_cnt; queue++)
1394                 stmmac_clear_rx_descriptors(priv, queue);
1395
1396         /* Clear the TX descriptors */
1397         for (queue = 0; queue < tx_queue_cnt; queue++)
1398                 stmmac_clear_tx_descriptors(priv, queue);
1399 }
1400
1401 /**
1402  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1403  * @priv: driver private structure
1404  * @p: descriptor pointer
1405  * @i: descriptor index
1406  * @flags: gfp flag
1407  * @queue: RX queue index
1408  * Description: this function is called to allocate a receive buffer, perform
1409  * the DMA mapping and init the descriptor.
1410  */
1411 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1412                                   int i, gfp_t flags, u32 queue)
1413 {
1414         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1415         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1416         gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
1417
1418         if (priv->dma_cap.addr64 <= 32)
1419                 gfp |= GFP_DMA32;
1420
1421         if (!buf->page) {
1422                 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1423                 if (!buf->page)
1424                         return -ENOMEM;
1425                 buf->page_offset = stmmac_rx_offset(priv);
1426         }
1427
1428         if (priv->sph && !buf->sec_page) {
1429                 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1430                 if (!buf->sec_page)
1431                         return -ENOMEM;
1432
1433                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1434                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1435         } else {
1436                 buf->sec_page = NULL;
1437                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1438         }
1439
1440         buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1441
1442         stmmac_set_desc_addr(priv, p, buf->addr);
1443         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1444                 stmmac_init_desc3(priv, p);
1445
1446         return 0;
1447 }
1448
1449 /**
1450  * stmmac_free_rx_buffer - free RX dma buffers
1451  * @priv: private structure
1452  * @queue: RX queue index
1453  * @i: buffer index.
1454  */
1455 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1456 {
1457         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1458         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1459
1460         if (buf->page)
1461                 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1462         buf->page = NULL;
1463
1464         if (buf->sec_page)
1465                 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1466         buf->sec_page = NULL;
1467 }
1468
1469 /**
1470  * stmmac_free_tx_buffer - free RX dma buffers
1471  * @priv: private structure
1472  * @queue: RX queue index
1473  * @i: buffer index.
1474  */
1475 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1476 {
1477         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1478
1479         if (tx_q->tx_skbuff_dma[i].buf &&
1480             tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1481                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1482                         dma_unmap_page(priv->device,
1483                                        tx_q->tx_skbuff_dma[i].buf,
1484                                        tx_q->tx_skbuff_dma[i].len,
1485                                        DMA_TO_DEVICE);
1486                 else
1487                         dma_unmap_single(priv->device,
1488                                          tx_q->tx_skbuff_dma[i].buf,
1489                                          tx_q->tx_skbuff_dma[i].len,
1490                                          DMA_TO_DEVICE);
1491         }
1492
1493         if (tx_q->xdpf[i] &&
1494             (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1495              tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1496                 xdp_return_frame(tx_q->xdpf[i]);
1497                 tx_q->xdpf[i] = NULL;
1498         }
1499
1500         if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1501                 tx_q->xsk_frames_done++;
1502
1503         if (tx_q->tx_skbuff[i] &&
1504             tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1505                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1506                 tx_q->tx_skbuff[i] = NULL;
1507         }
1508
1509         tx_q->tx_skbuff_dma[i].buf = 0;
1510         tx_q->tx_skbuff_dma[i].map_as_page = false;
1511 }
1512
1513 /**
1514  * dma_free_rx_skbufs - free RX dma buffers
1515  * @priv: private structure
1516  * @queue: RX queue index
1517  */
1518 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1519 {
1520         int i;
1521
1522         for (i = 0; i < priv->dma_rx_size; i++)
1523                 stmmac_free_rx_buffer(priv, queue, i);
1524 }
1525
1526 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
1527                                    gfp_t flags)
1528 {
1529         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1530         int i;
1531
1532         for (i = 0; i < priv->dma_rx_size; i++) {
1533                 struct dma_desc *p;
1534                 int ret;
1535
1536                 if (priv->extend_desc)
1537                         p = &((rx_q->dma_erx + i)->basic);
1538                 else
1539                         p = rx_q->dma_rx + i;
1540
1541                 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1542                                              queue);
1543                 if (ret)
1544                         return ret;
1545
1546                 rx_q->buf_alloc_num++;
1547         }
1548
1549         return 0;
1550 }
1551
1552 /**
1553  * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1554  * @priv: private structure
1555  * @queue: RX queue index
1556  */
1557 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
1558 {
1559         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1560         int i;
1561
1562         for (i = 0; i < priv->dma_rx_size; i++) {
1563                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1564
1565                 if (!buf->xdp)
1566                         continue;
1567
1568                 xsk_buff_free(buf->xdp);
1569                 buf->xdp = NULL;
1570         }
1571 }
1572
1573 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
1574 {
1575         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1576         int i;
1577
1578         for (i = 0; i < priv->dma_rx_size; i++) {
1579                 struct stmmac_rx_buffer *buf;
1580                 dma_addr_t dma_addr;
1581                 struct dma_desc *p;
1582
1583                 if (priv->extend_desc)
1584                         p = (struct dma_desc *)(rx_q->dma_erx + i);
1585                 else
1586                         p = rx_q->dma_rx + i;
1587
1588                 buf = &rx_q->buf_pool[i];
1589
1590                 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1591                 if (!buf->xdp)
1592                         return -ENOMEM;
1593
1594                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1595                 stmmac_set_desc_addr(priv, p, dma_addr);
1596                 rx_q->buf_alloc_num++;
1597         }
1598
1599         return 0;
1600 }
1601
1602 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1603 {
1604         if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1605                 return NULL;
1606
1607         return xsk_get_pool_from_qid(priv->dev, queue);
1608 }
1609
1610 /**
1611  * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1612  * @priv: driver private structure
1613  * @queue: RX queue index
1614  * @flags: gfp flag.
1615  * Description: this function initializes the DMA RX descriptors
1616  * and allocates the socket buffers. It supports the chained and ring
1617  * modes.
1618  */
1619 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
1620 {
1621         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1622         int ret;
1623
1624         netif_dbg(priv, probe, priv->dev,
1625                   "(%s) dma_rx_phy=0x%08x\n", __func__,
1626                   (u32)rx_q->dma_rx_phy);
1627
1628         stmmac_clear_rx_descriptors(priv, queue);
1629
1630         xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1631
1632         rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1633
1634         if (rx_q->xsk_pool) {
1635                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1636                                                    MEM_TYPE_XSK_BUFF_POOL,
1637                                                    NULL));
1638                 netdev_info(priv->dev,
1639                             "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1640                             rx_q->queue_index);
1641                 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1642         } else {
1643                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1644                                                    MEM_TYPE_PAGE_POOL,
1645                                                    rx_q->page_pool));
1646                 netdev_info(priv->dev,
1647                             "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1648                             rx_q->queue_index);
1649         }
1650
1651         if (rx_q->xsk_pool) {
1652                 /* RX XDP ZC buffer pool may not be populated, e.g.
1653                  * xdpsock TX-only.
1654                  */
1655                 stmmac_alloc_rx_buffers_zc(priv, queue);
1656         } else {
1657                 ret = stmmac_alloc_rx_buffers(priv, queue, flags);
1658                 if (ret < 0)
1659                         return -ENOMEM;
1660         }
1661
1662         rx_q->cur_rx = 0;
1663         rx_q->dirty_rx = 0;
1664
1665         /* Setup the chained descriptor addresses */
1666         if (priv->mode == STMMAC_CHAIN_MODE) {
1667                 if (priv->extend_desc)
1668                         stmmac_mode_init(priv, rx_q->dma_erx,
1669                                          rx_q->dma_rx_phy,
1670                                          priv->dma_rx_size, 1);
1671                 else
1672                         stmmac_mode_init(priv, rx_q->dma_rx,
1673                                          rx_q->dma_rx_phy,
1674                                          priv->dma_rx_size, 0);
1675         }
1676
1677         return 0;
1678 }
1679
1680 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1681 {
1682         struct stmmac_priv *priv = netdev_priv(dev);
1683         u32 rx_count = priv->plat->rx_queues_to_use;
1684         u32 queue;
1685         int ret;
1686
1687         /* RX INITIALIZATION */
1688         netif_dbg(priv, probe, priv->dev,
1689                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1690
1691         for (queue = 0; queue < rx_count; queue++) {
1692                 ret = __init_dma_rx_desc_rings(priv, queue, flags);
1693                 if (ret)
1694                         goto err_init_rx_buffers;
1695         }
1696
1697         return 0;
1698
1699 err_init_rx_buffers:
1700         while (queue >= 0) {
1701                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1702
1703                 if (rx_q->xsk_pool)
1704                         dma_free_rx_xskbufs(priv, queue);
1705                 else
1706                         dma_free_rx_skbufs(priv, queue);
1707
1708                 rx_q->buf_alloc_num = 0;
1709                 rx_q->xsk_pool = NULL;
1710
1711                 if (queue == 0)
1712                         break;
1713
1714                 queue--;
1715         }
1716
1717         return ret;
1718 }
1719
1720 /**
1721  * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1722  * @priv: driver private structure
1723  * @queue : TX queue index
1724  * Description: this function initializes the DMA TX descriptors
1725  * and allocates the socket buffers. It supports the chained and ring
1726  * modes.
1727  */
1728 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
1729 {
1730         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1731         int i;
1732
1733         netif_dbg(priv, probe, priv->dev,
1734                   "(%s) dma_tx_phy=0x%08x\n", __func__,
1735                   (u32)tx_q->dma_tx_phy);
1736
1737         /* Setup the chained descriptor addresses */
1738         if (priv->mode == STMMAC_CHAIN_MODE) {
1739                 if (priv->extend_desc)
1740                         stmmac_mode_init(priv, tx_q->dma_etx,
1741                                          tx_q->dma_tx_phy,
1742                                          priv->dma_tx_size, 1);
1743                 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1744                         stmmac_mode_init(priv, tx_q->dma_tx,
1745                                          tx_q->dma_tx_phy,
1746                                          priv->dma_tx_size, 0);
1747         }
1748
1749         tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1750
1751         for (i = 0; i < priv->dma_tx_size; i++) {
1752                 struct dma_desc *p;
1753
1754                 if (priv->extend_desc)
1755                         p = &((tx_q->dma_etx + i)->basic);
1756                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1757                         p = &((tx_q->dma_entx + i)->basic);
1758                 else
1759                         p = tx_q->dma_tx + i;
1760
1761                 stmmac_clear_desc(priv, p);
1762
1763                 tx_q->tx_skbuff_dma[i].buf = 0;
1764                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1765                 tx_q->tx_skbuff_dma[i].len = 0;
1766                 tx_q->tx_skbuff_dma[i].last_segment = false;
1767                 tx_q->tx_skbuff[i] = NULL;
1768         }
1769
1770         tx_q->dirty_tx = 0;
1771         tx_q->cur_tx = 0;
1772         tx_q->mss = 0;
1773
1774         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1775
1776         return 0;
1777 }
1778
1779 static int init_dma_tx_desc_rings(struct net_device *dev)
1780 {
1781         struct stmmac_priv *priv = netdev_priv(dev);
1782         u32 tx_queue_cnt;
1783         u32 queue;
1784
1785         tx_queue_cnt = priv->plat->tx_queues_to_use;
1786
1787         for (queue = 0; queue < tx_queue_cnt; queue++)
1788                 __init_dma_tx_desc_rings(priv, queue);
1789
1790         return 0;
1791 }
1792
1793 /**
1794  * init_dma_desc_rings - init the RX/TX descriptor rings
1795  * @dev: net device structure
1796  * @flags: gfp flag.
1797  * Description: this function initializes the DMA RX/TX descriptors
1798  * and allocates the socket buffers. It supports the chained and ring
1799  * modes.
1800  */
1801 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1802 {
1803         struct stmmac_priv *priv = netdev_priv(dev);
1804         int ret;
1805
1806         ret = init_dma_rx_desc_rings(dev, flags);
1807         if (ret)
1808                 return ret;
1809
1810         ret = init_dma_tx_desc_rings(dev);
1811
1812         stmmac_clear_descriptors(priv);
1813
1814         if (netif_msg_hw(priv))
1815                 stmmac_display_rings(priv);
1816
1817         return ret;
1818 }
1819
1820 /**
1821  * dma_free_tx_skbufs - free TX dma buffers
1822  * @priv: private structure
1823  * @queue: TX queue index
1824  */
1825 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1826 {
1827         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1828         int i;
1829
1830         tx_q->xsk_frames_done = 0;
1831
1832         for (i = 0; i < priv->dma_tx_size; i++)
1833                 stmmac_free_tx_buffer(priv, queue, i);
1834
1835         if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1836                 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1837                 tx_q->xsk_frames_done = 0;
1838                 tx_q->xsk_pool = NULL;
1839         }
1840 }
1841
1842 /**
1843  * stmmac_free_tx_skbufs - free TX skb buffers
1844  * @priv: private structure
1845  */
1846 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1847 {
1848         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1849         u32 queue;
1850
1851         for (queue = 0; queue < tx_queue_cnt; queue++)
1852                 dma_free_tx_skbufs(priv, queue);
1853 }
1854
1855 /**
1856  * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1857  * @priv: private structure
1858  * @queue: RX queue index
1859  */
1860 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1861 {
1862         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1863
1864         /* Release the DMA RX socket buffers */
1865         if (rx_q->xsk_pool)
1866                 dma_free_rx_xskbufs(priv, queue);
1867         else
1868                 dma_free_rx_skbufs(priv, queue);
1869
1870         rx_q->buf_alloc_num = 0;
1871         rx_q->xsk_pool = NULL;
1872
1873         /* Free DMA regions of consistent memory previously allocated */
1874         if (!priv->extend_desc)
1875                 dma_free_coherent(priv->device, priv->dma_rx_size *
1876                                   sizeof(struct dma_desc),
1877                                   rx_q->dma_rx, rx_q->dma_rx_phy);
1878         else
1879                 dma_free_coherent(priv->device, priv->dma_rx_size *
1880                                   sizeof(struct dma_extended_desc),
1881                                   rx_q->dma_erx, rx_q->dma_rx_phy);
1882
1883         if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1884                 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1885
1886         kfree(rx_q->buf_pool);
1887         if (rx_q->page_pool)
1888                 page_pool_destroy(rx_q->page_pool);
1889 }
1890
1891 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1892 {
1893         u32 rx_count = priv->plat->rx_queues_to_use;
1894         u32 queue;
1895
1896         /* Free RX queue resources */
1897         for (queue = 0; queue < rx_count; queue++)
1898                 __free_dma_rx_desc_resources(priv, queue);
1899 }
1900
1901 /**
1902  * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1903  * @priv: private structure
1904  * @queue: TX queue index
1905  */
1906 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
1907 {
1908         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1909         size_t size;
1910         void *addr;
1911
1912         /* Release the DMA TX socket buffers */
1913         dma_free_tx_skbufs(priv, queue);
1914
1915         if (priv->extend_desc) {
1916                 size = sizeof(struct dma_extended_desc);
1917                 addr = tx_q->dma_etx;
1918         } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1919                 size = sizeof(struct dma_edesc);
1920                 addr = tx_q->dma_entx;
1921         } else {
1922                 size = sizeof(struct dma_desc);
1923                 addr = tx_q->dma_tx;
1924         }
1925
1926         size *= priv->dma_tx_size;
1927
1928         dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1929
1930         kfree(tx_q->tx_skbuff_dma);
1931         kfree(tx_q->tx_skbuff);
1932 }
1933
1934 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1935 {
1936         u32 tx_count = priv->plat->tx_queues_to_use;
1937         u32 queue;
1938
1939         /* Free TX queue resources */
1940         for (queue = 0; queue < tx_count; queue++)
1941                 __free_dma_tx_desc_resources(priv, queue);
1942 }
1943
1944 /**
1945  * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
1946  * @priv: private structure
1947  * @queue: RX queue index
1948  * Description: according to which descriptor can be used (extend or basic)
1949  * this function allocates the resources for TX and RX paths. In case of
1950  * reception, for example, it pre-allocated the RX socket buffer in order to
1951  * allow zero-copy mechanism.
1952  */
1953 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1954 {
1955         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1956         struct stmmac_channel *ch = &priv->channel[queue];
1957         bool xdp_prog = stmmac_xdp_is_enabled(priv);
1958         struct page_pool_params pp_params = { 0 };
1959         unsigned int num_pages;
1960         unsigned int napi_id;
1961         int ret;
1962
1963         rx_q->queue_index = queue;
1964         rx_q->priv_data = priv;
1965
1966         pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
1967         pp_params.pool_size = priv->dma_rx_size;
1968         num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1969         pp_params.order = ilog2(num_pages);
1970         pp_params.nid = dev_to_node(priv->device);
1971         pp_params.dev = priv->device;
1972         pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
1973         pp_params.offset = stmmac_rx_offset(priv);
1974         pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
1975
1976         rx_q->page_pool = page_pool_create(&pp_params);
1977         if (IS_ERR(rx_q->page_pool)) {
1978                 ret = PTR_ERR(rx_q->page_pool);
1979                 rx_q->page_pool = NULL;
1980                 return ret;
1981         }
1982
1983         rx_q->buf_pool = kcalloc(priv->dma_rx_size,
1984                                  sizeof(*rx_q->buf_pool),
1985                                  GFP_KERNEL);
1986         if (!rx_q->buf_pool)
1987                 return -ENOMEM;
1988
1989         if (priv->extend_desc) {
1990                 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1991                                                    priv->dma_rx_size *
1992                                                    sizeof(struct dma_extended_desc),
1993                                                    &rx_q->dma_rx_phy,
1994                                                    GFP_KERNEL);
1995                 if (!rx_q->dma_erx)
1996                         return -ENOMEM;
1997
1998         } else {
1999                 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2000                                                   priv->dma_rx_size *
2001                                                   sizeof(struct dma_desc),
2002                                                   &rx_q->dma_rx_phy,
2003                                                   GFP_KERNEL);
2004                 if (!rx_q->dma_rx)
2005                         return -ENOMEM;
2006         }
2007
2008         if (stmmac_xdp_is_enabled(priv) &&
2009             test_bit(queue, priv->af_xdp_zc_qps))
2010                 napi_id = ch->rxtx_napi.napi_id;
2011         else
2012                 napi_id = ch->rx_napi.napi_id;
2013
2014         ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2015                                rx_q->queue_index,
2016                                napi_id);
2017         if (ret) {
2018                 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2019                 return -EINVAL;
2020         }
2021
2022         return 0;
2023 }
2024
2025 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
2026 {
2027         u32 rx_count = priv->plat->rx_queues_to_use;
2028         u32 queue;
2029         int ret;
2030
2031         /* RX queues buffers and DMA */
2032         for (queue = 0; queue < rx_count; queue++) {
2033                 ret = __alloc_dma_rx_desc_resources(priv, queue);
2034                 if (ret)
2035                         goto err_dma;
2036         }
2037
2038         return 0;
2039
2040 err_dma:
2041         free_dma_rx_desc_resources(priv);
2042
2043         return ret;
2044 }
2045
2046 /**
2047  * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2048  * @priv: private structure
2049  * @queue: TX queue index
2050  * Description: according to which descriptor can be used (extend or basic)
2051  * this function allocates the resources for TX and RX paths. In case of
2052  * reception, for example, it pre-allocated the RX socket buffer in order to
2053  * allow zero-copy mechanism.
2054  */
2055 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
2056 {
2057         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2058         size_t size;
2059         void *addr;
2060
2061         tx_q->queue_index = queue;
2062         tx_q->priv_data = priv;
2063
2064         tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
2065                                       sizeof(*tx_q->tx_skbuff_dma),
2066                                       GFP_KERNEL);
2067         if (!tx_q->tx_skbuff_dma)
2068                 return -ENOMEM;
2069
2070         tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
2071                                   sizeof(struct sk_buff *),
2072                                   GFP_KERNEL);
2073         if (!tx_q->tx_skbuff)
2074                 return -ENOMEM;
2075
2076         if (priv->extend_desc)
2077                 size = sizeof(struct dma_extended_desc);
2078         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2079                 size = sizeof(struct dma_edesc);
2080         else
2081                 size = sizeof(struct dma_desc);
2082
2083         size *= priv->dma_tx_size;
2084
2085         addr = dma_alloc_coherent(priv->device, size,
2086                                   &tx_q->dma_tx_phy, GFP_KERNEL);
2087         if (!addr)
2088                 return -ENOMEM;
2089
2090         if (priv->extend_desc)
2091                 tx_q->dma_etx = addr;
2092         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2093                 tx_q->dma_entx = addr;
2094         else
2095                 tx_q->dma_tx = addr;
2096
2097         return 0;
2098 }
2099
2100 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
2101 {
2102         u32 tx_count = priv->plat->tx_queues_to_use;
2103         u32 queue;
2104         int ret;
2105
2106         /* TX queues buffers and DMA */
2107         for (queue = 0; queue < tx_count; queue++) {
2108                 ret = __alloc_dma_tx_desc_resources(priv, queue);
2109                 if (ret)
2110                         goto err_dma;
2111         }
2112
2113         return 0;
2114
2115 err_dma:
2116         free_dma_tx_desc_resources(priv);
2117         return ret;
2118 }
2119
2120 /**
2121  * alloc_dma_desc_resources - alloc TX/RX resources.
2122  * @priv: private structure
2123  * Description: according to which descriptor can be used (extend or basic)
2124  * this function allocates the resources for TX and RX paths. In case of
2125  * reception, for example, it pre-allocated the RX socket buffer in order to
2126  * allow zero-copy mechanism.
2127  */
2128 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
2129 {
2130         /* RX Allocation */
2131         int ret = alloc_dma_rx_desc_resources(priv);
2132
2133         if (ret)
2134                 return ret;
2135
2136         ret = alloc_dma_tx_desc_resources(priv);
2137
2138         return ret;
2139 }
2140
2141 /**
2142  * free_dma_desc_resources - free dma desc resources
2143  * @priv: private structure
2144  */
2145 static void free_dma_desc_resources(struct stmmac_priv *priv)
2146 {
2147         /* Release the DMA TX socket buffers */
2148         free_dma_tx_desc_resources(priv);
2149
2150         /* Release the DMA RX socket buffers later
2151          * to ensure all pending XDP_TX buffers are returned.
2152          */
2153         free_dma_rx_desc_resources(priv);
2154 }
2155
2156 /**
2157  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
2158  *  @priv: driver private structure
2159  *  Description: It is used for enabling the rx queues in the MAC
2160  */
2161 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2162 {
2163         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2164         int queue;
2165         u8 mode;
2166
2167         for (queue = 0; queue < rx_queues_count; queue++) {
2168                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2169                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2170         }
2171 }
2172
2173 /**
2174  * stmmac_start_rx_dma - start RX DMA channel
2175  * @priv: driver private structure
2176  * @chan: RX channel index
2177  * Description:
2178  * This starts a RX DMA channel
2179  */
2180 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2181 {
2182         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2183         stmmac_start_rx(priv, priv->ioaddr, chan);
2184 }
2185
2186 /**
2187  * stmmac_start_tx_dma - start TX DMA channel
2188  * @priv: driver private structure
2189  * @chan: TX channel index
2190  * Description:
2191  * This starts a TX DMA channel
2192  */
2193 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2194 {
2195         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2196         stmmac_start_tx(priv, priv->ioaddr, chan);
2197 }
2198
2199 /**
2200  * stmmac_stop_rx_dma - stop RX DMA channel
2201  * @priv: driver private structure
2202  * @chan: RX channel index
2203  * Description:
2204  * This stops a RX DMA channel
2205  */
2206 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2207 {
2208         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2209         stmmac_stop_rx(priv, priv->ioaddr, chan);
2210 }
2211
2212 /**
2213  * stmmac_stop_tx_dma - stop TX DMA channel
2214  * @priv: driver private structure
2215  * @chan: TX channel index
2216  * Description:
2217  * This stops a TX DMA channel
2218  */
2219 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2220 {
2221         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2222         stmmac_stop_tx(priv, priv->ioaddr, chan);
2223 }
2224
2225 /**
2226  * stmmac_start_all_dma - start all RX and TX DMA channels
2227  * @priv: driver private structure
2228  * Description:
2229  * This starts all the RX and TX DMA channels
2230  */
2231 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2232 {
2233         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2234         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2235         u32 chan = 0;
2236
2237         for (chan = 0; chan < rx_channels_count; chan++)
2238                 stmmac_start_rx_dma(priv, chan);
2239
2240         for (chan = 0; chan < tx_channels_count; chan++)
2241                 stmmac_start_tx_dma(priv, chan);
2242 }
2243
2244 /**
2245  * stmmac_stop_all_dma - stop all RX and TX DMA channels
2246  * @priv: driver private structure
2247  * Description:
2248  * This stops the RX and TX DMA channels
2249  */
2250 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2251 {
2252         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2253         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2254         u32 chan = 0;
2255
2256         for (chan = 0; chan < rx_channels_count; chan++)
2257                 stmmac_stop_rx_dma(priv, chan);
2258
2259         for (chan = 0; chan < tx_channels_count; chan++)
2260                 stmmac_stop_tx_dma(priv, chan);
2261 }
2262
2263 /**
2264  *  stmmac_dma_operation_mode - HW DMA operation mode
2265  *  @priv: driver private structure
2266  *  Description: it is used for configuring the DMA operation mode register in
2267  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2268  */
2269 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2270 {
2271         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2272         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2273         int rxfifosz = priv->plat->rx_fifo_size;
2274         int txfifosz = priv->plat->tx_fifo_size;
2275         u32 txmode = 0;
2276         u32 rxmode = 0;
2277         u32 chan = 0;
2278         u8 qmode = 0;
2279
2280         if (rxfifosz == 0)
2281                 rxfifosz = priv->dma_cap.rx_fifo_size;
2282         if (txfifosz == 0)
2283                 txfifosz = priv->dma_cap.tx_fifo_size;
2284
2285         /* Adjust for real per queue fifo size */
2286         rxfifosz /= rx_channels_count;
2287         txfifosz /= tx_channels_count;
2288
2289         if (priv->plat->force_thresh_dma_mode) {
2290                 txmode = tc;
2291                 rxmode = tc;
2292         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2293                 /*
2294                  * In case of GMAC, SF mode can be enabled
2295                  * to perform the TX COE in HW. This depends on:
2296                  * 1) TX COE if actually supported
2297                  * 2) There is no bugged Jumbo frame support
2298                  *    that needs to not insert csum in the TDES.
2299                  */
2300                 txmode = SF_DMA_MODE;
2301                 rxmode = SF_DMA_MODE;
2302                 priv->xstats.threshold = SF_DMA_MODE;
2303         } else {
2304                 txmode = tc;
2305                 rxmode = SF_DMA_MODE;
2306         }
2307
2308         /* configure all channels */
2309         for (chan = 0; chan < rx_channels_count; chan++) {
2310                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2311                 u32 buf_size;
2312
2313                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2314
2315                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2316                                 rxfifosz, qmode);
2317
2318                 if (rx_q->xsk_pool) {
2319                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2320                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2321                                               buf_size,
2322                                               chan);
2323                 } else {
2324                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2325                                               priv->dma_buf_sz,
2326                                               chan);
2327                 }
2328         }
2329
2330         for (chan = 0; chan < tx_channels_count; chan++) {
2331                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2332
2333                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2334                                 txfifosz, qmode);
2335         }
2336 }
2337
2338 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2339 {
2340         struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2341         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2342         struct xsk_buff_pool *pool = tx_q->xsk_pool;
2343         unsigned int entry = tx_q->cur_tx;
2344         struct dma_desc *tx_desc = NULL;
2345         struct xdp_desc xdp_desc;
2346         bool work_done = true;
2347
2348         /* Avoids TX time-out as we are sharing with slow path */
2349         txq_trans_cond_update(nq);
2350
2351         budget = min(budget, stmmac_tx_avail(priv, queue));
2352
2353         while (budget-- > 0) {
2354                 dma_addr_t dma_addr;
2355                 bool set_ic;
2356
2357                 /* We are sharing with slow path and stop XSK TX desc submission when
2358                  * available TX ring is less than threshold.
2359                  */
2360                 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2361                     !netif_carrier_ok(priv->dev)) {
2362                         work_done = false;
2363                         break;
2364                 }
2365
2366                 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2367                         break;
2368
2369                 if (likely(priv->extend_desc))
2370                         tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2371                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2372                         tx_desc = &tx_q->dma_entx[entry].basic;
2373                 else
2374                         tx_desc = tx_q->dma_tx + entry;
2375
2376                 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2377                 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2378
2379                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2380
2381                 /* To return XDP buffer to XSK pool, we simple call
2382                  * xsk_tx_completed(), so we don't need to fill up
2383                  * 'buf' and 'xdpf'.
2384                  */
2385                 tx_q->tx_skbuff_dma[entry].buf = 0;
2386                 tx_q->xdpf[entry] = NULL;
2387
2388                 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2389                 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2390                 tx_q->tx_skbuff_dma[entry].last_segment = true;
2391                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2392
2393                 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2394
2395                 tx_q->tx_count_frames++;
2396
2397                 if (!priv->tx_coal_frames[queue])
2398                         set_ic = false;
2399                 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2400                         set_ic = true;
2401                 else
2402                         set_ic = false;
2403
2404                 if (set_ic) {
2405                         tx_q->tx_count_frames = 0;
2406                         stmmac_set_tx_ic(priv, tx_desc);
2407                         priv->xstats.tx_set_ic_bit++;
2408                 }
2409
2410                 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2411                                        true, priv->mode, true, true,
2412                                        xdp_desc.len);
2413
2414                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2415
2416                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
2417                 entry = tx_q->cur_tx;
2418         }
2419
2420         if (tx_desc) {
2421                 stmmac_flush_tx_descriptors(priv, queue);
2422                 xsk_tx_release(pool);
2423         }
2424
2425         /* Return true if all of the 3 conditions are met
2426          *  a) TX Budget is still available
2427          *  b) work_done = true when XSK TX desc peek is empty (no more
2428          *     pending XSK TX for transmission)
2429          */
2430         return !!budget && work_done;
2431 }
2432
2433 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan)
2434 {
2435         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) {
2436                 tc += 64;
2437
2438                 if (priv->plat->force_thresh_dma_mode)
2439                         stmmac_set_dma_operation_mode(priv, tc, tc, chan);
2440                 else
2441                         stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE,
2442                                                       chan);
2443
2444                 priv->xstats.threshold = tc;
2445         }
2446 }
2447
2448 /**
2449  * stmmac_tx_clean - to manage the transmission completion
2450  * @priv: driver private structure
2451  * @budget: napi budget limiting this functions packet handling
2452  * @queue: TX queue index
2453  * Description: it reclaims the transmit resources after transmission completes.
2454  */
2455 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2456 {
2457         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2458         unsigned int bytes_compl = 0, pkts_compl = 0;
2459         unsigned int entry, xmits = 0, count = 0;
2460
2461         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2462
2463         priv->xstats.tx_clean++;
2464
2465         tx_q->xsk_frames_done = 0;
2466
2467         entry = tx_q->dirty_tx;
2468
2469         /* Try to clean all TX complete frame in 1 shot */
2470         while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
2471                 struct xdp_frame *xdpf;
2472                 struct sk_buff *skb;
2473                 struct dma_desc *p;
2474                 int status;
2475
2476                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2477                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2478                         xdpf = tx_q->xdpf[entry];
2479                         skb = NULL;
2480                 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2481                         xdpf = NULL;
2482                         skb = tx_q->tx_skbuff[entry];
2483                 } else {
2484                         xdpf = NULL;
2485                         skb = NULL;
2486                 }
2487
2488                 if (priv->extend_desc)
2489                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
2490                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2491                         p = &tx_q->dma_entx[entry].basic;
2492                 else
2493                         p = tx_q->dma_tx + entry;
2494
2495                 status = stmmac_tx_status(priv, &priv->dev->stats,
2496                                 &priv->xstats, p, priv->ioaddr);
2497                 /* Check if the descriptor is owned by the DMA */
2498                 if (unlikely(status & tx_dma_own))
2499                         break;
2500
2501                 count++;
2502
2503                 /* Make sure descriptor fields are read after reading
2504                  * the own bit.
2505                  */
2506                 dma_rmb();
2507
2508                 /* Just consider the last segment and ...*/
2509                 if (likely(!(status & tx_not_ls))) {
2510                         /* ... verify the status error condition */
2511                         if (unlikely(status & tx_err)) {
2512                                 priv->dev->stats.tx_errors++;
2513                                 if (unlikely(status & tx_err_bump_tc))
2514                                         stmmac_bump_dma_threshold(priv, queue);
2515                         } else {
2516                                 priv->dev->stats.tx_packets++;
2517                                 priv->xstats.tx_pkt_n++;
2518                                 priv->xstats.txq_stats[queue].tx_pkt_n++;
2519                         }
2520                         if (skb)
2521                                 stmmac_get_tx_hwtstamp(priv, p, skb);
2522                 }
2523
2524                 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2525                            tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2526                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
2527                                 dma_unmap_page(priv->device,
2528                                                tx_q->tx_skbuff_dma[entry].buf,
2529                                                tx_q->tx_skbuff_dma[entry].len,
2530                                                DMA_TO_DEVICE);
2531                         else
2532                                 dma_unmap_single(priv->device,
2533                                                  tx_q->tx_skbuff_dma[entry].buf,
2534                                                  tx_q->tx_skbuff_dma[entry].len,
2535                                                  DMA_TO_DEVICE);
2536                         tx_q->tx_skbuff_dma[entry].buf = 0;
2537                         tx_q->tx_skbuff_dma[entry].len = 0;
2538                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
2539                 }
2540
2541                 stmmac_clean_desc3(priv, tx_q, p);
2542
2543                 tx_q->tx_skbuff_dma[entry].last_segment = false;
2544                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2545
2546                 if (xdpf &&
2547                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2548                         xdp_return_frame_rx_napi(xdpf);
2549                         tx_q->xdpf[entry] = NULL;
2550                 }
2551
2552                 if (xdpf &&
2553                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2554                         xdp_return_frame(xdpf);
2555                         tx_q->xdpf[entry] = NULL;
2556                 }
2557
2558                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2559                         tx_q->xsk_frames_done++;
2560
2561                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2562                         if (likely(skb)) {
2563                                 pkts_compl++;
2564                                 bytes_compl += skb->len;
2565                                 dev_consume_skb_any(skb);
2566                                 tx_q->tx_skbuff[entry] = NULL;
2567                         }
2568                 }
2569
2570                 stmmac_release_tx_desc(priv, p, priv->mode);
2571
2572                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
2573         }
2574         tx_q->dirty_tx = entry;
2575
2576         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2577                                   pkts_compl, bytes_compl);
2578
2579         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2580                                                                 queue))) &&
2581             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2582
2583                 netif_dbg(priv, tx_done, priv->dev,
2584                           "%s: restart transmit\n", __func__);
2585                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2586         }
2587
2588         if (tx_q->xsk_pool) {
2589                 bool work_done;
2590
2591                 if (tx_q->xsk_frames_done)
2592                         xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2593
2594                 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2595                         xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2596
2597                 /* For XSK TX, we try to send as many as possible.
2598                  * If XSK work done (XSK TX desc empty and budget still
2599                  * available), return "budget - 1" to reenable TX IRQ.
2600                  * Else, return "budget" to make NAPI continue polling.
2601                  */
2602                 work_done = stmmac_xdp_xmit_zc(priv, queue,
2603                                                STMMAC_XSK_TX_BUDGET_MAX);
2604                 if (work_done)
2605                         xmits = budget - 1;
2606                 else
2607                         xmits = budget;
2608         }
2609
2610         if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2611             priv->eee_sw_timer_en) {
2612                 stmmac_enable_eee_mode(priv);
2613                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2614         }
2615
2616         /* We still have pending packets, let's call for a new scheduling */
2617         if (tx_q->dirty_tx != tx_q->cur_tx)
2618                 hrtimer_start(&tx_q->txtimer,
2619                               STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2620                               HRTIMER_MODE_REL);
2621
2622         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2623
2624         /* Combine decisions from TX clean and XSK TX */
2625         return max(count, xmits);
2626 }
2627
2628 /**
2629  * stmmac_tx_err - to manage the tx error
2630  * @priv: driver private structure
2631  * @chan: channel index
2632  * Description: it cleans the descriptors and restarts the transmission
2633  * in case of transmission errors.
2634  */
2635 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2636 {
2637         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2638
2639         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2640
2641         stmmac_stop_tx_dma(priv, chan);
2642         dma_free_tx_skbufs(priv, chan);
2643         stmmac_clear_tx_descriptors(priv, chan);
2644         tx_q->dirty_tx = 0;
2645         tx_q->cur_tx = 0;
2646         tx_q->mss = 0;
2647         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2648         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2649                             tx_q->dma_tx_phy, chan);
2650         stmmac_start_tx_dma(priv, chan);
2651
2652         priv->dev->stats.tx_errors++;
2653         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2654 }
2655
2656 /**
2657  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2658  *  @priv: driver private structure
2659  *  @txmode: TX operating mode
2660  *  @rxmode: RX operating mode
2661  *  @chan: channel index
2662  *  Description: it is used for configuring of the DMA operation mode in
2663  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2664  *  mode.
2665  */
2666 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2667                                           u32 rxmode, u32 chan)
2668 {
2669         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2670         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2671         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2672         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2673         int rxfifosz = priv->plat->rx_fifo_size;
2674         int txfifosz = priv->plat->tx_fifo_size;
2675
2676         if (rxfifosz == 0)
2677                 rxfifosz = priv->dma_cap.rx_fifo_size;
2678         if (txfifosz == 0)
2679                 txfifosz = priv->dma_cap.tx_fifo_size;
2680
2681         /* Adjust for real per queue fifo size */
2682         rxfifosz /= rx_channels_count;
2683         txfifosz /= tx_channels_count;
2684
2685         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2686         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2687 }
2688
2689 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2690 {
2691         int ret;
2692
2693         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2694                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2695         if (ret && (ret != -EINVAL)) {
2696                 stmmac_global_err(priv);
2697                 return true;
2698         }
2699
2700         return false;
2701 }
2702
2703 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2704 {
2705         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2706                                                  &priv->xstats, chan, dir);
2707         struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2708         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2709         struct stmmac_channel *ch = &priv->channel[chan];
2710         struct napi_struct *rx_napi;
2711         struct napi_struct *tx_napi;
2712         unsigned long flags;
2713
2714         rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2715         tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2716
2717         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2718                 if (napi_schedule_prep(rx_napi)) {
2719                         spin_lock_irqsave(&ch->lock, flags);
2720                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2721                         spin_unlock_irqrestore(&ch->lock, flags);
2722                         __napi_schedule(rx_napi);
2723                 }
2724         }
2725
2726         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2727                 if (napi_schedule_prep(tx_napi)) {
2728                         spin_lock_irqsave(&ch->lock, flags);
2729                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2730                         spin_unlock_irqrestore(&ch->lock, flags);
2731                         __napi_schedule(tx_napi);
2732                 }
2733         }
2734
2735         return status;
2736 }
2737
2738 /**
2739  * stmmac_dma_interrupt - DMA ISR
2740  * @priv: driver private structure
2741  * Description: this is the DMA ISR. It is called by the main ISR.
2742  * It calls the dwmac dma routine and schedule poll method in case of some
2743  * work can be done.
2744  */
2745 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2746 {
2747         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2748         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2749         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2750                                 tx_channel_count : rx_channel_count;
2751         u32 chan;
2752         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2753
2754         /* Make sure we never check beyond our status buffer. */
2755         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2756                 channels_to_check = ARRAY_SIZE(status);
2757
2758         for (chan = 0; chan < channels_to_check; chan++)
2759                 status[chan] = stmmac_napi_check(priv, chan,
2760                                                  DMA_DIR_RXTX);
2761
2762         for (chan = 0; chan < tx_channel_count; chan++) {
2763                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2764                         /* Try to bump up the dma threshold on this failure */
2765                         stmmac_bump_dma_threshold(priv, chan);
2766                 } else if (unlikely(status[chan] == tx_hard_error)) {
2767                         stmmac_tx_err(priv, chan);
2768                 }
2769         }
2770 }
2771
2772 /**
2773  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2774  * @priv: driver private structure
2775  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2776  */
2777 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2778 {
2779         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2780                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2781
2782         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2783
2784         if (priv->dma_cap.rmon) {
2785                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2786                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2787         } else
2788                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2789 }
2790
2791 /**
2792  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2793  * @priv: driver private structure
2794  * Description:
2795  *  new GMAC chip generations have a new register to indicate the
2796  *  presence of the optional feature/functions.
2797  *  This can be also used to override the value passed through the
2798  *  platform and necessary for old MAC10/100 and GMAC chips.
2799  */
2800 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2801 {
2802         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2803 }
2804
2805 /**
2806  * stmmac_check_ether_addr - check if the MAC addr is valid
2807  * @priv: driver private structure
2808  * Description:
2809  * it is to verify if the MAC address is valid, in case of failures it
2810  * generates a random MAC address
2811  */
2812 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2813 {
2814         u8 addr[ETH_ALEN];
2815
2816         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2817                 stmmac_get_umac_addr(priv, priv->hw, addr, 0);
2818                 if (is_valid_ether_addr(addr))
2819                         eth_hw_addr_set(priv->dev, addr);
2820                 else
2821                         eth_hw_addr_random(priv->dev);
2822                 dev_info(priv->device, "device MAC address %pM\n",
2823                          priv->dev->dev_addr);
2824         }
2825 }
2826
2827 /**
2828  * stmmac_init_dma_engine - DMA init.
2829  * @priv: driver private structure
2830  * Description:
2831  * It inits the DMA invoking the specific MAC/GMAC callback.
2832  * Some DMA parameters can be passed from the platform;
2833  * in case of these are not passed a default is kept for the MAC or GMAC.
2834  */
2835 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2836 {
2837         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2838         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2839         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2840         struct stmmac_rx_queue *rx_q;
2841         struct stmmac_tx_queue *tx_q;
2842         u32 chan = 0;
2843         int atds = 0;
2844         int ret = 0;
2845
2846         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2847                 dev_err(priv->device, "Invalid DMA configuration\n");
2848                 return -EINVAL;
2849         }
2850
2851         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2852                 atds = 1;
2853
2854         ret = stmmac_reset(priv, priv->ioaddr);
2855         if (ret) {
2856                 dev_err(priv->device, "Failed to reset the dma\n");
2857                 return ret;
2858         }
2859
2860         /* DMA Configuration */
2861         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2862
2863         if (priv->plat->axi)
2864                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2865
2866         /* DMA CSR Channel configuration */
2867         for (chan = 0; chan < dma_csr_ch; chan++)
2868                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2869
2870         /* DMA RX Channel Configuration */
2871         for (chan = 0; chan < rx_channels_count; chan++) {
2872                 rx_q = &priv->rx_queue[chan];
2873
2874                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2875                                     rx_q->dma_rx_phy, chan);
2876
2877                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2878                                      (rx_q->buf_alloc_num *
2879                                       sizeof(struct dma_desc));
2880                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2881                                        rx_q->rx_tail_addr, chan);
2882         }
2883
2884         /* DMA TX Channel Configuration */
2885         for (chan = 0; chan < tx_channels_count; chan++) {
2886                 tx_q = &priv->tx_queue[chan];
2887
2888                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2889                                     tx_q->dma_tx_phy, chan);
2890
2891                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2892                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2893                                        tx_q->tx_tail_addr, chan);
2894         }
2895
2896         return ret;
2897 }
2898
2899 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2900 {
2901         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2902
2903         hrtimer_start(&tx_q->txtimer,
2904                       STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2905                       HRTIMER_MODE_REL);
2906 }
2907
2908 /**
2909  * stmmac_tx_timer - mitigation sw timer for tx.
2910  * @t: data pointer
2911  * Description:
2912  * This is the timer handler to directly invoke the stmmac_tx_clean.
2913  */
2914 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
2915 {
2916         struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
2917         struct stmmac_priv *priv = tx_q->priv_data;
2918         struct stmmac_channel *ch;
2919         struct napi_struct *napi;
2920
2921         ch = &priv->channel[tx_q->queue_index];
2922         napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2923
2924         if (likely(napi_schedule_prep(napi))) {
2925                 unsigned long flags;
2926
2927                 spin_lock_irqsave(&ch->lock, flags);
2928                 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2929                 spin_unlock_irqrestore(&ch->lock, flags);
2930                 __napi_schedule(napi);
2931         }
2932
2933         return HRTIMER_NORESTART;
2934 }
2935
2936 /**
2937  * stmmac_init_coalesce - init mitigation options.
2938  * @priv: driver private structure
2939  * Description:
2940  * This inits the coalesce parameters: i.e. timer rate,
2941  * timer handler and default threshold used for enabling the
2942  * interrupt on completion bit.
2943  */
2944 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2945 {
2946         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2947         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2948         u32 chan;
2949
2950         for (chan = 0; chan < tx_channel_count; chan++) {
2951                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2952
2953                 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
2954                 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
2955
2956                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2957                 tx_q->txtimer.function = stmmac_tx_timer;
2958         }
2959
2960         for (chan = 0; chan < rx_channel_count; chan++)
2961                 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
2962 }
2963
2964 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2965 {
2966         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2967         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2968         u32 chan;
2969
2970         /* set TX ring length */
2971         for (chan = 0; chan < tx_channels_count; chan++)
2972                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2973                                        (priv->dma_tx_size - 1), chan);
2974
2975         /* set RX ring length */
2976         for (chan = 0; chan < rx_channels_count; chan++)
2977                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2978                                        (priv->dma_rx_size - 1), chan);
2979 }
2980
2981 /**
2982  *  stmmac_set_tx_queue_weight - Set TX queue weight
2983  *  @priv: driver private structure
2984  *  Description: It is used for setting TX queues weight
2985  */
2986 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2987 {
2988         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2989         u32 weight;
2990         u32 queue;
2991
2992         for (queue = 0; queue < tx_queues_count; queue++) {
2993                 weight = priv->plat->tx_queues_cfg[queue].weight;
2994                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2995         }
2996 }
2997
2998 /**
2999  *  stmmac_configure_cbs - Configure CBS in TX queue
3000  *  @priv: driver private structure
3001  *  Description: It is used for configuring CBS in AVB TX queues
3002  */
3003 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3004 {
3005         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3006         u32 mode_to_use;
3007         u32 queue;
3008
3009         /* queue 0 is reserved for legacy traffic */
3010         for (queue = 1; queue < tx_queues_count; queue++) {
3011                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3012                 if (mode_to_use == MTL_QUEUE_DCB)
3013                         continue;
3014
3015                 stmmac_config_cbs(priv, priv->hw,
3016                                 priv->plat->tx_queues_cfg[queue].send_slope,
3017                                 priv->plat->tx_queues_cfg[queue].idle_slope,
3018                                 priv->plat->tx_queues_cfg[queue].high_credit,
3019                                 priv->plat->tx_queues_cfg[queue].low_credit,
3020                                 queue);
3021         }
3022 }
3023
3024 /**
3025  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3026  *  @priv: driver private structure
3027  *  Description: It is used for mapping RX queues to RX dma channels
3028  */
3029 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3030 {
3031         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3032         u32 queue;
3033         u32 chan;
3034
3035         for (queue = 0; queue < rx_queues_count; queue++) {
3036                 chan = priv->plat->rx_queues_cfg[queue].chan;
3037                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3038         }
3039 }
3040
3041 /**
3042  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3043  *  @priv: driver private structure
3044  *  Description: It is used for configuring the RX Queue Priority
3045  */
3046 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3047 {
3048         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3049         u32 queue;
3050         u32 prio;
3051
3052         for (queue = 0; queue < rx_queues_count; queue++) {
3053                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3054                         continue;
3055
3056                 prio = priv->plat->rx_queues_cfg[queue].prio;
3057                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3058         }
3059 }
3060
3061 /**
3062  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3063  *  @priv: driver private structure
3064  *  Description: It is used for configuring the TX Queue Priority
3065  */
3066 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3067 {
3068         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3069         u32 queue;
3070         u32 prio;
3071
3072         for (queue = 0; queue < tx_queues_count; queue++) {
3073                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3074                         continue;
3075
3076                 prio = priv->plat->tx_queues_cfg[queue].prio;
3077                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3078         }
3079 }
3080
3081 /**
3082  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3083  *  @priv: driver private structure
3084  *  Description: It is used for configuring the RX queue routing
3085  */
3086 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3087 {
3088         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3089         u32 queue;
3090         u8 packet;
3091
3092         for (queue = 0; queue < rx_queues_count; queue++) {
3093                 /* no specific packet type routing specified for the queue */
3094                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3095                         continue;
3096
3097                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3098                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3099         }
3100 }
3101
3102 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3103 {
3104         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3105                 priv->rss.enable = false;
3106                 return;
3107         }
3108
3109         if (priv->dev->features & NETIF_F_RXHASH)
3110                 priv->rss.enable = true;
3111         else
3112                 priv->rss.enable = false;
3113
3114         stmmac_rss_configure(priv, priv->hw, &priv->rss,
3115                              priv->plat->rx_queues_to_use);
3116 }
3117
3118 /**
3119  *  stmmac_mtl_configuration - Configure MTL
3120  *  @priv: driver private structure
3121  *  Description: It is used for configurring MTL
3122  */
3123 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3124 {
3125         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3126         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3127
3128         if (tx_queues_count > 1)
3129                 stmmac_set_tx_queue_weight(priv);
3130
3131         /* Configure MTL RX algorithms */
3132         if (rx_queues_count > 1)
3133                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3134                                 priv->plat->rx_sched_algorithm);
3135
3136         /* Configure MTL TX algorithms */
3137         if (tx_queues_count > 1)
3138                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3139                                 priv->plat->tx_sched_algorithm);
3140
3141         /* Configure CBS in AVB TX queues */
3142         if (tx_queues_count > 1)
3143                 stmmac_configure_cbs(priv);
3144
3145         /* Map RX MTL to DMA channels */
3146         stmmac_rx_queue_dma_chan_map(priv);
3147
3148         /* Enable MAC RX Queues */
3149         stmmac_mac_enable_rx_queues(priv);
3150
3151         /* Set RX priorities */
3152         if (rx_queues_count > 1)
3153                 stmmac_mac_config_rx_queues_prio(priv);
3154
3155         /* Set TX priorities */
3156         if (tx_queues_count > 1)
3157                 stmmac_mac_config_tx_queues_prio(priv);
3158
3159         /* Set RX routing */
3160         if (rx_queues_count > 1)
3161                 stmmac_mac_config_rx_queues_routing(priv);
3162
3163         /* Receive Side Scaling */
3164         if (rx_queues_count > 1)
3165                 stmmac_mac_config_rss(priv);
3166 }
3167
3168 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3169 {
3170         if (priv->dma_cap.asp) {
3171                 netdev_info(priv->dev, "Enabling Safety Features\n");
3172                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3173                                           priv->plat->safety_feat_cfg);
3174         } else {
3175                 netdev_info(priv->dev, "No Safety Features support found\n");
3176         }
3177 }
3178
3179 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3180 {
3181         char *name;
3182
3183         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3184         clear_bit(__FPE_REMOVING,  &priv->fpe_task_state);
3185
3186         name = priv->wq_name;
3187         sprintf(name, "%s-fpe", priv->dev->name);
3188
3189         priv->fpe_wq = create_singlethread_workqueue(name);
3190         if (!priv->fpe_wq) {
3191                 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3192
3193                 return -ENOMEM;
3194         }
3195         netdev_info(priv->dev, "FPE workqueue start");
3196
3197         return 0;
3198 }
3199
3200 /**
3201  * stmmac_hw_setup - setup mac in a usable state.
3202  *  @dev : pointer to the device structure.
3203  *  @init_ptp: initialize PTP if set
3204  *  Description:
3205  *  this is the main function to setup the HW in a usable state because the
3206  *  dma engine is reset, the core registers are configured (e.g. AXI,
3207  *  Checksum features, timers). The DMA is ready to start receiving and
3208  *  transmitting.
3209  *  Return value:
3210  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3211  *  file on failure.
3212  */
3213 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
3214 {
3215         struct stmmac_priv *priv = netdev_priv(dev);
3216         u32 rx_cnt = priv->plat->rx_queues_to_use;
3217         u32 tx_cnt = priv->plat->tx_queues_to_use;
3218         bool sph_en;
3219         u32 chan;
3220         int ret;
3221
3222         /* DMA initialization and SW reset */
3223         ret = stmmac_init_dma_engine(priv);
3224         if (ret < 0) {
3225                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3226                            __func__);
3227                 return ret;
3228         }
3229
3230         /* Copy the MAC addr into the HW  */
3231         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3232
3233         /* PS and related bits will be programmed according to the speed */
3234         if (priv->hw->pcs) {
3235                 int speed = priv->plat->mac_port_sel_speed;
3236
3237                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3238                     (speed == SPEED_1000)) {
3239                         priv->hw->ps = speed;
3240                 } else {
3241                         dev_warn(priv->device, "invalid port speed\n");
3242                         priv->hw->ps = 0;
3243                 }
3244         }
3245
3246         /* Initialize the MAC Core */
3247         stmmac_core_init(priv, priv->hw, dev);
3248
3249         /* Initialize MTL*/
3250         stmmac_mtl_configuration(priv);
3251
3252         /* Initialize Safety Features */
3253         stmmac_safety_feat_configuration(priv);
3254
3255         ret = stmmac_rx_ipc(priv, priv->hw);
3256         if (!ret) {
3257                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3258                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3259                 priv->hw->rx_csum = 0;
3260         }
3261
3262         /* Enable the MAC Rx/Tx */
3263         stmmac_mac_set(priv, priv->ioaddr, true);
3264
3265         /* Set the HW DMA mode and the COE */
3266         stmmac_dma_operation_mode(priv);
3267
3268         stmmac_mmc_setup(priv);
3269
3270         if (init_ptp) {
3271                 ret = stmmac_init_ptp(priv);
3272                 if (ret == -EOPNOTSUPP)
3273                         netdev_warn(priv->dev, "PTP not supported by HW\n");
3274                 else if (ret)
3275                         netdev_warn(priv->dev, "PTP init failed\n");
3276         }
3277
3278         priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3279
3280         /* Convert the timer from msec to usec */
3281         if (!priv->tx_lpi_timer)
3282                 priv->tx_lpi_timer = eee_timer * 1000;
3283
3284         if (priv->use_riwt) {
3285                 u32 queue;
3286
3287                 for (queue = 0; queue < rx_cnt; queue++) {
3288                         if (!priv->rx_riwt[queue])
3289                                 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3290
3291                         stmmac_rx_watchdog(priv, priv->ioaddr,
3292                                            priv->rx_riwt[queue], queue);
3293                 }
3294         }
3295
3296         if (priv->hw->pcs)
3297                 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3298
3299         /* set TX and RX rings length */
3300         stmmac_set_rings_length(priv);
3301
3302         /* Enable TSO */
3303         if (priv->tso) {
3304                 for (chan = 0; chan < tx_cnt; chan++) {
3305                         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3306
3307                         /* TSO and TBS cannot co-exist */
3308                         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3309                                 continue;
3310
3311                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3312                 }
3313         }
3314
3315         /* Enable Split Header */
3316         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3317         for (chan = 0; chan < rx_cnt; chan++)
3318                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3319
3320
3321         /* VLAN Tag Insertion */
3322         if (priv->dma_cap.vlins)
3323                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3324
3325         /* TBS */
3326         for (chan = 0; chan < tx_cnt; chan++) {
3327                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3328                 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3329
3330                 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3331         }
3332
3333         /* Configure real RX and TX queues */
3334         netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3335         netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3336
3337         /* Start the ball rolling... */
3338         stmmac_start_all_dma(priv);
3339
3340         if (priv->dma_cap.fpesel) {
3341                 stmmac_fpe_start_wq(priv);
3342
3343                 if (priv->plat->fpe_cfg->enable)
3344                         stmmac_fpe_handshake(priv, true);
3345         }
3346
3347         return 0;
3348 }
3349
3350 static void stmmac_hw_teardown(struct net_device *dev)
3351 {
3352         struct stmmac_priv *priv = netdev_priv(dev);
3353
3354         clk_disable_unprepare(priv->plat->clk_ptp_ref);
3355 }
3356
3357 static void stmmac_free_irq(struct net_device *dev,
3358                             enum request_irq_err irq_err, int irq_idx)
3359 {
3360         struct stmmac_priv *priv = netdev_priv(dev);
3361         int j;
3362
3363         switch (irq_err) {
3364         case REQ_IRQ_ERR_ALL:
3365                 irq_idx = priv->plat->tx_queues_to_use;
3366                 fallthrough;
3367         case REQ_IRQ_ERR_TX:
3368                 for (j = irq_idx - 1; j >= 0; j--) {
3369                         if (priv->tx_irq[j] > 0) {
3370                                 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3371                                 free_irq(priv->tx_irq[j], &priv->tx_queue[j]);
3372                         }
3373                 }
3374                 irq_idx = priv->plat->rx_queues_to_use;
3375                 fallthrough;
3376         case REQ_IRQ_ERR_RX:
3377                 for (j = irq_idx - 1; j >= 0; j--) {
3378                         if (priv->rx_irq[j] > 0) {
3379                                 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3380                                 free_irq(priv->rx_irq[j], &priv->rx_queue[j]);
3381                         }
3382                 }
3383
3384                 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3385                         free_irq(priv->sfty_ue_irq, dev);
3386                 fallthrough;
3387         case REQ_IRQ_ERR_SFTY_UE:
3388                 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3389                         free_irq(priv->sfty_ce_irq, dev);
3390                 fallthrough;
3391         case REQ_IRQ_ERR_SFTY_CE:
3392                 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3393                         free_irq(priv->lpi_irq, dev);
3394                 fallthrough;
3395         case REQ_IRQ_ERR_LPI:
3396                 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3397                         free_irq(priv->wol_irq, dev);
3398                 fallthrough;
3399         case REQ_IRQ_ERR_WOL:
3400                 free_irq(dev->irq, dev);
3401                 fallthrough;
3402         case REQ_IRQ_ERR_MAC:
3403         case REQ_IRQ_ERR_NO:
3404                 /* If MAC IRQ request error, no more IRQ to free */
3405                 break;
3406         }
3407 }
3408
3409 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3410 {
3411         struct stmmac_priv *priv = netdev_priv(dev);
3412         enum request_irq_err irq_err;
3413         cpumask_t cpu_mask;
3414         int irq_idx = 0;
3415         char *int_name;
3416         int ret;
3417         int i;
3418
3419         /* For common interrupt */
3420         int_name = priv->int_name_mac;
3421         sprintf(int_name, "%s:%s", dev->name, "mac");
3422         ret = request_irq(dev->irq, stmmac_mac_interrupt,
3423                           0, int_name, dev);
3424         if (unlikely(ret < 0)) {
3425                 netdev_err(priv->dev,
3426                            "%s: alloc mac MSI %d (error: %d)\n",
3427                            __func__, dev->irq, ret);
3428                 irq_err = REQ_IRQ_ERR_MAC;
3429                 goto irq_error;
3430         }
3431
3432         /* Request the Wake IRQ in case of another line
3433          * is used for WoL
3434          */
3435         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3436                 int_name = priv->int_name_wol;
3437                 sprintf(int_name, "%s:%s", dev->name, "wol");
3438                 ret = request_irq(priv->wol_irq,
3439                                   stmmac_mac_interrupt,
3440                                   0, int_name, dev);
3441                 if (unlikely(ret < 0)) {
3442                         netdev_err(priv->dev,
3443                                    "%s: alloc wol MSI %d (error: %d)\n",
3444                                    __func__, priv->wol_irq, ret);
3445                         irq_err = REQ_IRQ_ERR_WOL;
3446                         goto irq_error;
3447                 }
3448         }
3449
3450         /* Request the LPI IRQ in case of another line
3451          * is used for LPI
3452          */
3453         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3454                 int_name = priv->int_name_lpi;
3455                 sprintf(int_name, "%s:%s", dev->name, "lpi");
3456                 ret = request_irq(priv->lpi_irq,
3457                                   stmmac_mac_interrupt,
3458                                   0, int_name, dev);
3459                 if (unlikely(ret < 0)) {
3460                         netdev_err(priv->dev,
3461                                    "%s: alloc lpi MSI %d (error: %d)\n",
3462                                    __func__, priv->lpi_irq, ret);
3463                         irq_err = REQ_IRQ_ERR_LPI;
3464                         goto irq_error;
3465                 }
3466         }
3467
3468         /* Request the Safety Feature Correctible Error line in
3469          * case of another line is used
3470          */
3471         if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3472                 int_name = priv->int_name_sfty_ce;
3473                 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3474                 ret = request_irq(priv->sfty_ce_irq,
3475                                   stmmac_safety_interrupt,
3476                                   0, int_name, dev);
3477                 if (unlikely(ret < 0)) {
3478                         netdev_err(priv->dev,
3479                                    "%s: alloc sfty ce MSI %d (error: %d)\n",
3480                                    __func__, priv->sfty_ce_irq, ret);
3481                         irq_err = REQ_IRQ_ERR_SFTY_CE;
3482                         goto irq_error;
3483                 }
3484         }
3485
3486         /* Request the Safety Feature Uncorrectible Error line in
3487          * case of another line is used
3488          */
3489         if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3490                 int_name = priv->int_name_sfty_ue;
3491                 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3492                 ret = request_irq(priv->sfty_ue_irq,
3493                                   stmmac_safety_interrupt,
3494                                   0, int_name, dev);
3495                 if (unlikely(ret < 0)) {
3496                         netdev_err(priv->dev,
3497                                    "%s: alloc sfty ue MSI %d (error: %d)\n",
3498                                    __func__, priv->sfty_ue_irq, ret);
3499                         irq_err = REQ_IRQ_ERR_SFTY_UE;
3500                         goto irq_error;
3501                 }
3502         }
3503
3504         /* Request Rx MSI irq */
3505         for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3506                 if (i >= MTL_MAX_RX_QUEUES)
3507                         break;
3508                 if (priv->rx_irq[i] == 0)
3509                         continue;
3510
3511                 int_name = priv->int_name_rx_irq[i];
3512                 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3513                 ret = request_irq(priv->rx_irq[i],
3514                                   stmmac_msi_intr_rx,
3515                                   0, int_name, &priv->rx_queue[i]);
3516                 if (unlikely(ret < 0)) {
3517                         netdev_err(priv->dev,
3518                                    "%s: alloc rx-%d  MSI %d (error: %d)\n",
3519                                    __func__, i, priv->rx_irq[i], ret);
3520                         irq_err = REQ_IRQ_ERR_RX;
3521                         irq_idx = i;
3522                         goto irq_error;
3523                 }
3524                 cpumask_clear(&cpu_mask);
3525                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3526                 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3527         }
3528
3529         /* Request Tx MSI irq */
3530         for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3531                 if (i >= MTL_MAX_TX_QUEUES)
3532                         break;
3533                 if (priv->tx_irq[i] == 0)
3534                         continue;
3535
3536                 int_name = priv->int_name_tx_irq[i];
3537                 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3538                 ret = request_irq(priv->tx_irq[i],
3539                                   stmmac_msi_intr_tx,
3540                                   0, int_name, &priv->tx_queue[i]);
3541                 if (unlikely(ret < 0)) {
3542                         netdev_err(priv->dev,
3543                                    "%s: alloc tx-%d  MSI %d (error: %d)\n",
3544                                    __func__, i, priv->tx_irq[i], ret);
3545                         irq_err = REQ_IRQ_ERR_TX;
3546                         irq_idx = i;
3547                         goto irq_error;
3548                 }
3549                 cpumask_clear(&cpu_mask);
3550                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3551                 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3552         }
3553
3554         return 0;
3555
3556 irq_error:
3557         stmmac_free_irq(dev, irq_err, irq_idx);
3558         return ret;
3559 }
3560
3561 static int stmmac_request_irq_single(struct net_device *dev)
3562 {
3563         struct stmmac_priv *priv = netdev_priv(dev);
3564         enum request_irq_err irq_err;
3565         int ret;
3566
3567         ret = request_irq(dev->irq, stmmac_interrupt,
3568                           IRQF_SHARED, dev->name, dev);
3569         if (unlikely(ret < 0)) {
3570                 netdev_err(priv->dev,
3571                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3572                            __func__, dev->irq, ret);
3573                 irq_err = REQ_IRQ_ERR_MAC;
3574                 goto irq_error;
3575         }
3576
3577         /* Request the Wake IRQ in case of another line
3578          * is used for WoL
3579          */
3580         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3581                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3582                                   IRQF_SHARED, dev->name, dev);
3583                 if (unlikely(ret < 0)) {
3584                         netdev_err(priv->dev,
3585                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3586                                    __func__, priv->wol_irq, ret);
3587                         irq_err = REQ_IRQ_ERR_WOL;
3588                         goto irq_error;
3589                 }
3590         }
3591
3592         /* Request the IRQ lines */
3593         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3594                 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3595                                   IRQF_SHARED, dev->name, dev);
3596                 if (unlikely(ret < 0)) {
3597                         netdev_err(priv->dev,
3598                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3599                                    __func__, priv->lpi_irq, ret);
3600                         irq_err = REQ_IRQ_ERR_LPI;
3601                         goto irq_error;
3602                 }
3603         }
3604
3605         return 0;
3606
3607 irq_error:
3608         stmmac_free_irq(dev, irq_err, 0);
3609         return ret;
3610 }
3611
3612 static int stmmac_request_irq(struct net_device *dev)
3613 {
3614         struct stmmac_priv *priv = netdev_priv(dev);
3615         int ret;
3616
3617         /* Request the IRQ lines */
3618         if (priv->plat->multi_msi_en)
3619                 ret = stmmac_request_irq_multi_msi(dev);
3620         else
3621                 ret = stmmac_request_irq_single(dev);
3622
3623         return ret;
3624 }
3625
3626 /**
3627  *  stmmac_open - open entry point of the driver
3628  *  @dev : pointer to the device structure.
3629  *  Description:
3630  *  This function is the open entry point of the driver.
3631  *  Return value:
3632  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3633  *  file on failure.
3634  */
3635 static int stmmac_open(struct net_device *dev)
3636 {
3637         struct stmmac_priv *priv = netdev_priv(dev);
3638         int mode = priv->plat->phy_interface;
3639         int bfsize = 0;
3640         u32 chan;
3641         int ret;
3642
3643         ret = pm_runtime_get_sync(priv->device);
3644         if (ret < 0) {
3645                 pm_runtime_put_noidle(priv->device);
3646                 return ret;
3647         }
3648
3649         if (priv->hw->pcs != STMMAC_PCS_TBI &&
3650             priv->hw->pcs != STMMAC_PCS_RTBI &&
3651             (!priv->hw->xpcs ||
3652              xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3653                 ret = stmmac_init_phy(dev);
3654                 if (ret) {
3655                         netdev_err(priv->dev,
3656                                    "%s: Cannot attach to PHY (error: %d)\n",
3657                                    __func__, ret);
3658                         goto init_phy_error;
3659                 }
3660         }
3661
3662         /* Extra statistics */
3663         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3664         priv->xstats.threshold = tc;
3665
3666         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
3667         if (bfsize < 0)
3668                 bfsize = 0;
3669
3670         if (bfsize < BUF_SIZE_16KiB)
3671                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
3672
3673         priv->dma_buf_sz = bfsize;
3674         buf_sz = bfsize;
3675
3676         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3677
3678         if (!priv->dma_tx_size)
3679                 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3680         if (!priv->dma_rx_size)
3681                 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3682
3683         /* Earlier check for TBS */
3684         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3685                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3686                 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3687
3688                 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3689                 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3690         }
3691
3692         ret = alloc_dma_desc_resources(priv);
3693         if (ret < 0) {
3694                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3695                            __func__);
3696                 goto dma_desc_error;
3697         }
3698
3699         ret = init_dma_desc_rings(dev, GFP_KERNEL);
3700         if (ret < 0) {
3701                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3702                            __func__);
3703                 goto init_error;
3704         }
3705
3706         ret = stmmac_hw_setup(dev, true);
3707         if (ret < 0) {
3708                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3709                 goto init_error;
3710         }
3711
3712         stmmac_init_coalesce(priv);
3713
3714         phylink_start(priv->phylink);
3715         /* We may have called phylink_speed_down before */
3716         phylink_speed_up(priv->phylink);
3717
3718         ret = stmmac_request_irq(dev);
3719         if (ret)
3720                 goto irq_error;
3721
3722         stmmac_enable_all_queues(priv);
3723         netif_tx_start_all_queues(priv->dev);
3724
3725         return 0;
3726
3727 irq_error:
3728         phylink_stop(priv->phylink);
3729
3730         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3731                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3732
3733         stmmac_hw_teardown(dev);
3734 init_error:
3735         free_dma_desc_resources(priv);
3736 dma_desc_error:
3737         phylink_disconnect_phy(priv->phylink);
3738 init_phy_error:
3739         pm_runtime_put(priv->device);
3740         return ret;
3741 }
3742
3743 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3744 {
3745         set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3746
3747         if (priv->fpe_wq)
3748                 destroy_workqueue(priv->fpe_wq);
3749
3750         netdev_info(priv->dev, "FPE workqueue stop");
3751 }
3752
3753 /**
3754  *  stmmac_release - close entry point of the driver
3755  *  @dev : device pointer.
3756  *  Description:
3757  *  This is the stop entry point of the driver.
3758  */
3759 static int stmmac_release(struct net_device *dev)
3760 {
3761         struct stmmac_priv *priv = netdev_priv(dev);
3762         u32 chan;
3763
3764         netif_tx_disable(dev);
3765
3766         if (device_may_wakeup(priv->device))
3767                 phylink_speed_down(priv->phylink, false);
3768         /* Stop and disconnect the PHY */
3769         phylink_stop(priv->phylink);
3770         phylink_disconnect_phy(priv->phylink);
3771
3772         stmmac_disable_all_queues(priv);
3773
3774         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3775                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3776
3777         /* Free the IRQ lines */
3778         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3779
3780         if (priv->eee_enabled) {
3781                 priv->tx_path_in_lpi_mode = false;
3782                 del_timer_sync(&priv->eee_ctrl_timer);
3783         }
3784
3785         /* Stop TX/RX DMA and clear the descriptors */
3786         stmmac_stop_all_dma(priv);
3787
3788         /* Release and free the Rx/Tx resources */
3789         free_dma_desc_resources(priv);
3790
3791         /* Disable the MAC Rx/Tx */
3792         stmmac_mac_set(priv, priv->ioaddr, false);
3793
3794         netif_carrier_off(dev);
3795
3796         stmmac_release_ptp(priv);
3797
3798         pm_runtime_put(priv->device);
3799
3800         if (priv->dma_cap.fpesel)
3801                 stmmac_fpe_stop_wq(priv);
3802
3803         return 0;
3804 }
3805
3806 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3807                                struct stmmac_tx_queue *tx_q)
3808 {
3809         u16 tag = 0x0, inner_tag = 0x0;
3810         u32 inner_type = 0x0;
3811         struct dma_desc *p;
3812
3813         if (!priv->dma_cap.vlins)
3814                 return false;
3815         if (!skb_vlan_tag_present(skb))
3816                 return false;
3817         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3818                 inner_tag = skb_vlan_tag_get(skb);
3819                 inner_type = STMMAC_VLAN_INSERT;
3820         }
3821
3822         tag = skb_vlan_tag_get(skb);
3823
3824         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3825                 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3826         else
3827                 p = &tx_q->dma_tx[tx_q->cur_tx];
3828
3829         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3830                 return false;
3831
3832         stmmac_set_tx_owner(priv, p);
3833         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
3834         return true;
3835 }
3836
3837 /**
3838  *  stmmac_tso_allocator - close entry point of the driver
3839  *  @priv: driver private structure
3840  *  @des: buffer start address
3841  *  @total_len: total length to fill in descriptors
3842  *  @last_segment: condition for the last descriptor
3843  *  @queue: TX queue index
3844  *  Description:
3845  *  This function fills descriptor and request new descriptors according to
3846  *  buffer length to fill
3847  */
3848 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
3849                                  int total_len, bool last_segment, u32 queue)
3850 {
3851         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3852         struct dma_desc *desc;
3853         u32 buff_size;
3854         int tmp_len;
3855
3856         tmp_len = total_len;
3857
3858         while (tmp_len > 0) {
3859                 dma_addr_t curr_addr;
3860
3861                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3862                                                 priv->dma_tx_size);
3863                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3864
3865                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3866                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3867                 else
3868                         desc = &tx_q->dma_tx[tx_q->cur_tx];
3869
3870                 curr_addr = des + (total_len - tmp_len);
3871                 if (priv->dma_cap.addr64 <= 32)
3872                         desc->des0 = cpu_to_le32(curr_addr);
3873                 else
3874                         stmmac_set_desc_addr(priv, desc, curr_addr);
3875
3876                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
3877                             TSO_MAX_BUFF_SIZE : tmp_len;
3878
3879                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3880                                 0, 1,
3881                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3882                                 0, 0);
3883
3884                 tmp_len -= TSO_MAX_BUFF_SIZE;
3885         }
3886 }
3887
3888 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
3889 {
3890         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3891         int desc_size;
3892
3893         if (likely(priv->extend_desc))
3894                 desc_size = sizeof(struct dma_extended_desc);
3895         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3896                 desc_size = sizeof(struct dma_edesc);
3897         else
3898                 desc_size = sizeof(struct dma_desc);
3899
3900         /* The own bit must be the latest setting done when prepare the
3901          * descriptor and then barrier is needed to make sure that
3902          * all is coherent before granting the DMA engine.
3903          */
3904         wmb();
3905
3906         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3907         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3908 }
3909
3910 /**
3911  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3912  *  @skb : the socket buffer
3913  *  @dev : device pointer
3914  *  Description: this is the transmit function that is called on TSO frames
3915  *  (support available on GMAC4 and newer chips).
3916  *  Diagram below show the ring programming in case of TSO frames:
3917  *
3918  *  First Descriptor
3919  *   --------
3920  *   | DES0 |---> buffer1 = L2/L3/L4 header
3921  *   | DES1 |---> TCP Payload (can continue on next descr...)
3922  *   | DES2 |---> buffer 1 and 2 len
3923  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3924  *   --------
3925  *      |
3926  *     ...
3927  *      |
3928  *   --------
3929  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
3930  *   | DES1 | --|
3931  *   | DES2 | --> buffer 1 and 2 len
3932  *   | DES3 |
3933  *   --------
3934  *
3935  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3936  */
3937 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3938 {
3939         struct dma_desc *desc, *first, *mss_desc = NULL;
3940         struct stmmac_priv *priv = netdev_priv(dev);
3941         int nfrags = skb_shinfo(skb)->nr_frags;
3942         u32 queue = skb_get_queue_mapping(skb);
3943         unsigned int first_entry, tx_packets;
3944         int tmp_pay_len = 0, first_tx;
3945         struct stmmac_tx_queue *tx_q;
3946         bool has_vlan, set_ic;
3947         u8 proto_hdr_len, hdr;
3948         u32 pay_len, mss;
3949         dma_addr_t des;
3950         int i;
3951
3952         tx_q = &priv->tx_queue[queue];
3953         first_tx = tx_q->cur_tx;
3954
3955         /* Compute header lengths */
3956         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3957                 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3958                 hdr = sizeof(struct udphdr);
3959         } else {
3960                 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3961                 hdr = tcp_hdrlen(skb);
3962         }
3963
3964         /* Desc availability based on threshold should be enough safe */
3965         if (unlikely(stmmac_tx_avail(priv, queue) <
3966                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
3967                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3968                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3969                                                                 queue));
3970                         /* This is a hard error, log it. */
3971                         netdev_err(priv->dev,
3972                                    "%s: Tx Ring full when queue awake\n",
3973                                    __func__);
3974                 }
3975                 return NETDEV_TX_BUSY;
3976         }
3977
3978         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
3979
3980         mss = skb_shinfo(skb)->gso_size;
3981
3982         /* set new MSS value if needed */
3983         if (mss != tx_q->mss) {
3984                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3985                         mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3986                 else
3987                         mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
3988
3989                 stmmac_set_mss(priv, mss_desc, mss);
3990                 tx_q->mss = mss;
3991                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3992                                                 priv->dma_tx_size);
3993                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3994         }
3995
3996         if (netif_msg_tx_queued(priv)) {
3997                 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
3998                         __func__, hdr, proto_hdr_len, pay_len, mss);
3999                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
4000                         skb->data_len);
4001         }
4002
4003         /* Check if VLAN can be inserted by HW */
4004         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4005
4006         first_entry = tx_q->cur_tx;
4007         WARN_ON(tx_q->tx_skbuff[first_entry]);
4008
4009         if (tx_q->tbs & STMMAC_TBS_AVAIL)
4010                 desc = &tx_q->dma_entx[first_entry].basic;
4011         else
4012                 desc = &tx_q->dma_tx[first_entry];
4013         first = desc;
4014
4015         if (has_vlan)
4016                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4017
4018         /* first descriptor: fill Headers on Buf1 */
4019         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4020                              DMA_TO_DEVICE);
4021         if (dma_mapping_error(priv->device, des))
4022                 goto dma_map_err;
4023
4024         tx_q->tx_skbuff_dma[first_entry].buf = des;
4025         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4026         tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4027         tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4028
4029         if (priv->dma_cap.addr64 <= 32) {
4030                 first->des0 = cpu_to_le32(des);
4031
4032                 /* Fill start of payload in buff2 of first descriptor */
4033                 if (pay_len)
4034                         first->des1 = cpu_to_le32(des + proto_hdr_len);
4035
4036                 /* If needed take extra descriptors to fill the remaining payload */
4037                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4038         } else {
4039                 stmmac_set_desc_addr(priv, first, des);
4040                 tmp_pay_len = pay_len;
4041                 des += proto_hdr_len;
4042                 pay_len = 0;
4043         }
4044
4045         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4046
4047         /* Prepare fragments */
4048         for (i = 0; i < nfrags; i++) {
4049                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4050
4051                 des = skb_frag_dma_map(priv->device, frag, 0,
4052                                        skb_frag_size(frag),
4053                                        DMA_TO_DEVICE);
4054                 if (dma_mapping_error(priv->device, des))
4055                         goto dma_map_err;
4056
4057                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4058                                      (i == nfrags - 1), queue);
4059
4060                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4061                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4062                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4063                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4064         }
4065
4066         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4067
4068         /* Only the last descriptor gets to point to the skb. */
4069         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4070         tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4071
4072         /* Manage tx mitigation */
4073         tx_packets = (tx_q->cur_tx + 1) - first_tx;
4074         tx_q->tx_count_frames += tx_packets;
4075
4076         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4077                 set_ic = true;
4078         else if (!priv->tx_coal_frames[queue])
4079                 set_ic = false;
4080         else if (tx_packets > priv->tx_coal_frames[queue])
4081                 set_ic = true;
4082         else if ((tx_q->tx_count_frames %
4083                   priv->tx_coal_frames[queue]) < tx_packets)
4084                 set_ic = true;
4085         else
4086                 set_ic = false;
4087
4088         if (set_ic) {
4089                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4090                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4091                 else
4092                         desc = &tx_q->dma_tx[tx_q->cur_tx];
4093
4094                 tx_q->tx_count_frames = 0;
4095                 stmmac_set_tx_ic(priv, desc);
4096                 priv->xstats.tx_set_ic_bit++;
4097         }
4098
4099         /* We've used all descriptors we need for this skb, however,
4100          * advance cur_tx so that it references a fresh descriptor.
4101          * ndo_start_xmit will fill this descriptor the next time it's
4102          * called and stmmac_tx_clean may clean up to this descriptor.
4103          */
4104         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
4105
4106         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4107                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4108                           __func__);
4109                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4110         }
4111
4112         dev->stats.tx_bytes += skb->len;
4113         priv->xstats.tx_tso_frames++;
4114         priv->xstats.tx_tso_nfrags += nfrags;
4115
4116         if (priv->sarc_type)
4117                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4118
4119         skb_tx_timestamp(skb);
4120
4121         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4122                      priv->hwts_tx_en)) {
4123                 /* declare that device is doing timestamping */
4124                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4125                 stmmac_enable_tx_timestamp(priv, first);
4126         }
4127
4128         /* Complete the first descriptor before granting the DMA */
4129         stmmac_prepare_tso_tx_desc(priv, first, 1,
4130                         proto_hdr_len,
4131                         pay_len,
4132                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4133                         hdr / 4, (skb->len - proto_hdr_len));
4134
4135         /* If context desc is used to change MSS */
4136         if (mss_desc) {
4137                 /* Make sure that first descriptor has been completely
4138                  * written, including its own bit. This is because MSS is
4139                  * actually before first descriptor, so we need to make
4140                  * sure that MSS's own bit is the last thing written.
4141                  */
4142                 dma_wmb();
4143                 stmmac_set_tx_owner(priv, mss_desc);
4144         }
4145
4146         if (netif_msg_pktdata(priv)) {
4147                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4148                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4149                         tx_q->cur_tx, first, nfrags);
4150                 pr_info(">>> frame to be transmitted: ");
4151                 print_pkt(skb->data, skb_headlen(skb));
4152         }
4153
4154         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4155
4156         stmmac_flush_tx_descriptors(priv, queue);
4157         stmmac_tx_timer_arm(priv, queue);
4158
4159         return NETDEV_TX_OK;
4160
4161 dma_map_err:
4162         dev_err(priv->device, "Tx dma map failed\n");
4163         dev_kfree_skb(skb);
4164         priv->dev->stats.tx_dropped++;
4165         return NETDEV_TX_OK;
4166 }
4167
4168 /**
4169  *  stmmac_xmit - Tx entry point of the driver
4170  *  @skb : the socket buffer
4171  *  @dev : device pointer
4172  *  Description : this is the tx entry point of the driver.
4173  *  It programs the chain or the ring and supports oversized frames
4174  *  and SG feature.
4175  */
4176 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4177 {
4178         unsigned int first_entry, tx_packets, enh_desc;
4179         struct stmmac_priv *priv = netdev_priv(dev);
4180         unsigned int nopaged_len = skb_headlen(skb);
4181         int i, csum_insertion = 0, is_jumbo = 0;
4182         u32 queue = skb_get_queue_mapping(skb);
4183         int nfrags = skb_shinfo(skb)->nr_frags;
4184         int gso = skb_shinfo(skb)->gso_type;
4185         struct dma_edesc *tbs_desc = NULL;
4186         struct dma_desc *desc, *first;
4187         struct stmmac_tx_queue *tx_q;
4188         bool has_vlan, set_ic;
4189         int entry, first_tx;
4190         dma_addr_t des;
4191
4192         tx_q = &priv->tx_queue[queue];
4193         first_tx = tx_q->cur_tx;
4194
4195         if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4196                 stmmac_disable_eee_mode(priv);
4197
4198         /* Manage oversized TCP frames for GMAC4 device */
4199         if (skb_is_gso(skb) && priv->tso) {
4200                 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4201                         return stmmac_tso_xmit(skb, dev);
4202                 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4203                         return stmmac_tso_xmit(skb, dev);
4204         }
4205
4206         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4207                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4208                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4209                                                                 queue));
4210                         /* This is a hard error, log it. */
4211                         netdev_err(priv->dev,
4212                                    "%s: Tx Ring full when queue awake\n",
4213                                    __func__);
4214                 }
4215                 return NETDEV_TX_BUSY;
4216         }
4217
4218         /* Check if VLAN can be inserted by HW */
4219         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4220
4221         entry = tx_q->cur_tx;
4222         first_entry = entry;
4223         WARN_ON(tx_q->tx_skbuff[first_entry]);
4224
4225         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4226
4227         if (likely(priv->extend_desc))
4228                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4229         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4230                 desc = &tx_q->dma_entx[entry].basic;
4231         else
4232                 desc = tx_q->dma_tx + entry;
4233
4234         first = desc;
4235
4236         if (has_vlan)
4237                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4238
4239         enh_desc = priv->plat->enh_desc;
4240         /* To program the descriptors according to the size of the frame */
4241         if (enh_desc)
4242                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4243
4244         if (unlikely(is_jumbo)) {
4245                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4246                 if (unlikely(entry < 0) && (entry != -EINVAL))
4247                         goto dma_map_err;
4248         }
4249
4250         for (i = 0; i < nfrags; i++) {
4251                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4252                 int len = skb_frag_size(frag);
4253                 bool last_segment = (i == (nfrags - 1));
4254
4255                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4256                 WARN_ON(tx_q->tx_skbuff[entry]);
4257
4258                 if (likely(priv->extend_desc))
4259                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4260                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4261                         desc = &tx_q->dma_entx[entry].basic;
4262                 else
4263                         desc = tx_q->dma_tx + entry;
4264
4265                 des = skb_frag_dma_map(priv->device, frag, 0, len,
4266                                        DMA_TO_DEVICE);
4267                 if (dma_mapping_error(priv->device, des))
4268                         goto dma_map_err; /* should reuse desc w/o issues */
4269
4270                 tx_q->tx_skbuff_dma[entry].buf = des;
4271
4272                 stmmac_set_desc_addr(priv, desc, des);
4273
4274                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4275                 tx_q->tx_skbuff_dma[entry].len = len;
4276                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4277                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4278
4279                 /* Prepare the descriptor and set the own bit too */
4280                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4281                                 priv->mode, 1, last_segment, skb->len);
4282         }
4283
4284         /* Only the last descriptor gets to point to the skb. */
4285         tx_q->tx_skbuff[entry] = skb;
4286         tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4287
4288         /* According to the coalesce parameter the IC bit for the latest
4289          * segment is reset and the timer re-started to clean the tx status.
4290          * This approach takes care about the fragments: desc is the first
4291          * element in case of no SG.
4292          */
4293         tx_packets = (entry + 1) - first_tx;
4294         tx_q->tx_count_frames += tx_packets;
4295
4296         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4297                 set_ic = true;
4298         else if (!priv->tx_coal_frames[queue])
4299                 set_ic = false;
4300         else if (tx_packets > priv->tx_coal_frames[queue])
4301                 set_ic = true;
4302         else if ((tx_q->tx_count_frames %
4303                   priv->tx_coal_frames[queue]) < tx_packets)
4304                 set_ic = true;
4305         else
4306                 set_ic = false;
4307
4308         if (set_ic) {
4309                 if (likely(priv->extend_desc))
4310                         desc = &tx_q->dma_etx[entry].basic;
4311                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4312                         desc = &tx_q->dma_entx[entry].basic;
4313                 else
4314                         desc = &tx_q->dma_tx[entry];
4315
4316                 tx_q->tx_count_frames = 0;
4317                 stmmac_set_tx_ic(priv, desc);
4318                 priv->xstats.tx_set_ic_bit++;
4319         }
4320
4321         /* We've used all descriptors we need for this skb, however,
4322          * advance cur_tx so that it references a fresh descriptor.
4323          * ndo_start_xmit will fill this descriptor the next time it's
4324          * called and stmmac_tx_clean may clean up to this descriptor.
4325          */
4326         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4327         tx_q->cur_tx = entry;
4328
4329         if (netif_msg_pktdata(priv)) {
4330                 netdev_dbg(priv->dev,
4331                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4332                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4333                            entry, first, nfrags);
4334
4335                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4336                 print_pkt(skb->data, skb->len);
4337         }
4338
4339         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4340                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4341                           __func__);
4342                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4343         }
4344
4345         dev->stats.tx_bytes += skb->len;
4346
4347         if (priv->sarc_type)
4348                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4349
4350         skb_tx_timestamp(skb);
4351
4352         /* Ready to fill the first descriptor and set the OWN bit w/o any
4353          * problems because all the descriptors are actually ready to be
4354          * passed to the DMA engine.
4355          */
4356         if (likely(!is_jumbo)) {
4357                 bool last_segment = (nfrags == 0);
4358
4359                 des = dma_map_single(priv->device, skb->data,
4360                                      nopaged_len, DMA_TO_DEVICE);
4361                 if (dma_mapping_error(priv->device, des))
4362                         goto dma_map_err;
4363
4364                 tx_q->tx_skbuff_dma[first_entry].buf = des;
4365                 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4366                 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4367
4368                 stmmac_set_desc_addr(priv, first, des);
4369
4370                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4371                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4372
4373                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4374                              priv->hwts_tx_en)) {
4375                         /* declare that device is doing timestamping */
4376                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4377                         stmmac_enable_tx_timestamp(priv, first);
4378                 }
4379
4380                 /* Prepare the first descriptor setting the OWN bit too */
4381                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4382                                 csum_insertion, priv->mode, 0, last_segment,
4383                                 skb->len);
4384         }
4385
4386         if (tx_q->tbs & STMMAC_TBS_EN) {
4387                 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4388
4389                 tbs_desc = &tx_q->dma_entx[first_entry];
4390                 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4391         }
4392
4393         stmmac_set_tx_owner(priv, first);
4394
4395         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4396
4397         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4398
4399         stmmac_flush_tx_descriptors(priv, queue);
4400         stmmac_tx_timer_arm(priv, queue);
4401
4402         return NETDEV_TX_OK;
4403
4404 dma_map_err:
4405         netdev_err(priv->dev, "Tx DMA map failed\n");
4406         dev_kfree_skb(skb);
4407         priv->dev->stats.tx_dropped++;
4408         return NETDEV_TX_OK;
4409 }
4410
4411 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4412 {
4413         struct vlan_ethhdr *veth;
4414         __be16 vlan_proto;
4415         u16 vlanid;
4416
4417         veth = (struct vlan_ethhdr *)skb->data;
4418         vlan_proto = veth->h_vlan_proto;
4419
4420         if ((vlan_proto == htons(ETH_P_8021Q) &&
4421              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4422             (vlan_proto == htons(ETH_P_8021AD) &&
4423              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4424                 /* pop the vlan tag */
4425                 vlanid = ntohs(veth->h_vlan_TCI);
4426                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4427                 skb_pull(skb, VLAN_HLEN);
4428                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4429         }
4430 }
4431
4432 /**
4433  * stmmac_rx_refill - refill used skb preallocated buffers
4434  * @priv: driver private structure
4435  * @queue: RX queue index
4436  * Description : this is to reallocate the skb for the reception process
4437  * that is based on zero-copy.
4438  */
4439 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4440 {
4441         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4442         int dirty = stmmac_rx_dirty(priv, queue);
4443         unsigned int entry = rx_q->dirty_rx;
4444         gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
4445
4446         if (priv->dma_cap.addr64 <= 32)
4447                 gfp |= GFP_DMA32;
4448
4449         while (dirty-- > 0) {
4450                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4451                 struct dma_desc *p;
4452                 bool use_rx_wd;
4453
4454                 if (priv->extend_desc)
4455                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4456                 else
4457                         p = rx_q->dma_rx + entry;
4458
4459                 if (!buf->page) {
4460                         buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4461                         if (!buf->page)
4462                                 break;
4463                 }
4464
4465                 if (priv->sph && !buf->sec_page) {
4466                         buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4467                         if (!buf->sec_page)
4468                                 break;
4469
4470                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4471                 }
4472
4473                 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4474
4475                 stmmac_set_desc_addr(priv, p, buf->addr);
4476                 if (priv->sph)
4477                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4478                 else
4479                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4480                 stmmac_refill_desc3(priv, rx_q, p);
4481
4482                 rx_q->rx_count_frames++;
4483                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4484                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4485                         rx_q->rx_count_frames = 0;
4486
4487                 use_rx_wd = !priv->rx_coal_frames[queue];
4488                 use_rx_wd |= rx_q->rx_count_frames > 0;
4489                 if (!priv->use_riwt)
4490                         use_rx_wd = false;
4491
4492                 dma_wmb();
4493                 stmmac_set_rx_owner(priv, p, use_rx_wd);
4494
4495                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4496         }
4497         rx_q->dirty_rx = entry;
4498         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4499                             (rx_q->dirty_rx * sizeof(struct dma_desc));
4500         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4501 }
4502
4503 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4504                                        struct dma_desc *p,
4505                                        int status, unsigned int len)
4506 {
4507         unsigned int plen = 0, hlen = 0;
4508         int coe = priv->hw->rx_csum;
4509
4510         /* Not first descriptor, buffer is always zero */
4511         if (priv->sph && len)
4512                 return 0;
4513
4514         /* First descriptor, get split header length */
4515         stmmac_get_rx_header_len(priv, p, &hlen);
4516         if (priv->sph && hlen) {
4517                 priv->xstats.rx_split_hdr_pkt_n++;
4518                 return hlen;
4519         }
4520
4521         /* First descriptor, not last descriptor and not split header */
4522         if (status & rx_not_ls)
4523                 return priv->dma_buf_sz;
4524
4525         plen = stmmac_get_rx_frame_len(priv, p, coe);
4526
4527         /* First descriptor and last descriptor and not split header */
4528         return min_t(unsigned int, priv->dma_buf_sz, plen);
4529 }
4530
4531 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4532                                        struct dma_desc *p,
4533                                        int status, unsigned int len)
4534 {
4535         int coe = priv->hw->rx_csum;
4536         unsigned int plen = 0;
4537
4538         /* Not split header, buffer is not available */
4539         if (!priv->sph)
4540                 return 0;
4541
4542         /* Not last descriptor */
4543         if (status & rx_not_ls)
4544                 return priv->dma_buf_sz;
4545
4546         plen = stmmac_get_rx_frame_len(priv, p, coe);
4547
4548         /* Last descriptor */
4549         return plen - len;
4550 }
4551
4552 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4553                                 struct xdp_frame *xdpf, bool dma_map)
4554 {
4555         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4556         unsigned int entry = tx_q->cur_tx;
4557         struct dma_desc *tx_desc;
4558         dma_addr_t dma_addr;
4559         bool set_ic;
4560
4561         if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4562                 return STMMAC_XDP_CONSUMED;
4563
4564         if (likely(priv->extend_desc))
4565                 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4566         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4567                 tx_desc = &tx_q->dma_entx[entry].basic;
4568         else
4569                 tx_desc = tx_q->dma_tx + entry;
4570
4571         if (dma_map) {
4572                 dma_addr = dma_map_single(priv->device, xdpf->data,
4573                                           xdpf->len, DMA_TO_DEVICE);
4574                 if (dma_mapping_error(priv->device, dma_addr))
4575                         return STMMAC_XDP_CONSUMED;
4576
4577                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4578         } else {
4579                 struct page *page = virt_to_page(xdpf->data);
4580
4581                 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4582                            xdpf->headroom;
4583                 dma_sync_single_for_device(priv->device, dma_addr,
4584                                            xdpf->len, DMA_BIDIRECTIONAL);
4585
4586                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4587         }
4588
4589         tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4590         tx_q->tx_skbuff_dma[entry].map_as_page = false;
4591         tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4592         tx_q->tx_skbuff_dma[entry].last_segment = true;
4593         tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4594
4595         tx_q->xdpf[entry] = xdpf;
4596
4597         stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4598
4599         stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4600                                true, priv->mode, true, true,
4601                                xdpf->len);
4602
4603         tx_q->tx_count_frames++;
4604
4605         if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4606                 set_ic = true;
4607         else
4608                 set_ic = false;
4609
4610         if (set_ic) {
4611                 tx_q->tx_count_frames = 0;
4612                 stmmac_set_tx_ic(priv, tx_desc);
4613                 priv->xstats.tx_set_ic_bit++;
4614         }
4615
4616         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4617
4618         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4619         tx_q->cur_tx = entry;
4620
4621         return STMMAC_XDP_TX;
4622 }
4623
4624 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4625                                    int cpu)
4626 {
4627         int index = cpu;
4628
4629         if (unlikely(index < 0))
4630                 index = 0;
4631
4632         while (index >= priv->plat->tx_queues_to_use)
4633                 index -= priv->plat->tx_queues_to_use;
4634
4635         return index;
4636 }
4637
4638 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4639                                 struct xdp_buff *xdp)
4640 {
4641         struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4642         int cpu = smp_processor_id();
4643         struct netdev_queue *nq;
4644         int queue;
4645         int res;
4646
4647         if (unlikely(!xdpf))
4648                 return STMMAC_XDP_CONSUMED;
4649
4650         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4651         nq = netdev_get_tx_queue(priv->dev, queue);
4652
4653         __netif_tx_lock(nq, cpu);
4654         /* Avoids TX time-out as we are sharing with slow path */
4655         txq_trans_cond_update(nq);
4656
4657         res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4658         if (res == STMMAC_XDP_TX)
4659                 stmmac_flush_tx_descriptors(priv, queue);
4660
4661         __netif_tx_unlock(nq);
4662
4663         return res;
4664 }
4665
4666 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4667                                  struct bpf_prog *prog,
4668                                  struct xdp_buff *xdp)
4669 {
4670         u32 act;
4671         int res;
4672
4673         act = bpf_prog_run_xdp(prog, xdp);
4674         switch (act) {
4675         case XDP_PASS:
4676                 res = STMMAC_XDP_PASS;
4677                 break;
4678         case XDP_TX:
4679                 res = stmmac_xdp_xmit_back(priv, xdp);
4680                 break;
4681         case XDP_REDIRECT:
4682                 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4683                         res = STMMAC_XDP_CONSUMED;
4684                 else
4685                         res = STMMAC_XDP_REDIRECT;
4686                 break;
4687         default:
4688                 bpf_warn_invalid_xdp_action(priv->dev, prog, act);
4689                 fallthrough;
4690         case XDP_ABORTED:
4691                 trace_xdp_exception(priv->dev, prog, act);
4692                 fallthrough;
4693         case XDP_DROP:
4694                 res = STMMAC_XDP_CONSUMED;
4695                 break;
4696         }
4697
4698         return res;
4699 }
4700
4701 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4702                                            struct xdp_buff *xdp)
4703 {
4704         struct bpf_prog *prog;
4705         int res;
4706
4707         prog = READ_ONCE(priv->xdp_prog);
4708         if (!prog) {
4709                 res = STMMAC_XDP_PASS;
4710                 goto out;
4711         }
4712
4713         res = __stmmac_xdp_run_prog(priv, prog, xdp);
4714 out:
4715         return ERR_PTR(-res);
4716 }
4717
4718 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4719                                    int xdp_status)
4720 {
4721         int cpu = smp_processor_id();
4722         int queue;
4723
4724         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4725
4726         if (xdp_status & STMMAC_XDP_TX)
4727                 stmmac_tx_timer_arm(priv, queue);
4728
4729         if (xdp_status & STMMAC_XDP_REDIRECT)
4730                 xdp_do_flush();
4731 }
4732
4733 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4734                                                struct xdp_buff *xdp)
4735 {
4736         unsigned int metasize = xdp->data - xdp->data_meta;
4737         unsigned int datasize = xdp->data_end - xdp->data;
4738         struct sk_buff *skb;
4739
4740         skb = __napi_alloc_skb(&ch->rxtx_napi,
4741                                xdp->data_end - xdp->data_hard_start,
4742                                GFP_ATOMIC | __GFP_NOWARN);
4743         if (unlikely(!skb))
4744                 return NULL;
4745
4746         skb_reserve(skb, xdp->data - xdp->data_hard_start);
4747         memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4748         if (metasize)
4749                 skb_metadata_set(skb, metasize);
4750
4751         return skb;
4752 }
4753
4754 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4755                                    struct dma_desc *p, struct dma_desc *np,
4756                                    struct xdp_buff *xdp)
4757 {
4758         struct stmmac_channel *ch = &priv->channel[queue];
4759         unsigned int len = xdp->data_end - xdp->data;
4760         enum pkt_hash_types hash_type;
4761         int coe = priv->hw->rx_csum;
4762         struct sk_buff *skb;
4763         u32 hash;
4764
4765         skb = stmmac_construct_skb_zc(ch, xdp);
4766         if (!skb) {
4767                 priv->dev->stats.rx_dropped++;
4768                 return;
4769         }
4770
4771         stmmac_get_rx_hwtstamp(priv, p, np, skb);
4772         stmmac_rx_vlan(priv->dev, skb);
4773         skb->protocol = eth_type_trans(skb, priv->dev);
4774
4775         if (unlikely(!coe))
4776                 skb_checksum_none_assert(skb);
4777         else
4778                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4779
4780         if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4781                 skb_set_hash(skb, hash, hash_type);
4782
4783         skb_record_rx_queue(skb, queue);
4784         napi_gro_receive(&ch->rxtx_napi, skb);
4785
4786         priv->dev->stats.rx_packets++;
4787         priv->dev->stats.rx_bytes += len;
4788 }
4789
4790 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4791 {
4792         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4793         unsigned int entry = rx_q->dirty_rx;
4794         struct dma_desc *rx_desc = NULL;
4795         bool ret = true;
4796
4797         budget = min(budget, stmmac_rx_dirty(priv, queue));
4798
4799         while (budget-- > 0 && entry != rx_q->cur_rx) {
4800                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4801                 dma_addr_t dma_addr;
4802                 bool use_rx_wd;
4803
4804                 if (!buf->xdp) {
4805                         buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4806                         if (!buf->xdp) {
4807                                 ret = false;
4808                                 break;
4809                         }
4810                 }
4811
4812                 if (priv->extend_desc)
4813                         rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4814                 else
4815                         rx_desc = rx_q->dma_rx + entry;
4816
4817                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4818                 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4819                 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4820                 stmmac_refill_desc3(priv, rx_q, rx_desc);
4821
4822                 rx_q->rx_count_frames++;
4823                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4824                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4825                         rx_q->rx_count_frames = 0;
4826
4827                 use_rx_wd = !priv->rx_coal_frames[queue];
4828                 use_rx_wd |= rx_q->rx_count_frames > 0;
4829                 if (!priv->use_riwt)
4830                         use_rx_wd = false;
4831
4832                 dma_wmb();
4833                 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4834
4835                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4836         }
4837
4838         if (rx_desc) {
4839                 rx_q->dirty_rx = entry;
4840                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4841                                      (rx_q->dirty_rx * sizeof(struct dma_desc));
4842                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4843         }
4844
4845         return ret;
4846 }
4847
4848 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
4849 {
4850         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4851         unsigned int count = 0, error = 0, len = 0;
4852         int dirty = stmmac_rx_dirty(priv, queue);
4853         unsigned int next_entry = rx_q->cur_rx;
4854         unsigned int desc_size;
4855         struct bpf_prog *prog;
4856         bool failure = false;
4857         int xdp_status = 0;
4858         int status = 0;
4859
4860         if (netif_msg_rx_status(priv)) {
4861                 void *rx_head;
4862
4863                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
4864                 if (priv->extend_desc) {
4865                         rx_head = (void *)rx_q->dma_erx;
4866                         desc_size = sizeof(struct dma_extended_desc);
4867                 } else {
4868                         rx_head = (void *)rx_q->dma_rx;
4869                         desc_size = sizeof(struct dma_desc);
4870                 }
4871
4872                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
4873                                     rx_q->dma_rx_phy, desc_size);
4874         }
4875         while (count < limit) {
4876                 struct stmmac_rx_buffer *buf;
4877                 unsigned int buf1_len = 0;
4878                 struct dma_desc *np, *p;
4879                 int entry;
4880                 int res;
4881
4882                 if (!count && rx_q->state_saved) {
4883                         error = rx_q->state.error;
4884                         len = rx_q->state.len;
4885                 } else {
4886                         rx_q->state_saved = false;
4887                         error = 0;
4888                         len = 0;
4889                 }
4890
4891                 if (count >= limit)
4892                         break;
4893
4894 read_again:
4895                 buf1_len = 0;
4896                 entry = next_entry;
4897                 buf = &rx_q->buf_pool[entry];
4898
4899                 if (dirty >= STMMAC_RX_FILL_BATCH) {
4900                         failure = failure ||
4901                                   !stmmac_rx_refill_zc(priv, queue, dirty);
4902                         dirty = 0;
4903                 }
4904
4905                 if (priv->extend_desc)
4906                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4907                 else
4908                         p = rx_q->dma_rx + entry;
4909
4910                 /* read the status of the incoming frame */
4911                 status = stmmac_rx_status(priv, &priv->dev->stats,
4912                                           &priv->xstats, p);
4913                 /* check if managed by the DMA otherwise go ahead */
4914                 if (unlikely(status & dma_own))
4915                         break;
4916
4917                 /* Prefetch the next RX descriptor */
4918                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
4919                                                 priv->dma_rx_size);
4920                 next_entry = rx_q->cur_rx;
4921
4922                 if (priv->extend_desc)
4923                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
4924                 else
4925                         np = rx_q->dma_rx + next_entry;
4926
4927                 prefetch(np);
4928
4929                 /* Ensure a valid XSK buffer before proceed */
4930                 if (!buf->xdp)
4931                         break;
4932
4933                 if (priv->extend_desc)
4934                         stmmac_rx_extended_status(priv, &priv->dev->stats,
4935                                                   &priv->xstats,
4936                                                   rx_q->dma_erx + entry);
4937                 if (unlikely(status == discard_frame)) {
4938                         xsk_buff_free(buf->xdp);
4939                         buf->xdp = NULL;
4940                         dirty++;
4941                         error = 1;
4942                         if (!priv->hwts_rx_en)
4943                                 priv->dev->stats.rx_errors++;
4944                 }
4945
4946                 if (unlikely(error && (status & rx_not_ls)))
4947                         goto read_again;
4948                 if (unlikely(error)) {
4949                         count++;
4950                         continue;
4951                 }
4952
4953                 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
4954                 if (likely(status & rx_not_ls)) {
4955                         xsk_buff_free(buf->xdp);
4956                         buf->xdp = NULL;
4957                         dirty++;
4958                         count++;
4959                         goto read_again;
4960                 }
4961
4962                 /* XDP ZC Frame only support primary buffers for now */
4963                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
4964                 len += buf1_len;
4965
4966                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
4967                  * Type frames (LLC/LLC-SNAP)
4968                  *
4969                  * llc_snap is never checked in GMAC >= 4, so this ACS
4970                  * feature is always disabled and packets need to be
4971                  * stripped manually.
4972                  */
4973                 if (likely(!(status & rx_not_ls)) &&
4974                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
4975                      unlikely(status != llc_snap))) {
4976                         buf1_len -= ETH_FCS_LEN;
4977                         len -= ETH_FCS_LEN;
4978                 }
4979
4980                 /* RX buffer is good and fit into a XSK pool buffer */
4981                 buf->xdp->data_end = buf->xdp->data + buf1_len;
4982                 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
4983
4984                 prog = READ_ONCE(priv->xdp_prog);
4985                 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
4986
4987                 switch (res) {
4988                 case STMMAC_XDP_PASS:
4989                         stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
4990                         xsk_buff_free(buf->xdp);
4991                         break;
4992                 case STMMAC_XDP_CONSUMED:
4993                         xsk_buff_free(buf->xdp);
4994                         priv->dev->stats.rx_dropped++;
4995                         break;
4996                 case STMMAC_XDP_TX:
4997                 case STMMAC_XDP_REDIRECT:
4998                         xdp_status |= res;
4999                         break;
5000                 }
5001
5002                 buf->xdp = NULL;
5003                 dirty++;
5004                 count++;
5005         }
5006
5007         if (status & rx_not_ls) {
5008                 rx_q->state_saved = true;
5009                 rx_q->state.error = error;
5010                 rx_q->state.len = len;
5011         }
5012
5013         stmmac_finalize_xdp_rx(priv, xdp_status);
5014
5015         priv->xstats.rx_pkt_n += count;
5016         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5017
5018         if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5019                 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5020                         xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5021                 else
5022                         xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5023
5024                 return (int)count;
5025         }
5026
5027         return failure ? limit : (int)count;
5028 }
5029
5030 /**
5031  * stmmac_rx - manage the receive process
5032  * @priv: driver private structure
5033  * @limit: napi bugget
5034  * @queue: RX queue index.
5035  * Description :  this the function called by the napi poll method.
5036  * It gets all the frames inside the ring.
5037  */
5038 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5039 {
5040         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5041         struct stmmac_channel *ch = &priv->channel[queue];
5042         unsigned int count = 0, error = 0, len = 0;
5043         int status = 0, coe = priv->hw->rx_csum;
5044         unsigned int next_entry = rx_q->cur_rx;
5045         enum dma_data_direction dma_dir;
5046         unsigned int desc_size;
5047         struct sk_buff *skb = NULL;
5048         struct xdp_buff xdp;
5049         int xdp_status = 0;
5050         int buf_sz;
5051
5052         dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5053         buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5054
5055         if (netif_msg_rx_status(priv)) {
5056                 void *rx_head;
5057
5058                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5059                 if (priv->extend_desc) {
5060                         rx_head = (void *)rx_q->dma_erx;
5061                         desc_size = sizeof(struct dma_extended_desc);
5062                 } else {
5063                         rx_head = (void *)rx_q->dma_rx;
5064                         desc_size = sizeof(struct dma_desc);
5065                 }
5066
5067                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
5068                                     rx_q->dma_rx_phy, desc_size);
5069         }
5070         while (count < limit) {
5071                 unsigned int buf1_len = 0, buf2_len = 0;
5072                 enum pkt_hash_types hash_type;
5073                 struct stmmac_rx_buffer *buf;
5074                 struct dma_desc *np, *p;
5075                 int entry;
5076                 u32 hash;
5077
5078                 if (!count && rx_q->state_saved) {
5079                         skb = rx_q->state.skb;
5080                         error = rx_q->state.error;
5081                         len = rx_q->state.len;
5082                 } else {
5083                         rx_q->state_saved = false;
5084                         skb = NULL;
5085                         error = 0;
5086                         len = 0;
5087                 }
5088
5089                 if (count >= limit)
5090                         break;
5091
5092 read_again:
5093                 buf1_len = 0;
5094                 buf2_len = 0;
5095                 entry = next_entry;
5096                 buf = &rx_q->buf_pool[entry];
5097
5098                 if (priv->extend_desc)
5099                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
5100                 else
5101                         p = rx_q->dma_rx + entry;
5102
5103                 /* read the status of the incoming frame */
5104                 status = stmmac_rx_status(priv, &priv->dev->stats,
5105                                 &priv->xstats, p);
5106                 /* check if managed by the DMA otherwise go ahead */
5107                 if (unlikely(status & dma_own))
5108                         break;
5109
5110                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5111                                                 priv->dma_rx_size);
5112                 next_entry = rx_q->cur_rx;
5113
5114                 if (priv->extend_desc)
5115                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5116                 else
5117                         np = rx_q->dma_rx + next_entry;
5118
5119                 prefetch(np);
5120
5121                 if (priv->extend_desc)
5122                         stmmac_rx_extended_status(priv, &priv->dev->stats,
5123                                         &priv->xstats, rx_q->dma_erx + entry);
5124                 if (unlikely(status == discard_frame)) {
5125                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5126                         buf->page = NULL;
5127                         error = 1;
5128                         if (!priv->hwts_rx_en)
5129                                 priv->dev->stats.rx_errors++;
5130                 }
5131
5132                 if (unlikely(error && (status & rx_not_ls)))
5133                         goto read_again;
5134                 if (unlikely(error)) {
5135                         dev_kfree_skb(skb);
5136                         skb = NULL;
5137                         count++;
5138                         continue;
5139                 }
5140
5141                 /* Buffer is good. Go on. */
5142
5143                 prefetch(page_address(buf->page) + buf->page_offset);
5144                 if (buf->sec_page)
5145                         prefetch(page_address(buf->sec_page));
5146
5147                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5148                 len += buf1_len;
5149                 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5150                 len += buf2_len;
5151
5152                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5153                  * Type frames (LLC/LLC-SNAP)
5154                  *
5155                  * llc_snap is never checked in GMAC >= 4, so this ACS
5156                  * feature is always disabled and packets need to be
5157                  * stripped manually.
5158                  */
5159                 if (likely(!(status & rx_not_ls)) &&
5160                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5161                      unlikely(status != llc_snap))) {
5162                         if (buf2_len) {
5163                                 buf2_len -= ETH_FCS_LEN;
5164                                 len -= ETH_FCS_LEN;
5165                         } else if (buf1_len) {
5166                                 buf1_len -= ETH_FCS_LEN;
5167                                 len -= ETH_FCS_LEN;
5168                         }
5169                 }
5170
5171                 if (!skb) {
5172                         unsigned int pre_len, sync_len;
5173
5174                         dma_sync_single_for_cpu(priv->device, buf->addr,
5175                                                 buf1_len, dma_dir);
5176
5177                         xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq);
5178                         xdp_prepare_buff(&xdp, page_address(buf->page),
5179                                          buf->page_offset, buf1_len, false);
5180
5181                         pre_len = xdp.data_end - xdp.data_hard_start -
5182                                   buf->page_offset;
5183                         skb = stmmac_xdp_run_prog(priv, &xdp);
5184                         /* Due xdp_adjust_tail: DMA sync for_device
5185                          * cover max len CPU touch
5186                          */
5187                         sync_len = xdp.data_end - xdp.data_hard_start -
5188                                    buf->page_offset;
5189                         sync_len = max(sync_len, pre_len);
5190
5191                         /* For Not XDP_PASS verdict */
5192                         if (IS_ERR(skb)) {
5193                                 unsigned int xdp_res = -PTR_ERR(skb);
5194
5195                                 if (xdp_res & STMMAC_XDP_CONSUMED) {
5196                                         page_pool_put_page(rx_q->page_pool,
5197                                                            virt_to_head_page(xdp.data),
5198                                                            sync_len, true);
5199                                         buf->page = NULL;
5200                                         priv->dev->stats.rx_dropped++;
5201
5202                                         /* Clear skb as it was set as
5203                                          * status by XDP program.
5204                                          */
5205                                         skb = NULL;
5206
5207                                         if (unlikely((status & rx_not_ls)))
5208                                                 goto read_again;
5209
5210                                         count++;
5211                                         continue;
5212                                 } else if (xdp_res & (STMMAC_XDP_TX |
5213                                                       STMMAC_XDP_REDIRECT)) {
5214                                         xdp_status |= xdp_res;
5215                                         buf->page = NULL;
5216                                         skb = NULL;
5217                                         count++;
5218                                         continue;
5219                                 }
5220                         }
5221                 }
5222
5223                 if (!skb) {
5224                         /* XDP program may expand or reduce tail */
5225                         buf1_len = xdp.data_end - xdp.data;
5226
5227                         skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5228                         if (!skb) {
5229                                 priv->dev->stats.rx_dropped++;
5230                                 count++;
5231                                 goto drain_data;
5232                         }
5233
5234                         /* XDP program may adjust header */
5235                         skb_copy_to_linear_data(skb, xdp.data, buf1_len);
5236                         skb_put(skb, buf1_len);
5237
5238                         /* Data payload copied into SKB, page ready for recycle */
5239                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5240                         buf->page = NULL;
5241                 } else if (buf1_len) {
5242                         dma_sync_single_for_cpu(priv->device, buf->addr,
5243                                                 buf1_len, dma_dir);
5244                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5245                                         buf->page, buf->page_offset, buf1_len,
5246                                         priv->dma_buf_sz);
5247
5248                         /* Data payload appended into SKB */
5249                         page_pool_release_page(rx_q->page_pool, buf->page);
5250                         buf->page = NULL;
5251                 }
5252
5253                 if (buf2_len) {
5254                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5255                                                 buf2_len, dma_dir);
5256                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5257                                         buf->sec_page, 0, buf2_len,
5258                                         priv->dma_buf_sz);
5259
5260                         /* Data payload appended into SKB */
5261                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
5262                         buf->sec_page = NULL;
5263                 }
5264
5265 drain_data:
5266                 if (likely(status & rx_not_ls))
5267                         goto read_again;
5268                 if (!skb)
5269                         continue;
5270
5271                 /* Got entire packet into SKB. Finish it. */
5272
5273                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5274                 stmmac_rx_vlan(priv->dev, skb);
5275                 skb->protocol = eth_type_trans(skb, priv->dev);
5276
5277                 if (unlikely(!coe))
5278                         skb_checksum_none_assert(skb);
5279                 else
5280                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5281
5282                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5283                         skb_set_hash(skb, hash, hash_type);
5284
5285                 skb_record_rx_queue(skb, queue);
5286                 napi_gro_receive(&ch->rx_napi, skb);
5287                 skb = NULL;
5288
5289                 priv->dev->stats.rx_packets++;
5290                 priv->dev->stats.rx_bytes += len;
5291                 count++;
5292         }
5293
5294         if (status & rx_not_ls || skb) {
5295                 rx_q->state_saved = true;
5296                 rx_q->state.skb = skb;
5297                 rx_q->state.error = error;
5298                 rx_q->state.len = len;
5299         }
5300
5301         stmmac_finalize_xdp_rx(priv, xdp_status);
5302
5303         stmmac_rx_refill(priv, queue);
5304
5305         priv->xstats.rx_pkt_n += count;
5306         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5307
5308         return count;
5309 }
5310
5311 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5312 {
5313         struct stmmac_channel *ch =
5314                 container_of(napi, struct stmmac_channel, rx_napi);
5315         struct stmmac_priv *priv = ch->priv_data;
5316         u32 chan = ch->index;
5317         int work_done;
5318
5319         priv->xstats.napi_poll++;
5320
5321         work_done = stmmac_rx(priv, budget, chan);
5322         if (work_done < budget && napi_complete_done(napi, work_done)) {
5323                 unsigned long flags;
5324
5325                 spin_lock_irqsave(&ch->lock, flags);
5326                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5327                 spin_unlock_irqrestore(&ch->lock, flags);
5328         }
5329
5330         return work_done;
5331 }
5332
5333 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5334 {
5335         struct stmmac_channel *ch =
5336                 container_of(napi, struct stmmac_channel, tx_napi);
5337         struct stmmac_priv *priv = ch->priv_data;
5338         u32 chan = ch->index;
5339         int work_done;
5340
5341         priv->xstats.napi_poll++;
5342
5343         work_done = stmmac_tx_clean(priv, budget, chan);
5344         work_done = min(work_done, budget);
5345
5346         if (work_done < budget && napi_complete_done(napi, work_done)) {
5347                 unsigned long flags;
5348
5349                 spin_lock_irqsave(&ch->lock, flags);
5350                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5351                 spin_unlock_irqrestore(&ch->lock, flags);
5352         }
5353
5354         return work_done;
5355 }
5356
5357 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5358 {
5359         struct stmmac_channel *ch =
5360                 container_of(napi, struct stmmac_channel, rxtx_napi);
5361         struct stmmac_priv *priv = ch->priv_data;
5362         int rx_done, tx_done, rxtx_done;
5363         u32 chan = ch->index;
5364
5365         priv->xstats.napi_poll++;
5366
5367         tx_done = stmmac_tx_clean(priv, budget, chan);
5368         tx_done = min(tx_done, budget);
5369
5370         rx_done = stmmac_rx_zc(priv, budget, chan);
5371
5372         rxtx_done = max(tx_done, rx_done);
5373
5374         /* If either TX or RX work is not complete, return budget
5375          * and keep pooling
5376          */
5377         if (rxtx_done >= budget)
5378                 return budget;
5379
5380         /* all work done, exit the polling mode */
5381         if (napi_complete_done(napi, rxtx_done)) {
5382                 unsigned long flags;
5383
5384                 spin_lock_irqsave(&ch->lock, flags);
5385                 /* Both RX and TX work done are compelte,
5386                  * so enable both RX & TX IRQs.
5387                  */
5388                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5389                 spin_unlock_irqrestore(&ch->lock, flags);
5390         }
5391
5392         return min(rxtx_done, budget - 1);
5393 }
5394
5395 /**
5396  *  stmmac_tx_timeout
5397  *  @dev : Pointer to net device structure
5398  *  @txqueue: the index of the hanging transmit queue
5399  *  Description: this function is called when a packet transmission fails to
5400  *   complete within a reasonable time. The driver will mark the error in the
5401  *   netdev structure and arrange for the device to be reset to a sane state
5402  *   in order to transmit a new packet.
5403  */
5404 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5405 {
5406         struct stmmac_priv *priv = netdev_priv(dev);
5407
5408         stmmac_global_err(priv);
5409 }
5410
5411 /**
5412  *  stmmac_set_rx_mode - entry point for multicast addressing
5413  *  @dev : pointer to the device structure
5414  *  Description:
5415  *  This function is a driver entry point which gets called by the kernel
5416  *  whenever multicast addresses must be enabled/disabled.
5417  *  Return value:
5418  *  void.
5419  */
5420 static void stmmac_set_rx_mode(struct net_device *dev)
5421 {
5422         struct stmmac_priv *priv = netdev_priv(dev);
5423
5424         stmmac_set_filter(priv, priv->hw, dev);
5425 }
5426
5427 /**
5428  *  stmmac_change_mtu - entry point to change MTU size for the device.
5429  *  @dev : device pointer.
5430  *  @new_mtu : the new MTU size for the device.
5431  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
5432  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
5433  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
5434  *  Return value:
5435  *  0 on success and an appropriate (-)ve integer as defined in errno.h
5436  *  file on failure.
5437  */
5438 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5439 {
5440         struct stmmac_priv *priv = netdev_priv(dev);
5441         int txfifosz = priv->plat->tx_fifo_size;
5442         const int mtu = new_mtu;
5443
5444         if (txfifosz == 0)
5445                 txfifosz = priv->dma_cap.tx_fifo_size;
5446
5447         txfifosz /= priv->plat->tx_queues_to_use;
5448
5449         if (netif_running(dev)) {
5450                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
5451                 return -EBUSY;
5452         }
5453
5454         if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5455                 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5456                 return -EINVAL;
5457         }
5458
5459         new_mtu = STMMAC_ALIGN(new_mtu);
5460
5461         /* If condition true, FIFO is too small or MTU too large */
5462         if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5463                 return -EINVAL;
5464
5465         dev->mtu = mtu;
5466
5467         netdev_update_features(dev);
5468
5469         return 0;
5470 }
5471
5472 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5473                                              netdev_features_t features)
5474 {
5475         struct stmmac_priv *priv = netdev_priv(dev);
5476
5477         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5478                 features &= ~NETIF_F_RXCSUM;
5479
5480         if (!priv->plat->tx_coe)
5481                 features &= ~NETIF_F_CSUM_MASK;
5482
5483         /* Some GMAC devices have a bugged Jumbo frame support that
5484          * needs to have the Tx COE disabled for oversized frames
5485          * (due to limited buffer sizes). In this case we disable
5486          * the TX csum insertion in the TDES and not use SF.
5487          */
5488         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5489                 features &= ~NETIF_F_CSUM_MASK;
5490
5491         /* Disable tso if asked by ethtool */
5492         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
5493                 if (features & NETIF_F_TSO)
5494                         priv->tso = true;
5495                 else
5496                         priv->tso = false;
5497         }
5498
5499         return features;
5500 }
5501
5502 static int stmmac_set_features(struct net_device *netdev,
5503                                netdev_features_t features)
5504 {
5505         struct stmmac_priv *priv = netdev_priv(netdev);
5506
5507         /* Keep the COE Type in case of csum is supporting */
5508         if (features & NETIF_F_RXCSUM)
5509                 priv->hw->rx_csum = priv->plat->rx_coe;
5510         else
5511                 priv->hw->rx_csum = 0;
5512         /* No check needed because rx_coe has been set before and it will be
5513          * fixed in case of issue.
5514          */
5515         stmmac_rx_ipc(priv, priv->hw);
5516
5517         if (priv->sph_cap) {
5518                 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5519                 u32 chan;
5520
5521                 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5522                         stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5523         }
5524
5525         return 0;
5526 }
5527
5528 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5529 {
5530         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5531         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5532         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5533         bool *hs_enable = &fpe_cfg->hs_enable;
5534
5535         if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5536                 return;
5537
5538         /* If LP has sent verify mPacket, LP is FPE capable */
5539         if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5540                 if (*lp_state < FPE_STATE_CAPABLE)
5541                         *lp_state = FPE_STATE_CAPABLE;
5542
5543                 /* If user has requested FPE enable, quickly response */
5544                 if (*hs_enable)
5545                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5546                                                 MPACKET_RESPONSE);
5547         }
5548
5549         /* If Local has sent verify mPacket, Local is FPE capable */
5550         if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5551                 if (*lo_state < FPE_STATE_CAPABLE)
5552                         *lo_state = FPE_STATE_CAPABLE;
5553         }
5554
5555         /* If LP has sent response mPacket, LP is entering FPE ON */
5556         if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5557                 *lp_state = FPE_STATE_ENTERING_ON;
5558
5559         /* If Local has sent response mPacket, Local is entering FPE ON */
5560         if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5561                 *lo_state = FPE_STATE_ENTERING_ON;
5562
5563         if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5564             !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5565             priv->fpe_wq) {
5566                 queue_work(priv->fpe_wq, &priv->fpe_task);
5567         }
5568 }
5569
5570 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5571 {
5572         u32 rx_cnt = priv->plat->rx_queues_to_use;
5573         u32 tx_cnt = priv->plat->tx_queues_to_use;
5574         u32 queues_count;
5575         u32 queue;
5576         bool xmac;
5577
5578         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5579         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5580
5581         if (priv->irq_wake)
5582                 pm_wakeup_event(priv->device, 0);
5583
5584         if (priv->dma_cap.estsel)
5585                 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5586                                       &priv->xstats, tx_cnt);
5587
5588         if (priv->dma_cap.fpesel) {
5589                 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5590                                                    priv->dev);
5591
5592                 stmmac_fpe_event_status(priv, status);
5593         }
5594
5595         /* To handle GMAC own interrupts */
5596         if ((priv->plat->has_gmac) || xmac) {
5597                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5598
5599                 if (unlikely(status)) {
5600                         /* For LPI we need to save the tx status */
5601                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5602                                 priv->tx_path_in_lpi_mode = true;
5603                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5604                                 priv->tx_path_in_lpi_mode = false;
5605                 }
5606
5607                 for (queue = 0; queue < queues_count; queue++) {
5608                         status = stmmac_host_mtl_irq_status(priv, priv->hw,
5609                                                             queue);
5610                 }
5611
5612                 /* PCS link status */
5613                 if (priv->hw->pcs) {
5614                         if (priv->xstats.pcs_link)
5615                                 netif_carrier_on(priv->dev);
5616                         else
5617                                 netif_carrier_off(priv->dev);
5618                 }
5619
5620                 stmmac_timestamp_interrupt(priv, priv);
5621         }
5622 }
5623
5624 /**
5625  *  stmmac_interrupt - main ISR
5626  *  @irq: interrupt number.
5627  *  @dev_id: to pass the net device pointer.
5628  *  Description: this is the main driver interrupt service routine.
5629  *  It can call:
5630  *  o DMA service routine (to manage incoming frame reception and transmission
5631  *    status)
5632  *  o Core interrupts to manage: remote wake-up, management counter, LPI
5633  *    interrupts.
5634  */
5635 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5636 {
5637         struct net_device *dev = (struct net_device *)dev_id;
5638         struct stmmac_priv *priv = netdev_priv(dev);
5639
5640         /* Check if adapter is up */
5641         if (test_bit(STMMAC_DOWN, &priv->state))
5642                 return IRQ_HANDLED;
5643
5644         /* Check if a fatal error happened */
5645         if (stmmac_safety_feat_interrupt(priv))
5646                 return IRQ_HANDLED;
5647
5648         /* To handle Common interrupts */
5649         stmmac_common_interrupt(priv);
5650
5651         /* To handle DMA interrupts */
5652         stmmac_dma_interrupt(priv);
5653
5654         return IRQ_HANDLED;
5655 }
5656
5657 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5658 {
5659         struct net_device *dev = (struct net_device *)dev_id;
5660         struct stmmac_priv *priv = netdev_priv(dev);
5661
5662         if (unlikely(!dev)) {
5663                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5664                 return IRQ_NONE;
5665         }
5666
5667         /* Check if adapter is up */
5668         if (test_bit(STMMAC_DOWN, &priv->state))
5669                 return IRQ_HANDLED;
5670
5671         /* To handle Common interrupts */
5672         stmmac_common_interrupt(priv);
5673
5674         return IRQ_HANDLED;
5675 }
5676
5677 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5678 {
5679         struct net_device *dev = (struct net_device *)dev_id;
5680         struct stmmac_priv *priv = netdev_priv(dev);
5681
5682         if (unlikely(!dev)) {
5683                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5684                 return IRQ_NONE;
5685         }
5686
5687         /* Check if adapter is up */
5688         if (test_bit(STMMAC_DOWN, &priv->state))
5689                 return IRQ_HANDLED;
5690
5691         /* Check if a fatal error happened */
5692         stmmac_safety_feat_interrupt(priv);
5693
5694         return IRQ_HANDLED;
5695 }
5696
5697 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5698 {
5699         struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5700         int chan = tx_q->queue_index;
5701         struct stmmac_priv *priv;
5702         int status;
5703
5704         priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]);
5705
5706         if (unlikely(!data)) {
5707                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5708                 return IRQ_NONE;
5709         }
5710
5711         /* Check if adapter is up */
5712         if (test_bit(STMMAC_DOWN, &priv->state))
5713                 return IRQ_HANDLED;
5714
5715         status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5716
5717         if (unlikely(status & tx_hard_error_bump_tc)) {
5718                 /* Try to bump up the dma threshold on this failure */
5719                 stmmac_bump_dma_threshold(priv, chan);
5720         } else if (unlikely(status == tx_hard_error)) {
5721                 stmmac_tx_err(priv, chan);
5722         }
5723
5724         return IRQ_HANDLED;
5725 }
5726
5727 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5728 {
5729         struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5730         int chan = rx_q->queue_index;
5731         struct stmmac_priv *priv;
5732
5733         priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]);
5734
5735         if (unlikely(!data)) {
5736                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5737                 return IRQ_NONE;
5738         }
5739
5740         /* Check if adapter is up */
5741         if (test_bit(STMMAC_DOWN, &priv->state))
5742                 return IRQ_HANDLED;
5743
5744         stmmac_napi_check(priv, chan, DMA_DIR_RX);
5745
5746         return IRQ_HANDLED;
5747 }
5748
5749 #ifdef CONFIG_NET_POLL_CONTROLLER
5750 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5751  * to allow network I/O with interrupts disabled.
5752  */
5753 static void stmmac_poll_controller(struct net_device *dev)
5754 {
5755         struct stmmac_priv *priv = netdev_priv(dev);
5756         int i;
5757
5758         /* If adapter is down, do nothing */
5759         if (test_bit(STMMAC_DOWN, &priv->state))
5760                 return;
5761
5762         if (priv->plat->multi_msi_en) {
5763                 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5764                         stmmac_msi_intr_rx(0, &priv->rx_queue[i]);
5765
5766                 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5767                         stmmac_msi_intr_tx(0, &priv->tx_queue[i]);
5768         } else {
5769                 disable_irq(dev->irq);
5770                 stmmac_interrupt(dev->irq, dev);
5771                 enable_irq(dev->irq);
5772         }
5773 }
5774 #endif
5775
5776 /**
5777  *  stmmac_ioctl - Entry point for the Ioctl
5778  *  @dev: Device pointer.
5779  *  @rq: An IOCTL specefic structure, that can contain a pointer to
5780  *  a proprietary structure used to pass information to the driver.
5781  *  @cmd: IOCTL command
5782  *  Description:
5783  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5784  */
5785 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5786 {
5787         struct stmmac_priv *priv = netdev_priv (dev);
5788         int ret = -EOPNOTSUPP;
5789
5790         if (!netif_running(dev))
5791                 return -EINVAL;
5792
5793         switch (cmd) {
5794         case SIOCGMIIPHY:
5795         case SIOCGMIIREG:
5796         case SIOCSMIIREG:
5797                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5798                 break;
5799         case SIOCSHWTSTAMP:
5800                 ret = stmmac_hwtstamp_set(dev, rq);
5801                 break;
5802         case SIOCGHWTSTAMP:
5803                 ret = stmmac_hwtstamp_get(dev, rq);
5804                 break;
5805         default:
5806                 break;
5807         }
5808
5809         return ret;
5810 }
5811
5812 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5813                                     void *cb_priv)
5814 {
5815         struct stmmac_priv *priv = cb_priv;
5816         int ret = -EOPNOTSUPP;
5817
5818         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
5819                 return ret;
5820
5821         __stmmac_disable_all_queues(priv);
5822
5823         switch (type) {
5824         case TC_SETUP_CLSU32:
5825                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
5826                 break;
5827         case TC_SETUP_CLSFLOWER:
5828                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
5829                 break;
5830         default:
5831                 break;
5832         }
5833
5834         stmmac_enable_all_queues(priv);
5835         return ret;
5836 }
5837
5838 static LIST_HEAD(stmmac_block_cb_list);
5839
5840 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
5841                            void *type_data)
5842 {
5843         struct stmmac_priv *priv = netdev_priv(ndev);
5844
5845         switch (type) {
5846         case TC_SETUP_BLOCK:
5847                 return flow_block_cb_setup_simple(type_data,
5848                                                   &stmmac_block_cb_list,
5849                                                   stmmac_setup_tc_block_cb,
5850                                                   priv, priv, true);
5851         case TC_SETUP_QDISC_CBS:
5852                 return stmmac_tc_setup_cbs(priv, priv, type_data);
5853         case TC_SETUP_QDISC_TAPRIO:
5854                 return stmmac_tc_setup_taprio(priv, priv, type_data);
5855         case TC_SETUP_QDISC_ETF:
5856                 return stmmac_tc_setup_etf(priv, priv, type_data);
5857         default:
5858                 return -EOPNOTSUPP;
5859         }
5860 }
5861
5862 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
5863                                struct net_device *sb_dev)
5864 {
5865         int gso = skb_shinfo(skb)->gso_type;
5866
5867         if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
5868                 /*
5869                  * There is no way to determine the number of TSO/USO
5870                  * capable Queues. Let's use always the Queue 0
5871                  * because if TSO/USO is supported then at least this
5872                  * one will be capable.
5873                  */
5874                 return 0;
5875         }
5876
5877         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
5878 }
5879
5880 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
5881 {
5882         struct stmmac_priv *priv = netdev_priv(ndev);
5883         int ret = 0;
5884
5885         ret = pm_runtime_get_sync(priv->device);
5886         if (ret < 0) {
5887                 pm_runtime_put_noidle(priv->device);
5888                 return ret;
5889         }
5890
5891         ret = eth_mac_addr(ndev, addr);
5892         if (ret)
5893                 goto set_mac_error;
5894
5895         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
5896
5897 set_mac_error:
5898         pm_runtime_put(priv->device);
5899
5900         return ret;
5901 }
5902
5903 #ifdef CONFIG_DEBUG_FS
5904 static struct dentry *stmmac_fs_dir;
5905
5906 static void sysfs_display_ring(void *head, int size, int extend_desc,
5907                                struct seq_file *seq, dma_addr_t dma_phy_addr)
5908 {
5909         int i;
5910         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
5911         struct dma_desc *p = (struct dma_desc *)head;
5912         dma_addr_t dma_addr;
5913
5914         for (i = 0; i < size; i++) {
5915                 if (extend_desc) {
5916                         dma_addr = dma_phy_addr + i * sizeof(*ep);
5917                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5918                                    i, &dma_addr,
5919                                    le32_to_cpu(ep->basic.des0),
5920                                    le32_to_cpu(ep->basic.des1),
5921                                    le32_to_cpu(ep->basic.des2),
5922                                    le32_to_cpu(ep->basic.des3));
5923                         ep++;
5924                 } else {
5925                         dma_addr = dma_phy_addr + i * sizeof(*p);
5926                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5927                                    i, &dma_addr,
5928                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
5929                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
5930                         p++;
5931                 }
5932                 seq_printf(seq, "\n");
5933         }
5934 }
5935
5936 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
5937 {
5938         struct net_device *dev = seq->private;
5939         struct stmmac_priv *priv = netdev_priv(dev);
5940         u32 rx_count = priv->plat->rx_queues_to_use;
5941         u32 tx_count = priv->plat->tx_queues_to_use;
5942         u32 queue;
5943
5944         if ((dev->flags & IFF_UP) == 0)
5945                 return 0;
5946
5947         for (queue = 0; queue < rx_count; queue++) {
5948                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5949
5950                 seq_printf(seq, "RX Queue %d:\n", queue);
5951
5952                 if (priv->extend_desc) {
5953                         seq_printf(seq, "Extended descriptor ring:\n");
5954                         sysfs_display_ring((void *)rx_q->dma_erx,
5955                                            priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy);
5956                 } else {
5957                         seq_printf(seq, "Descriptor ring:\n");
5958                         sysfs_display_ring((void *)rx_q->dma_rx,
5959                                            priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy);
5960                 }
5961         }
5962
5963         for (queue = 0; queue < tx_count; queue++) {
5964                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5965
5966                 seq_printf(seq, "TX Queue %d:\n", queue);
5967
5968                 if (priv->extend_desc) {
5969                         seq_printf(seq, "Extended descriptor ring:\n");
5970                         sysfs_display_ring((void *)tx_q->dma_etx,
5971                                            priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy);
5972                 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
5973                         seq_printf(seq, "Descriptor ring:\n");
5974                         sysfs_display_ring((void *)tx_q->dma_tx,
5975                                            priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy);
5976                 }
5977         }
5978
5979         return 0;
5980 }
5981 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
5982
5983 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
5984 {
5985         struct net_device *dev = seq->private;
5986         struct stmmac_priv *priv = netdev_priv(dev);
5987
5988         if (!priv->hw_cap_support) {
5989                 seq_printf(seq, "DMA HW features not supported\n");
5990                 return 0;
5991         }
5992
5993         seq_printf(seq, "==============================\n");
5994         seq_printf(seq, "\tDMA HW features\n");
5995         seq_printf(seq, "==============================\n");
5996
5997         seq_printf(seq, "\t10/100 Mbps: %s\n",
5998                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
5999         seq_printf(seq, "\t1000 Mbps: %s\n",
6000                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
6001         seq_printf(seq, "\tHalf duplex: %s\n",
6002                    (priv->dma_cap.half_duplex) ? "Y" : "N");
6003         seq_printf(seq, "\tHash Filter: %s\n",
6004                    (priv->dma_cap.hash_filter) ? "Y" : "N");
6005         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6006                    (priv->dma_cap.multi_addr) ? "Y" : "N");
6007         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6008                    (priv->dma_cap.pcs) ? "Y" : "N");
6009         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6010                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
6011         seq_printf(seq, "\tPMT Remote wake up: %s\n",
6012                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6013         seq_printf(seq, "\tPMT Magic Frame: %s\n",
6014                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6015         seq_printf(seq, "\tRMON module: %s\n",
6016                    (priv->dma_cap.rmon) ? "Y" : "N");
6017         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6018                    (priv->dma_cap.time_stamp) ? "Y" : "N");
6019         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6020                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
6021         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6022                    (priv->dma_cap.eee) ? "Y" : "N");
6023         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6024         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6025                    (priv->dma_cap.tx_coe) ? "Y" : "N");
6026         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6027                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6028                            (priv->dma_cap.rx_coe) ? "Y" : "N");
6029         } else {
6030                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6031                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6032                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6033                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6034         }
6035         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6036                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6037         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6038                    priv->dma_cap.number_rx_channel);
6039         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6040                    priv->dma_cap.number_tx_channel);
6041         seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6042                    priv->dma_cap.number_rx_queues);
6043         seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6044                    priv->dma_cap.number_tx_queues);
6045         seq_printf(seq, "\tEnhanced descriptors: %s\n",
6046                    (priv->dma_cap.enh_desc) ? "Y" : "N");
6047         seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6048         seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6049         seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6050         seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6051         seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6052                    priv->dma_cap.pps_out_num);
6053         seq_printf(seq, "\tSafety Features: %s\n",
6054                    priv->dma_cap.asp ? "Y" : "N");
6055         seq_printf(seq, "\tFlexible RX Parser: %s\n",
6056                    priv->dma_cap.frpsel ? "Y" : "N");
6057         seq_printf(seq, "\tEnhanced Addressing: %d\n",
6058                    priv->dma_cap.addr64);
6059         seq_printf(seq, "\tReceive Side Scaling: %s\n",
6060                    priv->dma_cap.rssen ? "Y" : "N");
6061         seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6062                    priv->dma_cap.vlhash ? "Y" : "N");
6063         seq_printf(seq, "\tSplit Header: %s\n",
6064                    priv->dma_cap.sphen ? "Y" : "N");
6065         seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6066                    priv->dma_cap.vlins ? "Y" : "N");
6067         seq_printf(seq, "\tDouble VLAN: %s\n",
6068                    priv->dma_cap.dvlan ? "Y" : "N");
6069         seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6070                    priv->dma_cap.l3l4fnum);
6071         seq_printf(seq, "\tARP Offloading: %s\n",
6072                    priv->dma_cap.arpoffsel ? "Y" : "N");
6073         seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6074                    priv->dma_cap.estsel ? "Y" : "N");
6075         seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6076                    priv->dma_cap.fpesel ? "Y" : "N");
6077         seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6078                    priv->dma_cap.tbssel ? "Y" : "N");
6079         return 0;
6080 }
6081 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6082
6083 /* Use network device events to rename debugfs file entries.
6084  */
6085 static int stmmac_device_event(struct notifier_block *unused,
6086                                unsigned long event, void *ptr)
6087 {
6088         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6089         struct stmmac_priv *priv = netdev_priv(dev);
6090
6091         if (dev->netdev_ops != &stmmac_netdev_ops)
6092                 goto done;
6093
6094         switch (event) {
6095         case NETDEV_CHANGENAME:
6096                 if (priv->dbgfs_dir)
6097                         priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6098                                                          priv->dbgfs_dir,
6099                                                          stmmac_fs_dir,
6100                                                          dev->name);
6101                 break;
6102         }
6103 done:
6104         return NOTIFY_DONE;
6105 }
6106
6107 static struct notifier_block stmmac_notifier = {
6108         .notifier_call = stmmac_device_event,
6109 };
6110
6111 static void stmmac_init_fs(struct net_device *dev)
6112 {
6113         struct stmmac_priv *priv = netdev_priv(dev);
6114
6115         rtnl_lock();
6116
6117         /* Create per netdev entries */
6118         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6119
6120         /* Entry to report DMA RX/TX rings */
6121         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6122                             &stmmac_rings_status_fops);
6123
6124         /* Entry to report the DMA HW features */
6125         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6126                             &stmmac_dma_cap_fops);
6127
6128         rtnl_unlock();
6129 }
6130
6131 static void stmmac_exit_fs(struct net_device *dev)
6132 {
6133         struct stmmac_priv *priv = netdev_priv(dev);
6134
6135         debugfs_remove_recursive(priv->dbgfs_dir);
6136 }
6137 #endif /* CONFIG_DEBUG_FS */
6138
6139 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6140 {
6141         unsigned char *data = (unsigned char *)&vid_le;
6142         unsigned char data_byte = 0;
6143         u32 crc = ~0x0;
6144         u32 temp = 0;
6145         int i, bits;
6146
6147         bits = get_bitmask_order(VLAN_VID_MASK);
6148         for (i = 0; i < bits; i++) {
6149                 if ((i % 8) == 0)
6150                         data_byte = data[i / 8];
6151
6152                 temp = ((crc & 1) ^ data_byte) & 1;
6153                 crc >>= 1;
6154                 data_byte >>= 1;
6155
6156                 if (temp)
6157                         crc ^= 0xedb88320;
6158         }
6159
6160         return crc;
6161 }
6162
6163 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6164 {
6165         u32 crc, hash = 0;
6166         __le16 pmatch = 0;
6167         int count = 0;
6168         u16 vid = 0;
6169
6170         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6171                 __le16 vid_le = cpu_to_le16(vid);
6172                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6173                 hash |= (1 << crc);
6174                 count++;
6175         }
6176
6177         if (!priv->dma_cap.vlhash) {
6178                 if (count > 2) /* VID = 0 always passes filter */
6179                         return -EOPNOTSUPP;
6180
6181                 pmatch = cpu_to_le16(vid);
6182                 hash = 0;
6183         }
6184
6185         return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6186 }
6187
6188 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6189 {
6190         struct stmmac_priv *priv = netdev_priv(ndev);
6191         bool is_double = false;
6192         int ret;
6193
6194         if (be16_to_cpu(proto) == ETH_P_8021AD)
6195                 is_double = true;
6196
6197         set_bit(vid, priv->active_vlans);
6198         ret = stmmac_vlan_update(priv, is_double);
6199         if (ret) {
6200                 clear_bit(vid, priv->active_vlans);
6201                 return ret;
6202         }
6203
6204         if (priv->hw->num_vlan) {
6205                 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6206                 if (ret)
6207                         return ret;
6208         }
6209
6210         return 0;
6211 }
6212
6213 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6214 {
6215         struct stmmac_priv *priv = netdev_priv(ndev);
6216         bool is_double = false;
6217         int ret;
6218
6219         ret = pm_runtime_get_sync(priv->device);
6220         if (ret < 0) {
6221                 pm_runtime_put_noidle(priv->device);
6222                 return ret;
6223         }
6224
6225         if (be16_to_cpu(proto) == ETH_P_8021AD)
6226                 is_double = true;
6227
6228         clear_bit(vid, priv->active_vlans);
6229
6230         if (priv->hw->num_vlan) {
6231                 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6232                 if (ret)
6233                         goto del_vlan_error;
6234         }
6235
6236         ret = stmmac_vlan_update(priv, is_double);
6237
6238 del_vlan_error:
6239         pm_runtime_put(priv->device);
6240
6241         return ret;
6242 }
6243
6244 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6245 {
6246         struct stmmac_priv *priv = netdev_priv(dev);
6247
6248         switch (bpf->command) {
6249         case XDP_SETUP_PROG:
6250                 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6251         case XDP_SETUP_XSK_POOL:
6252                 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6253                                              bpf->xsk.queue_id);
6254         default:
6255                 return -EOPNOTSUPP;
6256         }
6257 }
6258
6259 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6260                            struct xdp_frame **frames, u32 flags)
6261 {
6262         struct stmmac_priv *priv = netdev_priv(dev);
6263         int cpu = smp_processor_id();
6264         struct netdev_queue *nq;
6265         int i, nxmit = 0;
6266         int queue;
6267
6268         if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6269                 return -ENETDOWN;
6270
6271         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6272                 return -EINVAL;
6273
6274         queue = stmmac_xdp_get_tx_queue(priv, cpu);
6275         nq = netdev_get_tx_queue(priv->dev, queue);
6276
6277         __netif_tx_lock(nq, cpu);
6278         /* Avoids TX time-out as we are sharing with slow path */
6279         txq_trans_cond_update(nq);
6280
6281         for (i = 0; i < num_frames; i++) {
6282                 int res;
6283
6284                 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6285                 if (res == STMMAC_XDP_CONSUMED)
6286                         break;
6287
6288                 nxmit++;
6289         }
6290
6291         if (flags & XDP_XMIT_FLUSH) {
6292                 stmmac_flush_tx_descriptors(priv, queue);
6293                 stmmac_tx_timer_arm(priv, queue);
6294         }
6295
6296         __netif_tx_unlock(nq);
6297
6298         return nxmit;
6299 }
6300
6301 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6302 {
6303         struct stmmac_channel *ch = &priv->channel[queue];
6304         unsigned long flags;
6305
6306         spin_lock_irqsave(&ch->lock, flags);
6307         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6308         spin_unlock_irqrestore(&ch->lock, flags);
6309
6310         stmmac_stop_rx_dma(priv, queue);
6311         __free_dma_rx_desc_resources(priv, queue);
6312 }
6313
6314 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6315 {
6316         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
6317         struct stmmac_channel *ch = &priv->channel[queue];
6318         unsigned long flags;
6319         u32 buf_size;
6320         int ret;
6321
6322         ret = __alloc_dma_rx_desc_resources(priv, queue);
6323         if (ret) {
6324                 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6325                 return;
6326         }
6327
6328         ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL);
6329         if (ret) {
6330                 __free_dma_rx_desc_resources(priv, queue);
6331                 netdev_err(priv->dev, "Failed to init RX desc.\n");
6332                 return;
6333         }
6334
6335         stmmac_clear_rx_descriptors(priv, queue);
6336
6337         stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6338                             rx_q->dma_rx_phy, rx_q->queue_index);
6339
6340         rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6341                              sizeof(struct dma_desc));
6342         stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6343                                rx_q->rx_tail_addr, rx_q->queue_index);
6344
6345         if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6346                 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6347                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6348                                       buf_size,
6349                                       rx_q->queue_index);
6350         } else {
6351                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6352                                       priv->dma_buf_sz,
6353                                       rx_q->queue_index);
6354         }
6355
6356         stmmac_start_rx_dma(priv, queue);
6357
6358         spin_lock_irqsave(&ch->lock, flags);
6359         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6360         spin_unlock_irqrestore(&ch->lock, flags);
6361 }
6362
6363 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6364 {
6365         struct stmmac_channel *ch = &priv->channel[queue];
6366         unsigned long flags;
6367
6368         spin_lock_irqsave(&ch->lock, flags);
6369         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6370         spin_unlock_irqrestore(&ch->lock, flags);
6371
6372         stmmac_stop_tx_dma(priv, queue);
6373         __free_dma_tx_desc_resources(priv, queue);
6374 }
6375
6376 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6377 {
6378         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6379         struct stmmac_channel *ch = &priv->channel[queue];
6380         unsigned long flags;
6381         int ret;
6382
6383         ret = __alloc_dma_tx_desc_resources(priv, queue);
6384         if (ret) {
6385                 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6386                 return;
6387         }
6388
6389         ret = __init_dma_tx_desc_rings(priv, queue);
6390         if (ret) {
6391                 __free_dma_tx_desc_resources(priv, queue);
6392                 netdev_err(priv->dev, "Failed to init TX desc.\n");
6393                 return;
6394         }
6395
6396         stmmac_clear_tx_descriptors(priv, queue);
6397
6398         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6399                             tx_q->dma_tx_phy, tx_q->queue_index);
6400
6401         if (tx_q->tbs & STMMAC_TBS_AVAIL)
6402                 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6403
6404         tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6405         stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6406                                tx_q->tx_tail_addr, tx_q->queue_index);
6407
6408         stmmac_start_tx_dma(priv, queue);
6409
6410         spin_lock_irqsave(&ch->lock, flags);
6411         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6412         spin_unlock_irqrestore(&ch->lock, flags);
6413 }
6414
6415 void stmmac_xdp_release(struct net_device *dev)
6416 {
6417         struct stmmac_priv *priv = netdev_priv(dev);
6418         u32 chan;
6419
6420         /* Disable NAPI process */
6421         stmmac_disable_all_queues(priv);
6422
6423         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6424                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
6425
6426         /* Free the IRQ lines */
6427         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
6428
6429         /* Stop TX/RX DMA channels */
6430         stmmac_stop_all_dma(priv);
6431
6432         /* Release and free the Rx/Tx resources */
6433         free_dma_desc_resources(priv);
6434
6435         /* Disable the MAC Rx/Tx */
6436         stmmac_mac_set(priv, priv->ioaddr, false);
6437
6438         /* set trans_start so we don't get spurious
6439          * watchdogs during reset
6440          */
6441         netif_trans_update(dev);
6442         netif_carrier_off(dev);
6443 }
6444
6445 int stmmac_xdp_open(struct net_device *dev)
6446 {
6447         struct stmmac_priv *priv = netdev_priv(dev);
6448         u32 rx_cnt = priv->plat->rx_queues_to_use;
6449         u32 tx_cnt = priv->plat->tx_queues_to_use;
6450         u32 dma_csr_ch = max(rx_cnt, tx_cnt);
6451         struct stmmac_rx_queue *rx_q;
6452         struct stmmac_tx_queue *tx_q;
6453         u32 buf_size;
6454         bool sph_en;
6455         u32 chan;
6456         int ret;
6457
6458         ret = alloc_dma_desc_resources(priv);
6459         if (ret < 0) {
6460                 netdev_err(dev, "%s: DMA descriptors allocation failed\n",
6461                            __func__);
6462                 goto dma_desc_error;
6463         }
6464
6465         ret = init_dma_desc_rings(dev, GFP_KERNEL);
6466         if (ret < 0) {
6467                 netdev_err(dev, "%s: DMA descriptors initialization failed\n",
6468                            __func__);
6469                 goto init_error;
6470         }
6471
6472         /* DMA CSR Channel configuration */
6473         for (chan = 0; chan < dma_csr_ch; chan++)
6474                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
6475
6476         /* Adjust Split header */
6477         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
6478
6479         /* DMA RX Channel Configuration */
6480         for (chan = 0; chan < rx_cnt; chan++) {
6481                 rx_q = &priv->rx_queue[chan];
6482
6483                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6484                                     rx_q->dma_rx_phy, chan);
6485
6486                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
6487                                      (rx_q->buf_alloc_num *
6488                                       sizeof(struct dma_desc));
6489                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6490                                        rx_q->rx_tail_addr, chan);
6491
6492                 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6493                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6494                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
6495                                               buf_size,
6496                                               rx_q->queue_index);
6497                 } else {
6498                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
6499                                               priv->dma_buf_sz,
6500                                               rx_q->queue_index);
6501                 }
6502
6503                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
6504         }
6505
6506         /* DMA TX Channel Configuration */
6507         for (chan = 0; chan < tx_cnt; chan++) {
6508                 tx_q = &priv->tx_queue[chan];
6509
6510                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6511                                     tx_q->dma_tx_phy, chan);
6512
6513                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6514                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6515                                        tx_q->tx_tail_addr, chan);
6516
6517                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
6518                 tx_q->txtimer.function = stmmac_tx_timer;
6519         }
6520
6521         /* Enable the MAC Rx/Tx */
6522         stmmac_mac_set(priv, priv->ioaddr, true);
6523
6524         /* Start Rx & Tx DMA Channels */
6525         stmmac_start_all_dma(priv);
6526
6527         ret = stmmac_request_irq(dev);
6528         if (ret)
6529                 goto irq_error;
6530
6531         /* Enable NAPI process*/
6532         stmmac_enable_all_queues(priv);
6533         netif_carrier_on(dev);
6534         netif_tx_start_all_queues(dev);
6535
6536         return 0;
6537
6538 irq_error:
6539         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6540                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
6541
6542         stmmac_hw_teardown(dev);
6543 init_error:
6544         free_dma_desc_resources(priv);
6545 dma_desc_error:
6546         return ret;
6547 }
6548
6549 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6550 {
6551         struct stmmac_priv *priv = netdev_priv(dev);
6552         struct stmmac_rx_queue *rx_q;
6553         struct stmmac_tx_queue *tx_q;
6554         struct stmmac_channel *ch;
6555
6556         if (test_bit(STMMAC_DOWN, &priv->state) ||
6557             !netif_carrier_ok(priv->dev))
6558                 return -ENETDOWN;
6559
6560         if (!stmmac_xdp_is_enabled(priv))
6561                 return -ENXIO;
6562
6563         if (queue >= priv->plat->rx_queues_to_use ||
6564             queue >= priv->plat->tx_queues_to_use)
6565                 return -EINVAL;
6566
6567         rx_q = &priv->rx_queue[queue];
6568         tx_q = &priv->tx_queue[queue];
6569         ch = &priv->channel[queue];
6570
6571         if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6572                 return -ENXIO;
6573
6574         if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6575                 /* EQoS does not have per-DMA channel SW interrupt,
6576                  * so we schedule RX Napi straight-away.
6577                  */
6578                 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6579                         __napi_schedule(&ch->rxtx_napi);
6580         }
6581
6582         return 0;
6583 }
6584
6585 static const struct net_device_ops stmmac_netdev_ops = {
6586         .ndo_open = stmmac_open,
6587         .ndo_start_xmit = stmmac_xmit,
6588         .ndo_stop = stmmac_release,
6589         .ndo_change_mtu = stmmac_change_mtu,
6590         .ndo_fix_features = stmmac_fix_features,
6591         .ndo_set_features = stmmac_set_features,
6592         .ndo_set_rx_mode = stmmac_set_rx_mode,
6593         .ndo_tx_timeout = stmmac_tx_timeout,
6594         .ndo_eth_ioctl = stmmac_ioctl,
6595         .ndo_setup_tc = stmmac_setup_tc,
6596         .ndo_select_queue = stmmac_select_queue,
6597 #ifdef CONFIG_NET_POLL_CONTROLLER
6598         .ndo_poll_controller = stmmac_poll_controller,
6599 #endif
6600         .ndo_set_mac_address = stmmac_set_mac_address,
6601         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6602         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6603         .ndo_bpf = stmmac_bpf,
6604         .ndo_xdp_xmit = stmmac_xdp_xmit,
6605         .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6606 };
6607
6608 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6609 {
6610         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6611                 return;
6612         if (test_bit(STMMAC_DOWN, &priv->state))
6613                 return;
6614
6615         netdev_err(priv->dev, "Reset adapter.\n");
6616
6617         rtnl_lock();
6618         netif_trans_update(priv->dev);
6619         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6620                 usleep_range(1000, 2000);
6621
6622         set_bit(STMMAC_DOWN, &priv->state);
6623         dev_close(priv->dev);
6624         dev_open(priv->dev, NULL);
6625         clear_bit(STMMAC_DOWN, &priv->state);
6626         clear_bit(STMMAC_RESETING, &priv->state);
6627         rtnl_unlock();
6628 }
6629
6630 static void stmmac_service_task(struct work_struct *work)
6631 {
6632         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6633                         service_task);
6634
6635         stmmac_reset_subtask(priv);
6636         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6637 }
6638
6639 /**
6640  *  stmmac_hw_init - Init the MAC device
6641  *  @priv: driver private structure
6642  *  Description: this function is to configure the MAC device according to
6643  *  some platform parameters or the HW capability register. It prepares the
6644  *  driver to use either ring or chain modes and to setup either enhanced or
6645  *  normal descriptors.
6646  */
6647 static int stmmac_hw_init(struct stmmac_priv *priv)
6648 {
6649         int ret;
6650
6651         /* dwmac-sun8i only work in chain mode */
6652         if (priv->plat->has_sun8i)
6653                 chain_mode = 1;
6654         priv->chain_mode = chain_mode;
6655
6656         /* Initialize HW Interface */
6657         ret = stmmac_hwif_init(priv);
6658         if (ret)
6659                 return ret;
6660
6661         /* Get the HW capability (new GMAC newer than 3.50a) */
6662         priv->hw_cap_support = stmmac_get_hw_features(priv);
6663         if (priv->hw_cap_support) {
6664                 dev_info(priv->device, "DMA HW capability register supported\n");
6665
6666                 /* We can override some gmac/dma configuration fields: e.g.
6667                  * enh_desc, tx_coe (e.g. that are passed through the
6668                  * platform) with the values from the HW capability
6669                  * register (if supported).
6670                  */
6671                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6672                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6673                                 !priv->plat->use_phy_wol;
6674                 priv->hw->pmt = priv->plat->pmt;
6675                 if (priv->dma_cap.hash_tb_sz) {
6676                         priv->hw->multicast_filter_bins =
6677                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
6678                         priv->hw->mcast_bits_log2 =
6679                                         ilog2(priv->hw->multicast_filter_bins);
6680                 }
6681
6682                 /* TXCOE doesn't work in thresh DMA mode */
6683                 if (priv->plat->force_thresh_dma_mode)
6684                         priv->plat->tx_coe = 0;
6685                 else
6686                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
6687
6688                 /* In case of GMAC4 rx_coe is from HW cap register. */
6689                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6690
6691                 if (priv->dma_cap.rx_coe_type2)
6692                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6693                 else if (priv->dma_cap.rx_coe_type1)
6694                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6695
6696         } else {
6697                 dev_info(priv->device, "No HW DMA feature register supported\n");
6698         }
6699
6700         if (priv->plat->rx_coe) {
6701                 priv->hw->rx_csum = priv->plat->rx_coe;
6702                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6703                 if (priv->synopsys_id < DWMAC_CORE_4_00)
6704                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6705         }
6706         if (priv->plat->tx_coe)
6707                 dev_info(priv->device, "TX Checksum insertion supported\n");
6708
6709         if (priv->plat->pmt) {
6710                 dev_info(priv->device, "Wake-Up On Lan supported\n");
6711                 device_set_wakeup_capable(priv->device, 1);
6712         }
6713
6714         if (priv->dma_cap.tsoen)
6715                 dev_info(priv->device, "TSO supported\n");
6716
6717         priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6718         priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6719
6720         /* Run HW quirks, if any */
6721         if (priv->hwif_quirks) {
6722                 ret = priv->hwif_quirks(priv);
6723                 if (ret)
6724                         return ret;
6725         }
6726
6727         /* Rx Watchdog is available in the COREs newer than the 3.40.
6728          * In some case, for example on bugged HW this feature
6729          * has to be disable and this can be done by passing the
6730          * riwt_off field from the platform.
6731          */
6732         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6733             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6734                 priv->use_riwt = 1;
6735                 dev_info(priv->device,
6736                          "Enable RX Mitigation via HW Watchdog Timer\n");
6737         }
6738
6739         return 0;
6740 }
6741
6742 static void stmmac_napi_add(struct net_device *dev)
6743 {
6744         struct stmmac_priv *priv = netdev_priv(dev);
6745         u32 queue, maxq;
6746
6747         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6748
6749         for (queue = 0; queue < maxq; queue++) {
6750                 struct stmmac_channel *ch = &priv->channel[queue];
6751
6752                 ch->priv_data = priv;
6753                 ch->index = queue;
6754                 spin_lock_init(&ch->lock);
6755
6756                 if (queue < priv->plat->rx_queues_to_use) {
6757                         netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
6758                                        NAPI_POLL_WEIGHT);
6759                 }
6760                 if (queue < priv->plat->tx_queues_to_use) {
6761                         netif_tx_napi_add(dev, &ch->tx_napi,
6762                                           stmmac_napi_poll_tx,
6763                                           NAPI_POLL_WEIGHT);
6764                 }
6765                 if (queue < priv->plat->rx_queues_to_use &&
6766                     queue < priv->plat->tx_queues_to_use) {
6767                         netif_napi_add(dev, &ch->rxtx_napi,
6768                                        stmmac_napi_poll_rxtx,
6769                                        NAPI_POLL_WEIGHT);
6770                 }
6771         }
6772 }
6773
6774 static void stmmac_napi_del(struct net_device *dev)
6775 {
6776         struct stmmac_priv *priv = netdev_priv(dev);
6777         u32 queue, maxq;
6778
6779         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6780
6781         for (queue = 0; queue < maxq; queue++) {
6782                 struct stmmac_channel *ch = &priv->channel[queue];
6783
6784                 if (queue < priv->plat->rx_queues_to_use)
6785                         netif_napi_del(&ch->rx_napi);
6786                 if (queue < priv->plat->tx_queues_to_use)
6787                         netif_napi_del(&ch->tx_napi);
6788                 if (queue < priv->plat->rx_queues_to_use &&
6789                     queue < priv->plat->tx_queues_to_use) {
6790                         netif_napi_del(&ch->rxtx_napi);
6791                 }
6792         }
6793 }
6794
6795 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
6796 {
6797         struct stmmac_priv *priv = netdev_priv(dev);
6798         int ret = 0;
6799
6800         if (netif_running(dev))
6801                 stmmac_release(dev);
6802
6803         stmmac_napi_del(dev);
6804
6805         priv->plat->rx_queues_to_use = rx_cnt;
6806         priv->plat->tx_queues_to_use = tx_cnt;
6807
6808         stmmac_napi_add(dev);
6809
6810         if (netif_running(dev))
6811                 ret = stmmac_open(dev);
6812
6813         return ret;
6814 }
6815
6816 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
6817 {
6818         struct stmmac_priv *priv = netdev_priv(dev);
6819         int ret = 0;
6820
6821         if (netif_running(dev))
6822                 stmmac_release(dev);
6823
6824         priv->dma_rx_size = rx_size;
6825         priv->dma_tx_size = tx_size;
6826
6827         if (netif_running(dev))
6828                 ret = stmmac_open(dev);
6829
6830         return ret;
6831 }
6832
6833 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
6834 static void stmmac_fpe_lp_task(struct work_struct *work)
6835 {
6836         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6837                                                 fpe_task);
6838         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
6839         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
6840         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
6841         bool *hs_enable = &fpe_cfg->hs_enable;
6842         bool *enable = &fpe_cfg->enable;
6843         int retries = 20;
6844
6845         while (retries-- > 0) {
6846                 /* Bail out immediately if FPE handshake is OFF */
6847                 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
6848                         break;
6849
6850                 if (*lo_state == FPE_STATE_ENTERING_ON &&
6851                     *lp_state == FPE_STATE_ENTERING_ON) {
6852                         stmmac_fpe_configure(priv, priv->ioaddr,
6853                                              priv->plat->tx_queues_to_use,
6854                                              priv->plat->rx_queues_to_use,
6855                                              *enable);
6856
6857                         netdev_info(priv->dev, "configured FPE\n");
6858
6859                         *lo_state = FPE_STATE_ON;
6860                         *lp_state = FPE_STATE_ON;
6861                         netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
6862                         break;
6863                 }
6864
6865                 if ((*lo_state == FPE_STATE_CAPABLE ||
6866                      *lo_state == FPE_STATE_ENTERING_ON) &&
6867                      *lp_state != FPE_STATE_ON) {
6868                         netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
6869                                     *lo_state, *lp_state);
6870                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6871                                                 MPACKET_VERIFY);
6872                 }
6873                 /* Sleep then retry */
6874                 msleep(500);
6875         }
6876
6877         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
6878 }
6879
6880 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
6881 {
6882         if (priv->plat->fpe_cfg->hs_enable != enable) {
6883                 if (enable) {
6884                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6885                                                 MPACKET_VERIFY);
6886                 } else {
6887                         priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
6888                         priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
6889                 }
6890
6891                 priv->plat->fpe_cfg->hs_enable = enable;
6892         }
6893 }
6894
6895 /**
6896  * stmmac_dvr_probe
6897  * @device: device pointer
6898  * @plat_dat: platform data pointer
6899  * @res: stmmac resource pointer
6900  * Description: this is the main probe function used to
6901  * call the alloc_etherdev, allocate the priv structure.
6902  * Return:
6903  * returns 0 on success, otherwise errno.
6904  */
6905 int stmmac_dvr_probe(struct device *device,
6906                      struct plat_stmmacenet_data *plat_dat,
6907                      struct stmmac_resources *res)
6908 {
6909         struct net_device *ndev = NULL;
6910         struct stmmac_priv *priv;
6911         u32 rxq;
6912         int i, ret = 0;
6913
6914         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
6915                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
6916         if (!ndev)
6917                 return -ENOMEM;
6918
6919         SET_NETDEV_DEV(ndev, device);
6920
6921         priv = netdev_priv(ndev);
6922         priv->device = device;
6923         priv->dev = ndev;
6924
6925         stmmac_set_ethtool_ops(ndev);
6926         priv->pause = pause;
6927         priv->plat = plat_dat;
6928         priv->ioaddr = res->addr;
6929         priv->dev->base_addr = (unsigned long)res->addr;
6930         priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
6931
6932         priv->dev->irq = res->irq;
6933         priv->wol_irq = res->wol_irq;
6934         priv->lpi_irq = res->lpi_irq;
6935         priv->sfty_ce_irq = res->sfty_ce_irq;
6936         priv->sfty_ue_irq = res->sfty_ue_irq;
6937         for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
6938                 priv->rx_irq[i] = res->rx_irq[i];
6939         for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
6940                 priv->tx_irq[i] = res->tx_irq[i];
6941
6942         if (!is_zero_ether_addr(res->mac))
6943                 eth_hw_addr_set(priv->dev, res->mac);
6944
6945         dev_set_drvdata(device, priv->dev);
6946
6947         /* Verify driver arguments */
6948         stmmac_verify_args();
6949
6950         priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
6951         if (!priv->af_xdp_zc_qps)
6952                 return -ENOMEM;
6953
6954         /* Allocate workqueue */
6955         priv->wq = create_singlethread_workqueue("stmmac_wq");
6956         if (!priv->wq) {
6957                 dev_err(priv->device, "failed to create workqueue\n");
6958                 return -ENOMEM;
6959         }
6960
6961         INIT_WORK(&priv->service_task, stmmac_service_task);
6962
6963         /* Initialize Link Partner FPE workqueue */
6964         INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
6965
6966         /* Override with kernel parameters if supplied XXX CRS XXX
6967          * this needs to have multiple instances
6968          */
6969         if ((phyaddr >= 0) && (phyaddr <= 31))
6970                 priv->plat->phy_addr = phyaddr;
6971
6972         if (priv->plat->stmmac_rst) {
6973                 ret = reset_control_assert(priv->plat->stmmac_rst);
6974                 reset_control_deassert(priv->plat->stmmac_rst);
6975                 /* Some reset controllers have only reset callback instead of
6976                  * assert + deassert callbacks pair.
6977                  */
6978                 if (ret == -ENOTSUPP)
6979                         reset_control_reset(priv->plat->stmmac_rst);
6980         }
6981
6982         ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
6983         if (ret == -ENOTSUPP)
6984                 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
6985                         ERR_PTR(ret));
6986
6987         /* Init MAC and get the capabilities */
6988         ret = stmmac_hw_init(priv);
6989         if (ret)
6990                 goto error_hw_init;
6991
6992         /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
6993          */
6994         if (priv->synopsys_id < DWMAC_CORE_5_20)
6995                 priv->plat->dma_cfg->dche = false;
6996
6997         stmmac_check_ether_addr(priv);
6998
6999         ndev->netdev_ops = &stmmac_netdev_ops;
7000
7001         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
7002                             NETIF_F_RXCSUM;
7003
7004         ret = stmmac_tc_init(priv, priv);
7005         if (!ret) {
7006                 ndev->hw_features |= NETIF_F_HW_TC;
7007         }
7008
7009         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
7010                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
7011                 if (priv->plat->has_gmac4)
7012                         ndev->hw_features |= NETIF_F_GSO_UDP_L4;
7013                 priv->tso = true;
7014                 dev_info(priv->device, "TSO feature enabled\n");
7015         }
7016
7017         if (priv->dma_cap.sphen) {
7018                 ndev->hw_features |= NETIF_F_GRO;
7019                 priv->sph_cap = true;
7020                 priv->sph = priv->sph_cap;
7021                 dev_info(priv->device, "SPH feature enabled\n");
7022         }
7023
7024         /* The current IP register MAC_HW_Feature1[ADDR64] only define
7025          * 32/40/64 bit width, but some SOC support others like i.MX8MP
7026          * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
7027          * So overwrite dma_cap.addr64 according to HW real design.
7028          */
7029         if (priv->plat->addr64)
7030                 priv->dma_cap.addr64 = priv->plat->addr64;
7031
7032         if (priv->dma_cap.addr64) {
7033                 ret = dma_set_mask_and_coherent(device,
7034                                 DMA_BIT_MASK(priv->dma_cap.addr64));
7035                 if (!ret) {
7036                         dev_info(priv->device, "Using %d bits DMA width\n",
7037                                  priv->dma_cap.addr64);
7038
7039                         /*
7040                          * If more than 32 bits can be addressed, make sure to
7041                          * enable enhanced addressing mode.
7042                          */
7043                         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
7044                                 priv->plat->dma_cfg->eame = true;
7045                 } else {
7046                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
7047                         if (ret) {
7048                                 dev_err(priv->device, "Failed to set DMA Mask\n");
7049                                 goto error_hw_init;
7050                         }
7051
7052                         priv->dma_cap.addr64 = 32;
7053                 }
7054         }
7055
7056         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
7057         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
7058 #ifdef STMMAC_VLAN_TAG_USED
7059         /* Both mac100 and gmac support receive VLAN tag detection */
7060         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
7061         if (priv->dma_cap.vlhash) {
7062                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7063                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
7064         }
7065         if (priv->dma_cap.vlins) {
7066                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
7067                 if (priv->dma_cap.dvlan)
7068                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
7069         }
7070 #endif
7071         priv->msg_enable = netif_msg_init(debug, default_msg_level);
7072
7073         /* Initialize RSS */
7074         rxq = priv->plat->rx_queues_to_use;
7075         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
7076         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7077                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
7078
7079         if (priv->dma_cap.rssen && priv->plat->rss_en)
7080                 ndev->features |= NETIF_F_RXHASH;
7081
7082         /* MTU range: 46 - hw-specific max */
7083         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
7084         if (priv->plat->has_xgmac)
7085                 ndev->max_mtu = XGMAC_JUMBO_LEN;
7086         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
7087                 ndev->max_mtu = JUMBO_LEN;
7088         else
7089                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
7090         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
7091          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
7092          */
7093         if ((priv->plat->maxmtu < ndev->max_mtu) &&
7094             (priv->plat->maxmtu >= ndev->min_mtu))
7095                 ndev->max_mtu = priv->plat->maxmtu;
7096         else if (priv->plat->maxmtu < ndev->min_mtu)
7097                 dev_warn(priv->device,
7098                          "%s: warning: maxmtu having invalid value (%d)\n",
7099                          __func__, priv->plat->maxmtu);
7100
7101         if (flow_ctrl)
7102                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
7103
7104         /* Setup channels NAPI */
7105         stmmac_napi_add(ndev);
7106
7107         mutex_init(&priv->lock);
7108
7109         /* If a specific clk_csr value is passed from the platform
7110          * this means that the CSR Clock Range selection cannot be
7111          * changed at run-time and it is fixed. Viceversa the driver'll try to
7112          * set the MDC clock dynamically according to the csr actual
7113          * clock input.
7114          */
7115         if (priv->plat->clk_csr >= 0)
7116                 priv->clk_csr = priv->plat->clk_csr;
7117         else
7118                 stmmac_clk_csr_set(priv);
7119
7120         stmmac_check_pcs_mode(priv);
7121
7122         pm_runtime_get_noresume(device);
7123         pm_runtime_set_active(device);
7124         if (!pm_runtime_enabled(device))
7125                 pm_runtime_enable(device);
7126
7127         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7128             priv->hw->pcs != STMMAC_PCS_RTBI) {
7129                 /* MDIO bus Registration */
7130                 ret = stmmac_mdio_register(ndev);
7131                 if (ret < 0) {
7132                         dev_err(priv->device,
7133                                 "%s: MDIO bus (id: %d) registration failed",
7134                                 __func__, priv->plat->bus_id);
7135                         goto error_mdio_register;
7136                 }
7137         }
7138
7139         if (priv->plat->speed_mode_2500)
7140                 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7141
7142         if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7143                 ret = stmmac_xpcs_setup(priv->mii);
7144                 if (ret)
7145                         goto error_xpcs_setup;
7146         }
7147
7148         ret = stmmac_phy_setup(priv);
7149         if (ret) {
7150                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7151                 goto error_phy_setup;
7152         }
7153
7154         ret = register_netdev(ndev);
7155         if (ret) {
7156                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7157                         __func__, ret);
7158                 goto error_netdev_register;
7159         }
7160
7161         if (priv->plat->serdes_powerup) {
7162                 ret = priv->plat->serdes_powerup(ndev,
7163                                                  priv->plat->bsp_priv);
7164
7165                 if (ret < 0)
7166                         goto error_serdes_powerup;
7167         }
7168
7169 #ifdef CONFIG_DEBUG_FS
7170         stmmac_init_fs(ndev);
7171 #endif
7172
7173         if (priv->plat->dump_debug_regs)
7174                 priv->plat->dump_debug_regs(priv->plat->bsp_priv);
7175
7176         /* Let pm_runtime_put() disable the clocks.
7177          * If CONFIG_PM is not enabled, the clocks will stay powered.
7178          */
7179         pm_runtime_put(device);
7180
7181         return ret;
7182
7183 error_serdes_powerup:
7184         unregister_netdev(ndev);
7185 error_netdev_register:
7186         phylink_destroy(priv->phylink);
7187 error_xpcs_setup:
7188 error_phy_setup:
7189         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7190             priv->hw->pcs != STMMAC_PCS_RTBI)
7191                 stmmac_mdio_unregister(ndev);
7192 error_mdio_register:
7193         stmmac_napi_del(ndev);
7194 error_hw_init:
7195         destroy_workqueue(priv->wq);
7196         bitmap_free(priv->af_xdp_zc_qps);
7197
7198         return ret;
7199 }
7200 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7201
7202 /**
7203  * stmmac_dvr_remove
7204  * @dev: device pointer
7205  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7206  * changes the link status, releases the DMA descriptor rings.
7207  */
7208 int stmmac_dvr_remove(struct device *dev)
7209 {
7210         struct net_device *ndev = dev_get_drvdata(dev);
7211         struct stmmac_priv *priv = netdev_priv(ndev);
7212
7213         netdev_info(priv->dev, "%s: removing driver", __func__);
7214
7215         stmmac_stop_all_dma(priv);
7216         stmmac_mac_set(priv, priv->ioaddr, false);
7217         netif_carrier_off(ndev);
7218         unregister_netdev(ndev);
7219
7220         /* Serdes power down needs to happen after VLAN filter
7221          * is deleted that is triggered by unregister_netdev().
7222          */
7223         if (priv->plat->serdes_powerdown)
7224                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7225
7226 #ifdef CONFIG_DEBUG_FS
7227         stmmac_exit_fs(ndev);
7228 #endif
7229         phylink_destroy(priv->phylink);
7230         if (priv->plat->stmmac_rst)
7231                 reset_control_assert(priv->plat->stmmac_rst);
7232         reset_control_assert(priv->plat->stmmac_ahb_rst);
7233         pm_runtime_put(dev);
7234         pm_runtime_disable(dev);
7235         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7236             priv->hw->pcs != STMMAC_PCS_RTBI)
7237                 stmmac_mdio_unregister(ndev);
7238         destroy_workqueue(priv->wq);
7239         mutex_destroy(&priv->lock);
7240         bitmap_free(priv->af_xdp_zc_qps);
7241
7242         return 0;
7243 }
7244 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7245
7246 /**
7247  * stmmac_suspend - suspend callback
7248  * @dev: device pointer
7249  * Description: this is the function to suspend the device and it is called
7250  * by the platform driver to stop the network queue, release the resources,
7251  * program the PMT register (for WoL), clean and release driver resources.
7252  */
7253 int stmmac_suspend(struct device *dev)
7254 {
7255         struct net_device *ndev = dev_get_drvdata(dev);
7256         struct stmmac_priv *priv = netdev_priv(ndev);
7257         u32 chan;
7258
7259         if (!ndev || !netif_running(ndev))
7260                 return 0;
7261
7262         mutex_lock(&priv->lock);
7263
7264         netif_device_detach(ndev);
7265
7266         stmmac_disable_all_queues(priv);
7267
7268         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7269                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
7270
7271         if (priv->eee_enabled) {
7272                 priv->tx_path_in_lpi_mode = false;
7273                 del_timer_sync(&priv->eee_ctrl_timer);
7274         }
7275
7276         /* Stop TX/RX DMA */
7277         stmmac_stop_all_dma(priv);
7278
7279         if (priv->plat->serdes_powerdown)
7280                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7281
7282         /* Enable Power down mode by programming the PMT regs */
7283         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7284                 stmmac_pmt(priv, priv->hw, priv->wolopts);
7285                 priv->irq_wake = 1;
7286         } else {
7287                 stmmac_mac_set(priv, priv->ioaddr, false);
7288                 pinctrl_pm_select_sleep_state(priv->device);
7289         }
7290
7291         mutex_unlock(&priv->lock);
7292
7293         rtnl_lock();
7294         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7295                 phylink_suspend(priv->phylink, true);
7296         } else {
7297                 if (device_may_wakeup(priv->device))
7298                         phylink_speed_down(priv->phylink, false);
7299                 phylink_suspend(priv->phylink, false);
7300         }
7301         rtnl_unlock();
7302
7303         if (priv->dma_cap.fpesel) {
7304                 /* Disable FPE */
7305                 stmmac_fpe_configure(priv, priv->ioaddr,
7306                                      priv->plat->tx_queues_to_use,
7307                                      priv->plat->rx_queues_to_use, false);
7308
7309                 stmmac_fpe_handshake(priv, false);
7310                 stmmac_fpe_stop_wq(priv);
7311         }
7312
7313         priv->speed = SPEED_UNKNOWN;
7314         return 0;
7315 }
7316 EXPORT_SYMBOL_GPL(stmmac_suspend);
7317
7318 /**
7319  * stmmac_reset_queues_param - reset queue parameters
7320  * @priv: device pointer
7321  */
7322 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7323 {
7324         u32 rx_cnt = priv->plat->rx_queues_to_use;
7325         u32 tx_cnt = priv->plat->tx_queues_to_use;
7326         u32 queue;
7327
7328         for (queue = 0; queue < rx_cnt; queue++) {
7329                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
7330
7331                 rx_q->cur_rx = 0;
7332                 rx_q->dirty_rx = 0;
7333         }
7334
7335         for (queue = 0; queue < tx_cnt; queue++) {
7336                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
7337
7338                 tx_q->cur_tx = 0;
7339                 tx_q->dirty_tx = 0;
7340                 tx_q->mss = 0;
7341
7342                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7343         }
7344 }
7345
7346 /**
7347  * stmmac_resume - resume callback
7348  * @dev: device pointer
7349  * Description: when resume this function is invoked to setup the DMA and CORE
7350  * in a usable state.
7351  */
7352 int stmmac_resume(struct device *dev)
7353 {
7354         struct net_device *ndev = dev_get_drvdata(dev);
7355         struct stmmac_priv *priv = netdev_priv(ndev);
7356         int ret;
7357
7358         if (!netif_running(ndev))
7359                 return 0;
7360
7361         /* Power Down bit, into the PM register, is cleared
7362          * automatically as soon as a magic packet or a Wake-up frame
7363          * is received. Anyway, it's better to manually clear
7364          * this bit because it can generate problems while resuming
7365          * from another devices (e.g. serial console).
7366          */
7367         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7368                 mutex_lock(&priv->lock);
7369                 stmmac_pmt(priv, priv->hw, 0);
7370                 mutex_unlock(&priv->lock);
7371                 priv->irq_wake = 0;
7372         } else {
7373                 pinctrl_pm_select_default_state(priv->device);
7374                 /* reset the phy so that it's ready */
7375                 if (priv->mii)
7376                         stmmac_mdio_reset(priv->mii);
7377         }
7378
7379         if (priv->plat->serdes_powerup) {
7380                 ret = priv->plat->serdes_powerup(ndev,
7381                                                  priv->plat->bsp_priv);
7382
7383                 if (ret < 0)
7384                         return ret;
7385         }
7386
7387         rtnl_lock();
7388         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7389                 phylink_resume(priv->phylink);
7390         } else {
7391                 phylink_resume(priv->phylink);
7392                 if (device_may_wakeup(priv->device))
7393                         phylink_speed_up(priv->phylink);
7394         }
7395         rtnl_unlock();
7396
7397         rtnl_lock();
7398         mutex_lock(&priv->lock);
7399
7400         stmmac_reset_queues_param(priv);
7401
7402         stmmac_free_tx_skbufs(priv);
7403         stmmac_clear_descriptors(priv);
7404
7405         stmmac_hw_setup(ndev, false);
7406         stmmac_init_coalesce(priv);
7407         stmmac_set_rx_mode(ndev);
7408
7409         stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7410
7411         stmmac_enable_all_queues(priv);
7412
7413         mutex_unlock(&priv->lock);
7414         rtnl_unlock();
7415
7416         netif_device_attach(ndev);
7417
7418         return 0;
7419 }
7420 EXPORT_SYMBOL_GPL(stmmac_resume);
7421
7422 #ifndef MODULE
7423 static int __init stmmac_cmdline_opt(char *str)
7424 {
7425         char *opt;
7426
7427         if (!str || !*str)
7428                 return -EINVAL;
7429         while ((opt = strsep(&str, ",")) != NULL) {
7430                 if (!strncmp(opt, "debug:", 6)) {
7431                         if (kstrtoint(opt + 6, 0, &debug))
7432                                 goto err;
7433                 } else if (!strncmp(opt, "phyaddr:", 8)) {
7434                         if (kstrtoint(opt + 8, 0, &phyaddr))
7435                                 goto err;
7436                 } else if (!strncmp(opt, "buf_sz:", 7)) {
7437                         if (kstrtoint(opt + 7, 0, &buf_sz))
7438                                 goto err;
7439                 } else if (!strncmp(opt, "tc:", 3)) {
7440                         if (kstrtoint(opt + 3, 0, &tc))
7441                                 goto err;
7442                 } else if (!strncmp(opt, "watchdog:", 9)) {
7443                         if (kstrtoint(opt + 9, 0, &watchdog))
7444                                 goto err;
7445                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7446                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
7447                                 goto err;
7448                 } else if (!strncmp(opt, "pause:", 6)) {
7449                         if (kstrtoint(opt + 6, 0, &pause))
7450                                 goto err;
7451                 } else if (!strncmp(opt, "eee_timer:", 10)) {
7452                         if (kstrtoint(opt + 10, 0, &eee_timer))
7453                                 goto err;
7454                 } else if (!strncmp(opt, "chain_mode:", 11)) {
7455                         if (kstrtoint(opt + 11, 0, &chain_mode))
7456                                 goto err;
7457                 }
7458         }
7459         return 0;
7460
7461 err:
7462         pr_err("%s: ERROR broken module parameter conversion", __func__);
7463         return -EINVAL;
7464 }
7465
7466 __setup("stmmaceth=", stmmac_cmdline_opt);
7467 #endif /* MODULE */
7468
7469 static int __init stmmac_init(void)
7470 {
7471 #ifdef CONFIG_DEBUG_FS
7472         /* Create debugfs main directory if it doesn't exist yet */
7473         if (!stmmac_fs_dir)
7474                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7475         register_netdevice_notifier(&stmmac_notifier);
7476 #endif
7477
7478         return 0;
7479 }
7480
7481 static void __exit stmmac_exit(void)
7482 {
7483 #ifdef CONFIG_DEBUG_FS
7484         unregister_netdevice_notifier(&stmmac_notifier);
7485         debugfs_remove_recursive(stmmac_fs_dir);
7486 #endif
7487 }
7488
7489 module_init(stmmac_init)
7490 module_exit(stmmac_exit)
7491
7492 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7493 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7494 MODULE_LICENSE("GPL");