1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/prefetch.h>
33 #include <linux/pinctrl/consumer.h>
34 #ifdef CONFIG_DEBUG_FS
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #endif /* CONFIG_DEBUG_FS */
38 #include <linux/net_tstamp.h>
39 #include <linux/phylink.h>
40 #include <linux/udp.h>
41 #include <linux/bpf_trace.h>
42 #include <net/pkt_cls.h>
43 #include <net/xdp_sock_drv.h>
44 #include "stmmac_ptp.h"
46 #include "stmmac_xdp.h"
47 #include <linux/reset.h>
48 #include <linux/of_mdio.h>
49 #include "dwmac1000.h"
53 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
54 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
56 /* Module parameters */
58 static int watchdog = TX_TIMEO;
59 module_param(watchdog, int, 0644);
60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
62 static int debug = -1;
63 module_param(debug, int, 0644);
64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
66 static int phyaddr = -1;
67 module_param(phyaddr, int, 0444);
68 MODULE_PARM_DESC(phyaddr, "Physical device address");
70 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4)
71 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4)
73 /* Limit to make sure XDP TX and slow path can coexist */
74 #define STMMAC_XSK_TX_BUDGET_MAX 256
75 #define STMMAC_TX_XSK_AVAIL 16
76 #define STMMAC_RX_FILL_BATCH 16
78 #define STMMAC_XDP_PASS 0
79 #define STMMAC_XDP_CONSUMED BIT(0)
80 #define STMMAC_XDP_TX BIT(1)
81 #define STMMAC_XDP_REDIRECT BIT(2)
83 static int flow_ctrl = FLOW_AUTO;
84 module_param(flow_ctrl, int, 0644);
85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
87 static int pause = PAUSE_TIME;
88 module_param(pause, int, 0644);
89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
92 static int tc = TC_DEFAULT;
93 module_param(tc, int, 0644);
94 MODULE_PARM_DESC(tc, "DMA threshold control value");
96 #define DEFAULT_BUFSIZE 1536
97 static int buf_sz = DEFAULT_BUFSIZE;
98 module_param(buf_sz, int, 0644);
99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
101 #define STMMAC_RX_COPYBREAK 256
103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
104 NETIF_MSG_LINK | NETIF_MSG_IFUP |
105 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
107 #define STMMAC_DEFAULT_LPI_TIMER 1000
108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
109 module_param(eee_timer, int, 0644);
110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
113 /* By default the driver will use the ring mode to manage tx and rx descriptors,
114 * but allow user to force to use the chain instead of the ring
116 static unsigned int chain_mode;
117 module_param(chain_mode, int, 0444);
118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
121 /* For MSI interrupts handling */
122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
129 #ifdef CONFIG_DEBUG_FS
130 static const struct net_device_ops stmmac_netdev_ops;
131 static void stmmac_init_fs(struct net_device *dev);
132 static void stmmac_exit_fs(struct net_device *dev);
135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
142 ret = clk_prepare_enable(priv->plat->stmmac_clk);
145 ret = clk_prepare_enable(priv->plat->pclk);
147 clk_disable_unprepare(priv->plat->stmmac_clk);
150 if (priv->plat->clks_config) {
151 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
153 clk_disable_unprepare(priv->plat->stmmac_clk);
154 clk_disable_unprepare(priv->plat->pclk);
159 clk_disable_unprepare(priv->plat->stmmac_clk);
160 clk_disable_unprepare(priv->plat->pclk);
161 if (priv->plat->clks_config)
162 priv->plat->clks_config(priv->plat->bsp_priv, enabled);
167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
170 * stmmac_verify_args - verify the driver parameters.
171 * Description: it checks the driver parameters and set a default in case of
174 static void stmmac_verify_args(void)
176 if (unlikely(watchdog < 0))
178 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
179 buf_sz = DEFAULT_BUFSIZE;
180 if (unlikely(flow_ctrl > 1))
181 flow_ctrl = FLOW_AUTO;
182 else if (likely(flow_ctrl < 0))
183 flow_ctrl = FLOW_OFF;
184 if (unlikely((pause < 0) || (pause > 0xffff)))
187 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
192 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
193 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
194 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
197 for (queue = 0; queue < maxq; queue++) {
198 struct stmmac_channel *ch = &priv->channel[queue];
200 if (stmmac_xdp_is_enabled(priv) &&
201 test_bit(queue, priv->af_xdp_zc_qps)) {
202 napi_disable(&ch->rxtx_napi);
206 if (queue < rx_queues_cnt)
207 napi_disable(&ch->rx_napi);
208 if (queue < tx_queues_cnt)
209 napi_disable(&ch->tx_napi);
214 * stmmac_disable_all_queues - Disable all queues
215 * @priv: driver private structure
217 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
219 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
220 struct stmmac_rx_queue *rx_q;
223 /* synchronize_rcu() needed for pending XDP buffers to drain */
224 for (queue = 0; queue < rx_queues_cnt; queue++) {
225 rx_q = &priv->rx_queue[queue];
226 if (rx_q->xsk_pool) {
232 __stmmac_disable_all_queues(priv);
236 * stmmac_enable_all_queues - Enable all queues
237 * @priv: driver private structure
239 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
241 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
242 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
243 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
246 for (queue = 0; queue < maxq; queue++) {
247 struct stmmac_channel *ch = &priv->channel[queue];
249 if (stmmac_xdp_is_enabled(priv) &&
250 test_bit(queue, priv->af_xdp_zc_qps)) {
251 napi_enable(&ch->rxtx_napi);
255 if (queue < rx_queues_cnt)
256 napi_enable(&ch->rx_napi);
257 if (queue < tx_queues_cnt)
258 napi_enable(&ch->tx_napi);
262 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
264 if (!test_bit(STMMAC_DOWN, &priv->state) &&
265 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
266 queue_work(priv->wq, &priv->service_task);
269 static void stmmac_global_err(struct stmmac_priv *priv)
271 netif_carrier_off(priv->dev);
272 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
273 stmmac_service_event_schedule(priv);
277 * stmmac_clk_csr_set - dynamically set the MDC clock
278 * @priv: driver private structure
279 * Description: this is to dynamically set the MDC clock according to the csr
282 * If a specific clk_csr value is passed from the platform
283 * this means that the CSR Clock Range selection cannot be
284 * changed at run-time and it is fixed (as reported in the driver
285 * documentation). Viceversa the driver will try to set the MDC
286 * clock dynamically according to the actual clock input.
288 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
292 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
294 /* Platform provided default clk_csr would be assumed valid
295 * for all other cases except for the below mentioned ones.
296 * For values higher than the IEEE 802.3 specified frequency
297 * we can not estimate the proper divider as it is not known
298 * the frequency of clk_csr_i. So we do not change the default
301 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
302 if (clk_rate < CSR_F_35M)
303 priv->clk_csr = STMMAC_CSR_20_35M;
304 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
305 priv->clk_csr = STMMAC_CSR_35_60M;
306 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
307 priv->clk_csr = STMMAC_CSR_60_100M;
308 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
309 priv->clk_csr = STMMAC_CSR_100_150M;
310 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
311 priv->clk_csr = STMMAC_CSR_150_250M;
312 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
313 priv->clk_csr = STMMAC_CSR_250_300M;
316 if (priv->plat->has_sun8i) {
317 if (clk_rate > 160000000)
318 priv->clk_csr = 0x03;
319 else if (clk_rate > 80000000)
320 priv->clk_csr = 0x02;
321 else if (clk_rate > 40000000)
322 priv->clk_csr = 0x01;
327 if (priv->plat->has_xgmac) {
328 if (clk_rate > 400000000)
330 else if (clk_rate > 350000000)
332 else if (clk_rate > 300000000)
334 else if (clk_rate > 250000000)
336 else if (clk_rate > 150000000)
343 static void print_pkt(unsigned char *buf, int len)
345 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
346 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
354 if (tx_q->dirty_tx > tx_q->cur_tx)
355 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
357 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
363 * stmmac_rx_dirty - Get RX queue dirty
364 * @priv: driver private structure
365 * @queue: RX queue index
367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
369 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
372 if (rx_q->dirty_rx <= rx_q->cur_rx)
373 dirty = rx_q->cur_rx - rx_q->dirty_rx;
375 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
384 /* Clear/set the SW EEE timer flag based on LPI ET enablement */
385 priv->eee_sw_timer_en = en ? 0 : 1;
386 tx_lpi_timer = en ? priv->tx_lpi_timer : 0;
387 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
391 * stmmac_enable_eee_mode - check and enter in LPI mode
392 * @priv: driver private structure
393 * Description: this function is to verify and enter in LPI mode in case of
396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
398 u32 tx_cnt = priv->plat->tx_queues_to_use;
401 /* check if all TX queues have the work finished */
402 for (queue = 0; queue < tx_cnt; queue++) {
403 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
405 if (tx_q->dirty_tx != tx_q->cur_tx)
406 return; /* still unfinished work */
409 /* Check and enter in LPI mode */
410 if (!priv->tx_path_in_lpi_mode)
411 stmmac_set_eee_mode(priv, priv->hw,
412 priv->plat->en_tx_lpi_clockgating);
416 * stmmac_disable_eee_mode - disable and exit from LPI mode
417 * @priv: driver private structure
418 * Description: this function is to exit and disable EEE in case of
419 * LPI state is true. This is called by the xmit.
421 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
423 if (!priv->eee_sw_timer_en) {
424 stmmac_lpi_entry_timer_config(priv, 0);
428 stmmac_reset_eee_mode(priv, priv->hw);
429 del_timer_sync(&priv->eee_ctrl_timer);
430 priv->tx_path_in_lpi_mode = false;
434 * stmmac_eee_ctrl_timer - EEE TX SW timer.
435 * @t: timer_list struct containing private info
437 * if there is no data transfer and if we are not in LPI state,
438 * then MAC Transmitter can be moved to LPI state.
440 static void stmmac_eee_ctrl_timer(struct timer_list *t)
442 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
444 stmmac_enable_eee_mode(priv);
445 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
449 * stmmac_eee_init - init EEE
450 * @priv: driver private structure
452 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
453 * can also manage EEE, this function enable the LPI state and start related
456 bool stmmac_eee_init(struct stmmac_priv *priv)
458 int eee_tw_timer = priv->eee_tw_timer;
460 /* Using PCS we cannot dial with the phy registers at this stage
461 * so we do not support extra feature like EEE.
463 if (priv->hw->pcs == STMMAC_PCS_TBI ||
464 priv->hw->pcs == STMMAC_PCS_RTBI)
467 /* Check if MAC core supports the EEE feature. */
468 if (!priv->dma_cap.eee)
471 mutex_lock(&priv->lock);
473 /* Check if it needs to be deactivated */
474 if (!priv->eee_active) {
475 if (priv->eee_enabled) {
476 netdev_dbg(priv->dev, "disable EEE\n");
477 stmmac_lpi_entry_timer_config(priv, 0);
478 del_timer_sync(&priv->eee_ctrl_timer);
479 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
481 xpcs_config_eee(priv->hw->xpcs,
482 priv->plat->mult_fact_100ns,
485 mutex_unlock(&priv->lock);
489 if (priv->eee_active && !priv->eee_enabled) {
490 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
491 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
494 xpcs_config_eee(priv->hw->xpcs,
495 priv->plat->mult_fact_100ns,
499 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
500 del_timer_sync(&priv->eee_ctrl_timer);
501 priv->tx_path_in_lpi_mode = false;
502 stmmac_lpi_entry_timer_config(priv, 1);
504 stmmac_lpi_entry_timer_config(priv, 0);
505 mod_timer(&priv->eee_ctrl_timer,
506 STMMAC_LPI_T(priv->tx_lpi_timer));
509 mutex_unlock(&priv->lock);
510 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
514 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
515 * @priv: driver private structure
516 * @p : descriptor pointer
517 * @skb : the socket buffer
519 * This function will read timestamp from the descriptor & pass it to stack.
520 * and also perform some sanity checks.
522 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
523 struct dma_desc *p, struct sk_buff *skb)
525 struct skb_shared_hwtstamps shhwtstamp;
530 if (!priv->hwts_tx_en)
533 /* exit if skb doesn't support hw tstamp */
534 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
537 /* check tx tstamp status */
538 if (stmmac_get_tx_timestamp_status(priv, p)) {
539 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
541 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
546 /* Correct the clk domain crossing(CDC) error */
547 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
548 adjust += -(2 * (NSEC_PER_SEC /
549 priv->plat->clk_ptp_rate));
553 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
554 shhwtstamp.hwtstamp = ns_to_ktime(ns);
556 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
557 /* pass tstamp to stack */
558 skb_tstamp_tx(skb, &shhwtstamp);
562 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
563 * @priv: driver private structure
564 * @p : descriptor pointer
565 * @np : next descriptor pointer
566 * @skb : the socket buffer
568 * This function will read received packet's timestamp from the descriptor
569 * and pass it to stack. It also perform some sanity checks.
571 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
572 struct dma_desc *np, struct sk_buff *skb)
574 struct skb_shared_hwtstamps *shhwtstamp = NULL;
575 struct dma_desc *desc = p;
579 if (!priv->hwts_rx_en)
581 /* For GMAC4, the valid timestamp is from CTX next desc. */
582 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
585 /* Check if timestamp is available */
586 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
587 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
589 /* Correct the clk domain crossing(CDC) error */
590 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
591 adjust += 2 * (NSEC_PER_SEC / priv->plat->clk_ptp_rate);
595 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
596 shhwtstamp = skb_hwtstamps(skb);
597 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
598 shhwtstamp->hwtstamp = ns_to_ktime(ns);
600 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
605 * stmmac_hwtstamp_set - control hardware timestamping.
606 * @dev: device pointer.
607 * @ifr: An IOCTL specific structure, that can contain a pointer to
608 * a proprietary structure used to pass information to the driver.
610 * This function configures the MAC to enable/disable both outgoing(TX)
611 * and incoming(RX) packets time stamping based on user input.
613 * 0 on success and an appropriate -ve integer on failure.
615 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
617 struct stmmac_priv *priv = netdev_priv(dev);
618 struct hwtstamp_config config;
619 struct timespec64 now;
623 u32 ptp_over_ipv4_udp = 0;
624 u32 ptp_over_ipv6_udp = 0;
625 u32 ptp_over_ethernet = 0;
626 u32 snap_type_sel = 0;
627 u32 ts_master_en = 0;
633 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
635 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
636 netdev_alert(priv->dev, "No support for HW time stamping\n");
637 priv->hwts_tx_en = 0;
638 priv->hwts_rx_en = 0;
643 if (copy_from_user(&config, ifr->ifr_data,
647 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
648 __func__, config.flags, config.tx_type, config.rx_filter);
650 /* reserved for future extensions */
654 if (config.tx_type != HWTSTAMP_TX_OFF &&
655 config.tx_type != HWTSTAMP_TX_ON)
659 switch (config.rx_filter) {
660 case HWTSTAMP_FILTER_NONE:
661 /* time stamp no incoming packet at all */
662 config.rx_filter = HWTSTAMP_FILTER_NONE;
665 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
666 /* PTP v1, UDP, any kind of event packet */
667 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
668 /* 'xmac' hardware can support Sync, Pdelay_Req and
669 * Pdelay_resp by setting bit14 and bits17/16 to 01
670 * This leaves Delay_Req timestamps out.
671 * Enable all events *and* general purpose message
674 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
675 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
676 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
679 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
680 /* PTP v1, UDP, Sync packet */
681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
682 /* take time stamp for SYNC messages only */
683 ts_event_en = PTP_TCR_TSEVNTENA;
685 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
686 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
689 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
690 /* PTP v1, UDP, Delay_req packet */
691 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
692 /* take time stamp for Delay_Req messages only */
693 ts_master_en = PTP_TCR_TSMSTRENA;
694 ts_event_en = PTP_TCR_TSEVNTENA;
696 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
697 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
700 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
701 /* PTP v2, UDP, any kind of event packet */
702 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
703 ptp_v2 = PTP_TCR_TSVER2ENA;
704 /* take time stamp for all event messages */
705 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
707 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
708 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
711 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
712 /* PTP v2, UDP, Sync packet */
713 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
714 ptp_v2 = PTP_TCR_TSVER2ENA;
715 /* take time stamp for SYNC messages only */
716 ts_event_en = PTP_TCR_TSEVNTENA;
718 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
719 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
722 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
723 /* PTP v2, UDP, Delay_req packet */
724 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
725 ptp_v2 = PTP_TCR_TSVER2ENA;
726 /* take time stamp for Delay_Req messages only */
727 ts_master_en = PTP_TCR_TSMSTRENA;
728 ts_event_en = PTP_TCR_TSEVNTENA;
730 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
731 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
734 case HWTSTAMP_FILTER_PTP_V2_EVENT:
735 /* PTP v2/802.AS1 any layer, any kind of event packet */
736 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
737 ptp_v2 = PTP_TCR_TSVER2ENA;
738 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
739 if (priv->synopsys_id != DWMAC_CORE_5_10)
740 ts_event_en = PTP_TCR_TSEVNTENA;
741 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
742 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
743 ptp_over_ethernet = PTP_TCR_TSIPENA;
746 case HWTSTAMP_FILTER_PTP_V2_SYNC:
747 /* PTP v2/802.AS1, any layer, Sync packet */
748 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
749 ptp_v2 = PTP_TCR_TSVER2ENA;
750 /* take time stamp for SYNC messages only */
751 ts_event_en = PTP_TCR_TSEVNTENA;
753 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
754 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
755 ptp_over_ethernet = PTP_TCR_TSIPENA;
758 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
759 /* PTP v2/802.AS1, any layer, Delay_req packet */
760 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
761 ptp_v2 = PTP_TCR_TSVER2ENA;
762 /* take time stamp for Delay_Req messages only */
763 ts_master_en = PTP_TCR_TSMSTRENA;
764 ts_event_en = PTP_TCR_TSEVNTENA;
766 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
767 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
768 ptp_over_ethernet = PTP_TCR_TSIPENA;
771 case HWTSTAMP_FILTER_NTP_ALL:
772 case HWTSTAMP_FILTER_ALL:
773 /* time stamp any incoming packet */
774 config.rx_filter = HWTSTAMP_FILTER_ALL;
775 tstamp_all = PTP_TCR_TSENALL;
782 switch (config.rx_filter) {
783 case HWTSTAMP_FILTER_NONE:
784 config.rx_filter = HWTSTAMP_FILTER_NONE;
787 /* PTP v1, UDP, any kind of event packet */
788 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
792 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
793 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
795 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
796 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
798 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
799 tstamp_all | ptp_v2 | ptp_over_ethernet |
800 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
801 ts_master_en | snap_type_sel);
802 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
804 /* program Sub Second Increment reg */
805 stmmac_config_sub_second_increment(priv,
806 priv->ptpaddr, priv->plat->clk_ptp_rate,
808 temp = div_u64(1000000000ULL, sec_inc);
810 /* Store sub second increment and flags for later use */
811 priv->sub_second_inc = sec_inc;
812 priv->systime_flags = value;
814 /* calculate default added value:
816 * addend = (2^32)/freq_div_ratio;
817 * where, freq_div_ratio = 1e9ns/sec_inc
819 temp = (u64)(temp << 32);
820 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
821 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
823 /* initialize system time */
824 ktime_get_real_ts64(&now);
826 /* lower 32 bits of tv_sec are safe until y2106 */
827 stmmac_init_systime(priv, priv->ptpaddr,
828 (u32)now.tv_sec, now.tv_nsec);
831 memcpy(&priv->tstamp_config, &config, sizeof(config));
833 return copy_to_user(ifr->ifr_data, &config,
834 sizeof(config)) ? -EFAULT : 0;
838 * stmmac_hwtstamp_get - read hardware timestamping.
839 * @dev: device pointer.
840 * @ifr: An IOCTL specific structure, that can contain a pointer to
841 * a proprietary structure used to pass information to the driver.
843 * This function obtain the current hardware timestamping settings
846 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
848 struct stmmac_priv *priv = netdev_priv(dev);
849 struct hwtstamp_config *config = &priv->tstamp_config;
851 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
854 return copy_to_user(ifr->ifr_data, config,
855 sizeof(*config)) ? -EFAULT : 0;
859 * stmmac_init_ptp - init PTP
860 * @priv: driver private structure
861 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
862 * This is done by looking at the HW cap. register.
863 * This function also registers the ptp driver.
865 static int stmmac_init_ptp(struct stmmac_priv *priv)
867 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
869 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
873 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
874 if (xmac && priv->dma_cap.atime_stamp)
876 /* Dwmac 3.x core with extend_desc can support adv_ts */
877 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
880 if (priv->dma_cap.time_stamp)
881 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
884 netdev_info(priv->dev,
885 "IEEE 1588-2008 Advanced Timestamp supported\n");
887 priv->hwts_tx_en = 0;
888 priv->hwts_rx_en = 0;
890 stmmac_ptp_register(priv);
895 static void stmmac_release_ptp(struct stmmac_priv *priv)
897 clk_disable_unprepare(priv->plat->clk_ptp_ref);
898 stmmac_ptp_unregister(priv);
902 * stmmac_mac_flow_ctrl - Configure flow control in all queues
903 * @priv: driver private structure
904 * @duplex: duplex passed to the next function
905 * Description: It is used for configuring the flow control in all queues
907 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
909 u32 tx_cnt = priv->plat->tx_queues_to_use;
911 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
912 priv->pause, tx_cnt);
915 static void stmmac_validate(struct phylink_config *config,
916 unsigned long *supported,
917 struct phylink_link_state *state)
919 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
920 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
921 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
922 int tx_cnt = priv->plat->tx_queues_to_use;
923 int max_speed = priv->plat->max_speed;
925 phylink_set(mac_supported, 10baseT_Half);
926 phylink_set(mac_supported, 10baseT_Full);
927 phylink_set(mac_supported, 100baseT_Half);
928 phylink_set(mac_supported, 100baseT_Full);
929 phylink_set(mac_supported, 1000baseT_Half);
930 phylink_set(mac_supported, 1000baseT_Full);
931 phylink_set(mac_supported, 1000baseKX_Full);
933 phylink_set(mac_supported, Autoneg);
934 phylink_set(mac_supported, Pause);
935 phylink_set(mac_supported, Asym_Pause);
936 phylink_set_port_modes(mac_supported);
938 /* Cut down 1G if asked to */
939 if ((max_speed > 0) && (max_speed < 1000)) {
940 phylink_set(mask, 1000baseT_Full);
941 phylink_set(mask, 1000baseX_Full);
942 } else if (priv->plat->has_gmac4) {
943 if (!max_speed || max_speed >= 2500) {
944 phylink_set(mac_supported, 2500baseT_Full);
945 phylink_set(mac_supported, 2500baseX_Full);
947 } else if (priv->plat->has_xgmac) {
948 if (!max_speed || (max_speed >= 2500)) {
949 phylink_set(mac_supported, 2500baseT_Full);
950 phylink_set(mac_supported, 2500baseX_Full);
952 if (!max_speed || (max_speed >= 5000)) {
953 phylink_set(mac_supported, 5000baseT_Full);
955 if (!max_speed || (max_speed >= 10000)) {
956 phylink_set(mac_supported, 10000baseSR_Full);
957 phylink_set(mac_supported, 10000baseLR_Full);
958 phylink_set(mac_supported, 10000baseER_Full);
959 phylink_set(mac_supported, 10000baseLRM_Full);
960 phylink_set(mac_supported, 10000baseT_Full);
961 phylink_set(mac_supported, 10000baseKX4_Full);
962 phylink_set(mac_supported, 10000baseKR_Full);
964 if (!max_speed || (max_speed >= 25000)) {
965 phylink_set(mac_supported, 25000baseCR_Full);
966 phylink_set(mac_supported, 25000baseKR_Full);
967 phylink_set(mac_supported, 25000baseSR_Full);
969 if (!max_speed || (max_speed >= 40000)) {
970 phylink_set(mac_supported, 40000baseKR4_Full);
971 phylink_set(mac_supported, 40000baseCR4_Full);
972 phylink_set(mac_supported, 40000baseSR4_Full);
973 phylink_set(mac_supported, 40000baseLR4_Full);
975 if (!max_speed || (max_speed >= 50000)) {
976 phylink_set(mac_supported, 50000baseCR2_Full);
977 phylink_set(mac_supported, 50000baseKR2_Full);
978 phylink_set(mac_supported, 50000baseSR2_Full);
979 phylink_set(mac_supported, 50000baseKR_Full);
980 phylink_set(mac_supported, 50000baseSR_Full);
981 phylink_set(mac_supported, 50000baseCR_Full);
982 phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
983 phylink_set(mac_supported, 50000baseDR_Full);
985 if (!max_speed || (max_speed >= 100000)) {
986 phylink_set(mac_supported, 100000baseKR4_Full);
987 phylink_set(mac_supported, 100000baseSR4_Full);
988 phylink_set(mac_supported, 100000baseCR4_Full);
989 phylink_set(mac_supported, 100000baseLR4_ER4_Full);
990 phylink_set(mac_supported, 100000baseKR2_Full);
991 phylink_set(mac_supported, 100000baseSR2_Full);
992 phylink_set(mac_supported, 100000baseCR2_Full);
993 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
994 phylink_set(mac_supported, 100000baseDR2_Full);
998 /* Half-Duplex can only work with single queue */
1000 phylink_set(mask, 10baseT_Half);
1001 phylink_set(mask, 100baseT_Half);
1002 phylink_set(mask, 1000baseT_Half);
1005 linkmode_and(supported, supported, mac_supported);
1006 linkmode_andnot(supported, supported, mask);
1008 linkmode_and(state->advertising, state->advertising, mac_supported);
1009 linkmode_andnot(state->advertising, state->advertising, mask);
1011 /* If PCS is supported, check which modes it supports. */
1013 xpcs_validate(priv->hw->xpcs, supported, state);
1016 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
1017 const struct phylink_link_state *state)
1019 /* Nothing to do, xpcs_config() handles everything */
1022 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
1024 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
1025 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
1026 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
1027 bool *hs_enable = &fpe_cfg->hs_enable;
1029 if (is_up && *hs_enable) {
1030 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
1032 *lo_state = FPE_STATE_OFF;
1033 *lp_state = FPE_STATE_OFF;
1037 static void stmmac_mac_link_down(struct phylink_config *config,
1038 unsigned int mode, phy_interface_t interface)
1040 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1042 stmmac_mac_set(priv, priv->ioaddr, false);
1043 priv->eee_active = false;
1044 priv->tx_lpi_enabled = false;
1045 priv->eee_enabled = stmmac_eee_init(priv);
1046 stmmac_set_eee_pls(priv, priv->hw, false);
1048 if (priv->dma_cap.fpesel)
1049 stmmac_fpe_link_state_handle(priv, false);
1052 static void stmmac_mac_link_up(struct phylink_config *config,
1053 struct phy_device *phy,
1054 unsigned int mode, phy_interface_t interface,
1055 int speed, int duplex,
1056 bool tx_pause, bool rx_pause)
1058 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1061 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
1062 ctrl &= ~priv->hw->link.speed_mask;
1064 if (interface == PHY_INTERFACE_MODE_USXGMII) {
1067 ctrl |= priv->hw->link.xgmii.speed10000;
1070 ctrl |= priv->hw->link.xgmii.speed5000;
1073 ctrl |= priv->hw->link.xgmii.speed2500;
1078 } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1081 ctrl |= priv->hw->link.xlgmii.speed100000;
1084 ctrl |= priv->hw->link.xlgmii.speed50000;
1087 ctrl |= priv->hw->link.xlgmii.speed40000;
1090 ctrl |= priv->hw->link.xlgmii.speed25000;
1093 ctrl |= priv->hw->link.xgmii.speed10000;
1096 ctrl |= priv->hw->link.speed2500;
1099 ctrl |= priv->hw->link.speed1000;
1107 ctrl |= priv->hw->link.speed2500;
1110 ctrl |= priv->hw->link.speed1000;
1113 ctrl |= priv->hw->link.speed100;
1116 ctrl |= priv->hw->link.speed10;
1123 priv->speed = speed;
1125 if (priv->plat->fix_mac_speed)
1126 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1129 ctrl &= ~priv->hw->link.duplex;
1131 ctrl |= priv->hw->link.duplex;
1133 /* Flow Control operation */
1134 if (tx_pause && rx_pause)
1135 stmmac_mac_flow_ctrl(priv, duplex);
1137 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1139 stmmac_mac_set(priv, priv->ioaddr, true);
1140 if (phy && priv->dma_cap.eee) {
1141 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1142 priv->eee_enabled = stmmac_eee_init(priv);
1143 priv->tx_lpi_enabled = priv->eee_enabled;
1144 stmmac_set_eee_pls(priv, priv->hw, true);
1147 if (priv->dma_cap.fpesel)
1148 stmmac_fpe_link_state_handle(priv, true);
1151 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1152 .validate = stmmac_validate,
1153 .mac_config = stmmac_mac_config,
1154 .mac_link_down = stmmac_mac_link_down,
1155 .mac_link_up = stmmac_mac_link_up,
1159 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1160 * @priv: driver private structure
1161 * Description: this is to verify if the HW supports the PCS.
1162 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1163 * configured for the TBI, RTBI, or SGMII PHY interface.
1165 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1167 int interface = priv->plat->interface;
1169 if (priv->dma_cap.pcs) {
1170 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1171 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1172 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1173 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1174 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1175 priv->hw->pcs = STMMAC_PCS_RGMII;
1176 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1177 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1178 priv->hw->pcs = STMMAC_PCS_SGMII;
1184 * stmmac_init_phy - PHY initialization
1185 * @dev: net device structure
1186 * Description: it initializes the driver's PHY state, and attaches the PHY
1187 * to the mac driver.
1191 static int stmmac_init_phy(struct net_device *dev)
1193 struct stmmac_priv *priv = netdev_priv(dev);
1194 struct device_node *node;
1197 node = priv->plat->phylink_node;
1200 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1202 /* Some DT bindings do not set-up the PHY handle. Let's try to
1206 int addr = priv->plat->phy_addr;
1207 struct phy_device *phydev;
1209 phydev = mdiobus_get_phy(priv->mii, addr);
1211 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1215 ret = phylink_connect_phy(priv->phylink, phydev);
1218 if (!priv->plat->pmt) {
1219 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1221 phylink_ethtool_get_wol(priv->phylink, &wol);
1222 device_set_wakeup_capable(priv->device, !!wol.supported);
1228 static int stmmac_phy_setup(struct stmmac_priv *priv)
1230 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1231 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1232 int mode = priv->plat->phy_interface;
1233 struct phylink *phylink;
1235 priv->phylink_config.dev = &priv->dev->dev;
1236 priv->phylink_config.type = PHYLINK_NETDEV;
1237 priv->phylink_config.pcs_poll = true;
1238 if (priv->plat->mdio_bus_data)
1239 priv->phylink_config.ovr_an_inband =
1240 mdio_bus_data->xpcs_an_inband;
1243 fwnode = dev_fwnode(priv->device);
1245 phylink = phylink_create(&priv->phylink_config, fwnode,
1246 mode, &stmmac_phylink_mac_ops);
1247 if (IS_ERR(phylink))
1248 return PTR_ERR(phylink);
1251 phylink_set_pcs(phylink, &priv->hw->xpcs->pcs);
1253 priv->phylink = phylink;
1257 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1259 u32 rx_cnt = priv->plat->rx_queues_to_use;
1260 unsigned int desc_size;
1264 /* Display RX rings */
1265 for (queue = 0; queue < rx_cnt; queue++) {
1266 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1268 pr_info("\tRX Queue %u rings\n", queue);
1270 if (priv->extend_desc) {
1271 head_rx = (void *)rx_q->dma_erx;
1272 desc_size = sizeof(struct dma_extended_desc);
1274 head_rx = (void *)rx_q->dma_rx;
1275 desc_size = sizeof(struct dma_desc);
1278 /* Display RX ring */
1279 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
1280 rx_q->dma_rx_phy, desc_size);
1284 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1286 u32 tx_cnt = priv->plat->tx_queues_to_use;
1287 unsigned int desc_size;
1291 /* Display TX rings */
1292 for (queue = 0; queue < tx_cnt; queue++) {
1293 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1295 pr_info("\tTX Queue %d rings\n", queue);
1297 if (priv->extend_desc) {
1298 head_tx = (void *)tx_q->dma_etx;
1299 desc_size = sizeof(struct dma_extended_desc);
1300 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1301 head_tx = (void *)tx_q->dma_entx;
1302 desc_size = sizeof(struct dma_edesc);
1304 head_tx = (void *)tx_q->dma_tx;
1305 desc_size = sizeof(struct dma_desc);
1308 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
1309 tx_q->dma_tx_phy, desc_size);
1313 static void stmmac_display_rings(struct stmmac_priv *priv)
1315 /* Display RX ring */
1316 stmmac_display_rx_rings(priv);
1318 /* Display TX ring */
1319 stmmac_display_tx_rings(priv);
1322 static int stmmac_set_bfsize(int mtu, int bufsize)
1326 if (mtu >= BUF_SIZE_8KiB)
1327 ret = BUF_SIZE_16KiB;
1328 else if (mtu >= BUF_SIZE_4KiB)
1329 ret = BUF_SIZE_8KiB;
1330 else if (mtu >= BUF_SIZE_2KiB)
1331 ret = BUF_SIZE_4KiB;
1332 else if (mtu > DEFAULT_BUFSIZE)
1333 ret = BUF_SIZE_2KiB;
1335 ret = DEFAULT_BUFSIZE;
1341 * stmmac_clear_rx_descriptors - clear RX descriptors
1342 * @priv: driver private structure
1343 * @queue: RX queue index
1344 * Description: this function is called to clear the RX descriptors
1345 * in case of both basic and extended descriptors are used.
1347 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1349 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1352 /* Clear the RX descriptors */
1353 for (i = 0; i < priv->dma_rx_size; i++)
1354 if (priv->extend_desc)
1355 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1356 priv->use_riwt, priv->mode,
1357 (i == priv->dma_rx_size - 1),
1360 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1361 priv->use_riwt, priv->mode,
1362 (i == priv->dma_rx_size - 1),
1367 * stmmac_clear_tx_descriptors - clear tx descriptors
1368 * @priv: driver private structure
1369 * @queue: TX queue index.
1370 * Description: this function is called to clear the TX descriptors
1371 * in case of both basic and extended descriptors are used.
1373 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1375 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1378 /* Clear the TX descriptors */
1379 for (i = 0; i < priv->dma_tx_size; i++) {
1380 int last = (i == (priv->dma_tx_size - 1));
1383 if (priv->extend_desc)
1384 p = &tx_q->dma_etx[i].basic;
1385 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1386 p = &tx_q->dma_entx[i].basic;
1388 p = &tx_q->dma_tx[i];
1390 stmmac_init_tx_desc(priv, p, priv->mode, last);
1395 * stmmac_clear_descriptors - clear descriptors
1396 * @priv: driver private structure
1397 * Description: this function is called to clear the TX and RX descriptors
1398 * in case of both basic and extended descriptors are used.
1400 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1402 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1403 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1406 /* Clear the RX descriptors */
1407 for (queue = 0; queue < rx_queue_cnt; queue++)
1408 stmmac_clear_rx_descriptors(priv, queue);
1410 /* Clear the TX descriptors */
1411 for (queue = 0; queue < tx_queue_cnt; queue++)
1412 stmmac_clear_tx_descriptors(priv, queue);
1416 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1417 * @priv: driver private structure
1418 * @p: descriptor pointer
1419 * @i: descriptor index
1421 * @queue: RX queue index
1422 * Description: this function is called to allocate a receive buffer, perform
1423 * the DMA mapping and init the descriptor.
1425 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1426 int i, gfp_t flags, u32 queue)
1428 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1429 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1432 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1435 buf->page_offset = stmmac_rx_offset(priv);
1438 if (priv->sph && !buf->sec_page) {
1439 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1443 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1444 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1446 buf->sec_page = NULL;
1447 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1450 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1452 stmmac_set_desc_addr(priv, p, buf->addr);
1453 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1454 stmmac_init_desc3(priv, p);
1460 * stmmac_free_rx_buffer - free RX dma buffers
1461 * @priv: private structure
1462 * @queue: RX queue index
1465 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1467 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1468 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1471 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1475 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1476 buf->sec_page = NULL;
1480 * stmmac_free_tx_buffer - free RX dma buffers
1481 * @priv: private structure
1482 * @queue: RX queue index
1485 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1487 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1489 if (tx_q->tx_skbuff_dma[i].buf &&
1490 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1491 if (tx_q->tx_skbuff_dma[i].map_as_page)
1492 dma_unmap_page(priv->device,
1493 tx_q->tx_skbuff_dma[i].buf,
1494 tx_q->tx_skbuff_dma[i].len,
1497 dma_unmap_single(priv->device,
1498 tx_q->tx_skbuff_dma[i].buf,
1499 tx_q->tx_skbuff_dma[i].len,
1503 if (tx_q->xdpf[i] &&
1504 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1505 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1506 xdp_return_frame(tx_q->xdpf[i]);
1507 tx_q->xdpf[i] = NULL;
1510 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1511 tx_q->xsk_frames_done++;
1513 if (tx_q->tx_skbuff[i] &&
1514 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1515 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1516 tx_q->tx_skbuff[i] = NULL;
1519 tx_q->tx_skbuff_dma[i].buf = 0;
1520 tx_q->tx_skbuff_dma[i].map_as_page = false;
1524 * dma_free_rx_skbufs - free RX dma buffers
1525 * @priv: private structure
1526 * @queue: RX queue index
1528 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1532 for (i = 0; i < priv->dma_rx_size; i++)
1533 stmmac_free_rx_buffer(priv, queue, i);
1536 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
1539 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1542 for (i = 0; i < priv->dma_rx_size; i++) {
1546 if (priv->extend_desc)
1547 p = &((rx_q->dma_erx + i)->basic);
1549 p = rx_q->dma_rx + i;
1551 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1556 rx_q->buf_alloc_num++;
1563 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1564 * @priv: private structure
1565 * @queue: RX queue index
1567 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
1569 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1572 for (i = 0; i < priv->dma_rx_size; i++) {
1573 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1578 xsk_buff_free(buf->xdp);
1583 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
1585 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1588 for (i = 0; i < priv->dma_rx_size; i++) {
1589 struct stmmac_rx_buffer *buf;
1590 dma_addr_t dma_addr;
1593 if (priv->extend_desc)
1594 p = (struct dma_desc *)(rx_q->dma_erx + i);
1596 p = rx_q->dma_rx + i;
1598 buf = &rx_q->buf_pool[i];
1600 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1604 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1605 stmmac_set_desc_addr(priv, p, dma_addr);
1606 rx_q->buf_alloc_num++;
1612 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1614 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1617 return xsk_get_pool_from_qid(priv->dev, queue);
1621 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1622 * @priv: driver private structure
1623 * @queue: RX queue index
1625 * Description: this function initializes the DMA RX descriptors
1626 * and allocates the socket buffers. It supports the chained and ring
1629 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
1631 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1634 netif_dbg(priv, probe, priv->dev,
1635 "(%s) dma_rx_phy=0x%08x\n", __func__,
1636 (u32)rx_q->dma_rx_phy);
1638 stmmac_clear_rx_descriptors(priv, queue);
1640 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1642 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1644 if (rx_q->xsk_pool) {
1645 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1646 MEM_TYPE_XSK_BUFF_POOL,
1648 netdev_info(priv->dev,
1649 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1651 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1653 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1656 netdev_info(priv->dev,
1657 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1661 if (rx_q->xsk_pool) {
1662 /* RX XDP ZC buffer pool may not be populated, e.g.
1665 stmmac_alloc_rx_buffers_zc(priv, queue);
1667 ret = stmmac_alloc_rx_buffers(priv, queue, flags);
1675 /* Setup the chained descriptor addresses */
1676 if (priv->mode == STMMAC_CHAIN_MODE) {
1677 if (priv->extend_desc)
1678 stmmac_mode_init(priv, rx_q->dma_erx,
1680 priv->dma_rx_size, 1);
1682 stmmac_mode_init(priv, rx_q->dma_rx,
1684 priv->dma_rx_size, 0);
1690 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1692 struct stmmac_priv *priv = netdev_priv(dev);
1693 u32 rx_count = priv->plat->rx_queues_to_use;
1697 /* RX INITIALIZATION */
1698 netif_dbg(priv, probe, priv->dev,
1699 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1701 for (queue = 0; queue < rx_count; queue++) {
1702 ret = __init_dma_rx_desc_rings(priv, queue, flags);
1704 goto err_init_rx_buffers;
1709 err_init_rx_buffers:
1710 while (queue >= 0) {
1711 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1714 dma_free_rx_xskbufs(priv, queue);
1716 dma_free_rx_skbufs(priv, queue);
1718 rx_q->buf_alloc_num = 0;
1719 rx_q->xsk_pool = NULL;
1731 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1732 * @priv: driver private structure
1733 * @queue : TX queue index
1734 * Description: this function initializes the DMA TX descriptors
1735 * and allocates the socket buffers. It supports the chained and ring
1738 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
1740 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1743 netif_dbg(priv, probe, priv->dev,
1744 "(%s) dma_tx_phy=0x%08x\n", __func__,
1745 (u32)tx_q->dma_tx_phy);
1747 /* Setup the chained descriptor addresses */
1748 if (priv->mode == STMMAC_CHAIN_MODE) {
1749 if (priv->extend_desc)
1750 stmmac_mode_init(priv, tx_q->dma_etx,
1752 priv->dma_tx_size, 1);
1753 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1754 stmmac_mode_init(priv, tx_q->dma_tx,
1756 priv->dma_tx_size, 0);
1759 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1761 for (i = 0; i < priv->dma_tx_size; i++) {
1764 if (priv->extend_desc)
1765 p = &((tx_q->dma_etx + i)->basic);
1766 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1767 p = &((tx_q->dma_entx + i)->basic);
1769 p = tx_q->dma_tx + i;
1771 stmmac_clear_desc(priv, p);
1773 tx_q->tx_skbuff_dma[i].buf = 0;
1774 tx_q->tx_skbuff_dma[i].map_as_page = false;
1775 tx_q->tx_skbuff_dma[i].len = 0;
1776 tx_q->tx_skbuff_dma[i].last_segment = false;
1777 tx_q->tx_skbuff[i] = NULL;
1784 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1789 static int init_dma_tx_desc_rings(struct net_device *dev)
1791 struct stmmac_priv *priv = netdev_priv(dev);
1795 tx_queue_cnt = priv->plat->tx_queues_to_use;
1797 for (queue = 0; queue < tx_queue_cnt; queue++)
1798 __init_dma_tx_desc_rings(priv, queue);
1804 * init_dma_desc_rings - init the RX/TX descriptor rings
1805 * @dev: net device structure
1807 * Description: this function initializes the DMA RX/TX descriptors
1808 * and allocates the socket buffers. It supports the chained and ring
1811 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1813 struct stmmac_priv *priv = netdev_priv(dev);
1816 ret = init_dma_rx_desc_rings(dev, flags);
1820 ret = init_dma_tx_desc_rings(dev);
1822 stmmac_clear_descriptors(priv);
1824 if (netif_msg_hw(priv))
1825 stmmac_display_rings(priv);
1831 * dma_free_tx_skbufs - free TX dma buffers
1832 * @priv: private structure
1833 * @queue: TX queue index
1835 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1837 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1840 tx_q->xsk_frames_done = 0;
1842 for (i = 0; i < priv->dma_tx_size; i++)
1843 stmmac_free_tx_buffer(priv, queue, i);
1845 if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1846 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1847 tx_q->xsk_frames_done = 0;
1848 tx_q->xsk_pool = NULL;
1853 * stmmac_free_tx_skbufs - free TX skb buffers
1854 * @priv: private structure
1856 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1858 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1861 for (queue = 0; queue < tx_queue_cnt; queue++)
1862 dma_free_tx_skbufs(priv, queue);
1866 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1867 * @priv: private structure
1868 * @queue: RX queue index
1870 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1872 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1874 /* Release the DMA RX socket buffers */
1876 dma_free_rx_xskbufs(priv, queue);
1878 dma_free_rx_skbufs(priv, queue);
1880 rx_q->buf_alloc_num = 0;
1881 rx_q->xsk_pool = NULL;
1883 /* Free DMA regions of consistent memory previously allocated */
1884 if (!priv->extend_desc)
1885 dma_free_coherent(priv->device, priv->dma_rx_size *
1886 sizeof(struct dma_desc),
1887 rx_q->dma_rx, rx_q->dma_rx_phy);
1889 dma_free_coherent(priv->device, priv->dma_rx_size *
1890 sizeof(struct dma_extended_desc),
1891 rx_q->dma_erx, rx_q->dma_rx_phy);
1893 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1894 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1896 kfree(rx_q->buf_pool);
1897 if (rx_q->page_pool)
1898 page_pool_destroy(rx_q->page_pool);
1901 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1903 u32 rx_count = priv->plat->rx_queues_to_use;
1906 /* Free RX queue resources */
1907 for (queue = 0; queue < rx_count; queue++)
1908 __free_dma_rx_desc_resources(priv, queue);
1912 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1913 * @priv: private structure
1914 * @queue: TX queue index
1916 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
1918 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1922 /* Release the DMA TX socket buffers */
1923 dma_free_tx_skbufs(priv, queue);
1925 if (priv->extend_desc) {
1926 size = sizeof(struct dma_extended_desc);
1927 addr = tx_q->dma_etx;
1928 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1929 size = sizeof(struct dma_edesc);
1930 addr = tx_q->dma_entx;
1932 size = sizeof(struct dma_desc);
1933 addr = tx_q->dma_tx;
1936 size *= priv->dma_tx_size;
1938 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1940 kfree(tx_q->tx_skbuff_dma);
1941 kfree(tx_q->tx_skbuff);
1944 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1946 u32 tx_count = priv->plat->tx_queues_to_use;
1949 /* Free TX queue resources */
1950 for (queue = 0; queue < tx_count; queue++)
1951 __free_dma_tx_desc_resources(priv, queue);
1955 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
1956 * @priv: private structure
1957 * @queue: RX queue index
1958 * Description: according to which descriptor can be used (extend or basic)
1959 * this function allocates the resources for TX and RX paths. In case of
1960 * reception, for example, it pre-allocated the RX socket buffer in order to
1961 * allow zero-copy mechanism.
1963 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1965 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1966 struct stmmac_channel *ch = &priv->channel[queue];
1967 bool xdp_prog = stmmac_xdp_is_enabled(priv);
1968 struct page_pool_params pp_params = { 0 };
1969 unsigned int num_pages;
1970 unsigned int napi_id;
1973 rx_q->queue_index = queue;
1974 rx_q->priv_data = priv;
1976 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
1977 pp_params.pool_size = priv->dma_rx_size;
1978 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1979 pp_params.order = ilog2(num_pages);
1980 pp_params.nid = dev_to_node(priv->device);
1981 pp_params.dev = priv->device;
1982 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
1983 pp_params.offset = stmmac_rx_offset(priv);
1984 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
1986 rx_q->page_pool = page_pool_create(&pp_params);
1987 if (IS_ERR(rx_q->page_pool)) {
1988 ret = PTR_ERR(rx_q->page_pool);
1989 rx_q->page_pool = NULL;
1993 rx_q->buf_pool = kcalloc(priv->dma_rx_size,
1994 sizeof(*rx_q->buf_pool),
1996 if (!rx_q->buf_pool)
1999 if (priv->extend_desc) {
2000 rx_q->dma_erx = dma_alloc_coherent(priv->device,
2002 sizeof(struct dma_extended_desc),
2009 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2011 sizeof(struct dma_desc),
2018 if (stmmac_xdp_is_enabled(priv) &&
2019 test_bit(queue, priv->af_xdp_zc_qps))
2020 napi_id = ch->rxtx_napi.napi_id;
2022 napi_id = ch->rx_napi.napi_id;
2024 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2028 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2035 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
2037 u32 rx_count = priv->plat->rx_queues_to_use;
2041 /* RX queues buffers and DMA */
2042 for (queue = 0; queue < rx_count; queue++) {
2043 ret = __alloc_dma_rx_desc_resources(priv, queue);
2051 free_dma_rx_desc_resources(priv);
2057 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2058 * @priv: private structure
2059 * @queue: TX queue index
2060 * Description: according to which descriptor can be used (extend or basic)
2061 * this function allocates the resources for TX and RX paths. In case of
2062 * reception, for example, it pre-allocated the RX socket buffer in order to
2063 * allow zero-copy mechanism.
2065 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
2067 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2071 tx_q->queue_index = queue;
2072 tx_q->priv_data = priv;
2074 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
2075 sizeof(*tx_q->tx_skbuff_dma),
2077 if (!tx_q->tx_skbuff_dma)
2080 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
2081 sizeof(struct sk_buff *),
2083 if (!tx_q->tx_skbuff)
2086 if (priv->extend_desc)
2087 size = sizeof(struct dma_extended_desc);
2088 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2089 size = sizeof(struct dma_edesc);
2091 size = sizeof(struct dma_desc);
2093 size *= priv->dma_tx_size;
2095 addr = dma_alloc_coherent(priv->device, size,
2096 &tx_q->dma_tx_phy, GFP_KERNEL);
2100 if (priv->extend_desc)
2101 tx_q->dma_etx = addr;
2102 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2103 tx_q->dma_entx = addr;
2105 tx_q->dma_tx = addr;
2110 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
2112 u32 tx_count = priv->plat->tx_queues_to_use;
2116 /* TX queues buffers and DMA */
2117 for (queue = 0; queue < tx_count; queue++) {
2118 ret = __alloc_dma_tx_desc_resources(priv, queue);
2126 free_dma_tx_desc_resources(priv);
2131 * alloc_dma_desc_resources - alloc TX/RX resources.
2132 * @priv: private structure
2133 * Description: according to which descriptor can be used (extend or basic)
2134 * this function allocates the resources for TX and RX paths. In case of
2135 * reception, for example, it pre-allocated the RX socket buffer in order to
2136 * allow zero-copy mechanism.
2138 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
2141 int ret = alloc_dma_rx_desc_resources(priv);
2146 ret = alloc_dma_tx_desc_resources(priv);
2152 * free_dma_desc_resources - free dma desc resources
2153 * @priv: private structure
2155 static void free_dma_desc_resources(struct stmmac_priv *priv)
2157 /* Release the DMA TX socket buffers */
2158 free_dma_tx_desc_resources(priv);
2160 /* Release the DMA RX socket buffers later
2161 * to ensure all pending XDP_TX buffers are returned.
2163 free_dma_rx_desc_resources(priv);
2167 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
2168 * @priv: driver private structure
2169 * Description: It is used for enabling the rx queues in the MAC
2171 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2173 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2177 for (queue = 0; queue < rx_queues_count; queue++) {
2178 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2179 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2184 * stmmac_start_rx_dma - start RX DMA channel
2185 * @priv: driver private structure
2186 * @chan: RX channel index
2188 * This starts a RX DMA channel
2190 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2192 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2193 stmmac_start_rx(priv, priv->ioaddr, chan);
2197 * stmmac_start_tx_dma - start TX DMA channel
2198 * @priv: driver private structure
2199 * @chan: TX channel index
2201 * This starts a TX DMA channel
2203 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2205 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2206 stmmac_start_tx(priv, priv->ioaddr, chan);
2210 * stmmac_stop_rx_dma - stop RX DMA channel
2211 * @priv: driver private structure
2212 * @chan: RX channel index
2214 * This stops a RX DMA channel
2216 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2218 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2219 stmmac_stop_rx(priv, priv->ioaddr, chan);
2223 * stmmac_stop_tx_dma - stop TX DMA channel
2224 * @priv: driver private structure
2225 * @chan: TX channel index
2227 * This stops a TX DMA channel
2229 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2231 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2232 stmmac_stop_tx(priv, priv->ioaddr, chan);
2236 * stmmac_start_all_dma - start all RX and TX DMA channels
2237 * @priv: driver private structure
2239 * This starts all the RX and TX DMA channels
2241 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2243 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2244 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2247 for (chan = 0; chan < rx_channels_count; chan++)
2248 stmmac_start_rx_dma(priv, chan);
2250 for (chan = 0; chan < tx_channels_count; chan++)
2251 stmmac_start_tx_dma(priv, chan);
2255 * stmmac_stop_all_dma - stop all RX and TX DMA channels
2256 * @priv: driver private structure
2258 * This stops the RX and TX DMA channels
2260 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2262 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2263 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2266 for (chan = 0; chan < rx_channels_count; chan++)
2267 stmmac_stop_rx_dma(priv, chan);
2269 for (chan = 0; chan < tx_channels_count; chan++)
2270 stmmac_stop_tx_dma(priv, chan);
2274 * stmmac_dma_operation_mode - HW DMA operation mode
2275 * @priv: driver private structure
2276 * Description: it is used for configuring the DMA operation mode register in
2277 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2279 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2281 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2282 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2283 int rxfifosz = priv->plat->rx_fifo_size;
2284 int txfifosz = priv->plat->tx_fifo_size;
2291 rxfifosz = priv->dma_cap.rx_fifo_size;
2293 txfifosz = priv->dma_cap.tx_fifo_size;
2295 /* Adjust for real per queue fifo size */
2296 rxfifosz /= rx_channels_count;
2297 txfifosz /= tx_channels_count;
2299 if (priv->plat->force_thresh_dma_mode) {
2302 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2304 * In case of GMAC, SF mode can be enabled
2305 * to perform the TX COE in HW. This depends on:
2306 * 1) TX COE if actually supported
2307 * 2) There is no bugged Jumbo frame support
2308 * that needs to not insert csum in the TDES.
2310 txmode = SF_DMA_MODE;
2311 rxmode = SF_DMA_MODE;
2312 priv->xstats.threshold = SF_DMA_MODE;
2315 rxmode = SF_DMA_MODE;
2318 /* configure all channels */
2319 for (chan = 0; chan < rx_channels_count; chan++) {
2320 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2323 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2325 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2328 if (rx_q->xsk_pool) {
2329 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2330 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2334 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2340 for (chan = 0; chan < tx_channels_count; chan++) {
2341 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2343 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2348 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2350 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2352 struct xsk_buff_pool *pool = tx_q->xsk_pool;
2353 unsigned int entry = tx_q->cur_tx;
2354 struct dma_desc *tx_desc = NULL;
2355 struct xdp_desc xdp_desc;
2356 bool work_done = true;
2358 /* Avoids TX time-out as we are sharing with slow path */
2359 nq->trans_start = jiffies;
2361 budget = min(budget, stmmac_tx_avail(priv, queue));
2363 while (budget-- > 0) {
2364 dma_addr_t dma_addr;
2367 /* We are sharing with slow path and stop XSK TX desc submission when
2368 * available TX ring is less than threshold.
2370 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2371 !netif_carrier_ok(priv->dev)) {
2376 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2379 if (likely(priv->extend_desc))
2380 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2381 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2382 tx_desc = &tx_q->dma_entx[entry].basic;
2384 tx_desc = tx_q->dma_tx + entry;
2386 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2387 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2389 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2391 /* To return XDP buffer to XSK pool, we simple call
2392 * xsk_tx_completed(), so we don't need to fill up
2395 tx_q->tx_skbuff_dma[entry].buf = 0;
2396 tx_q->xdpf[entry] = NULL;
2398 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2399 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2400 tx_q->tx_skbuff_dma[entry].last_segment = true;
2401 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2403 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2405 tx_q->tx_count_frames++;
2407 if (!priv->tx_coal_frames[queue])
2409 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2415 tx_q->tx_count_frames = 0;
2416 stmmac_set_tx_ic(priv, tx_desc);
2417 priv->xstats.tx_set_ic_bit++;
2420 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2421 true, priv->mode, true, true,
2424 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2426 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
2427 entry = tx_q->cur_tx;
2431 stmmac_flush_tx_descriptors(priv, queue);
2432 xsk_tx_release(pool);
2435 /* Return true if all of the 3 conditions are met
2436 * a) TX Budget is still available
2437 * b) work_done = true when XSK TX desc peek is empty (no more
2438 * pending XSK TX for transmission)
2440 return !!budget && work_done;
2444 * stmmac_tx_clean - to manage the transmission completion
2445 * @priv: driver private structure
2446 * @budget: napi budget limiting this functions packet handling
2447 * @queue: TX queue index
2448 * Description: it reclaims the transmit resources after transmission completes.
2450 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2452 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2453 unsigned int bytes_compl = 0, pkts_compl = 0;
2454 unsigned int entry, xmits = 0, count = 0;
2456 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2458 priv->xstats.tx_clean++;
2460 tx_q->xsk_frames_done = 0;
2462 entry = tx_q->dirty_tx;
2464 /* Try to clean all TX complete frame in 1 shot */
2465 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
2466 struct xdp_frame *xdpf;
2467 struct sk_buff *skb;
2471 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2472 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2473 xdpf = tx_q->xdpf[entry];
2475 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2477 skb = tx_q->tx_skbuff[entry];
2483 if (priv->extend_desc)
2484 p = (struct dma_desc *)(tx_q->dma_etx + entry);
2485 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2486 p = &tx_q->dma_entx[entry].basic;
2488 p = tx_q->dma_tx + entry;
2490 status = stmmac_tx_status(priv, &priv->dev->stats,
2491 &priv->xstats, p, priv->ioaddr);
2492 /* Check if the descriptor is owned by the DMA */
2493 if (unlikely(status & tx_dma_own))
2498 /* Make sure descriptor fields are read after reading
2503 /* Just consider the last segment and ...*/
2504 if (likely(!(status & tx_not_ls))) {
2505 /* ... verify the status error condition */
2506 if (unlikely(status & tx_err)) {
2507 priv->dev->stats.tx_errors++;
2509 priv->dev->stats.tx_packets++;
2510 priv->xstats.tx_pkt_n++;
2511 priv->xstats.txq_stats[queue].tx_pkt_n++;
2514 stmmac_get_tx_hwtstamp(priv, p, skb);
2517 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2518 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2519 if (tx_q->tx_skbuff_dma[entry].map_as_page)
2520 dma_unmap_page(priv->device,
2521 tx_q->tx_skbuff_dma[entry].buf,
2522 tx_q->tx_skbuff_dma[entry].len,
2525 dma_unmap_single(priv->device,
2526 tx_q->tx_skbuff_dma[entry].buf,
2527 tx_q->tx_skbuff_dma[entry].len,
2529 tx_q->tx_skbuff_dma[entry].buf = 0;
2530 tx_q->tx_skbuff_dma[entry].len = 0;
2531 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2534 stmmac_clean_desc3(priv, tx_q, p);
2536 tx_q->tx_skbuff_dma[entry].last_segment = false;
2537 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2540 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2541 xdp_return_frame_rx_napi(xdpf);
2542 tx_q->xdpf[entry] = NULL;
2546 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2547 xdp_return_frame(xdpf);
2548 tx_q->xdpf[entry] = NULL;
2551 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2552 tx_q->xsk_frames_done++;
2554 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2557 bytes_compl += skb->len;
2558 dev_consume_skb_any(skb);
2559 tx_q->tx_skbuff[entry] = NULL;
2563 stmmac_release_tx_desc(priv, p, priv->mode);
2565 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
2567 tx_q->dirty_tx = entry;
2569 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2570 pkts_compl, bytes_compl);
2572 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2574 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2576 netif_dbg(priv, tx_done, priv->dev,
2577 "%s: restart transmit\n", __func__);
2578 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2581 if (tx_q->xsk_pool) {
2584 if (tx_q->xsk_frames_done)
2585 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2587 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2588 xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2590 /* For XSK TX, we try to send as many as possible.
2591 * If XSK work done (XSK TX desc empty and budget still
2592 * available), return "budget - 1" to reenable TX IRQ.
2593 * Else, return "budget" to make NAPI continue polling.
2595 work_done = stmmac_xdp_xmit_zc(priv, queue,
2596 STMMAC_XSK_TX_BUDGET_MAX);
2603 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2604 priv->eee_sw_timer_en) {
2605 stmmac_enable_eee_mode(priv);
2606 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2609 /* We still have pending packets, let's call for a new scheduling */
2610 if (tx_q->dirty_tx != tx_q->cur_tx)
2611 hrtimer_start(&tx_q->txtimer,
2612 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2615 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2617 /* Combine decisions from TX clean and XSK TX */
2618 return max(count, xmits);
2622 * stmmac_tx_err - to manage the tx error
2623 * @priv: driver private structure
2624 * @chan: channel index
2625 * Description: it cleans the descriptors and restarts the transmission
2626 * in case of transmission errors.
2628 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2630 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2632 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2634 stmmac_stop_tx_dma(priv, chan);
2635 dma_free_tx_skbufs(priv, chan);
2636 stmmac_clear_tx_descriptors(priv, chan);
2640 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2641 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2642 tx_q->dma_tx_phy, chan);
2643 stmmac_start_tx_dma(priv, chan);
2645 priv->dev->stats.tx_errors++;
2646 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2650 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2651 * @priv: driver private structure
2652 * @txmode: TX operating mode
2653 * @rxmode: RX operating mode
2654 * @chan: channel index
2655 * Description: it is used for configuring of the DMA operation mode in
2656 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2659 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2660 u32 rxmode, u32 chan)
2662 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2663 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2664 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2665 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2666 int rxfifosz = priv->plat->rx_fifo_size;
2667 int txfifosz = priv->plat->tx_fifo_size;
2670 rxfifosz = priv->dma_cap.rx_fifo_size;
2672 txfifosz = priv->dma_cap.tx_fifo_size;
2674 /* Adjust for real per queue fifo size */
2675 rxfifosz /= rx_channels_count;
2676 txfifosz /= tx_channels_count;
2678 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2679 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2682 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2686 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2687 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2688 if (ret && (ret != -EINVAL)) {
2689 stmmac_global_err(priv);
2696 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2698 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2699 &priv->xstats, chan, dir);
2700 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2701 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2702 struct stmmac_channel *ch = &priv->channel[chan];
2703 struct napi_struct *rx_napi;
2704 struct napi_struct *tx_napi;
2705 unsigned long flags;
2707 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2708 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2710 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2711 if (napi_schedule_prep(rx_napi)) {
2712 spin_lock_irqsave(&ch->lock, flags);
2713 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2714 spin_unlock_irqrestore(&ch->lock, flags);
2715 __napi_schedule(rx_napi);
2719 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2720 if (napi_schedule_prep(tx_napi)) {
2721 spin_lock_irqsave(&ch->lock, flags);
2722 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2723 spin_unlock_irqrestore(&ch->lock, flags);
2724 __napi_schedule(tx_napi);
2732 * stmmac_dma_interrupt - DMA ISR
2733 * @priv: driver private structure
2734 * Description: this is the DMA ISR. It is called by the main ISR.
2735 * It calls the dwmac dma routine and schedule poll method in case of some
2738 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2740 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2741 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2742 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2743 tx_channel_count : rx_channel_count;
2745 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2747 /* Make sure we never check beyond our status buffer. */
2748 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2749 channels_to_check = ARRAY_SIZE(status);
2751 for (chan = 0; chan < channels_to_check; chan++)
2752 status[chan] = stmmac_napi_check(priv, chan,
2755 for (chan = 0; chan < tx_channel_count; chan++) {
2756 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2757 /* Try to bump up the dma threshold on this failure */
2758 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2761 if (priv->plat->force_thresh_dma_mode)
2762 stmmac_set_dma_operation_mode(priv,
2767 stmmac_set_dma_operation_mode(priv,
2771 priv->xstats.threshold = tc;
2773 } else if (unlikely(status[chan] == tx_hard_error)) {
2774 stmmac_tx_err(priv, chan);
2780 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2781 * @priv: driver private structure
2782 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2784 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2786 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2787 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2789 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2791 if (priv->dma_cap.rmon) {
2792 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2793 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2795 netdev_info(priv->dev, "No MAC Management Counters available\n");
2799 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2800 * @priv: driver private structure
2802 * new GMAC chip generations have a new register to indicate the
2803 * presence of the optional feature/functions.
2804 * This can be also used to override the value passed through the
2805 * platform and necessary for old MAC10/100 and GMAC chips.
2807 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2809 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2813 * stmmac_check_ether_addr - check if the MAC addr is valid
2814 * @priv: driver private structure
2816 * it is to verify if the MAC address is valid, in case of failures it
2817 * generates a random MAC address
2819 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2821 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2822 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2823 if (!is_valid_ether_addr(priv->dev->dev_addr))
2824 eth_hw_addr_random(priv->dev);
2825 dev_info(priv->device, "device MAC address %pM\n",
2826 priv->dev->dev_addr);
2831 * stmmac_init_dma_engine - DMA init.
2832 * @priv: driver private structure
2834 * It inits the DMA invoking the specific MAC/GMAC callback.
2835 * Some DMA parameters can be passed from the platform;
2836 * in case of these are not passed a default is kept for the MAC or GMAC.
2838 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2840 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2841 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2842 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2843 struct stmmac_rx_queue *rx_q;
2844 struct stmmac_tx_queue *tx_q;
2849 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2850 dev_err(priv->device, "Invalid DMA configuration\n");
2854 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2857 ret = stmmac_reset(priv, priv->ioaddr);
2859 dev_err(priv->device, "Failed to reset the dma\n");
2863 /* DMA Configuration */
2864 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2866 if (priv->plat->axi)
2867 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2869 /* DMA CSR Channel configuration */
2870 for (chan = 0; chan < dma_csr_ch; chan++)
2871 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2873 /* DMA RX Channel Configuration */
2874 for (chan = 0; chan < rx_channels_count; chan++) {
2875 rx_q = &priv->rx_queue[chan];
2877 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2878 rx_q->dma_rx_phy, chan);
2880 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2881 (rx_q->buf_alloc_num *
2882 sizeof(struct dma_desc));
2883 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2884 rx_q->rx_tail_addr, chan);
2887 /* DMA TX Channel Configuration */
2888 for (chan = 0; chan < tx_channels_count; chan++) {
2889 tx_q = &priv->tx_queue[chan];
2891 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2892 tx_q->dma_tx_phy, chan);
2894 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2895 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2896 tx_q->tx_tail_addr, chan);
2902 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2904 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2906 hrtimer_start(&tx_q->txtimer,
2907 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2912 * stmmac_tx_timer - mitigation sw timer for tx.
2915 * This is the timer handler to directly invoke the stmmac_tx_clean.
2917 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
2919 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
2920 struct stmmac_priv *priv = tx_q->priv_data;
2921 struct stmmac_channel *ch;
2922 struct napi_struct *napi;
2924 ch = &priv->channel[tx_q->queue_index];
2925 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2927 if (likely(napi_schedule_prep(napi))) {
2928 unsigned long flags;
2930 spin_lock_irqsave(&ch->lock, flags);
2931 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2932 spin_unlock_irqrestore(&ch->lock, flags);
2933 __napi_schedule(napi);
2936 return HRTIMER_NORESTART;
2940 * stmmac_init_coalesce - init mitigation options.
2941 * @priv: driver private structure
2943 * This inits the coalesce parameters: i.e. timer rate,
2944 * timer handler and default threshold used for enabling the
2945 * interrupt on completion bit.
2947 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2949 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2950 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2953 for (chan = 0; chan < tx_channel_count; chan++) {
2954 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2956 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
2957 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
2959 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2960 tx_q->txtimer.function = stmmac_tx_timer;
2963 for (chan = 0; chan < rx_channel_count; chan++)
2964 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
2967 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2969 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2970 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2973 /* set TX ring length */
2974 for (chan = 0; chan < tx_channels_count; chan++)
2975 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2976 (priv->dma_tx_size - 1), chan);
2978 /* set RX ring length */
2979 for (chan = 0; chan < rx_channels_count; chan++)
2980 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2981 (priv->dma_rx_size - 1), chan);
2985 * stmmac_set_tx_queue_weight - Set TX queue weight
2986 * @priv: driver private structure
2987 * Description: It is used for setting TX queues weight
2989 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2991 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2995 for (queue = 0; queue < tx_queues_count; queue++) {
2996 weight = priv->plat->tx_queues_cfg[queue].weight;
2997 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
3002 * stmmac_configure_cbs - Configure CBS in TX queue
3003 * @priv: driver private structure
3004 * Description: It is used for configuring CBS in AVB TX queues
3006 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3008 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3012 /* queue 0 is reserved for legacy traffic */
3013 for (queue = 1; queue < tx_queues_count; queue++) {
3014 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3015 if (mode_to_use == MTL_QUEUE_DCB)
3018 stmmac_config_cbs(priv, priv->hw,
3019 priv->plat->tx_queues_cfg[queue].send_slope,
3020 priv->plat->tx_queues_cfg[queue].idle_slope,
3021 priv->plat->tx_queues_cfg[queue].high_credit,
3022 priv->plat->tx_queues_cfg[queue].low_credit,
3028 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3029 * @priv: driver private structure
3030 * Description: It is used for mapping RX queues to RX dma channels
3032 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3034 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3038 for (queue = 0; queue < rx_queues_count; queue++) {
3039 chan = priv->plat->rx_queues_cfg[queue].chan;
3040 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3045 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3046 * @priv: driver private structure
3047 * Description: It is used for configuring the RX Queue Priority
3049 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3051 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3055 for (queue = 0; queue < rx_queues_count; queue++) {
3056 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3059 prio = priv->plat->rx_queues_cfg[queue].prio;
3060 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3065 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3066 * @priv: driver private structure
3067 * Description: It is used for configuring the TX Queue Priority
3069 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3071 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3075 for (queue = 0; queue < tx_queues_count; queue++) {
3076 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3079 prio = priv->plat->tx_queues_cfg[queue].prio;
3080 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3085 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3086 * @priv: driver private structure
3087 * Description: It is used for configuring the RX queue routing
3089 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3091 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3095 for (queue = 0; queue < rx_queues_count; queue++) {
3096 /* no specific packet type routing specified for the queue */
3097 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3100 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3101 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3105 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3107 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3108 priv->rss.enable = false;
3112 if (priv->dev->features & NETIF_F_RXHASH)
3113 priv->rss.enable = true;
3115 priv->rss.enable = false;
3117 stmmac_rss_configure(priv, priv->hw, &priv->rss,
3118 priv->plat->rx_queues_to_use);
3122 * stmmac_mtl_configuration - Configure MTL
3123 * @priv: driver private structure
3124 * Description: It is used for configurring MTL
3126 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3128 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3129 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3131 if (tx_queues_count > 1)
3132 stmmac_set_tx_queue_weight(priv);
3134 /* Configure MTL RX algorithms */
3135 if (rx_queues_count > 1)
3136 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3137 priv->plat->rx_sched_algorithm);
3139 /* Configure MTL TX algorithms */
3140 if (tx_queues_count > 1)
3141 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3142 priv->plat->tx_sched_algorithm);
3144 /* Configure CBS in AVB TX queues */
3145 if (tx_queues_count > 1)
3146 stmmac_configure_cbs(priv);
3148 /* Map RX MTL to DMA channels */
3149 stmmac_rx_queue_dma_chan_map(priv);
3151 /* Enable MAC RX Queues */
3152 stmmac_mac_enable_rx_queues(priv);
3154 /* Set RX priorities */
3155 if (rx_queues_count > 1)
3156 stmmac_mac_config_rx_queues_prio(priv);
3158 /* Set TX priorities */
3159 if (tx_queues_count > 1)
3160 stmmac_mac_config_tx_queues_prio(priv);
3162 /* Set RX routing */
3163 if (rx_queues_count > 1)
3164 stmmac_mac_config_rx_queues_routing(priv);
3166 /* Receive Side Scaling */
3167 if (rx_queues_count > 1)
3168 stmmac_mac_config_rss(priv);
3171 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3173 if (priv->dma_cap.asp) {
3174 netdev_info(priv->dev, "Enabling Safety Features\n");
3175 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3176 priv->plat->safety_feat_cfg);
3178 netdev_info(priv->dev, "No Safety Features support found\n");
3182 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3186 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3187 clear_bit(__FPE_REMOVING, &priv->fpe_task_state);
3189 name = priv->wq_name;
3190 sprintf(name, "%s-fpe", priv->dev->name);
3192 priv->fpe_wq = create_singlethread_workqueue(name);
3193 if (!priv->fpe_wq) {
3194 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3198 netdev_info(priv->dev, "FPE workqueue start");
3204 * stmmac_hw_setup - setup mac in a usable state.
3205 * @dev : pointer to the device structure.
3206 * @init_ptp: initialize PTP if set
3208 * this is the main function to setup the HW in a usable state because the
3209 * dma engine is reset, the core registers are configured (e.g. AXI,
3210 * Checksum features, timers). The DMA is ready to start receiving and
3213 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3216 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
3218 struct stmmac_priv *priv = netdev_priv(dev);
3219 u32 rx_cnt = priv->plat->rx_queues_to_use;
3220 u32 tx_cnt = priv->plat->tx_queues_to_use;
3225 /* DMA initialization and SW reset */
3226 ret = stmmac_init_dma_engine(priv);
3228 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3233 /* Copy the MAC addr into the HW */
3234 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3236 /* PS and related bits will be programmed according to the speed */
3237 if (priv->hw->pcs) {
3238 int speed = priv->plat->mac_port_sel_speed;
3240 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3241 (speed == SPEED_1000)) {
3242 priv->hw->ps = speed;
3244 dev_warn(priv->device, "invalid port speed\n");
3249 /* Initialize the MAC Core */
3250 stmmac_core_init(priv, priv->hw, dev);
3253 stmmac_mtl_configuration(priv);
3255 /* Initialize Safety Features */
3256 stmmac_safety_feat_configuration(priv);
3258 ret = stmmac_rx_ipc(priv, priv->hw);
3260 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3261 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3262 priv->hw->rx_csum = 0;
3265 /* Enable the MAC Rx/Tx */
3266 stmmac_mac_set(priv, priv->ioaddr, true);
3268 /* Set the HW DMA mode and the COE */
3269 stmmac_dma_operation_mode(priv);
3271 stmmac_mmc_setup(priv);
3274 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3276 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
3278 ret = stmmac_init_ptp(priv);
3279 if (ret == -EOPNOTSUPP)
3280 netdev_warn(priv->dev, "PTP not supported by HW\n");
3282 netdev_warn(priv->dev, "PTP init failed\n");
3285 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3287 /* Convert the timer from msec to usec */
3288 if (!priv->tx_lpi_timer)
3289 priv->tx_lpi_timer = eee_timer * 1000;
3291 if (priv->use_riwt) {
3294 for (queue = 0; queue < rx_cnt; queue++) {
3295 if (!priv->rx_riwt[queue])
3296 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3298 stmmac_rx_watchdog(priv, priv->ioaddr,
3299 priv->rx_riwt[queue], queue);
3304 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3306 /* set TX and RX rings length */
3307 stmmac_set_rings_length(priv);
3311 for (chan = 0; chan < tx_cnt; chan++) {
3312 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3314 /* TSO and TBS cannot co-exist */
3315 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3318 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3322 /* Enable Split Header */
3323 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3324 for (chan = 0; chan < rx_cnt; chan++)
3325 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3328 /* VLAN Tag Insertion */
3329 if (priv->dma_cap.vlins)
3330 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3333 for (chan = 0; chan < tx_cnt; chan++) {
3334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3335 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3337 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3340 /* Configure real RX and TX queues */
3341 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3342 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3344 /* Start the ball rolling... */
3345 stmmac_start_all_dma(priv);
3347 if (priv->dma_cap.fpesel) {
3348 stmmac_fpe_start_wq(priv);
3350 if (priv->plat->fpe_cfg->enable)
3351 stmmac_fpe_handshake(priv, true);
3357 static void stmmac_hw_teardown(struct net_device *dev)
3359 struct stmmac_priv *priv = netdev_priv(dev);
3361 clk_disable_unprepare(priv->plat->clk_ptp_ref);
3364 static void stmmac_free_irq(struct net_device *dev,
3365 enum request_irq_err irq_err, int irq_idx)
3367 struct stmmac_priv *priv = netdev_priv(dev);
3371 case REQ_IRQ_ERR_ALL:
3372 irq_idx = priv->plat->tx_queues_to_use;
3374 case REQ_IRQ_ERR_TX:
3375 for (j = irq_idx - 1; j >= 0; j--) {
3376 if (priv->tx_irq[j] > 0) {
3377 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3378 free_irq(priv->tx_irq[j], &priv->tx_queue[j]);
3381 irq_idx = priv->plat->rx_queues_to_use;
3383 case REQ_IRQ_ERR_RX:
3384 for (j = irq_idx - 1; j >= 0; j--) {
3385 if (priv->rx_irq[j] > 0) {
3386 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3387 free_irq(priv->rx_irq[j], &priv->rx_queue[j]);
3391 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3392 free_irq(priv->sfty_ue_irq, dev);
3394 case REQ_IRQ_ERR_SFTY_UE:
3395 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3396 free_irq(priv->sfty_ce_irq, dev);
3398 case REQ_IRQ_ERR_SFTY_CE:
3399 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3400 free_irq(priv->lpi_irq, dev);
3402 case REQ_IRQ_ERR_LPI:
3403 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3404 free_irq(priv->wol_irq, dev);
3406 case REQ_IRQ_ERR_WOL:
3407 free_irq(dev->irq, dev);
3409 case REQ_IRQ_ERR_MAC:
3410 case REQ_IRQ_ERR_NO:
3411 /* If MAC IRQ request error, no more IRQ to free */
3416 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3418 struct stmmac_priv *priv = netdev_priv(dev);
3419 enum request_irq_err irq_err;
3426 /* For common interrupt */
3427 int_name = priv->int_name_mac;
3428 sprintf(int_name, "%s:%s", dev->name, "mac");
3429 ret = request_irq(dev->irq, stmmac_mac_interrupt,
3431 if (unlikely(ret < 0)) {
3432 netdev_err(priv->dev,
3433 "%s: alloc mac MSI %d (error: %d)\n",
3434 __func__, dev->irq, ret);
3435 irq_err = REQ_IRQ_ERR_MAC;
3439 /* Request the Wake IRQ in case of another line
3442 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3443 int_name = priv->int_name_wol;
3444 sprintf(int_name, "%s:%s", dev->name, "wol");
3445 ret = request_irq(priv->wol_irq,
3446 stmmac_mac_interrupt,
3448 if (unlikely(ret < 0)) {
3449 netdev_err(priv->dev,
3450 "%s: alloc wol MSI %d (error: %d)\n",
3451 __func__, priv->wol_irq, ret);
3452 irq_err = REQ_IRQ_ERR_WOL;
3457 /* Request the LPI IRQ in case of another line
3460 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3461 int_name = priv->int_name_lpi;
3462 sprintf(int_name, "%s:%s", dev->name, "lpi");
3463 ret = request_irq(priv->lpi_irq,
3464 stmmac_mac_interrupt,
3466 if (unlikely(ret < 0)) {
3467 netdev_err(priv->dev,
3468 "%s: alloc lpi MSI %d (error: %d)\n",
3469 __func__, priv->lpi_irq, ret);
3470 irq_err = REQ_IRQ_ERR_LPI;
3475 /* Request the Safety Feature Correctible Error line in
3476 * case of another line is used
3478 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3479 int_name = priv->int_name_sfty_ce;
3480 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3481 ret = request_irq(priv->sfty_ce_irq,
3482 stmmac_safety_interrupt,
3484 if (unlikely(ret < 0)) {
3485 netdev_err(priv->dev,
3486 "%s: alloc sfty ce MSI %d (error: %d)\n",
3487 __func__, priv->sfty_ce_irq, ret);
3488 irq_err = REQ_IRQ_ERR_SFTY_CE;
3493 /* Request the Safety Feature Uncorrectible Error line in
3494 * case of another line is used
3496 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3497 int_name = priv->int_name_sfty_ue;
3498 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3499 ret = request_irq(priv->sfty_ue_irq,
3500 stmmac_safety_interrupt,
3502 if (unlikely(ret < 0)) {
3503 netdev_err(priv->dev,
3504 "%s: alloc sfty ue MSI %d (error: %d)\n",
3505 __func__, priv->sfty_ue_irq, ret);
3506 irq_err = REQ_IRQ_ERR_SFTY_UE;
3511 /* Request Rx MSI irq */
3512 for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3513 if (priv->rx_irq[i] == 0)
3516 int_name = priv->int_name_rx_irq[i];
3517 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3518 ret = request_irq(priv->rx_irq[i],
3520 0, int_name, &priv->rx_queue[i]);
3521 if (unlikely(ret < 0)) {
3522 netdev_err(priv->dev,
3523 "%s: alloc rx-%d MSI %d (error: %d)\n",
3524 __func__, i, priv->rx_irq[i], ret);
3525 irq_err = REQ_IRQ_ERR_RX;
3529 cpumask_clear(&cpu_mask);
3530 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3531 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3534 /* Request Tx MSI irq */
3535 for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3536 if (priv->tx_irq[i] == 0)
3539 int_name = priv->int_name_tx_irq[i];
3540 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3541 ret = request_irq(priv->tx_irq[i],
3543 0, int_name, &priv->tx_queue[i]);
3544 if (unlikely(ret < 0)) {
3545 netdev_err(priv->dev,
3546 "%s: alloc tx-%d MSI %d (error: %d)\n",
3547 __func__, i, priv->tx_irq[i], ret);
3548 irq_err = REQ_IRQ_ERR_TX;
3552 cpumask_clear(&cpu_mask);
3553 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3554 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3560 stmmac_free_irq(dev, irq_err, irq_idx);
3564 static int stmmac_request_irq_single(struct net_device *dev)
3566 struct stmmac_priv *priv = netdev_priv(dev);
3567 enum request_irq_err irq_err;
3570 ret = request_irq(dev->irq, stmmac_interrupt,
3571 IRQF_SHARED, dev->name, dev);
3572 if (unlikely(ret < 0)) {
3573 netdev_err(priv->dev,
3574 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3575 __func__, dev->irq, ret);
3576 irq_err = REQ_IRQ_ERR_MAC;
3580 /* Request the Wake IRQ in case of another line
3583 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3584 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3585 IRQF_SHARED, dev->name, dev);
3586 if (unlikely(ret < 0)) {
3587 netdev_err(priv->dev,
3588 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3589 __func__, priv->wol_irq, ret);
3590 irq_err = REQ_IRQ_ERR_WOL;
3595 /* Request the IRQ lines */
3596 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3597 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3598 IRQF_SHARED, dev->name, dev);
3599 if (unlikely(ret < 0)) {
3600 netdev_err(priv->dev,
3601 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3602 __func__, priv->lpi_irq, ret);
3603 irq_err = REQ_IRQ_ERR_LPI;
3611 stmmac_free_irq(dev, irq_err, 0);
3615 static int stmmac_request_irq(struct net_device *dev)
3617 struct stmmac_priv *priv = netdev_priv(dev);
3620 /* Request the IRQ lines */
3621 if (priv->plat->multi_msi_en)
3622 ret = stmmac_request_irq_multi_msi(dev);
3624 ret = stmmac_request_irq_single(dev);
3630 * stmmac_open - open entry point of the driver
3631 * @dev : pointer to the device structure.
3633 * This function is the open entry point of the driver.
3635 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3638 int stmmac_open(struct net_device *dev)
3640 struct stmmac_priv *priv = netdev_priv(dev);
3641 int mode = priv->plat->phy_interface;
3646 ret = pm_runtime_get_sync(priv->device);
3648 pm_runtime_put_noidle(priv->device);
3652 if (priv->hw->pcs != STMMAC_PCS_TBI &&
3653 priv->hw->pcs != STMMAC_PCS_RTBI &&
3655 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3656 ret = stmmac_init_phy(dev);
3658 netdev_err(priv->dev,
3659 "%s: Cannot attach to PHY (error: %d)\n",
3661 goto init_phy_error;
3665 /* Extra statistics */
3666 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3667 priv->xstats.threshold = tc;
3669 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
3673 if (bfsize < BUF_SIZE_16KiB)
3674 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
3676 priv->dma_buf_sz = bfsize;
3679 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3681 if (!priv->dma_tx_size)
3682 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3683 if (!priv->dma_rx_size)
3684 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3686 /* Earlier check for TBS */
3687 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3688 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3689 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3691 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3692 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3695 ret = alloc_dma_desc_resources(priv);
3697 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3699 goto dma_desc_error;
3702 ret = init_dma_desc_rings(dev, GFP_KERNEL);
3704 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3709 ret = stmmac_hw_setup(dev, true);
3711 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3715 stmmac_init_coalesce(priv);
3717 phylink_start(priv->phylink);
3718 /* We may have called phylink_speed_down before */
3719 phylink_speed_up(priv->phylink);
3721 ret = stmmac_request_irq(dev);
3725 stmmac_enable_all_queues(priv);
3726 netif_tx_start_all_queues(priv->dev);
3731 phylink_stop(priv->phylink);
3733 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3734 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3736 stmmac_hw_teardown(dev);
3738 free_dma_desc_resources(priv);
3740 phylink_disconnect_phy(priv->phylink);
3742 pm_runtime_put(priv->device);
3746 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3748 set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3751 destroy_workqueue(priv->fpe_wq);
3753 netdev_info(priv->dev, "FPE workqueue stop");
3757 * stmmac_release - close entry point of the driver
3758 * @dev : device pointer.
3760 * This is the stop entry point of the driver.
3762 int stmmac_release(struct net_device *dev)
3764 struct stmmac_priv *priv = netdev_priv(dev);
3767 if (device_may_wakeup(priv->device))
3768 phylink_speed_down(priv->phylink, false);
3769 /* Stop and disconnect the PHY */
3770 phylink_stop(priv->phylink);
3771 phylink_disconnect_phy(priv->phylink);
3773 stmmac_disable_all_queues(priv);
3775 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3776 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3778 /* Free the IRQ lines */
3779 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3781 if (priv->eee_enabled) {
3782 priv->tx_path_in_lpi_mode = false;
3783 del_timer_sync(&priv->eee_ctrl_timer);
3786 /* Stop TX/RX DMA and clear the descriptors */
3787 stmmac_stop_all_dma(priv);
3789 /* Release and free the Rx/Tx resources */
3790 free_dma_desc_resources(priv);
3792 /* Disable the MAC Rx/Tx */
3793 stmmac_mac_set(priv, priv->ioaddr, false);
3795 netif_carrier_off(dev);
3797 stmmac_release_ptp(priv);
3799 pm_runtime_put(priv->device);
3801 if (priv->dma_cap.fpesel)
3802 stmmac_fpe_stop_wq(priv);
3807 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3808 struct stmmac_tx_queue *tx_q)
3810 u16 tag = 0x0, inner_tag = 0x0;
3811 u32 inner_type = 0x0;
3814 if (!priv->dma_cap.vlins)
3816 if (!skb_vlan_tag_present(skb))
3818 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3819 inner_tag = skb_vlan_tag_get(skb);
3820 inner_type = STMMAC_VLAN_INSERT;
3823 tag = skb_vlan_tag_get(skb);
3825 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3826 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3828 p = &tx_q->dma_tx[tx_q->cur_tx];
3830 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3833 stmmac_set_tx_owner(priv, p);
3834 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
3839 * stmmac_tso_allocator - close entry point of the driver
3840 * @priv: driver private structure
3841 * @des: buffer start address
3842 * @total_len: total length to fill in descriptors
3843 * @last_segment: condition for the last descriptor
3844 * @queue: TX queue index
3846 * This function fills descriptor and request new descriptors according to
3847 * buffer length to fill
3849 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
3850 int total_len, bool last_segment, u32 queue)
3852 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3853 struct dma_desc *desc;
3857 tmp_len = total_len;
3859 while (tmp_len > 0) {
3860 dma_addr_t curr_addr;
3862 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3864 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3866 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3867 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3869 desc = &tx_q->dma_tx[tx_q->cur_tx];
3871 curr_addr = des + (total_len - tmp_len);
3872 if (priv->dma_cap.addr64 <= 32)
3873 desc->des0 = cpu_to_le32(curr_addr);
3875 stmmac_set_desc_addr(priv, desc, curr_addr);
3877 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
3878 TSO_MAX_BUFF_SIZE : tmp_len;
3880 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3882 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3885 tmp_len -= TSO_MAX_BUFF_SIZE;
3889 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
3891 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3894 if (likely(priv->extend_desc))
3895 desc_size = sizeof(struct dma_extended_desc);
3896 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3897 desc_size = sizeof(struct dma_edesc);
3899 desc_size = sizeof(struct dma_desc);
3901 /* The own bit must be the latest setting done when prepare the
3902 * descriptor and then barrier is needed to make sure that
3903 * all is coherent before granting the DMA engine.
3907 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3908 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3912 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3913 * @skb : the socket buffer
3914 * @dev : device pointer
3915 * Description: this is the transmit function that is called on TSO frames
3916 * (support available on GMAC4 and newer chips).
3917 * Diagram below show the ring programming in case of TSO frames:
3921 * | DES0 |---> buffer1 = L2/L3/L4 header
3922 * | DES1 |---> TCP Payload (can continue on next descr...)
3923 * | DES2 |---> buffer 1 and 2 len
3924 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3930 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
3932 * | DES2 | --> buffer 1 and 2 len
3936 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3938 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3940 struct dma_desc *desc, *first, *mss_desc = NULL;
3941 struct stmmac_priv *priv = netdev_priv(dev);
3942 int nfrags = skb_shinfo(skb)->nr_frags;
3943 u32 queue = skb_get_queue_mapping(skb);
3944 unsigned int first_entry, tx_packets;
3945 int tmp_pay_len = 0, first_tx;
3946 struct stmmac_tx_queue *tx_q;
3947 bool has_vlan, set_ic;
3948 u8 proto_hdr_len, hdr;
3953 tx_q = &priv->tx_queue[queue];
3954 first_tx = tx_q->cur_tx;
3956 /* Compute header lengths */
3957 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3958 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3959 hdr = sizeof(struct udphdr);
3961 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3962 hdr = tcp_hdrlen(skb);
3965 /* Desc availability based on threshold should be enough safe */
3966 if (unlikely(stmmac_tx_avail(priv, queue) <
3967 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
3968 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3969 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3971 /* This is a hard error, log it. */
3972 netdev_err(priv->dev,
3973 "%s: Tx Ring full when queue awake\n",
3976 return NETDEV_TX_BUSY;
3979 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
3981 mss = skb_shinfo(skb)->gso_size;
3983 /* set new MSS value if needed */
3984 if (mss != tx_q->mss) {
3985 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3986 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3988 mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
3990 stmmac_set_mss(priv, mss_desc, mss);
3992 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3994 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3997 if (netif_msg_tx_queued(priv)) {
3998 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
3999 __func__, hdr, proto_hdr_len, pay_len, mss);
4000 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
4004 /* Check if VLAN can be inserted by HW */
4005 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4007 first_entry = tx_q->cur_tx;
4008 WARN_ON(tx_q->tx_skbuff[first_entry]);
4010 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4011 desc = &tx_q->dma_entx[first_entry].basic;
4013 desc = &tx_q->dma_tx[first_entry];
4017 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4019 /* first descriptor: fill Headers on Buf1 */
4020 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4022 if (dma_mapping_error(priv->device, des))
4025 tx_q->tx_skbuff_dma[first_entry].buf = des;
4026 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4027 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4028 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4030 if (priv->dma_cap.addr64 <= 32) {
4031 first->des0 = cpu_to_le32(des);
4033 /* Fill start of payload in buff2 of first descriptor */
4035 first->des1 = cpu_to_le32(des + proto_hdr_len);
4037 /* If needed take extra descriptors to fill the remaining payload */
4038 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4040 stmmac_set_desc_addr(priv, first, des);
4041 tmp_pay_len = pay_len;
4042 des += proto_hdr_len;
4046 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4048 /* Prepare fragments */
4049 for (i = 0; i < nfrags; i++) {
4050 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4052 des = skb_frag_dma_map(priv->device, frag, 0,
4053 skb_frag_size(frag),
4055 if (dma_mapping_error(priv->device, des))
4058 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4059 (i == nfrags - 1), queue);
4061 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4062 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4063 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4064 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4067 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4069 /* Only the last descriptor gets to point to the skb. */
4070 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4071 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4073 /* Manage tx mitigation */
4074 tx_packets = (tx_q->cur_tx + 1) - first_tx;
4075 tx_q->tx_count_frames += tx_packets;
4077 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4079 else if (!priv->tx_coal_frames[queue])
4081 else if (tx_packets > priv->tx_coal_frames[queue])
4083 else if ((tx_q->tx_count_frames %
4084 priv->tx_coal_frames[queue]) < tx_packets)
4090 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4091 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4093 desc = &tx_q->dma_tx[tx_q->cur_tx];
4095 tx_q->tx_count_frames = 0;
4096 stmmac_set_tx_ic(priv, desc);
4097 priv->xstats.tx_set_ic_bit++;
4100 /* We've used all descriptors we need for this skb, however,
4101 * advance cur_tx so that it references a fresh descriptor.
4102 * ndo_start_xmit will fill this descriptor the next time it's
4103 * called and stmmac_tx_clean may clean up to this descriptor.
4105 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
4107 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4108 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4110 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4113 dev->stats.tx_bytes += skb->len;
4114 priv->xstats.tx_tso_frames++;
4115 priv->xstats.tx_tso_nfrags += nfrags;
4117 if (priv->sarc_type)
4118 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4120 skb_tx_timestamp(skb);
4122 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4123 priv->hwts_tx_en)) {
4124 /* declare that device is doing timestamping */
4125 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4126 stmmac_enable_tx_timestamp(priv, first);
4129 /* Complete the first descriptor before granting the DMA */
4130 stmmac_prepare_tso_tx_desc(priv, first, 1,
4133 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4134 hdr / 4, (skb->len - proto_hdr_len));
4136 /* If context desc is used to change MSS */
4138 /* Make sure that first descriptor has been completely
4139 * written, including its own bit. This is because MSS is
4140 * actually before first descriptor, so we need to make
4141 * sure that MSS's own bit is the last thing written.
4144 stmmac_set_tx_owner(priv, mss_desc);
4147 if (netif_msg_pktdata(priv)) {
4148 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4149 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4150 tx_q->cur_tx, first, nfrags);
4151 pr_info(">>> frame to be transmitted: ");
4152 print_pkt(skb->data, skb_headlen(skb));
4155 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4157 stmmac_flush_tx_descriptors(priv, queue);
4158 stmmac_tx_timer_arm(priv, queue);
4160 return NETDEV_TX_OK;
4163 dev_err(priv->device, "Tx dma map failed\n");
4165 priv->dev->stats.tx_dropped++;
4166 return NETDEV_TX_OK;
4170 * stmmac_xmit - Tx entry point of the driver
4171 * @skb : the socket buffer
4172 * @dev : device pointer
4173 * Description : this is the tx entry point of the driver.
4174 * It programs the chain or the ring and supports oversized frames
4177 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4179 unsigned int first_entry, tx_packets, enh_desc;
4180 struct stmmac_priv *priv = netdev_priv(dev);
4181 unsigned int nopaged_len = skb_headlen(skb);
4182 int i, csum_insertion = 0, is_jumbo = 0;
4183 u32 queue = skb_get_queue_mapping(skb);
4184 int nfrags = skb_shinfo(skb)->nr_frags;
4185 int gso = skb_shinfo(skb)->gso_type;
4186 struct dma_edesc *tbs_desc = NULL;
4187 struct dma_desc *desc, *first;
4188 struct stmmac_tx_queue *tx_q;
4189 bool has_vlan, set_ic;
4190 int entry, first_tx;
4193 tx_q = &priv->tx_queue[queue];
4194 first_tx = tx_q->cur_tx;
4196 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4197 stmmac_disable_eee_mode(priv);
4199 /* Manage oversized TCP frames for GMAC4 device */
4200 if (skb_is_gso(skb) && priv->tso) {
4201 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4202 return stmmac_tso_xmit(skb, dev);
4203 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4204 return stmmac_tso_xmit(skb, dev);
4207 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4208 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4209 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4211 /* This is a hard error, log it. */
4212 netdev_err(priv->dev,
4213 "%s: Tx Ring full when queue awake\n",
4216 return NETDEV_TX_BUSY;
4219 /* Check if VLAN can be inserted by HW */
4220 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4222 entry = tx_q->cur_tx;
4223 first_entry = entry;
4224 WARN_ON(tx_q->tx_skbuff[first_entry]);
4226 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4228 if (likely(priv->extend_desc))
4229 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4230 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4231 desc = &tx_q->dma_entx[entry].basic;
4233 desc = tx_q->dma_tx + entry;
4238 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4240 enh_desc = priv->plat->enh_desc;
4241 /* To program the descriptors according to the size of the frame */
4243 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4245 if (unlikely(is_jumbo)) {
4246 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4247 if (unlikely(entry < 0) && (entry != -EINVAL))
4251 for (i = 0; i < nfrags; i++) {
4252 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4253 int len = skb_frag_size(frag);
4254 bool last_segment = (i == (nfrags - 1));
4256 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4257 WARN_ON(tx_q->tx_skbuff[entry]);
4259 if (likely(priv->extend_desc))
4260 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4261 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4262 desc = &tx_q->dma_entx[entry].basic;
4264 desc = tx_q->dma_tx + entry;
4266 des = skb_frag_dma_map(priv->device, frag, 0, len,
4268 if (dma_mapping_error(priv->device, des))
4269 goto dma_map_err; /* should reuse desc w/o issues */
4271 tx_q->tx_skbuff_dma[entry].buf = des;
4273 stmmac_set_desc_addr(priv, desc, des);
4275 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4276 tx_q->tx_skbuff_dma[entry].len = len;
4277 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4278 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4280 /* Prepare the descriptor and set the own bit too */
4281 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4282 priv->mode, 1, last_segment, skb->len);
4285 /* Only the last descriptor gets to point to the skb. */
4286 tx_q->tx_skbuff[entry] = skb;
4287 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4289 /* According to the coalesce parameter the IC bit for the latest
4290 * segment is reset and the timer re-started to clean the tx status.
4291 * This approach takes care about the fragments: desc is the first
4292 * element in case of no SG.
4294 tx_packets = (entry + 1) - first_tx;
4295 tx_q->tx_count_frames += tx_packets;
4297 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4299 else if (!priv->tx_coal_frames[queue])
4301 else if (tx_packets > priv->tx_coal_frames[queue])
4303 else if ((tx_q->tx_count_frames %
4304 priv->tx_coal_frames[queue]) < tx_packets)
4310 if (likely(priv->extend_desc))
4311 desc = &tx_q->dma_etx[entry].basic;
4312 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4313 desc = &tx_q->dma_entx[entry].basic;
4315 desc = &tx_q->dma_tx[entry];
4317 tx_q->tx_count_frames = 0;
4318 stmmac_set_tx_ic(priv, desc);
4319 priv->xstats.tx_set_ic_bit++;
4322 /* We've used all descriptors we need for this skb, however,
4323 * advance cur_tx so that it references a fresh descriptor.
4324 * ndo_start_xmit will fill this descriptor the next time it's
4325 * called and stmmac_tx_clean may clean up to this descriptor.
4327 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4328 tx_q->cur_tx = entry;
4330 if (netif_msg_pktdata(priv)) {
4331 netdev_dbg(priv->dev,
4332 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4333 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4334 entry, first, nfrags);
4336 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4337 print_pkt(skb->data, skb->len);
4340 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4341 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4343 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4346 dev->stats.tx_bytes += skb->len;
4348 if (priv->sarc_type)
4349 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4351 skb_tx_timestamp(skb);
4353 /* Ready to fill the first descriptor and set the OWN bit w/o any
4354 * problems because all the descriptors are actually ready to be
4355 * passed to the DMA engine.
4357 if (likely(!is_jumbo)) {
4358 bool last_segment = (nfrags == 0);
4360 des = dma_map_single(priv->device, skb->data,
4361 nopaged_len, DMA_TO_DEVICE);
4362 if (dma_mapping_error(priv->device, des))
4365 tx_q->tx_skbuff_dma[first_entry].buf = des;
4366 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4367 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4369 stmmac_set_desc_addr(priv, first, des);
4371 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4372 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4374 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4375 priv->hwts_tx_en)) {
4376 /* declare that device is doing timestamping */
4377 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4378 stmmac_enable_tx_timestamp(priv, first);
4381 /* Prepare the first descriptor setting the OWN bit too */
4382 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4383 csum_insertion, priv->mode, 0, last_segment,
4387 if (tx_q->tbs & STMMAC_TBS_EN) {
4388 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4390 tbs_desc = &tx_q->dma_entx[first_entry];
4391 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4394 stmmac_set_tx_owner(priv, first);
4396 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4398 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4400 stmmac_flush_tx_descriptors(priv, queue);
4401 stmmac_tx_timer_arm(priv, queue);
4403 return NETDEV_TX_OK;
4406 netdev_err(priv->dev, "Tx DMA map failed\n");
4408 priv->dev->stats.tx_dropped++;
4409 return NETDEV_TX_OK;
4412 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4414 struct vlan_ethhdr *veth;
4418 veth = (struct vlan_ethhdr *)skb->data;
4419 vlan_proto = veth->h_vlan_proto;
4421 if ((vlan_proto == htons(ETH_P_8021Q) &&
4422 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4423 (vlan_proto == htons(ETH_P_8021AD) &&
4424 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4425 /* pop the vlan tag */
4426 vlanid = ntohs(veth->h_vlan_TCI);
4427 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4428 skb_pull(skb, VLAN_HLEN);
4429 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4434 * stmmac_rx_refill - refill used skb preallocated buffers
4435 * @priv: driver private structure
4436 * @queue: RX queue index
4437 * Description : this is to reallocate the skb for the reception process
4438 * that is based on zero-copy.
4440 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4442 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4443 int dirty = stmmac_rx_dirty(priv, queue);
4444 unsigned int entry = rx_q->dirty_rx;
4446 while (dirty-- > 0) {
4447 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4451 if (priv->extend_desc)
4452 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4454 p = rx_q->dma_rx + entry;
4457 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
4462 if (priv->sph && !buf->sec_page) {
4463 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
4467 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4470 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4472 stmmac_set_desc_addr(priv, p, buf->addr);
4474 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4476 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4477 stmmac_refill_desc3(priv, rx_q, p);
4479 rx_q->rx_count_frames++;
4480 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4481 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4482 rx_q->rx_count_frames = 0;
4484 use_rx_wd = !priv->rx_coal_frames[queue];
4485 use_rx_wd |= rx_q->rx_count_frames > 0;
4486 if (!priv->use_riwt)
4490 stmmac_set_rx_owner(priv, p, use_rx_wd);
4492 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4494 rx_q->dirty_rx = entry;
4495 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4496 (rx_q->dirty_rx * sizeof(struct dma_desc));
4497 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4500 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4502 int status, unsigned int len)
4504 unsigned int plen = 0, hlen = 0;
4505 int coe = priv->hw->rx_csum;
4507 /* Not first descriptor, buffer is always zero */
4508 if (priv->sph && len)
4511 /* First descriptor, get split header length */
4512 stmmac_get_rx_header_len(priv, p, &hlen);
4513 if (priv->sph && hlen) {
4514 priv->xstats.rx_split_hdr_pkt_n++;
4518 /* First descriptor, not last descriptor and not split header */
4519 if (status & rx_not_ls)
4520 return priv->dma_buf_sz;
4522 plen = stmmac_get_rx_frame_len(priv, p, coe);
4524 /* First descriptor and last descriptor and not split header */
4525 return min_t(unsigned int, priv->dma_buf_sz, plen);
4528 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4530 int status, unsigned int len)
4532 int coe = priv->hw->rx_csum;
4533 unsigned int plen = 0;
4535 /* Not split header, buffer is not available */
4539 /* Not last descriptor */
4540 if (status & rx_not_ls)
4541 return priv->dma_buf_sz;
4543 plen = stmmac_get_rx_frame_len(priv, p, coe);
4545 /* Last descriptor */
4549 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4550 struct xdp_frame *xdpf, bool dma_map)
4552 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4553 unsigned int entry = tx_q->cur_tx;
4554 struct dma_desc *tx_desc;
4555 dma_addr_t dma_addr;
4558 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4559 return STMMAC_XDP_CONSUMED;
4561 if (likely(priv->extend_desc))
4562 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4563 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4564 tx_desc = &tx_q->dma_entx[entry].basic;
4566 tx_desc = tx_q->dma_tx + entry;
4569 dma_addr = dma_map_single(priv->device, xdpf->data,
4570 xdpf->len, DMA_TO_DEVICE);
4571 if (dma_mapping_error(priv->device, dma_addr))
4572 return STMMAC_XDP_CONSUMED;
4574 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4576 struct page *page = virt_to_page(xdpf->data);
4578 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4580 dma_sync_single_for_device(priv->device, dma_addr,
4581 xdpf->len, DMA_BIDIRECTIONAL);
4583 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4586 tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4587 tx_q->tx_skbuff_dma[entry].map_as_page = false;
4588 tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4589 tx_q->tx_skbuff_dma[entry].last_segment = true;
4590 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4592 tx_q->xdpf[entry] = xdpf;
4594 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4596 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4597 true, priv->mode, true, true,
4600 tx_q->tx_count_frames++;
4602 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4608 tx_q->tx_count_frames = 0;
4609 stmmac_set_tx_ic(priv, tx_desc);
4610 priv->xstats.tx_set_ic_bit++;
4613 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4615 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4616 tx_q->cur_tx = entry;
4618 return STMMAC_XDP_TX;
4621 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4626 if (unlikely(index < 0))
4629 while (index >= priv->plat->tx_queues_to_use)
4630 index -= priv->plat->tx_queues_to_use;
4635 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4636 struct xdp_buff *xdp)
4638 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4639 int cpu = smp_processor_id();
4640 struct netdev_queue *nq;
4644 if (unlikely(!xdpf))
4645 return STMMAC_XDP_CONSUMED;
4647 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4648 nq = netdev_get_tx_queue(priv->dev, queue);
4650 __netif_tx_lock(nq, cpu);
4651 /* Avoids TX time-out as we are sharing with slow path */
4652 nq->trans_start = jiffies;
4654 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4655 if (res == STMMAC_XDP_TX)
4656 stmmac_flush_tx_descriptors(priv, queue);
4658 __netif_tx_unlock(nq);
4663 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4664 struct bpf_prog *prog,
4665 struct xdp_buff *xdp)
4670 act = bpf_prog_run_xdp(prog, xdp);
4673 res = STMMAC_XDP_PASS;
4676 res = stmmac_xdp_xmit_back(priv, xdp);
4679 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4680 res = STMMAC_XDP_CONSUMED;
4682 res = STMMAC_XDP_REDIRECT;
4685 bpf_warn_invalid_xdp_action(act);
4688 trace_xdp_exception(priv->dev, prog, act);
4691 res = STMMAC_XDP_CONSUMED;
4698 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4699 struct xdp_buff *xdp)
4701 struct bpf_prog *prog;
4704 prog = READ_ONCE(priv->xdp_prog);
4706 res = STMMAC_XDP_PASS;
4710 res = __stmmac_xdp_run_prog(priv, prog, xdp);
4712 return ERR_PTR(-res);
4715 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4718 int cpu = smp_processor_id();
4721 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4723 if (xdp_status & STMMAC_XDP_TX)
4724 stmmac_tx_timer_arm(priv, queue);
4726 if (xdp_status & STMMAC_XDP_REDIRECT)
4730 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4731 struct xdp_buff *xdp)
4733 unsigned int metasize = xdp->data - xdp->data_meta;
4734 unsigned int datasize = xdp->data_end - xdp->data;
4735 struct sk_buff *skb;
4737 skb = __napi_alloc_skb(&ch->rxtx_napi,
4738 xdp->data_end - xdp->data_hard_start,
4739 GFP_ATOMIC | __GFP_NOWARN);
4743 skb_reserve(skb, xdp->data - xdp->data_hard_start);
4744 memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4746 skb_metadata_set(skb, metasize);
4751 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4752 struct dma_desc *p, struct dma_desc *np,
4753 struct xdp_buff *xdp)
4755 struct stmmac_channel *ch = &priv->channel[queue];
4756 unsigned int len = xdp->data_end - xdp->data;
4757 enum pkt_hash_types hash_type;
4758 int coe = priv->hw->rx_csum;
4759 struct sk_buff *skb;
4762 skb = stmmac_construct_skb_zc(ch, xdp);
4764 priv->dev->stats.rx_dropped++;
4768 stmmac_get_rx_hwtstamp(priv, p, np, skb);
4769 stmmac_rx_vlan(priv->dev, skb);
4770 skb->protocol = eth_type_trans(skb, priv->dev);
4773 skb_checksum_none_assert(skb);
4775 skb->ip_summed = CHECKSUM_UNNECESSARY;
4777 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4778 skb_set_hash(skb, hash, hash_type);
4780 skb_record_rx_queue(skb, queue);
4781 napi_gro_receive(&ch->rxtx_napi, skb);
4783 priv->dev->stats.rx_packets++;
4784 priv->dev->stats.rx_bytes += len;
4787 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4789 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4790 unsigned int entry = rx_q->dirty_rx;
4791 struct dma_desc *rx_desc = NULL;
4794 budget = min(budget, stmmac_rx_dirty(priv, queue));
4796 while (budget-- > 0 && entry != rx_q->cur_rx) {
4797 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4798 dma_addr_t dma_addr;
4802 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4809 if (priv->extend_desc)
4810 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4812 rx_desc = rx_q->dma_rx + entry;
4814 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4815 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4816 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4817 stmmac_refill_desc3(priv, rx_q, rx_desc);
4819 rx_q->rx_count_frames++;
4820 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4821 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4822 rx_q->rx_count_frames = 0;
4824 use_rx_wd = !priv->rx_coal_frames[queue];
4825 use_rx_wd |= rx_q->rx_count_frames > 0;
4826 if (!priv->use_riwt)
4830 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4832 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4836 rx_q->dirty_rx = entry;
4837 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4838 (rx_q->dirty_rx * sizeof(struct dma_desc));
4839 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4845 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
4847 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4848 unsigned int count = 0, error = 0, len = 0;
4849 int dirty = stmmac_rx_dirty(priv, queue);
4850 unsigned int next_entry = rx_q->cur_rx;
4851 unsigned int desc_size;
4852 struct bpf_prog *prog;
4853 bool failure = false;
4857 if (netif_msg_rx_status(priv)) {
4860 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
4861 if (priv->extend_desc) {
4862 rx_head = (void *)rx_q->dma_erx;
4863 desc_size = sizeof(struct dma_extended_desc);
4865 rx_head = (void *)rx_q->dma_rx;
4866 desc_size = sizeof(struct dma_desc);
4869 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
4870 rx_q->dma_rx_phy, desc_size);
4872 while (count < limit) {
4873 struct stmmac_rx_buffer *buf;
4874 unsigned int buf1_len = 0;
4875 struct dma_desc *np, *p;
4879 if (!count && rx_q->state_saved) {
4880 error = rx_q->state.error;
4881 len = rx_q->state.len;
4883 rx_q->state_saved = false;
4894 buf = &rx_q->buf_pool[entry];
4896 if (dirty >= STMMAC_RX_FILL_BATCH) {
4897 failure = failure ||
4898 !stmmac_rx_refill_zc(priv, queue, dirty);
4902 if (priv->extend_desc)
4903 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4905 p = rx_q->dma_rx + entry;
4907 /* read the status of the incoming frame */
4908 status = stmmac_rx_status(priv, &priv->dev->stats,
4910 /* check if managed by the DMA otherwise go ahead */
4911 if (unlikely(status & dma_own))
4914 /* Prefetch the next RX descriptor */
4915 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
4917 next_entry = rx_q->cur_rx;
4919 if (priv->extend_desc)
4920 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
4922 np = rx_q->dma_rx + next_entry;
4926 /* Ensure a valid XSK buffer before proceed */
4930 if (priv->extend_desc)
4931 stmmac_rx_extended_status(priv, &priv->dev->stats,
4933 rx_q->dma_erx + entry);
4934 if (unlikely(status == discard_frame)) {
4935 xsk_buff_free(buf->xdp);
4939 if (!priv->hwts_rx_en)
4940 priv->dev->stats.rx_errors++;
4943 if (unlikely(error && (status & rx_not_ls)))
4945 if (unlikely(error)) {
4950 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
4951 if (likely(status & rx_not_ls)) {
4952 xsk_buff_free(buf->xdp);
4959 /* XDP ZC Frame only support primary buffers for now */
4960 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
4963 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
4964 * Type frames (LLC/LLC-SNAP)
4966 * llc_snap is never checked in GMAC >= 4, so this ACS
4967 * feature is always disabled and packets need to be
4968 * stripped manually.
4970 if (likely(!(status & rx_not_ls)) &&
4971 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
4972 unlikely(status != llc_snap))) {
4973 buf1_len -= ETH_FCS_LEN;
4977 /* RX buffer is good and fit into a XSK pool buffer */
4978 buf->xdp->data_end = buf->xdp->data + buf1_len;
4979 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
4981 prog = READ_ONCE(priv->xdp_prog);
4982 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
4985 case STMMAC_XDP_PASS:
4986 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
4987 xsk_buff_free(buf->xdp);
4989 case STMMAC_XDP_CONSUMED:
4990 xsk_buff_free(buf->xdp);
4991 priv->dev->stats.rx_dropped++;
4994 case STMMAC_XDP_REDIRECT:
5004 if (status & rx_not_ls) {
5005 rx_q->state_saved = true;
5006 rx_q->state.error = error;
5007 rx_q->state.len = len;
5010 stmmac_finalize_xdp_rx(priv, xdp_status);
5012 priv->xstats.rx_pkt_n += count;
5013 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5015 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5016 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5017 xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5019 xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5024 return failure ? limit : (int)count;
5028 * stmmac_rx - manage the receive process
5029 * @priv: driver private structure
5030 * @limit: napi bugget
5031 * @queue: RX queue index.
5032 * Description : this the function called by the napi poll method.
5033 * It gets all the frames inside the ring.
5035 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5037 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5038 struct stmmac_channel *ch = &priv->channel[queue];
5039 unsigned int count = 0, error = 0, len = 0;
5040 int status = 0, coe = priv->hw->rx_csum;
5041 unsigned int next_entry = rx_q->cur_rx;
5042 enum dma_data_direction dma_dir;
5043 unsigned int desc_size;
5044 struct sk_buff *skb = NULL;
5045 struct xdp_buff xdp;
5049 dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5050 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5052 if (netif_msg_rx_status(priv)) {
5055 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5056 if (priv->extend_desc) {
5057 rx_head = (void *)rx_q->dma_erx;
5058 desc_size = sizeof(struct dma_extended_desc);
5060 rx_head = (void *)rx_q->dma_rx;
5061 desc_size = sizeof(struct dma_desc);
5064 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
5065 rx_q->dma_rx_phy, desc_size);
5067 while (count < limit) {
5068 unsigned int buf1_len = 0, buf2_len = 0;
5069 enum pkt_hash_types hash_type;
5070 struct stmmac_rx_buffer *buf;
5071 struct dma_desc *np, *p;
5075 if (!count && rx_q->state_saved) {
5076 skb = rx_q->state.skb;
5077 error = rx_q->state.error;
5078 len = rx_q->state.len;
5080 rx_q->state_saved = false;
5093 buf = &rx_q->buf_pool[entry];
5095 if (priv->extend_desc)
5096 p = (struct dma_desc *)(rx_q->dma_erx + entry);
5098 p = rx_q->dma_rx + entry;
5100 /* read the status of the incoming frame */
5101 status = stmmac_rx_status(priv, &priv->dev->stats,
5103 /* check if managed by the DMA otherwise go ahead */
5104 if (unlikely(status & dma_own))
5107 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5109 next_entry = rx_q->cur_rx;
5111 if (priv->extend_desc)
5112 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5114 np = rx_q->dma_rx + next_entry;
5118 if (priv->extend_desc)
5119 stmmac_rx_extended_status(priv, &priv->dev->stats,
5120 &priv->xstats, rx_q->dma_erx + entry);
5121 if (unlikely(status == discard_frame)) {
5122 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5125 if (!priv->hwts_rx_en)
5126 priv->dev->stats.rx_errors++;
5129 if (unlikely(error && (status & rx_not_ls)))
5131 if (unlikely(error)) {
5138 /* Buffer is good. Go on. */
5140 prefetch(page_address(buf->page) + buf->page_offset);
5142 prefetch(page_address(buf->sec_page));
5144 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5146 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5149 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5150 * Type frames (LLC/LLC-SNAP)
5152 * llc_snap is never checked in GMAC >= 4, so this ACS
5153 * feature is always disabled and packets need to be
5154 * stripped manually.
5156 if (likely(!(status & rx_not_ls)) &&
5157 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5158 unlikely(status != llc_snap))) {
5160 buf2_len -= ETH_FCS_LEN;
5162 buf1_len -= ETH_FCS_LEN;
5168 unsigned int pre_len, sync_len;
5170 dma_sync_single_for_cpu(priv->device, buf->addr,
5173 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq);
5174 xdp_prepare_buff(&xdp, page_address(buf->page),
5175 buf->page_offset, buf1_len, false);
5177 pre_len = xdp.data_end - xdp.data_hard_start -
5179 skb = stmmac_xdp_run_prog(priv, &xdp);
5180 /* Due xdp_adjust_tail: DMA sync for_device
5181 * cover max len CPU touch
5183 sync_len = xdp.data_end - xdp.data_hard_start -
5185 sync_len = max(sync_len, pre_len);
5187 /* For Not XDP_PASS verdict */
5189 unsigned int xdp_res = -PTR_ERR(skb);
5191 if (xdp_res & STMMAC_XDP_CONSUMED) {
5192 page_pool_put_page(rx_q->page_pool,
5193 virt_to_head_page(xdp.data),
5196 priv->dev->stats.rx_dropped++;
5198 /* Clear skb as it was set as
5199 * status by XDP program.
5203 if (unlikely((status & rx_not_ls)))
5208 } else if (xdp_res & (STMMAC_XDP_TX |
5209 STMMAC_XDP_REDIRECT)) {
5210 xdp_status |= xdp_res;
5220 /* XDP program may expand or reduce tail */
5221 buf1_len = xdp.data_end - xdp.data;
5223 skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5225 priv->dev->stats.rx_dropped++;
5230 /* XDP program may adjust header */
5231 skb_copy_to_linear_data(skb, xdp.data, buf1_len);
5232 skb_put(skb, buf1_len);
5234 /* Data payload copied into SKB, page ready for recycle */
5235 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5237 } else if (buf1_len) {
5238 dma_sync_single_for_cpu(priv->device, buf->addr,
5240 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5241 buf->page, buf->page_offset, buf1_len,
5244 /* Data payload appended into SKB */
5245 page_pool_release_page(rx_q->page_pool, buf->page);
5250 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5252 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5253 buf->sec_page, 0, buf2_len,
5256 /* Data payload appended into SKB */
5257 page_pool_release_page(rx_q->page_pool, buf->sec_page);
5258 buf->sec_page = NULL;
5262 if (likely(status & rx_not_ls))
5267 /* Got entire packet into SKB. Finish it. */
5269 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5270 stmmac_rx_vlan(priv->dev, skb);
5271 skb->protocol = eth_type_trans(skb, priv->dev);
5274 skb_checksum_none_assert(skb);
5276 skb->ip_summed = CHECKSUM_UNNECESSARY;
5278 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5279 skb_set_hash(skb, hash, hash_type);
5281 skb_record_rx_queue(skb, queue);
5282 napi_gro_receive(&ch->rx_napi, skb);
5285 priv->dev->stats.rx_packets++;
5286 priv->dev->stats.rx_bytes += len;
5290 if (status & rx_not_ls || skb) {
5291 rx_q->state_saved = true;
5292 rx_q->state.skb = skb;
5293 rx_q->state.error = error;
5294 rx_q->state.len = len;
5297 stmmac_finalize_xdp_rx(priv, xdp_status);
5299 stmmac_rx_refill(priv, queue);
5301 priv->xstats.rx_pkt_n += count;
5302 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5307 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5309 struct stmmac_channel *ch =
5310 container_of(napi, struct stmmac_channel, rx_napi);
5311 struct stmmac_priv *priv = ch->priv_data;
5312 u32 chan = ch->index;
5315 priv->xstats.napi_poll++;
5317 work_done = stmmac_rx(priv, budget, chan);
5318 if (work_done < budget && napi_complete_done(napi, work_done)) {
5319 unsigned long flags;
5321 spin_lock_irqsave(&ch->lock, flags);
5322 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5323 spin_unlock_irqrestore(&ch->lock, flags);
5329 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5331 struct stmmac_channel *ch =
5332 container_of(napi, struct stmmac_channel, tx_napi);
5333 struct stmmac_priv *priv = ch->priv_data;
5334 u32 chan = ch->index;
5337 priv->xstats.napi_poll++;
5339 work_done = stmmac_tx_clean(priv, budget, chan);
5340 work_done = min(work_done, budget);
5342 if (work_done < budget && napi_complete_done(napi, work_done)) {
5343 unsigned long flags;
5345 spin_lock_irqsave(&ch->lock, flags);
5346 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5347 spin_unlock_irqrestore(&ch->lock, flags);
5353 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5355 struct stmmac_channel *ch =
5356 container_of(napi, struct stmmac_channel, rxtx_napi);
5357 struct stmmac_priv *priv = ch->priv_data;
5358 int rx_done, tx_done, rxtx_done;
5359 u32 chan = ch->index;
5361 priv->xstats.napi_poll++;
5363 tx_done = stmmac_tx_clean(priv, budget, chan);
5364 tx_done = min(tx_done, budget);
5366 rx_done = stmmac_rx_zc(priv, budget, chan);
5368 rxtx_done = max(tx_done, rx_done);
5370 /* If either TX or RX work is not complete, return budget
5373 if (rxtx_done >= budget)
5376 /* all work done, exit the polling mode */
5377 if (napi_complete_done(napi, rxtx_done)) {
5378 unsigned long flags;
5380 spin_lock_irqsave(&ch->lock, flags);
5381 /* Both RX and TX work done are compelte,
5382 * so enable both RX & TX IRQs.
5384 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5385 spin_unlock_irqrestore(&ch->lock, flags);
5388 return min(rxtx_done, budget - 1);
5393 * @dev : Pointer to net device structure
5394 * @txqueue: the index of the hanging transmit queue
5395 * Description: this function is called when a packet transmission fails to
5396 * complete within a reasonable time. The driver will mark the error in the
5397 * netdev structure and arrange for the device to be reset to a sane state
5398 * in order to transmit a new packet.
5400 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5402 struct stmmac_priv *priv = netdev_priv(dev);
5404 stmmac_global_err(priv);
5408 * stmmac_set_rx_mode - entry point for multicast addressing
5409 * @dev : pointer to the device structure
5411 * This function is a driver entry point which gets called by the kernel
5412 * whenever multicast addresses must be enabled/disabled.
5416 static void stmmac_set_rx_mode(struct net_device *dev)
5418 struct stmmac_priv *priv = netdev_priv(dev);
5420 stmmac_set_filter(priv, priv->hw, dev);
5424 * stmmac_change_mtu - entry point to change MTU size for the device.
5425 * @dev : device pointer.
5426 * @new_mtu : the new MTU size for the device.
5427 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
5428 * to drive packet transmission. Ethernet has an MTU of 1500 octets
5429 * (ETH_DATA_LEN). This value can be changed with ifconfig.
5431 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5434 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5436 struct stmmac_priv *priv = netdev_priv(dev);
5437 int txfifosz = priv->plat->tx_fifo_size;
5438 const int mtu = new_mtu;
5441 txfifosz = priv->dma_cap.tx_fifo_size;
5443 txfifosz /= priv->plat->tx_queues_to_use;
5445 if (netif_running(dev)) {
5446 netdev_err(priv->dev, "must be stopped to change its MTU\n");
5450 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5451 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5455 new_mtu = STMMAC_ALIGN(new_mtu);
5457 /* If condition true, FIFO is too small or MTU too large */
5458 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5463 netdev_update_features(dev);
5468 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5469 netdev_features_t features)
5471 struct stmmac_priv *priv = netdev_priv(dev);
5473 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5474 features &= ~NETIF_F_RXCSUM;
5476 if (!priv->plat->tx_coe)
5477 features &= ~NETIF_F_CSUM_MASK;
5479 /* Some GMAC devices have a bugged Jumbo frame support that
5480 * needs to have the Tx COE disabled for oversized frames
5481 * (due to limited buffer sizes). In this case we disable
5482 * the TX csum insertion in the TDES and not use SF.
5484 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5485 features &= ~NETIF_F_CSUM_MASK;
5487 /* Disable tso if asked by ethtool */
5488 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
5489 if (features & NETIF_F_TSO)
5498 static int stmmac_set_features(struct net_device *netdev,
5499 netdev_features_t features)
5501 struct stmmac_priv *priv = netdev_priv(netdev);
5505 /* Keep the COE Type in case of csum is supporting */
5506 if (features & NETIF_F_RXCSUM)
5507 priv->hw->rx_csum = priv->plat->rx_coe;
5509 priv->hw->rx_csum = 0;
5510 /* No check needed because rx_coe has been set before and it will be
5511 * fixed in case of issue.
5513 stmmac_rx_ipc(priv, priv->hw);
5515 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5517 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5518 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5523 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5525 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5526 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5527 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5528 bool *hs_enable = &fpe_cfg->hs_enable;
5530 if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5533 /* If LP has sent verify mPacket, LP is FPE capable */
5534 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5535 if (*lp_state < FPE_STATE_CAPABLE)
5536 *lp_state = FPE_STATE_CAPABLE;
5538 /* If user has requested FPE enable, quickly response */
5540 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5544 /* If Local has sent verify mPacket, Local is FPE capable */
5545 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5546 if (*lo_state < FPE_STATE_CAPABLE)
5547 *lo_state = FPE_STATE_CAPABLE;
5550 /* If LP has sent response mPacket, LP is entering FPE ON */
5551 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5552 *lp_state = FPE_STATE_ENTERING_ON;
5554 /* If Local has sent response mPacket, Local is entering FPE ON */
5555 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5556 *lo_state = FPE_STATE_ENTERING_ON;
5558 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5559 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5561 queue_work(priv->fpe_wq, &priv->fpe_task);
5565 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5567 u32 rx_cnt = priv->plat->rx_queues_to_use;
5568 u32 tx_cnt = priv->plat->tx_queues_to_use;
5573 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5574 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5577 pm_wakeup_event(priv->device, 0);
5579 if (priv->dma_cap.estsel)
5580 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5581 &priv->xstats, tx_cnt);
5583 if (priv->dma_cap.fpesel) {
5584 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5587 stmmac_fpe_event_status(priv, status);
5590 /* To handle GMAC own interrupts */
5591 if ((priv->plat->has_gmac) || xmac) {
5592 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5594 if (unlikely(status)) {
5595 /* For LPI we need to save the tx status */
5596 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5597 priv->tx_path_in_lpi_mode = true;
5598 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5599 priv->tx_path_in_lpi_mode = false;
5602 for (queue = 0; queue < queues_count; queue++) {
5603 status = stmmac_host_mtl_irq_status(priv, priv->hw,
5607 /* PCS link status */
5608 if (priv->hw->pcs) {
5609 if (priv->xstats.pcs_link)
5610 netif_carrier_on(priv->dev);
5612 netif_carrier_off(priv->dev);
5615 stmmac_timestamp_interrupt(priv, priv);
5620 * stmmac_interrupt - main ISR
5621 * @irq: interrupt number.
5622 * @dev_id: to pass the net device pointer.
5623 * Description: this is the main driver interrupt service routine.
5625 * o DMA service routine (to manage incoming frame reception and transmission
5627 * o Core interrupts to manage: remote wake-up, management counter, LPI
5630 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5632 struct net_device *dev = (struct net_device *)dev_id;
5633 struct stmmac_priv *priv = netdev_priv(dev);
5635 /* Check if adapter is up */
5636 if (test_bit(STMMAC_DOWN, &priv->state))
5639 /* Check if a fatal error happened */
5640 if (stmmac_safety_feat_interrupt(priv))
5643 /* To handle Common interrupts */
5644 stmmac_common_interrupt(priv);
5646 /* To handle DMA interrupts */
5647 stmmac_dma_interrupt(priv);
5652 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5654 struct net_device *dev = (struct net_device *)dev_id;
5655 struct stmmac_priv *priv = netdev_priv(dev);
5657 if (unlikely(!dev)) {
5658 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5662 /* Check if adapter is up */
5663 if (test_bit(STMMAC_DOWN, &priv->state))
5666 /* To handle Common interrupts */
5667 stmmac_common_interrupt(priv);
5672 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5674 struct net_device *dev = (struct net_device *)dev_id;
5675 struct stmmac_priv *priv = netdev_priv(dev);
5677 if (unlikely(!dev)) {
5678 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5682 /* Check if adapter is up */
5683 if (test_bit(STMMAC_DOWN, &priv->state))
5686 /* Check if a fatal error happened */
5687 stmmac_safety_feat_interrupt(priv);
5692 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5694 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5695 int chan = tx_q->queue_index;
5696 struct stmmac_priv *priv;
5699 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]);
5701 if (unlikely(!data)) {
5702 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5706 /* Check if adapter is up */
5707 if (test_bit(STMMAC_DOWN, &priv->state))
5710 status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5712 if (unlikely(status & tx_hard_error_bump_tc)) {
5713 /* Try to bump up the dma threshold on this failure */
5714 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
5717 if (priv->plat->force_thresh_dma_mode)
5718 stmmac_set_dma_operation_mode(priv,
5723 stmmac_set_dma_operation_mode(priv,
5727 priv->xstats.threshold = tc;
5729 } else if (unlikely(status == tx_hard_error)) {
5730 stmmac_tx_err(priv, chan);
5736 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5738 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5739 int chan = rx_q->queue_index;
5740 struct stmmac_priv *priv;
5742 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]);
5744 if (unlikely(!data)) {
5745 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5749 /* Check if adapter is up */
5750 if (test_bit(STMMAC_DOWN, &priv->state))
5753 stmmac_napi_check(priv, chan, DMA_DIR_RX);
5758 #ifdef CONFIG_NET_POLL_CONTROLLER
5759 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5760 * to allow network I/O with interrupts disabled.
5762 static void stmmac_poll_controller(struct net_device *dev)
5764 struct stmmac_priv *priv = netdev_priv(dev);
5767 /* If adapter is down, do nothing */
5768 if (test_bit(STMMAC_DOWN, &priv->state))
5771 if (priv->plat->multi_msi_en) {
5772 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5773 stmmac_msi_intr_rx(0, &priv->rx_queue[i]);
5775 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5776 stmmac_msi_intr_tx(0, &priv->tx_queue[i]);
5778 disable_irq(dev->irq);
5779 stmmac_interrupt(dev->irq, dev);
5780 enable_irq(dev->irq);
5786 * stmmac_ioctl - Entry point for the Ioctl
5787 * @dev: Device pointer.
5788 * @rq: An IOCTL specefic structure, that can contain a pointer to
5789 * a proprietary structure used to pass information to the driver.
5790 * @cmd: IOCTL command
5792 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5794 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5796 struct stmmac_priv *priv = netdev_priv (dev);
5797 int ret = -EOPNOTSUPP;
5799 if (!netif_running(dev))
5806 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5809 ret = stmmac_hwtstamp_set(dev, rq);
5812 ret = stmmac_hwtstamp_get(dev, rq);
5821 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5824 struct stmmac_priv *priv = cb_priv;
5825 int ret = -EOPNOTSUPP;
5827 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
5830 __stmmac_disable_all_queues(priv);
5833 case TC_SETUP_CLSU32:
5834 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
5836 case TC_SETUP_CLSFLOWER:
5837 ret = stmmac_tc_setup_cls(priv, priv, type_data);
5843 stmmac_enable_all_queues(priv);
5847 static LIST_HEAD(stmmac_block_cb_list);
5849 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
5852 struct stmmac_priv *priv = netdev_priv(ndev);
5855 case TC_SETUP_BLOCK:
5856 return flow_block_cb_setup_simple(type_data,
5857 &stmmac_block_cb_list,
5858 stmmac_setup_tc_block_cb,
5860 case TC_SETUP_QDISC_CBS:
5861 return stmmac_tc_setup_cbs(priv, priv, type_data);
5862 case TC_SETUP_QDISC_TAPRIO:
5863 return stmmac_tc_setup_taprio(priv, priv, type_data);
5864 case TC_SETUP_QDISC_ETF:
5865 return stmmac_tc_setup_etf(priv, priv, type_data);
5871 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
5872 struct net_device *sb_dev)
5874 int gso = skb_shinfo(skb)->gso_type;
5876 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
5878 * There is no way to determine the number of TSO/USO
5879 * capable Queues. Let's use always the Queue 0
5880 * because if TSO/USO is supported then at least this
5881 * one will be capable.
5886 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
5889 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
5891 struct stmmac_priv *priv = netdev_priv(ndev);
5894 ret = pm_runtime_get_sync(priv->device);
5896 pm_runtime_put_noidle(priv->device);
5900 ret = eth_mac_addr(ndev, addr);
5904 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
5907 pm_runtime_put(priv->device);
5912 #ifdef CONFIG_DEBUG_FS
5913 static struct dentry *stmmac_fs_dir;
5915 static void sysfs_display_ring(void *head, int size, int extend_desc,
5916 struct seq_file *seq, dma_addr_t dma_phy_addr)
5919 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
5920 struct dma_desc *p = (struct dma_desc *)head;
5921 dma_addr_t dma_addr;
5923 for (i = 0; i < size; i++) {
5925 dma_addr = dma_phy_addr + i * sizeof(*ep);
5926 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5928 le32_to_cpu(ep->basic.des0),
5929 le32_to_cpu(ep->basic.des1),
5930 le32_to_cpu(ep->basic.des2),
5931 le32_to_cpu(ep->basic.des3));
5934 dma_addr = dma_phy_addr + i * sizeof(*p);
5935 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5937 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
5938 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
5941 seq_printf(seq, "\n");
5945 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
5947 struct net_device *dev = seq->private;
5948 struct stmmac_priv *priv = netdev_priv(dev);
5949 u32 rx_count = priv->plat->rx_queues_to_use;
5950 u32 tx_count = priv->plat->tx_queues_to_use;
5953 if ((dev->flags & IFF_UP) == 0)
5956 for (queue = 0; queue < rx_count; queue++) {
5957 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5959 seq_printf(seq, "RX Queue %d:\n", queue);
5961 if (priv->extend_desc) {
5962 seq_printf(seq, "Extended descriptor ring:\n");
5963 sysfs_display_ring((void *)rx_q->dma_erx,
5964 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy);
5966 seq_printf(seq, "Descriptor ring:\n");
5967 sysfs_display_ring((void *)rx_q->dma_rx,
5968 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy);
5972 for (queue = 0; queue < tx_count; queue++) {
5973 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5975 seq_printf(seq, "TX Queue %d:\n", queue);
5977 if (priv->extend_desc) {
5978 seq_printf(seq, "Extended descriptor ring:\n");
5979 sysfs_display_ring((void *)tx_q->dma_etx,
5980 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy);
5981 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
5982 seq_printf(seq, "Descriptor ring:\n");
5983 sysfs_display_ring((void *)tx_q->dma_tx,
5984 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy);
5990 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
5992 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
5994 struct net_device *dev = seq->private;
5995 struct stmmac_priv *priv = netdev_priv(dev);
5997 if (!priv->hw_cap_support) {
5998 seq_printf(seq, "DMA HW features not supported\n");
6002 seq_printf(seq, "==============================\n");
6003 seq_printf(seq, "\tDMA HW features\n");
6004 seq_printf(seq, "==============================\n");
6006 seq_printf(seq, "\t10/100 Mbps: %s\n",
6007 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6008 seq_printf(seq, "\t1000 Mbps: %s\n",
6009 (priv->dma_cap.mbps_1000) ? "Y" : "N");
6010 seq_printf(seq, "\tHalf duplex: %s\n",
6011 (priv->dma_cap.half_duplex) ? "Y" : "N");
6012 seq_printf(seq, "\tHash Filter: %s\n",
6013 (priv->dma_cap.hash_filter) ? "Y" : "N");
6014 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6015 (priv->dma_cap.multi_addr) ? "Y" : "N");
6016 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6017 (priv->dma_cap.pcs) ? "Y" : "N");
6018 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6019 (priv->dma_cap.sma_mdio) ? "Y" : "N");
6020 seq_printf(seq, "\tPMT Remote wake up: %s\n",
6021 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6022 seq_printf(seq, "\tPMT Magic Frame: %s\n",
6023 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6024 seq_printf(seq, "\tRMON module: %s\n",
6025 (priv->dma_cap.rmon) ? "Y" : "N");
6026 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6027 (priv->dma_cap.time_stamp) ? "Y" : "N");
6028 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6029 (priv->dma_cap.atime_stamp) ? "Y" : "N");
6030 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6031 (priv->dma_cap.eee) ? "Y" : "N");
6032 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6033 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6034 (priv->dma_cap.tx_coe) ? "Y" : "N");
6035 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6036 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6037 (priv->dma_cap.rx_coe) ? "Y" : "N");
6039 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6040 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6041 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6042 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6044 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6045 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6046 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6047 priv->dma_cap.number_rx_channel);
6048 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6049 priv->dma_cap.number_tx_channel);
6050 seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6051 priv->dma_cap.number_rx_queues);
6052 seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6053 priv->dma_cap.number_tx_queues);
6054 seq_printf(seq, "\tEnhanced descriptors: %s\n",
6055 (priv->dma_cap.enh_desc) ? "Y" : "N");
6056 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6057 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6058 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6059 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6060 seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6061 priv->dma_cap.pps_out_num);
6062 seq_printf(seq, "\tSafety Features: %s\n",
6063 priv->dma_cap.asp ? "Y" : "N");
6064 seq_printf(seq, "\tFlexible RX Parser: %s\n",
6065 priv->dma_cap.frpsel ? "Y" : "N");
6066 seq_printf(seq, "\tEnhanced Addressing: %d\n",
6067 priv->dma_cap.addr64);
6068 seq_printf(seq, "\tReceive Side Scaling: %s\n",
6069 priv->dma_cap.rssen ? "Y" : "N");
6070 seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6071 priv->dma_cap.vlhash ? "Y" : "N");
6072 seq_printf(seq, "\tSplit Header: %s\n",
6073 priv->dma_cap.sphen ? "Y" : "N");
6074 seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6075 priv->dma_cap.vlins ? "Y" : "N");
6076 seq_printf(seq, "\tDouble VLAN: %s\n",
6077 priv->dma_cap.dvlan ? "Y" : "N");
6078 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6079 priv->dma_cap.l3l4fnum);
6080 seq_printf(seq, "\tARP Offloading: %s\n",
6081 priv->dma_cap.arpoffsel ? "Y" : "N");
6082 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6083 priv->dma_cap.estsel ? "Y" : "N");
6084 seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6085 priv->dma_cap.fpesel ? "Y" : "N");
6086 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6087 priv->dma_cap.tbssel ? "Y" : "N");
6090 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6092 /* Use network device events to rename debugfs file entries.
6094 static int stmmac_device_event(struct notifier_block *unused,
6095 unsigned long event, void *ptr)
6097 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6098 struct stmmac_priv *priv = netdev_priv(dev);
6100 if (dev->netdev_ops != &stmmac_netdev_ops)
6104 case NETDEV_CHANGENAME:
6105 if (priv->dbgfs_dir)
6106 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6116 static struct notifier_block stmmac_notifier = {
6117 .notifier_call = stmmac_device_event,
6120 static void stmmac_init_fs(struct net_device *dev)
6122 struct stmmac_priv *priv = netdev_priv(dev);
6126 /* Create per netdev entries */
6127 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6129 /* Entry to report DMA RX/TX rings */
6130 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6131 &stmmac_rings_status_fops);
6133 /* Entry to report the DMA HW features */
6134 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6135 &stmmac_dma_cap_fops);
6140 static void stmmac_exit_fs(struct net_device *dev)
6142 struct stmmac_priv *priv = netdev_priv(dev);
6144 debugfs_remove_recursive(priv->dbgfs_dir);
6146 #endif /* CONFIG_DEBUG_FS */
6148 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6150 unsigned char *data = (unsigned char *)&vid_le;
6151 unsigned char data_byte = 0;
6156 bits = get_bitmask_order(VLAN_VID_MASK);
6157 for (i = 0; i < bits; i++) {
6159 data_byte = data[i / 8];
6161 temp = ((crc & 1) ^ data_byte) & 1;
6172 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6179 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6180 __le16 vid_le = cpu_to_le16(vid);
6181 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6186 if (!priv->dma_cap.vlhash) {
6187 if (count > 2) /* VID = 0 always passes filter */
6190 pmatch = cpu_to_le16(vid);
6194 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6197 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6199 struct stmmac_priv *priv = netdev_priv(ndev);
6200 bool is_double = false;
6203 if (be16_to_cpu(proto) == ETH_P_8021AD)
6206 set_bit(vid, priv->active_vlans);
6207 ret = stmmac_vlan_update(priv, is_double);
6209 clear_bit(vid, priv->active_vlans);
6213 if (priv->hw->num_vlan) {
6214 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6222 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6224 struct stmmac_priv *priv = netdev_priv(ndev);
6225 bool is_double = false;
6228 ret = pm_runtime_get_sync(priv->device);
6230 pm_runtime_put_noidle(priv->device);
6234 if (be16_to_cpu(proto) == ETH_P_8021AD)
6237 clear_bit(vid, priv->active_vlans);
6239 if (priv->hw->num_vlan) {
6240 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6242 goto del_vlan_error;
6245 ret = stmmac_vlan_update(priv, is_double);
6248 pm_runtime_put(priv->device);
6253 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6255 struct stmmac_priv *priv = netdev_priv(dev);
6257 switch (bpf->command) {
6258 case XDP_SETUP_PROG:
6259 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6260 case XDP_SETUP_XSK_POOL:
6261 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6268 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6269 struct xdp_frame **frames, u32 flags)
6271 struct stmmac_priv *priv = netdev_priv(dev);
6272 int cpu = smp_processor_id();
6273 struct netdev_queue *nq;
6277 if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6280 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6283 queue = stmmac_xdp_get_tx_queue(priv, cpu);
6284 nq = netdev_get_tx_queue(priv->dev, queue);
6286 __netif_tx_lock(nq, cpu);
6287 /* Avoids TX time-out as we are sharing with slow path */
6288 nq->trans_start = jiffies;
6290 for (i = 0; i < num_frames; i++) {
6293 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6294 if (res == STMMAC_XDP_CONSUMED)
6300 if (flags & XDP_XMIT_FLUSH) {
6301 stmmac_flush_tx_descriptors(priv, queue);
6302 stmmac_tx_timer_arm(priv, queue);
6305 __netif_tx_unlock(nq);
6310 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6312 struct stmmac_channel *ch = &priv->channel[queue];
6313 unsigned long flags;
6315 spin_lock_irqsave(&ch->lock, flags);
6316 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6317 spin_unlock_irqrestore(&ch->lock, flags);
6319 stmmac_stop_rx_dma(priv, queue);
6320 __free_dma_rx_desc_resources(priv, queue);
6323 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6325 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
6326 struct stmmac_channel *ch = &priv->channel[queue];
6327 unsigned long flags;
6331 ret = __alloc_dma_rx_desc_resources(priv, queue);
6333 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6337 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL);
6339 __free_dma_rx_desc_resources(priv, queue);
6340 netdev_err(priv->dev, "Failed to init RX desc.\n");
6344 stmmac_clear_rx_descriptors(priv, queue);
6346 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6347 rx_q->dma_rx_phy, rx_q->queue_index);
6349 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6350 sizeof(struct dma_desc));
6351 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6352 rx_q->rx_tail_addr, rx_q->queue_index);
6354 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6355 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6356 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6360 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6365 stmmac_start_rx_dma(priv, queue);
6367 spin_lock_irqsave(&ch->lock, flags);
6368 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6369 spin_unlock_irqrestore(&ch->lock, flags);
6372 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6374 struct stmmac_channel *ch = &priv->channel[queue];
6375 unsigned long flags;
6377 spin_lock_irqsave(&ch->lock, flags);
6378 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6379 spin_unlock_irqrestore(&ch->lock, flags);
6381 stmmac_stop_tx_dma(priv, queue);
6382 __free_dma_tx_desc_resources(priv, queue);
6385 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6387 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6388 struct stmmac_channel *ch = &priv->channel[queue];
6389 unsigned long flags;
6392 ret = __alloc_dma_tx_desc_resources(priv, queue);
6394 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6398 ret = __init_dma_tx_desc_rings(priv, queue);
6400 __free_dma_tx_desc_resources(priv, queue);
6401 netdev_err(priv->dev, "Failed to init TX desc.\n");
6405 stmmac_clear_tx_descriptors(priv, queue);
6407 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6408 tx_q->dma_tx_phy, tx_q->queue_index);
6410 if (tx_q->tbs & STMMAC_TBS_AVAIL)
6411 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6413 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6414 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6415 tx_q->tx_tail_addr, tx_q->queue_index);
6417 stmmac_start_tx_dma(priv, queue);
6419 spin_lock_irqsave(&ch->lock, flags);
6420 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6421 spin_unlock_irqrestore(&ch->lock, flags);
6424 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6426 struct stmmac_priv *priv = netdev_priv(dev);
6427 struct stmmac_rx_queue *rx_q;
6428 struct stmmac_tx_queue *tx_q;
6429 struct stmmac_channel *ch;
6431 if (test_bit(STMMAC_DOWN, &priv->state) ||
6432 !netif_carrier_ok(priv->dev))
6435 if (!stmmac_xdp_is_enabled(priv))
6438 if (queue >= priv->plat->rx_queues_to_use ||
6439 queue >= priv->plat->tx_queues_to_use)
6442 rx_q = &priv->rx_queue[queue];
6443 tx_q = &priv->tx_queue[queue];
6444 ch = &priv->channel[queue];
6446 if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6449 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6450 /* EQoS does not have per-DMA channel SW interrupt,
6451 * so we schedule RX Napi straight-away.
6453 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6454 __napi_schedule(&ch->rxtx_napi);
6460 static const struct net_device_ops stmmac_netdev_ops = {
6461 .ndo_open = stmmac_open,
6462 .ndo_start_xmit = stmmac_xmit,
6463 .ndo_stop = stmmac_release,
6464 .ndo_change_mtu = stmmac_change_mtu,
6465 .ndo_fix_features = stmmac_fix_features,
6466 .ndo_set_features = stmmac_set_features,
6467 .ndo_set_rx_mode = stmmac_set_rx_mode,
6468 .ndo_tx_timeout = stmmac_tx_timeout,
6469 .ndo_eth_ioctl = stmmac_ioctl,
6470 .ndo_setup_tc = stmmac_setup_tc,
6471 .ndo_select_queue = stmmac_select_queue,
6472 #ifdef CONFIG_NET_POLL_CONTROLLER
6473 .ndo_poll_controller = stmmac_poll_controller,
6475 .ndo_set_mac_address = stmmac_set_mac_address,
6476 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6477 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6478 .ndo_bpf = stmmac_bpf,
6479 .ndo_xdp_xmit = stmmac_xdp_xmit,
6480 .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6483 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6485 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6487 if (test_bit(STMMAC_DOWN, &priv->state))
6490 netdev_err(priv->dev, "Reset adapter.\n");
6493 netif_trans_update(priv->dev);
6494 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6495 usleep_range(1000, 2000);
6497 set_bit(STMMAC_DOWN, &priv->state);
6498 dev_close(priv->dev);
6499 dev_open(priv->dev, NULL);
6500 clear_bit(STMMAC_DOWN, &priv->state);
6501 clear_bit(STMMAC_RESETING, &priv->state);
6505 static void stmmac_service_task(struct work_struct *work)
6507 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6510 stmmac_reset_subtask(priv);
6511 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6515 * stmmac_hw_init - Init the MAC device
6516 * @priv: driver private structure
6517 * Description: this function is to configure the MAC device according to
6518 * some platform parameters or the HW capability register. It prepares the
6519 * driver to use either ring or chain modes and to setup either enhanced or
6520 * normal descriptors.
6522 static int stmmac_hw_init(struct stmmac_priv *priv)
6526 /* dwmac-sun8i only work in chain mode */
6527 if (priv->plat->has_sun8i)
6529 priv->chain_mode = chain_mode;
6531 /* Initialize HW Interface */
6532 ret = stmmac_hwif_init(priv);
6536 /* Get the HW capability (new GMAC newer than 3.50a) */
6537 priv->hw_cap_support = stmmac_get_hw_features(priv);
6538 if (priv->hw_cap_support) {
6539 dev_info(priv->device, "DMA HW capability register supported\n");
6541 /* We can override some gmac/dma configuration fields: e.g.
6542 * enh_desc, tx_coe (e.g. that are passed through the
6543 * platform) with the values from the HW capability
6544 * register (if supported).
6546 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6547 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6548 !priv->plat->use_phy_wol;
6549 priv->hw->pmt = priv->plat->pmt;
6550 if (priv->dma_cap.hash_tb_sz) {
6551 priv->hw->multicast_filter_bins =
6552 (BIT(priv->dma_cap.hash_tb_sz) << 5);
6553 priv->hw->mcast_bits_log2 =
6554 ilog2(priv->hw->multicast_filter_bins);
6557 /* TXCOE doesn't work in thresh DMA mode */
6558 if (priv->plat->force_thresh_dma_mode)
6559 priv->plat->tx_coe = 0;
6561 priv->plat->tx_coe = priv->dma_cap.tx_coe;
6563 /* In case of GMAC4 rx_coe is from HW cap register. */
6564 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6566 if (priv->dma_cap.rx_coe_type2)
6567 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6568 else if (priv->dma_cap.rx_coe_type1)
6569 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6572 dev_info(priv->device, "No HW DMA feature register supported\n");
6575 if (priv->plat->rx_coe) {
6576 priv->hw->rx_csum = priv->plat->rx_coe;
6577 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6578 if (priv->synopsys_id < DWMAC_CORE_4_00)
6579 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6581 if (priv->plat->tx_coe)
6582 dev_info(priv->device, "TX Checksum insertion supported\n");
6584 if (priv->plat->pmt) {
6585 dev_info(priv->device, "Wake-Up On Lan supported\n");
6586 device_set_wakeup_capable(priv->device, 1);
6589 if (priv->dma_cap.tsoen)
6590 dev_info(priv->device, "TSO supported\n");
6592 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6593 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6595 /* Run HW quirks, if any */
6596 if (priv->hwif_quirks) {
6597 ret = priv->hwif_quirks(priv);
6602 /* Rx Watchdog is available in the COREs newer than the 3.40.
6603 * In some case, for example on bugged HW this feature
6604 * has to be disable and this can be done by passing the
6605 * riwt_off field from the platform.
6607 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6608 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6610 dev_info(priv->device,
6611 "Enable RX Mitigation via HW Watchdog Timer\n");
6617 static void stmmac_napi_add(struct net_device *dev)
6619 struct stmmac_priv *priv = netdev_priv(dev);
6622 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6624 for (queue = 0; queue < maxq; queue++) {
6625 struct stmmac_channel *ch = &priv->channel[queue];
6627 ch->priv_data = priv;
6629 spin_lock_init(&ch->lock);
6631 if (queue < priv->plat->rx_queues_to_use) {
6632 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
6635 if (queue < priv->plat->tx_queues_to_use) {
6636 netif_tx_napi_add(dev, &ch->tx_napi,
6637 stmmac_napi_poll_tx,
6640 if (queue < priv->plat->rx_queues_to_use &&
6641 queue < priv->plat->tx_queues_to_use) {
6642 netif_napi_add(dev, &ch->rxtx_napi,
6643 stmmac_napi_poll_rxtx,
6649 static void stmmac_napi_del(struct net_device *dev)
6651 struct stmmac_priv *priv = netdev_priv(dev);
6654 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6656 for (queue = 0; queue < maxq; queue++) {
6657 struct stmmac_channel *ch = &priv->channel[queue];
6659 if (queue < priv->plat->rx_queues_to_use)
6660 netif_napi_del(&ch->rx_napi);
6661 if (queue < priv->plat->tx_queues_to_use)
6662 netif_napi_del(&ch->tx_napi);
6663 if (queue < priv->plat->rx_queues_to_use &&
6664 queue < priv->plat->tx_queues_to_use) {
6665 netif_napi_del(&ch->rxtx_napi);
6670 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
6672 struct stmmac_priv *priv = netdev_priv(dev);
6675 if (netif_running(dev))
6676 stmmac_release(dev);
6678 stmmac_napi_del(dev);
6680 priv->plat->rx_queues_to_use = rx_cnt;
6681 priv->plat->tx_queues_to_use = tx_cnt;
6683 stmmac_napi_add(dev);
6685 if (netif_running(dev))
6686 ret = stmmac_open(dev);
6691 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
6693 struct stmmac_priv *priv = netdev_priv(dev);
6696 if (netif_running(dev))
6697 stmmac_release(dev);
6699 priv->dma_rx_size = rx_size;
6700 priv->dma_tx_size = tx_size;
6702 if (netif_running(dev))
6703 ret = stmmac_open(dev);
6708 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
6709 static void stmmac_fpe_lp_task(struct work_struct *work)
6711 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6713 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
6714 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
6715 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
6716 bool *hs_enable = &fpe_cfg->hs_enable;
6717 bool *enable = &fpe_cfg->enable;
6720 while (retries-- > 0) {
6721 /* Bail out immediately if FPE handshake is OFF */
6722 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
6725 if (*lo_state == FPE_STATE_ENTERING_ON &&
6726 *lp_state == FPE_STATE_ENTERING_ON) {
6727 stmmac_fpe_configure(priv, priv->ioaddr,
6728 priv->plat->tx_queues_to_use,
6729 priv->plat->rx_queues_to_use,
6732 netdev_info(priv->dev, "configured FPE\n");
6734 *lo_state = FPE_STATE_ON;
6735 *lp_state = FPE_STATE_ON;
6736 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
6740 if ((*lo_state == FPE_STATE_CAPABLE ||
6741 *lo_state == FPE_STATE_ENTERING_ON) &&
6742 *lp_state != FPE_STATE_ON) {
6743 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
6744 *lo_state, *lp_state);
6745 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6748 /* Sleep then retry */
6752 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
6755 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
6757 if (priv->plat->fpe_cfg->hs_enable != enable) {
6759 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6762 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
6763 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
6766 priv->plat->fpe_cfg->hs_enable = enable;
6772 * @device: device pointer
6773 * @plat_dat: platform data pointer
6774 * @res: stmmac resource pointer
6775 * Description: this is the main probe function used to
6776 * call the alloc_etherdev, allocate the priv structure.
6778 * returns 0 on success, otherwise errno.
6780 int stmmac_dvr_probe(struct device *device,
6781 struct plat_stmmacenet_data *plat_dat,
6782 struct stmmac_resources *res)
6784 struct net_device *ndev = NULL;
6785 struct stmmac_priv *priv;
6789 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
6790 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
6794 SET_NETDEV_DEV(ndev, device);
6796 priv = netdev_priv(ndev);
6797 priv->device = device;
6800 stmmac_set_ethtool_ops(ndev);
6801 priv->pause = pause;
6802 priv->plat = plat_dat;
6803 priv->ioaddr = res->addr;
6804 priv->dev->base_addr = (unsigned long)res->addr;
6805 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
6807 priv->dev->irq = res->irq;
6808 priv->wol_irq = res->wol_irq;
6809 priv->lpi_irq = res->lpi_irq;
6810 priv->sfty_ce_irq = res->sfty_ce_irq;
6811 priv->sfty_ue_irq = res->sfty_ue_irq;
6812 for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
6813 priv->rx_irq[i] = res->rx_irq[i];
6814 for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
6815 priv->tx_irq[i] = res->tx_irq[i];
6817 if (!is_zero_ether_addr(res->mac))
6818 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
6820 dev_set_drvdata(device, priv->dev);
6822 /* Verify driver arguments */
6823 stmmac_verify_args();
6825 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
6826 if (!priv->af_xdp_zc_qps)
6829 /* Allocate workqueue */
6830 priv->wq = create_singlethread_workqueue("stmmac_wq");
6832 dev_err(priv->device, "failed to create workqueue\n");
6836 INIT_WORK(&priv->service_task, stmmac_service_task);
6838 /* Initialize Link Partner FPE workqueue */
6839 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
6841 /* Override with kernel parameters if supplied XXX CRS XXX
6842 * this needs to have multiple instances
6844 if ((phyaddr >= 0) && (phyaddr <= 31))
6845 priv->plat->phy_addr = phyaddr;
6847 if (priv->plat->stmmac_rst) {
6848 ret = reset_control_assert(priv->plat->stmmac_rst);
6849 reset_control_deassert(priv->plat->stmmac_rst);
6850 /* Some reset controllers have only reset callback instead of
6851 * assert + deassert callbacks pair.
6853 if (ret == -ENOTSUPP)
6854 reset_control_reset(priv->plat->stmmac_rst);
6857 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
6858 if (ret == -ENOTSUPP)
6859 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
6862 /* Init MAC and get the capabilities */
6863 ret = stmmac_hw_init(priv);
6867 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
6869 if (priv->synopsys_id < DWMAC_CORE_5_20)
6870 priv->plat->dma_cfg->dche = false;
6872 stmmac_check_ether_addr(priv);
6874 ndev->netdev_ops = &stmmac_netdev_ops;
6876 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6879 ret = stmmac_tc_init(priv, priv);
6881 ndev->hw_features |= NETIF_F_HW_TC;
6884 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
6885 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
6886 if (priv->plat->has_gmac4)
6887 ndev->hw_features |= NETIF_F_GSO_UDP_L4;
6889 dev_info(priv->device, "TSO feature enabled\n");
6892 if (priv->dma_cap.sphen) {
6893 ndev->hw_features |= NETIF_F_GRO;
6894 priv->sph_cap = true;
6895 priv->sph = priv->sph_cap;
6896 dev_info(priv->device, "SPH feature enabled\n");
6899 /* The current IP register MAC_HW_Feature1[ADDR64] only define
6900 * 32/40/64 bit width, but some SOC support others like i.MX8MP
6901 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
6902 * So overwrite dma_cap.addr64 according to HW real design.
6904 if (priv->plat->addr64)
6905 priv->dma_cap.addr64 = priv->plat->addr64;
6907 if (priv->dma_cap.addr64) {
6908 ret = dma_set_mask_and_coherent(device,
6909 DMA_BIT_MASK(priv->dma_cap.addr64));
6911 dev_info(priv->device, "Using %d bits DMA width\n",
6912 priv->dma_cap.addr64);
6915 * If more than 32 bits can be addressed, make sure to
6916 * enable enhanced addressing mode.
6918 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
6919 priv->plat->dma_cfg->eame = true;
6921 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
6923 dev_err(priv->device, "Failed to set DMA Mask\n");
6927 priv->dma_cap.addr64 = 32;
6931 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
6932 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
6933 #ifdef STMMAC_VLAN_TAG_USED
6934 /* Both mac100 and gmac support receive VLAN tag detection */
6935 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
6936 if (priv->dma_cap.vlhash) {
6937 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
6938 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
6940 if (priv->dma_cap.vlins) {
6941 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
6942 if (priv->dma_cap.dvlan)
6943 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
6946 priv->msg_enable = netif_msg_init(debug, default_msg_level);
6948 /* Initialize RSS */
6949 rxq = priv->plat->rx_queues_to_use;
6950 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
6951 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
6952 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
6954 if (priv->dma_cap.rssen && priv->plat->rss_en)
6955 ndev->features |= NETIF_F_RXHASH;
6957 /* MTU range: 46 - hw-specific max */
6958 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
6959 if (priv->plat->has_xgmac)
6960 ndev->max_mtu = XGMAC_JUMBO_LEN;
6961 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
6962 ndev->max_mtu = JUMBO_LEN;
6964 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
6965 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
6966 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
6968 if ((priv->plat->maxmtu < ndev->max_mtu) &&
6969 (priv->plat->maxmtu >= ndev->min_mtu))
6970 ndev->max_mtu = priv->plat->maxmtu;
6971 else if (priv->plat->maxmtu < ndev->min_mtu)
6972 dev_warn(priv->device,
6973 "%s: warning: maxmtu having invalid value (%d)\n",
6974 __func__, priv->plat->maxmtu);
6977 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
6979 /* Setup channels NAPI */
6980 stmmac_napi_add(ndev);
6982 mutex_init(&priv->lock);
6984 /* If a specific clk_csr value is passed from the platform
6985 * this means that the CSR Clock Range selection cannot be
6986 * changed at run-time and it is fixed. Viceversa the driver'll try to
6987 * set the MDC clock dynamically according to the csr actual
6990 if (priv->plat->clk_csr >= 0)
6991 priv->clk_csr = priv->plat->clk_csr;
6993 stmmac_clk_csr_set(priv);
6995 stmmac_check_pcs_mode(priv);
6997 pm_runtime_get_noresume(device);
6998 pm_runtime_set_active(device);
6999 pm_runtime_enable(device);
7001 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7002 priv->hw->pcs != STMMAC_PCS_RTBI) {
7003 /* MDIO bus Registration */
7004 ret = stmmac_mdio_register(ndev);
7006 dev_err(priv->device,
7007 "%s: MDIO bus (id: %d) registration failed",
7008 __func__, priv->plat->bus_id);
7009 goto error_mdio_register;
7013 if (priv->plat->speed_mode_2500)
7014 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7016 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7017 ret = stmmac_xpcs_setup(priv->mii);
7019 goto error_xpcs_setup;
7022 ret = stmmac_phy_setup(priv);
7024 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7025 goto error_phy_setup;
7028 ret = register_netdev(ndev);
7030 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7032 goto error_netdev_register;
7035 if (priv->plat->serdes_powerup) {
7036 ret = priv->plat->serdes_powerup(ndev,
7037 priv->plat->bsp_priv);
7040 goto error_serdes_powerup;
7043 #ifdef CONFIG_DEBUG_FS
7044 stmmac_init_fs(ndev);
7047 /* Let pm_runtime_put() disable the clocks.
7048 * If CONFIG_PM is not enabled, the clocks will stay powered.
7050 pm_runtime_put(device);
7054 error_serdes_powerup:
7055 unregister_netdev(ndev);
7056 error_netdev_register:
7057 phylink_destroy(priv->phylink);
7060 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7061 priv->hw->pcs != STMMAC_PCS_RTBI)
7062 stmmac_mdio_unregister(ndev);
7063 error_mdio_register:
7064 stmmac_napi_del(ndev);
7066 destroy_workqueue(priv->wq);
7067 bitmap_free(priv->af_xdp_zc_qps);
7071 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7075 * @dev: device pointer
7076 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7077 * changes the link status, releases the DMA descriptor rings.
7079 int stmmac_dvr_remove(struct device *dev)
7081 struct net_device *ndev = dev_get_drvdata(dev);
7082 struct stmmac_priv *priv = netdev_priv(ndev);
7084 netdev_info(priv->dev, "%s: removing driver", __func__);
7086 stmmac_stop_all_dma(priv);
7087 stmmac_mac_set(priv, priv->ioaddr, false);
7088 netif_carrier_off(ndev);
7089 unregister_netdev(ndev);
7091 /* Serdes power down needs to happen after VLAN filter
7092 * is deleted that is triggered by unregister_netdev().
7094 if (priv->plat->serdes_powerdown)
7095 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7097 #ifdef CONFIG_DEBUG_FS
7098 stmmac_exit_fs(ndev);
7100 phylink_destroy(priv->phylink);
7101 if (priv->plat->stmmac_rst)
7102 reset_control_assert(priv->plat->stmmac_rst);
7103 reset_control_assert(priv->plat->stmmac_ahb_rst);
7104 pm_runtime_put(dev);
7105 pm_runtime_disable(dev);
7106 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7107 priv->hw->pcs != STMMAC_PCS_RTBI)
7108 stmmac_mdio_unregister(ndev);
7109 destroy_workqueue(priv->wq);
7110 mutex_destroy(&priv->lock);
7111 bitmap_free(priv->af_xdp_zc_qps);
7115 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7118 * stmmac_suspend - suspend callback
7119 * @dev: device pointer
7120 * Description: this is the function to suspend the device and it is called
7121 * by the platform driver to stop the network queue, release the resources,
7122 * program the PMT register (for WoL), clean and release driver resources.
7124 int stmmac_suspend(struct device *dev)
7126 struct net_device *ndev = dev_get_drvdata(dev);
7127 struct stmmac_priv *priv = netdev_priv(ndev);
7130 if (!ndev || !netif_running(ndev))
7133 mutex_lock(&priv->lock);
7135 netif_device_detach(ndev);
7137 stmmac_disable_all_queues(priv);
7139 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7140 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
7142 if (priv->eee_enabled) {
7143 priv->tx_path_in_lpi_mode = false;
7144 del_timer_sync(&priv->eee_ctrl_timer);
7147 /* Stop TX/RX DMA */
7148 stmmac_stop_all_dma(priv);
7150 if (priv->plat->serdes_powerdown)
7151 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7153 /* Enable Power down mode by programming the PMT regs */
7154 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7155 stmmac_pmt(priv, priv->hw, priv->wolopts);
7158 stmmac_mac_set(priv, priv->ioaddr, false);
7159 pinctrl_pm_select_sleep_state(priv->device);
7162 mutex_unlock(&priv->lock);
7165 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7166 phylink_suspend(priv->phylink, true);
7168 if (device_may_wakeup(priv->device))
7169 phylink_speed_down(priv->phylink, false);
7170 phylink_suspend(priv->phylink, false);
7174 if (priv->dma_cap.fpesel) {
7176 stmmac_fpe_configure(priv, priv->ioaddr,
7177 priv->plat->tx_queues_to_use,
7178 priv->plat->rx_queues_to_use, false);
7180 stmmac_fpe_handshake(priv, false);
7181 stmmac_fpe_stop_wq(priv);
7184 priv->speed = SPEED_UNKNOWN;
7187 EXPORT_SYMBOL_GPL(stmmac_suspend);
7190 * stmmac_reset_queues_param - reset queue parameters
7191 * @priv: device pointer
7193 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7195 u32 rx_cnt = priv->plat->rx_queues_to_use;
7196 u32 tx_cnt = priv->plat->tx_queues_to_use;
7199 for (queue = 0; queue < rx_cnt; queue++) {
7200 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
7206 for (queue = 0; queue < tx_cnt; queue++) {
7207 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
7213 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7218 * stmmac_resume - resume callback
7219 * @dev: device pointer
7220 * Description: when resume this function is invoked to setup the DMA and CORE
7221 * in a usable state.
7223 int stmmac_resume(struct device *dev)
7225 struct net_device *ndev = dev_get_drvdata(dev);
7226 struct stmmac_priv *priv = netdev_priv(ndev);
7229 if (!netif_running(ndev))
7232 /* Power Down bit, into the PM register, is cleared
7233 * automatically as soon as a magic packet or a Wake-up frame
7234 * is received. Anyway, it's better to manually clear
7235 * this bit because it can generate problems while resuming
7236 * from another devices (e.g. serial console).
7238 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7239 mutex_lock(&priv->lock);
7240 stmmac_pmt(priv, priv->hw, 0);
7241 mutex_unlock(&priv->lock);
7244 pinctrl_pm_select_default_state(priv->device);
7245 /* reset the phy so that it's ready */
7247 stmmac_mdio_reset(priv->mii);
7250 if (priv->plat->serdes_powerup) {
7251 ret = priv->plat->serdes_powerup(ndev,
7252 priv->plat->bsp_priv);
7259 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7260 phylink_resume(priv->phylink);
7262 phylink_resume(priv->phylink);
7263 if (device_may_wakeup(priv->device))
7264 phylink_speed_up(priv->phylink);
7269 mutex_lock(&priv->lock);
7271 stmmac_reset_queues_param(priv);
7273 stmmac_free_tx_skbufs(priv);
7274 stmmac_clear_descriptors(priv);
7276 stmmac_hw_setup(ndev, false);
7277 stmmac_init_coalesce(priv);
7278 stmmac_set_rx_mode(ndev);
7280 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7282 stmmac_enable_all_queues(priv);
7284 mutex_unlock(&priv->lock);
7287 netif_device_attach(ndev);
7291 EXPORT_SYMBOL_GPL(stmmac_resume);
7294 static int __init stmmac_cmdline_opt(char *str)
7300 while ((opt = strsep(&str, ",")) != NULL) {
7301 if (!strncmp(opt, "debug:", 6)) {
7302 if (kstrtoint(opt + 6, 0, &debug))
7304 } else if (!strncmp(opt, "phyaddr:", 8)) {
7305 if (kstrtoint(opt + 8, 0, &phyaddr))
7307 } else if (!strncmp(opt, "buf_sz:", 7)) {
7308 if (kstrtoint(opt + 7, 0, &buf_sz))
7310 } else if (!strncmp(opt, "tc:", 3)) {
7311 if (kstrtoint(opt + 3, 0, &tc))
7313 } else if (!strncmp(opt, "watchdog:", 9)) {
7314 if (kstrtoint(opt + 9, 0, &watchdog))
7316 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7317 if (kstrtoint(opt + 10, 0, &flow_ctrl))
7319 } else if (!strncmp(opt, "pause:", 6)) {
7320 if (kstrtoint(opt + 6, 0, &pause))
7322 } else if (!strncmp(opt, "eee_timer:", 10)) {
7323 if (kstrtoint(opt + 10, 0, &eee_timer))
7325 } else if (!strncmp(opt, "chain_mode:", 11)) {
7326 if (kstrtoint(opt + 11, 0, &chain_mode))
7333 pr_err("%s: ERROR broken module parameter conversion", __func__);
7337 __setup("stmmaceth=", stmmac_cmdline_opt);
7340 static int __init stmmac_init(void)
7342 #ifdef CONFIG_DEBUG_FS
7343 /* Create debugfs main directory if it doesn't exist yet */
7345 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7346 register_netdevice_notifier(&stmmac_notifier);
7352 static void __exit stmmac_exit(void)
7354 #ifdef CONFIG_DEBUG_FS
7355 unregister_netdevice_notifier(&stmmac_notifier);
7356 debugfs_remove_recursive(stmmac_fs_dir);
7360 module_init(stmmac_init)
7361 module_exit(stmmac_exit)
7363 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7364 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7365 MODULE_LICENSE("GPL");