drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <net/pkt_cls.h>
  40 #include "stmmac_ptp.h"
  41 #include "stmmac.h"
  42 #include <linux/reset.h>
  43 #include <linux/of_mdio.h>
  44 #include "dwmac1000.h"
  45 #include "dwxgmac2.h"
  46 #include "hwif.h"
  47
  48 #define STMMAC_ALIGN(x)         __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
  49 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  50
  51 /* Module parameters */
  52 #define TX_TIMEO        5000
  53 static int watchdog = TX_TIMEO;
  54 module_param(watchdog, int, 0644);
  55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  56
  57 static int debug = -1;
  58 module_param(debug, int, 0644);
  59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  60
  61 static int phyaddr = -1;
  62 module_param(phyaddr, int, 0444);
  63 MODULE_PARM_DESC(phyaddr, "Physical device address");
  64
  65 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  66 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  67
  68 static int flow_ctrl = FLOW_AUTO;
  69 module_param(flow_ctrl, int, 0644);
  70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  71
  72 static int pause = PAUSE_TIME;
  73 module_param(pause, int, 0644);
  74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  75
  76 #define TC_DEFAULT 64
  77 static int tc = TC_DEFAULT;
  78 module_param(tc, int, 0644);
  79 MODULE_PARM_DESC(tc, "DMA threshold control value");
  80
  81 #define DEFAULT_BUFSIZE 1536
  82 static int buf_sz = DEFAULT_BUFSIZE;
  83 module_param(buf_sz, int, 0644);
  84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  85
  86 #define STMMAC_RX_COPYBREAK     256
  87
  88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  89                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  90                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  91
  92 #define STMMAC_DEFAULT_LPI_TIMER        1000
  93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  94 module_param(eee_timer, int, 0644);
  95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  97
  98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
  99  * but allow user to force to use the chain instead of the ring
 100  */
 101 static unsigned int chain_mode;
 102 module_param(chain_mode, int, 0444);
 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 104
 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 106
 107 #ifdef CONFIG_DEBUG_FS
 108 static int stmmac_init_fs(struct net_device *dev);
 109 static void stmmac_exit_fs(struct net_device *dev);
 110 #endif
 111
 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 113
 114 /**
 115  * stmmac_verify_args - verify the driver parameters.
 116  * Description: it checks the driver parameters and set a default in case of
 117  * errors.
 118  */
 119 static void stmmac_verify_args(void)
 120 {
 121         if (unlikely(watchdog < 0))
 122                 watchdog = TX_TIMEO;
 123         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 124                 buf_sz = DEFAULT_BUFSIZE;
 125         if (unlikely(flow_ctrl > 1))
 126                 flow_ctrl = FLOW_AUTO;
 127         else if (likely(flow_ctrl < 0))
 128                 flow_ctrl = FLOW_OFF;
 129         if (unlikely((pause < 0) || (pause > 0xffff)))
 130                 pause = PAUSE_TIME;
 131         if (eee_timer < 0)
 132                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 133 }
 134
 135 /**
 136  * stmmac_disable_all_queues - Disable all queues
 137  * @priv: driver private structure
 138  */
 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 140 {
 141         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 142         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 143         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 144         u32 queue;
 145
 146         for (queue = 0; queue < maxq; queue++) {
 147                 struct stmmac_channel *ch = &priv->channel[queue];
 148
 149                 if (queue < rx_queues_cnt)
 150                         napi_disable(&ch->rx_napi);
 151                 if (queue < tx_queues_cnt)
 152                         napi_disable(&ch->tx_napi);
 153         }
 154 }
 155
 156 /**
 157  * stmmac_enable_all_queues - Enable all queues
 158  * @priv: driver private structure
 159  */
 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 161 {
 162         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 163         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 164         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 165         u32 queue;
 166
 167         for (queue = 0; queue < maxq; queue++) {
 168                 struct stmmac_channel *ch = &priv->channel[queue];
 169
 170                 if (queue < rx_queues_cnt)
 171                         napi_enable(&ch->rx_napi);
 172                 if (queue < tx_queues_cnt)
 173                         napi_enable(&ch->tx_napi);
 174         }
 175 }
 176
 177 /**
 178  * stmmac_stop_all_queues - Stop all queues
 179  * @priv: driver private structure
 180  */
 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 182 {
 183         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 184         u32 queue;
 185
 186         for (queue = 0; queue < tx_queues_cnt; queue++)
 187                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 188 }
 189
 190 /**
 191  * stmmac_start_all_queues - Start all queues
 192  * @priv: driver private structure
 193  */
 194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 195 {
 196         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 197         u32 queue;
 198
 199         for (queue = 0; queue < tx_queues_cnt; queue++)
 200                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 201 }
 202
 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 204 {
 205         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 206             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 207                 queue_work(priv->wq, &priv->service_task);
 208 }
 209
 210 static void stmmac_global_err(struct stmmac_priv *priv)
 211 {
 212         netif_carrier_off(priv->dev);
 213         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 214         stmmac_service_event_schedule(priv);
 215 }
 216
 217 /**
 218  * stmmac_clk_csr_set - dynamically set the MDC clock
 219  * @priv: driver private structure
 220  * Description: this is to dynamically set the MDC clock according to the csr
 221  * clock input.
 222  * Note:
 223  *      If a specific clk_csr value is passed from the platform
 224  *      this means that the CSR Clock Range selection cannot be
 225  *      changed at run-time and it is fixed (as reported in the driver
 226  *      documentation). Viceversa the driver will try to set the MDC
 227  *      clock dynamically according to the actual clock input.
 228  */
 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 230 {
 231         u32 clk_rate;
 232
 233         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 234
 235         /* Platform provided default clk_csr would be assumed valid
 236          * for all other cases except for the below mentioned ones.
 237          * For values higher than the IEEE 802.3 specified frequency
 238          * we can not estimate the proper divider as it is not known
 239          * the frequency of clk_csr_i. So we do not change the default
 240          * divider.
 241          */
 242         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 243                 if (clk_rate < CSR_F_35M)
 244                         priv->clk_csr = STMMAC_CSR_20_35M;
 245                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 246                         priv->clk_csr = STMMAC_CSR_35_60M;
 247                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 248                         priv->clk_csr = STMMAC_CSR_60_100M;
 249                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 250                         priv->clk_csr = STMMAC_CSR_100_150M;
 251                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 252                         priv->clk_csr = STMMAC_CSR_150_250M;
 253                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 254                         priv->clk_csr = STMMAC_CSR_250_300M;
 255         }
 256
 257         if (priv->plat->has_sun8i) {
 258                 if (clk_rate > 160000000)
 259                         priv->clk_csr = 0x03;
 260                 else if (clk_rate > 80000000)
 261                         priv->clk_csr = 0x02;
 262                 else if (clk_rate > 40000000)
 263                         priv->clk_csr = 0x01;
 264                 else
 265                         priv->clk_csr = 0;
 266         }
 267
 268         if (priv->plat->has_xgmac) {
 269                 if (clk_rate > 400000000)
 270                         priv->clk_csr = 0x5;
 271                 else if (clk_rate > 350000000)
 272                         priv->clk_csr = 0x4;
 273                 else if (clk_rate > 300000000)
 274                         priv->clk_csr = 0x3;
 275                 else if (clk_rate > 250000000)
 276                         priv->clk_csr = 0x2;
 277                 else if (clk_rate > 150000000)
 278                         priv->clk_csr = 0x1;
 279                 else
 280                         priv->clk_csr = 0x0;
 281         }
 282 }
 283
 284 static void print_pkt(unsigned char *buf, int len)
 285 {
 286         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 287         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 288 }
 289
 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 291 {
 292         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 293         u32 avail;
 294
 295         if (tx_q->dirty_tx > tx_q->cur_tx)
 296                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 297         else
 298                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 299
 300         return avail;
 301 }
 302
 303 /**
 304  * stmmac_rx_dirty - Get RX queue dirty
 305  * @priv: driver private structure
 306  * @queue: RX queue index
 307  */
 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 309 {
 310         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 311         u32 dirty;
 312
 313         if (rx_q->dirty_rx <= rx_q->cur_rx)
 314                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 315         else
 316                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 317
 318         return dirty;
 319 }
 320
 321 /**
 322  * stmmac_enable_eee_mode - check and enter in LPI mode
 323  * @priv: driver private structure
 324  * Description: this function is to verify and enter in LPI mode in case of
 325  * EEE.
 326  */
 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 328 {
 329         u32 tx_cnt = priv->plat->tx_queues_to_use;
 330         u32 queue;
 331
 332         /* check if all TX queues have the work finished */
 333         for (queue = 0; queue < tx_cnt; queue++) {
 334                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 335
 336                 if (tx_q->dirty_tx != tx_q->cur_tx)
 337                         return; /* still unfinished work */
 338         }
 339
 340         /* Check and enter in LPI mode */
 341         if (!priv->tx_path_in_lpi_mode)
 342                 stmmac_set_eee_mode(priv, priv->hw,
 343                                 priv->plat->en_tx_lpi_clockgating);
 344 }
 345
 346 /**
 347  * stmmac_disable_eee_mode - disable and exit from LPI mode
 348  * @priv: driver private structure
 349  * Description: this function is to exit and disable EEE in case of
 350  * LPI state is true. This is called by the xmit.
 351  */
 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 353 {
 354         stmmac_reset_eee_mode(priv, priv->hw);
 355         del_timer_sync(&priv->eee_ctrl_timer);
 356         priv->tx_path_in_lpi_mode = false;
 357 }
 358
 359 /**
 360  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 361  * @arg : data hook
 362  * Description:
 363  *  if there is no data transfer and if we are not in LPI state,
 364  *  then MAC Transmitter can be moved to LPI state.
 365  */
 366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 367 {
 368         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 369
 370         stmmac_enable_eee_mode(priv);
 371         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 372 }
 373
 374 /**
 375  * stmmac_eee_init - init EEE
 376  * @priv: driver private structure
 377  * Description:
 378  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 379  *  can also manage EEE, this function enable the LPI state and start related
 380  *  timer.
 381  */
 382 bool stmmac_eee_init(struct stmmac_priv *priv)
 383 {
 384         int tx_lpi_timer = priv->tx_lpi_timer;
 385
 386         /* Using PCS we cannot dial with the phy registers at this stage
 387          * so we do not support extra feature like EEE.
 388          */
 389         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 390             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 391             (priv->hw->pcs == STMMAC_PCS_RTBI))
 392                 return false;
 393
 394         /* Check if MAC core supports the EEE feature. */
 395         if (!priv->dma_cap.eee)
 396                 return false;
 397
 398         mutex_lock(&priv->lock);
 399
 400         /* Check if it needs to be deactivated */
 401         if (!priv->eee_active) {
 402                 if (priv->eee_enabled) {
 403                         netdev_dbg(priv->dev, "disable EEE\n");
 404                         del_timer_sync(&priv->eee_ctrl_timer);
 405                         stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 406                 }
 407                 mutex_unlock(&priv->lock);
 408                 return false;
 409         }
 410
 411         if (priv->eee_active && !priv->eee_enabled) {
 412                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 413                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 414                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 415                                      tx_lpi_timer);
 416         }
 417
 418         mutex_unlock(&priv->lock);
 419         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 420         return true;
 421 }
 422
 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 424  * @priv: driver private structure
 425  * @p : descriptor pointer
 426  * @skb : the socket buffer
 427  * Description :
 428  * This function will read timestamp from the descriptor & pass it to stack.
 429  * and also perform some sanity checks.
 430  */
 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 432                                    struct dma_desc *p, struct sk_buff *skb)
 433 {
 434         struct skb_shared_hwtstamps shhwtstamp;
 435         u64 ns = 0;
 436
 437         if (!priv->hwts_tx_en)
 438                 return;
 439
 440         /* exit if skb doesn't support hw tstamp */
 441         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 442                 return;
 443
 444         /* check tx tstamp status */
 445         if (stmmac_get_tx_timestamp_status(priv, p)) {
 446                 /* get the valid tstamp */
 447                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 448
 449                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 450                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 451
 452                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 453                 /* pass tstamp to stack */
 454                 skb_tstamp_tx(skb, &shhwtstamp);
 455         }
 456
 457         return;
 458 }
 459
 460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 461  * @priv: driver private structure
 462  * @p : descriptor pointer
 463  * @np : next descriptor pointer
 464  * @skb : the socket buffer
 465  * Description :
 466  * This function will read received packet's timestamp from the descriptor
 467  * and pass it to stack. It also perform some sanity checks.
 468  */
 469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 470                                    struct dma_desc *np, struct sk_buff *skb)
 471 {
 472         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 473         struct dma_desc *desc = p;
 474         u64 ns = 0;
 475
 476         if (!priv->hwts_rx_en)
 477                 return;
 478         /* For GMAC4, the valid timestamp is from CTX next desc. */
 479         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 480                 desc = np;
 481
 482         /* Check if timestamp is available */
 483         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 484                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 485                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 486                 shhwtstamp = skb_hwtstamps(skb);
 487                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 488                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 489         } else  {
 490                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 491         }
 492 }
 493
 494 /**
 495  *  stmmac_hwtstamp_set - control hardware timestamping.
 496  *  @dev: device pointer.
 497  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 498  *  a proprietary structure used to pass information to the driver.
 499  *  Description:
 500  *  This function configures the MAC to enable/disable both outgoing(TX)
 501  *  and incoming(RX) packets time stamping based on user input.
 502  *  Return Value:
 503  *  0 on success and an appropriate -ve integer on failure.
 504  */
 505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 506 {
 507         struct stmmac_priv *priv = netdev_priv(dev);
 508         struct hwtstamp_config config;
 509         struct timespec64 now;
 510         u64 temp = 0;
 511         u32 ptp_v2 = 0;
 512         u32 tstamp_all = 0;
 513         u32 ptp_over_ipv4_udp = 0;
 514         u32 ptp_over_ipv6_udp = 0;
 515         u32 ptp_over_ethernet = 0;
 516         u32 snap_type_sel = 0;
 517         u32 ts_master_en = 0;
 518         u32 ts_event_en = 0;
 519         u32 sec_inc = 0;
 520         u32 value = 0;
 521         bool xmac;
 522
 523         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 524
 525         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 526                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 527                 priv->hwts_tx_en = 0;
 528                 priv->hwts_rx_en = 0;
 529
 530                 return -EOPNOTSUPP;
 531         }
 532
 533         if (copy_from_user(&config, ifr->ifr_data,
 534                            sizeof(config)))
 535                 return -EFAULT;
 536
 537         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 538                    __func__, config.flags, config.tx_type, config.rx_filter);
 539
 540         /* reserved for future extensions */
 541         if (config.flags)
 542                 return -EINVAL;
 543
 544         if (config.tx_type != HWTSTAMP_TX_OFF &&
 545             config.tx_type != HWTSTAMP_TX_ON)
 546                 return -ERANGE;
 547
 548         if (priv->adv_ts) {
 549                 switch (config.rx_filter) {
 550                 case HWTSTAMP_FILTER_NONE:
 551                         /* time stamp no incoming packet at all */
 552                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 553                         break;
 554
 555                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 556                         /* PTP v1, UDP, any kind of event packet */
 557                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 558                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 559                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 560                          * This leaves Delay_Req timestamps out.
 561                          * Enable all events *and* general purpose message
 562                          * timestamping
 563                          */
 564                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 565                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 566                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 567                         break;
 568
 569                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 570                         /* PTP v1, UDP, Sync packet */
 571                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 572                         /* take time stamp for SYNC messages only */
 573                         ts_event_en = PTP_TCR_TSEVNTENA;
 574
 575                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 576                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 577                         break;
 578
 579                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 580                         /* PTP v1, UDP, Delay_req packet */
 581                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 582                         /* take time stamp for Delay_Req messages only */
 583                         ts_master_en = PTP_TCR_TSMSTRENA;
 584                         ts_event_en = PTP_TCR_TSEVNTENA;
 585
 586                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 587                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 588                         break;
 589
 590                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 591                         /* PTP v2, UDP, any kind of event packet */
 592                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 593                         ptp_v2 = PTP_TCR_TSVER2ENA;
 594                         /* take time stamp for all event messages */
 595                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 596
 597                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 598                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 599                         break;
 600
 601                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 602                         /* PTP v2, UDP, Sync packet */
 603                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 604                         ptp_v2 = PTP_TCR_TSVER2ENA;
 605                         /* take time stamp for SYNC messages only */
 606                         ts_event_en = PTP_TCR_TSEVNTENA;
 607
 608                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 609                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 610                         break;
 611
 612                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 613                         /* PTP v2, UDP, Delay_req packet */
 614                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 615                         ptp_v2 = PTP_TCR_TSVER2ENA;
 616                         /* take time stamp for Delay_Req messages only */
 617                         ts_master_en = PTP_TCR_TSMSTRENA;
 618                         ts_event_en = PTP_TCR_TSEVNTENA;
 619
 620                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 621                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 622                         break;
 623
 624                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 625                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 626                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 627                         ptp_v2 = PTP_TCR_TSVER2ENA;
 628                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 629                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 630                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 631                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 632                         break;
 633
 634                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 635                         /* PTP v2/802.AS1, any layer, Sync packet */
 636                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 637                         ptp_v2 = PTP_TCR_TSVER2ENA;
 638                         /* take time stamp for SYNC messages only */
 639                         ts_event_en = PTP_TCR_TSEVNTENA;
 640
 641                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 642                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 643                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 644                         break;
 645
 646                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 647                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 648                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 649                         ptp_v2 = PTP_TCR_TSVER2ENA;
 650                         /* take time stamp for Delay_Req messages only */
 651                         ts_master_en = PTP_TCR_TSMSTRENA;
 652                         ts_event_en = PTP_TCR_TSEVNTENA;
 653
 654                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 655                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 656                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 657                         break;
 658
 659                 case HWTSTAMP_FILTER_NTP_ALL:
 660                 case HWTSTAMP_FILTER_ALL:
 661                         /* time stamp any incoming packet */
 662                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 663                         tstamp_all = PTP_TCR_TSENALL;
 664                         break;
 665
 666                 default:
 667                         return -ERANGE;
 668                 }
 669         } else {
 670                 switch (config.rx_filter) {
 671                 case HWTSTAMP_FILTER_NONE:
 672                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 673                         break;
 674                 default:
 675                         /* PTP v1, UDP, any kind of event packet */
 676                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 677                         break;
 678                 }
 679         }
 680         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 681         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 682
 683         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 684                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 685         else {
 686                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 687                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 688                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 689                          ts_master_en | snap_type_sel);
 690                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 691
 692                 /* program Sub Second Increment reg */
 693                 stmmac_config_sub_second_increment(priv,
 694                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 695                                 xmac, &sec_inc);
 696                 temp = div_u64(1000000000ULL, sec_inc);
 697
 698                 /* Store sub second increment and flags for later use */
 699                 priv->sub_second_inc = sec_inc;
 700                 priv->systime_flags = value;
 701
 702                 /* calculate default added value:
 703                  * formula is :
 704                  * addend = (2^32)/freq_div_ratio;
 705                  * where, freq_div_ratio = 1e9ns/sec_inc
 706                  */
 707                 temp = (u64)(temp << 32);
 708                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 709                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 710
 711                 /* initialize system time */
 712                 ktime_get_real_ts64(&now);
 713
 714                 /* lower 32 bits of tv_sec are safe until y2106 */
 715                 stmmac_init_systime(priv, priv->ptpaddr,
 716                                 (u32)now.tv_sec, now.tv_nsec);
 717         }
 718
 719         memcpy(&priv->tstamp_config, &config, sizeof(config));
 720
 721         return copy_to_user(ifr->ifr_data, &config,
 722                             sizeof(config)) ? -EFAULT : 0;
 723 }
 724
 725 /**
 726  *  stmmac_hwtstamp_get - read hardware timestamping.
 727  *  @dev: device pointer.
 728  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 729  *  a proprietary structure used to pass information to the driver.
 730  *  Description:
 731  *  This function obtain the current hardware timestamping settings
 732     as requested.
 733  */
 734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 735 {
 736         struct stmmac_priv *priv = netdev_priv(dev);
 737         struct hwtstamp_config *config = &priv->tstamp_config;
 738
 739         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 740                 return -EOPNOTSUPP;
 741
 742         return copy_to_user(ifr->ifr_data, config,
 743                             sizeof(*config)) ? -EFAULT : 0;
 744 }
 745
 746 /**
 747  * stmmac_init_ptp - init PTP
 748  * @priv: driver private structure
 749  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 750  * This is done by looking at the HW cap. register.
 751  * This function also registers the ptp driver.
 752  */
 753 static int stmmac_init_ptp(struct stmmac_priv *priv)
 754 {
 755         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 756
 757         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 758                 return -EOPNOTSUPP;
 759
 760         priv->adv_ts = 0;
 761         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 762         if (xmac && priv->dma_cap.atime_stamp)
 763                 priv->adv_ts = 1;
 764         /* Dwmac 3.x core with extend_desc can support adv_ts */
 765         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 766                 priv->adv_ts = 1;
 767
 768         if (priv->dma_cap.time_stamp)
 769                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 770
 771         if (priv->adv_ts)
 772                 netdev_info(priv->dev,
 773                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 774
 775         priv->hwts_tx_en = 0;
 776         priv->hwts_rx_en = 0;
 777
 778         stmmac_ptp_register(priv);
 779
 780         return 0;
 781 }
 782
 783 static void stmmac_release_ptp(struct stmmac_priv *priv)
 784 {
 785         if (priv->plat->clk_ptp_ref)
 786                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 787         stmmac_ptp_unregister(priv);
 788 }
 789
 790 /**
 791  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 792  *  @priv: driver private structure
 793  *  Description: It is used for configuring the flow control in all queues
 794  */
 795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 796 {
 797         u32 tx_cnt = priv->plat->tx_queues_to_use;
 798
 799         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 800                         priv->pause, tx_cnt);
 801 }
 802
 803 static void stmmac_validate(struct phylink_config *config,
 804                             unsigned long *supported,
 805                             struct phylink_link_state *state)
 806 {
 807         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 808         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 809         int tx_cnt = priv->plat->tx_queues_to_use;
 810         int max_speed = priv->plat->max_speed;
 811
 812         /* Cut down 1G if asked to */
 813         if ((max_speed > 0) && (max_speed < 1000)) {
 814                 phylink_set(mask, 1000baseT_Full);
 815                 phylink_set(mask, 1000baseX_Full);
 816         }
 817
 818         /* Half-Duplex can only work with single queue */
 819         if (tx_cnt > 1) {
 820                 phylink_set(mask, 10baseT_Half);
 821                 phylink_set(mask, 100baseT_Half);
 822                 phylink_set(mask, 1000baseT_Half);
 823         }
 824
 825         bitmap_andnot(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 826         bitmap_andnot(state->advertising, state->advertising, mask,
 827                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 828 }
 829
 830 static int stmmac_mac_link_state(struct phylink_config *config,
 831                                  struct phylink_link_state *state)
 832 {
 833         return -EOPNOTSUPP;
 834 }
 835
 836 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 837                               const struct phylink_link_state *state)
 838 {
 839         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 840         u32 ctrl;
 841
 842         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 843         ctrl &= ~priv->hw->link.speed_mask;
 844
 845         switch (state->speed) {
 846         case SPEED_1000:
 847                 ctrl |= priv->hw->link.speed1000;
 848                 break;
 849         case SPEED_100:
 850                 ctrl |= priv->hw->link.speed100;
 851                 break;
 852         case SPEED_10:
 853                 ctrl |= priv->hw->link.speed10;
 854                 break;
 855         default:
 856                 return;
 857         }
 858
 859         priv->speed = state->speed;
 860
 861         if (priv->plat->fix_mac_speed)
 862                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
 863
 864         if (!state->duplex)
 865                 ctrl &= ~priv->hw->link.duplex;
 866         else
 867                 ctrl |= priv->hw->link.duplex;
 868
 869         /* Flow Control operation */
 870         if (state->pause)
 871                 stmmac_mac_flow_ctrl(priv, state->duplex);
 872
 873         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 874 }
 875
 876 static void stmmac_mac_an_restart(struct phylink_config *config)
 877 {
 878         /* Not Supported */
 879 }
 880
 881 static void stmmac_mac_link_down(struct phylink_config *config,
 882                                  unsigned int mode, phy_interface_t interface)
 883 {
 884         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 885
 886         stmmac_mac_set(priv, priv->ioaddr, false);
 887         priv->eee_active = false;
 888         stmmac_eee_init(priv);
 889         stmmac_set_eee_pls(priv, priv->hw, false);
 890 }
 891
 892 static void stmmac_mac_link_up(struct phylink_config *config,
 893                                unsigned int mode, phy_interface_t interface,
 894                                struct phy_device *phy)
 895 {
 896         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 897
 898         stmmac_mac_set(priv, priv->ioaddr, true);
 899         if (phy) {
 900                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
 901                 priv->eee_enabled = stmmac_eee_init(priv);
 902                 stmmac_set_eee_pls(priv, priv->hw, true);
 903         }
 904 }
 905
 906 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
 907         .validate = stmmac_validate,
 908         .mac_link_state = stmmac_mac_link_state,
 909         .mac_config = stmmac_mac_config,
 910         .mac_an_restart = stmmac_mac_an_restart,
 911         .mac_link_down = stmmac_mac_link_down,
 912         .mac_link_up = stmmac_mac_link_up,
 913 };
 914
 915 /**
 916  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 917  * @priv: driver private structure
 918  * Description: this is to verify if the HW supports the PCS.
 919  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 920  * configured for the TBI, RTBI, or SGMII PHY interface.
 921  */
 922 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 923 {
 924         int interface = priv->plat->interface;
 925
 926         if (priv->dma_cap.pcs) {
 927                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 928                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 929                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 930                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 931                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 932                         priv->hw->pcs = STMMAC_PCS_RGMII;
 933                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 934                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 935                         priv->hw->pcs = STMMAC_PCS_SGMII;
 936                 }
 937         }
 938 }
 939
 940 /**
 941  * stmmac_init_phy - PHY initialization
 942  * @dev: net device structure
 943  * Description: it initializes the driver's PHY state, and attaches the PHY
 944  * to the mac driver.
 945  *  Return value:
 946  *  0 on success
 947  */
 948 static int stmmac_init_phy(struct net_device *dev)
 949 {
 950         struct stmmac_priv *priv = netdev_priv(dev);
 951         struct device_node *node;
 952         int ret;
 953
 954         node = priv->plat->phylink_node;
 955
 956         if (node) {
 957                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
 958         } else {
 959                 int addr = priv->plat->phy_addr;
 960                 struct phy_device *phydev;
 961
 962                 phydev = mdiobus_get_phy(priv->mii, addr);
 963                 if (!phydev) {
 964                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
 965                         return -ENODEV;
 966                 }
 967
 968                 ret = phylink_connect_phy(priv->phylink, phydev);
 969         }
 970
 971         return ret;
 972 }
 973
 974 static int stmmac_phy_setup(struct stmmac_priv *priv)
 975 {
 976         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
 977         int mode = priv->plat->interface;
 978         struct phylink *phylink;
 979
 980         priv->phylink_config.dev = &priv->dev->dev;
 981         priv->phylink_config.type = PHYLINK_NETDEV;
 982
 983         phylink = phylink_create(&priv->phylink_config, fwnode,
 984                                  mode, &stmmac_phylink_mac_ops);
 985         if (IS_ERR(phylink))
 986                 return PTR_ERR(phylink);
 987
 988         priv->phylink = phylink;
 989         return 0;
 990 }
 991
 992 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
 993 {
 994         u32 rx_cnt = priv->plat->rx_queues_to_use;
 995         void *head_rx;
 996         u32 queue;
 997
 998         /* Display RX rings */
 999         for (queue = 0; queue < rx_cnt; queue++) {
1000                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1001
1002                 pr_info("\tRX Queue %u rings\n", queue);
1003
1004                 if (priv->extend_desc)
1005                         head_rx = (void *)rx_q->dma_erx;
1006                 else
1007                         head_rx = (void *)rx_q->dma_rx;
1008
1009                 /* Display RX ring */
1010                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1011         }
1012 }
1013
1014 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1015 {
1016         u32 tx_cnt = priv->plat->tx_queues_to_use;
1017         void *head_tx;
1018         u32 queue;
1019
1020         /* Display TX rings */
1021         for (queue = 0; queue < tx_cnt; queue++) {
1022                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1023
1024                 pr_info("\tTX Queue %d rings\n", queue);
1025
1026                 if (priv->extend_desc)
1027                         head_tx = (void *)tx_q->dma_etx;
1028                 else
1029                         head_tx = (void *)tx_q->dma_tx;
1030
1031                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1032         }
1033 }
1034
1035 static void stmmac_display_rings(struct stmmac_priv *priv)
1036 {
1037         /* Display RX ring */
1038         stmmac_display_rx_rings(priv);
1039
1040         /* Display TX ring */
1041         stmmac_display_tx_rings(priv);
1042 }
1043
1044 static int stmmac_set_bfsize(int mtu, int bufsize)
1045 {
1046         int ret = bufsize;
1047
1048         if (mtu >= BUF_SIZE_4KiB)
1049                 ret = BUF_SIZE_8KiB;
1050         else if (mtu >= BUF_SIZE_2KiB)
1051                 ret = BUF_SIZE_4KiB;
1052         else if (mtu > DEFAULT_BUFSIZE)
1053                 ret = BUF_SIZE_2KiB;
1054         else
1055                 ret = DEFAULT_BUFSIZE;
1056
1057         return ret;
1058 }
1059
1060 /**
1061  * stmmac_clear_rx_descriptors - clear RX descriptors
1062  * @priv: driver private structure
1063  * @queue: RX queue index
1064  * Description: this function is called to clear the RX descriptors
1065  * in case of both basic and extended descriptors are used.
1066  */
1067 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1068 {
1069         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1070         int i;
1071
1072         /* Clear the RX descriptors */
1073         for (i = 0; i < DMA_RX_SIZE; i++)
1074                 if (priv->extend_desc)
1075                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1076                                         priv->use_riwt, priv->mode,
1077                                         (i == DMA_RX_SIZE - 1),
1078                                         priv->dma_buf_sz);
1079                 else
1080                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1081                                         priv->use_riwt, priv->mode,
1082                                         (i == DMA_RX_SIZE - 1),
1083                                         priv->dma_buf_sz);
1084 }
1085
1086 /**
1087  * stmmac_clear_tx_descriptors - clear tx descriptors
1088  * @priv: driver private structure
1089  * @queue: TX queue index.
1090  * Description: this function is called to clear the TX descriptors
1091  * in case of both basic and extended descriptors are used.
1092  */
1093 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1094 {
1095         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1096         int i;
1097
1098         /* Clear the TX descriptors */
1099         for (i = 0; i < DMA_TX_SIZE; i++)
1100                 if (priv->extend_desc)
1101                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1102                                         priv->mode, (i == DMA_TX_SIZE - 1));
1103                 else
1104                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1105                                         priv->mode, (i == DMA_TX_SIZE - 1));
1106 }
1107
1108 /**
1109  * stmmac_clear_descriptors - clear descriptors
1110  * @priv: driver private structure
1111  * Description: this function is called to clear the TX and RX descriptors
1112  * in case of both basic and extended descriptors are used.
1113  */
1114 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1115 {
1116         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1117         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1118         u32 queue;
1119
1120         /* Clear the RX descriptors */
1121         for (queue = 0; queue < rx_queue_cnt; queue++)
1122                 stmmac_clear_rx_descriptors(priv, queue);
1123
1124         /* Clear the TX descriptors */
1125         for (queue = 0; queue < tx_queue_cnt; queue++)
1126                 stmmac_clear_tx_descriptors(priv, queue);
1127 }
1128
1129 /**
1130  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1131  * @priv: driver private structure
1132  * @p: descriptor pointer
1133  * @i: descriptor index
1134  * @flags: gfp flag
1135  * @queue: RX queue index
1136  * Description: this function is called to allocate a receive buffer, perform
1137  * the DMA mapping and init the descriptor.
1138  */
1139 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1140                                   int i, gfp_t flags, u32 queue)
1141 {
1142         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1143         struct sk_buff *skb;
1144
1145         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1146         if (!skb) {
1147                 netdev_err(priv->dev,
1148                            "%s: Rx init fails; skb is NULL\n", __func__);
1149                 return -ENOMEM;
1150         }
1151         rx_q->rx_skbuff[i] = skb;
1152         rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1153                                                 priv->dma_buf_sz,
1154                                                 DMA_FROM_DEVICE);
1155         if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1156                 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1157                 dev_kfree_skb_any(skb);
1158                 return -EINVAL;
1159         }
1160
1161         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1162
1163         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1164                 stmmac_init_desc3(priv, p);
1165
1166         return 0;
1167 }
1168
1169 /**
1170  * stmmac_free_rx_buffer - free RX dma buffers
1171  * @priv: private structure
1172  * @queue: RX queue index
1173  * @i: buffer index.
1174  */
1175 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1176 {
1177         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1178
1179         if (rx_q->rx_skbuff[i]) {
1180                 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1181                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1182                 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1183         }
1184         rx_q->rx_skbuff[i] = NULL;
1185 }
1186
1187 /**
1188  * stmmac_free_tx_buffer - free RX dma buffers
1189  * @priv: private structure
1190  * @queue: RX queue index
1191  * @i: buffer index.
1192  */
1193 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1194 {
1195         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1196
1197         if (tx_q->tx_skbuff_dma[i].buf) {
1198                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1199                         dma_unmap_page(priv->device,
1200                                        tx_q->tx_skbuff_dma[i].buf,
1201                                        tx_q->tx_skbuff_dma[i].len,
1202                                        DMA_TO_DEVICE);
1203                 else
1204                         dma_unmap_single(priv->device,
1205                                          tx_q->tx_skbuff_dma[i].buf,
1206                                          tx_q->tx_skbuff_dma[i].len,
1207                                          DMA_TO_DEVICE);
1208         }
1209
1210         if (tx_q->tx_skbuff[i]) {
1211                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1212                 tx_q->tx_skbuff[i] = NULL;
1213                 tx_q->tx_skbuff_dma[i].buf = 0;
1214                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1215         }
1216 }
1217
1218 /**
1219  * init_dma_rx_desc_rings - init the RX descriptor rings
1220  * @dev: net device structure
1221  * @flags: gfp flag.
1222  * Description: this function initializes the DMA RX descriptors
1223  * and allocates the socket buffers. It supports the chained and ring
1224  * modes.
1225  */
1226 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1227 {
1228         struct stmmac_priv *priv = netdev_priv(dev);
1229         u32 rx_count = priv->plat->rx_queues_to_use;
1230         int ret = -ENOMEM;
1231         int bfsize = 0;
1232         int queue;
1233         int i;
1234
1235         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1236         if (bfsize < 0)
1237                 bfsize = 0;
1238
1239         if (bfsize < BUF_SIZE_16KiB)
1240                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1241
1242         priv->dma_buf_sz = bfsize;
1243
1244         /* RX INITIALIZATION */
1245         netif_dbg(priv, probe, priv->dev,
1246                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1247
1248         for (queue = 0; queue < rx_count; queue++) {
1249                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1250
1251                 netif_dbg(priv, probe, priv->dev,
1252                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1253                           (u32)rx_q->dma_rx_phy);
1254
1255                 for (i = 0; i < DMA_RX_SIZE; i++) {
1256                         struct dma_desc *p;
1257
1258                         if (priv->extend_desc)
1259                                 p = &((rx_q->dma_erx + i)->basic);
1260                         else
1261                                 p = rx_q->dma_rx + i;
1262
1263                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1264                                                      queue);
1265                         if (ret)
1266                                 goto err_init_rx_buffers;
1267
1268                         netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1269                                   rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1270                                   (unsigned int)rx_q->rx_skbuff_dma[i]);
1271                 }
1272
1273                 rx_q->cur_rx = 0;
1274                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1275
1276                 stmmac_clear_rx_descriptors(priv, queue);
1277
1278                 /* Setup the chained descriptor addresses */
1279                 if (priv->mode == STMMAC_CHAIN_MODE) {
1280                         if (priv->extend_desc)
1281                                 stmmac_mode_init(priv, rx_q->dma_erx,
1282                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1283                         else
1284                                 stmmac_mode_init(priv, rx_q->dma_rx,
1285                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1286                 }
1287         }
1288
1289         buf_sz = bfsize;
1290
1291         return 0;
1292
1293 err_init_rx_buffers:
1294         while (queue >= 0) {
1295                 while (--i >= 0)
1296                         stmmac_free_rx_buffer(priv, queue, i);
1297
1298                 if (queue == 0)
1299                         break;
1300
1301                 i = DMA_RX_SIZE;
1302                 queue--;
1303         }
1304
1305         return ret;
1306 }
1307
1308 /**
1309  * init_dma_tx_desc_rings - init the TX descriptor rings
1310  * @dev: net device structure.
1311  * Description: this function initializes the DMA TX descriptors
1312  * and allocates the socket buffers. It supports the chained and ring
1313  * modes.
1314  */
1315 static int init_dma_tx_desc_rings(struct net_device *dev)
1316 {
1317         struct stmmac_priv *priv = netdev_priv(dev);
1318         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1319         u32 queue;
1320         int i;
1321
1322         for (queue = 0; queue < tx_queue_cnt; queue++) {
1323                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1324
1325                 netif_dbg(priv, probe, priv->dev,
1326                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1327                          (u32)tx_q->dma_tx_phy);
1328
1329                 /* Setup the chained descriptor addresses */
1330                 if (priv->mode == STMMAC_CHAIN_MODE) {
1331                         if (priv->extend_desc)
1332                                 stmmac_mode_init(priv, tx_q->dma_etx,
1333                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1334                         else
1335                                 stmmac_mode_init(priv, tx_q->dma_tx,
1336                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1337                 }
1338
1339                 for (i = 0; i < DMA_TX_SIZE; i++) {
1340                         struct dma_desc *p;
1341                         if (priv->extend_desc)
1342                                 p = &((tx_q->dma_etx + i)->basic);
1343                         else
1344                                 p = tx_q->dma_tx + i;
1345
1346                         stmmac_clear_desc(priv, p);
1347
1348                         tx_q->tx_skbuff_dma[i].buf = 0;
1349                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1350                         tx_q->tx_skbuff_dma[i].len = 0;
1351                         tx_q->tx_skbuff_dma[i].last_segment = false;
1352                         tx_q->tx_skbuff[i] = NULL;
1353                 }
1354
1355                 tx_q->dirty_tx = 0;
1356                 tx_q->cur_tx = 0;
1357                 tx_q->mss = 0;
1358
1359                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1360         }
1361
1362         return 0;
1363 }
1364
1365 /**
1366  * init_dma_desc_rings - init the RX/TX descriptor rings
1367  * @dev: net device structure
1368  * @flags: gfp flag.
1369  * Description: this function initializes the DMA RX/TX descriptors
1370  * and allocates the socket buffers. It supports the chained and ring
1371  * modes.
1372  */
1373 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1374 {
1375         struct stmmac_priv *priv = netdev_priv(dev);
1376         int ret;
1377
1378         ret = init_dma_rx_desc_rings(dev, flags);
1379         if (ret)
1380                 return ret;
1381
1382         ret = init_dma_tx_desc_rings(dev);
1383
1384         stmmac_clear_descriptors(priv);
1385
1386         if (netif_msg_hw(priv))
1387                 stmmac_display_rings(priv);
1388
1389         return ret;
1390 }
1391
1392 /**
1393  * dma_free_rx_skbufs - free RX dma buffers
1394  * @priv: private structure
1395  * @queue: RX queue index
1396  */
1397 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1398 {
1399         int i;
1400
1401         for (i = 0; i < DMA_RX_SIZE; i++)
1402                 stmmac_free_rx_buffer(priv, queue, i);
1403 }
1404
1405 /**
1406  * dma_free_tx_skbufs - free TX dma buffers
1407  * @priv: private structure
1408  * @queue: TX queue index
1409  */
1410 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1411 {
1412         int i;
1413
1414         for (i = 0; i < DMA_TX_SIZE; i++)
1415                 stmmac_free_tx_buffer(priv, queue, i);
1416 }
1417
1418 /**
1419  * free_dma_rx_desc_resources - free RX dma desc resources
1420  * @priv: private structure
1421  */
1422 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1423 {
1424         u32 rx_count = priv->plat->rx_queues_to_use;
1425         u32 queue;
1426
1427         /* Free RX queue resources */
1428         for (queue = 0; queue < rx_count; queue++) {
1429                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1430
1431                 /* Release the DMA RX socket buffers */
1432                 dma_free_rx_skbufs(priv, queue);
1433
1434                 /* Free DMA regions of consistent memory previously allocated */
1435                 if (!priv->extend_desc)
1436                         dma_free_coherent(priv->device,
1437                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1438                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1439                 else
1440                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1441                                           sizeof(struct dma_extended_desc),
1442                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1443
1444                 kfree(rx_q->rx_skbuff_dma);
1445                 kfree(rx_q->rx_skbuff);
1446         }
1447 }
1448
1449 /**
1450  * free_dma_tx_desc_resources - free TX dma desc resources
1451  * @priv: private structure
1452  */
1453 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1454 {
1455         u32 tx_count = priv->plat->tx_queues_to_use;
1456         u32 queue;
1457
1458         /* Free TX queue resources */
1459         for (queue = 0; queue < tx_count; queue++) {
1460                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1461
1462                 /* Release the DMA TX socket buffers */
1463                 dma_free_tx_skbufs(priv, queue);
1464
1465                 /* Free DMA regions of consistent memory previously allocated */
1466                 if (!priv->extend_desc)
1467                         dma_free_coherent(priv->device,
1468                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1469                                           tx_q->dma_tx, tx_q->dma_tx_phy);
1470                 else
1471                         dma_free_coherent(priv->device, DMA_TX_SIZE *
1472                                           sizeof(struct dma_extended_desc),
1473                                           tx_q->dma_etx, tx_q->dma_tx_phy);
1474
1475                 kfree(tx_q->tx_skbuff_dma);
1476                 kfree(tx_q->tx_skbuff);
1477         }
1478 }
1479
1480 /**
1481  * alloc_dma_rx_desc_resources - alloc RX resources.
1482  * @priv: private structure
1483  * Description: according to which descriptor can be used (extend or basic)
1484  * this function allocates the resources for TX and RX paths. In case of
1485  * reception, for example, it pre-allocated the RX socket buffer in order to
1486  * allow zero-copy mechanism.
1487  */
1488 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1489 {
1490         u32 rx_count = priv->plat->rx_queues_to_use;
1491         int ret = -ENOMEM;
1492         u32 queue;
1493
1494         /* RX queues buffers and DMA */
1495         for (queue = 0; queue < rx_count; queue++) {
1496                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1497
1498                 rx_q->queue_index = queue;
1499                 rx_q->priv_data = priv;
1500
1501                 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1502                                                     sizeof(dma_addr_t),
1503                                                     GFP_KERNEL);
1504                 if (!rx_q->rx_skbuff_dma)
1505                         goto err_dma;
1506
1507                 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1508                                                 sizeof(struct sk_buff *),
1509                                                 GFP_KERNEL);
1510                 if (!rx_q->rx_skbuff)
1511                         goto err_dma;
1512
1513                 if (priv->extend_desc) {
1514                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1515                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1516                                                            &rx_q->dma_rx_phy,
1517                                                            GFP_KERNEL);
1518                         if (!rx_q->dma_erx)
1519                                 goto err_dma;
1520
1521                 } else {
1522                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1523                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1524                                                           &rx_q->dma_rx_phy,
1525                                                           GFP_KERNEL);
1526                         if (!rx_q->dma_rx)
1527                                 goto err_dma;
1528                 }
1529         }
1530
1531         return 0;
1532
1533 err_dma:
1534         free_dma_rx_desc_resources(priv);
1535
1536         return ret;
1537 }
1538
1539 /**
1540  * alloc_dma_tx_desc_resources - alloc TX resources.
1541  * @priv: private structure
1542  * Description: according to which descriptor can be used (extend or basic)
1543  * this function allocates the resources for TX and RX paths. In case of
1544  * reception, for example, it pre-allocated the RX socket buffer in order to
1545  * allow zero-copy mechanism.
1546  */
1547 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1548 {
1549         u32 tx_count = priv->plat->tx_queues_to_use;
1550         int ret = -ENOMEM;
1551         u32 queue;
1552
1553         /* TX queues buffers and DMA */
1554         for (queue = 0; queue < tx_count; queue++) {
1555                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1556
1557                 tx_q->queue_index = queue;
1558                 tx_q->priv_data = priv;
1559
1560                 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1561                                                     sizeof(*tx_q->tx_skbuff_dma),
1562                                                     GFP_KERNEL);
1563                 if (!tx_q->tx_skbuff_dma)
1564                         goto err_dma;
1565
1566                 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1567                                                 sizeof(struct sk_buff *),
1568                                                 GFP_KERNEL);
1569                 if (!tx_q->tx_skbuff)
1570                         goto err_dma;
1571
1572                 if (priv->extend_desc) {
1573                         tx_q->dma_etx = dma_alloc_coherent(priv->device,
1574                                                            DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1575                                                            &tx_q->dma_tx_phy,
1576                                                            GFP_KERNEL);
1577                         if (!tx_q->dma_etx)
1578                                 goto err_dma;
1579                 } else {
1580                         tx_q->dma_tx = dma_alloc_coherent(priv->device,
1581                                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1582                                                           &tx_q->dma_tx_phy,
1583                                                           GFP_KERNEL);
1584                         if (!tx_q->dma_tx)
1585                                 goto err_dma;
1586                 }
1587         }
1588
1589         return 0;
1590
1591 err_dma:
1592         free_dma_tx_desc_resources(priv);
1593
1594         return ret;
1595 }
1596
1597 /**
1598  * alloc_dma_desc_resources - alloc TX/RX resources.
1599  * @priv: private structure
1600  * Description: according to which descriptor can be used (extend or basic)
1601  * this function allocates the resources for TX and RX paths. In case of
1602  * reception, for example, it pre-allocated the RX socket buffer in order to
1603  * allow zero-copy mechanism.
1604  */
1605 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1606 {
1607         /* RX Allocation */
1608         int ret = alloc_dma_rx_desc_resources(priv);
1609
1610         if (ret)
1611                 return ret;
1612
1613         ret = alloc_dma_tx_desc_resources(priv);
1614
1615         return ret;
1616 }
1617
1618 /**
1619  * free_dma_desc_resources - free dma desc resources
1620  * @priv: private structure
1621  */
1622 static void free_dma_desc_resources(struct stmmac_priv *priv)
1623 {
1624         /* Release the DMA RX socket buffers */
1625         free_dma_rx_desc_resources(priv);
1626
1627         /* Release the DMA TX socket buffers */
1628         free_dma_tx_desc_resources(priv);
1629 }
1630
1631 /**
1632  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1633  *  @priv: driver private structure
1634  *  Description: It is used for enabling the rx queues in the MAC
1635  */
1636 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1637 {
1638         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1639         int queue;
1640         u8 mode;
1641
1642         for (queue = 0; queue < rx_queues_count; queue++) {
1643                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1644                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1645         }
1646 }
1647
1648 /**
1649  * stmmac_start_rx_dma - start RX DMA channel
1650  * @priv: driver private structure
1651  * @chan: RX channel index
1652  * Description:
1653  * This starts a RX DMA channel
1654  */
1655 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1656 {
1657         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1658         stmmac_start_rx(priv, priv->ioaddr, chan);
1659 }
1660
1661 /**
1662  * stmmac_start_tx_dma - start TX DMA channel
1663  * @priv: driver private structure
1664  * @chan: TX channel index
1665  * Description:
1666  * This starts a TX DMA channel
1667  */
1668 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1669 {
1670         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1671         stmmac_start_tx(priv, priv->ioaddr, chan);
1672 }
1673
1674 /**
1675  * stmmac_stop_rx_dma - stop RX DMA channel
1676  * @priv: driver private structure
1677  * @chan: RX channel index
1678  * Description:
1679  * This stops a RX DMA channel
1680  */
1681 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1682 {
1683         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1684         stmmac_stop_rx(priv, priv->ioaddr, chan);
1685 }
1686
1687 /**
1688  * stmmac_stop_tx_dma - stop TX DMA channel
1689  * @priv: driver private structure
1690  * @chan: TX channel index
1691  * Description:
1692  * This stops a TX DMA channel
1693  */
1694 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1695 {
1696         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1697         stmmac_stop_tx(priv, priv->ioaddr, chan);
1698 }
1699
1700 /**
1701  * stmmac_start_all_dma - start all RX and TX DMA channels
1702  * @priv: driver private structure
1703  * Description:
1704  * This starts all the RX and TX DMA channels
1705  */
1706 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1707 {
1708         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1709         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1710         u32 chan = 0;
1711
1712         for (chan = 0; chan < rx_channels_count; chan++)
1713                 stmmac_start_rx_dma(priv, chan);
1714
1715         for (chan = 0; chan < tx_channels_count; chan++)
1716                 stmmac_start_tx_dma(priv, chan);
1717 }
1718
1719 /**
1720  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1721  * @priv: driver private structure
1722  * Description:
1723  * This stops the RX and TX DMA channels
1724  */
1725 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1726 {
1727         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1728         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1729         u32 chan = 0;
1730
1731         for (chan = 0; chan < rx_channels_count; chan++)
1732                 stmmac_stop_rx_dma(priv, chan);
1733
1734         for (chan = 0; chan < tx_channels_count; chan++)
1735                 stmmac_stop_tx_dma(priv, chan);
1736 }
1737
1738 /**
1739  *  stmmac_dma_operation_mode - HW DMA operation mode
1740  *  @priv: driver private structure
1741  *  Description: it is used for configuring the DMA operation mode register in
1742  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1743  */
1744 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1745 {
1746         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1747         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1748         int rxfifosz = priv->plat->rx_fifo_size;
1749         int txfifosz = priv->plat->tx_fifo_size;
1750         u32 txmode = 0;
1751         u32 rxmode = 0;
1752         u32 chan = 0;
1753         u8 qmode = 0;
1754
1755         if (rxfifosz == 0)
1756                 rxfifosz = priv->dma_cap.rx_fifo_size;
1757         if (txfifosz == 0)
1758                 txfifosz = priv->dma_cap.tx_fifo_size;
1759
1760         /* Adjust for real per queue fifo size */
1761         rxfifosz /= rx_channels_count;
1762         txfifosz /= tx_channels_count;
1763
1764         if (priv->plat->force_thresh_dma_mode) {
1765                 txmode = tc;
1766                 rxmode = tc;
1767         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1768                 /*
1769                  * In case of GMAC, SF mode can be enabled
1770                  * to perform the TX COE in HW. This depends on:
1771                  * 1) TX COE if actually supported
1772                  * 2) There is no bugged Jumbo frame support
1773                  *    that needs to not insert csum in the TDES.
1774                  */
1775                 txmode = SF_DMA_MODE;
1776                 rxmode = SF_DMA_MODE;
1777                 priv->xstats.threshold = SF_DMA_MODE;
1778         } else {
1779                 txmode = tc;
1780                 rxmode = SF_DMA_MODE;
1781         }
1782
1783         /* configure all channels */
1784         for (chan = 0; chan < rx_channels_count; chan++) {
1785                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1786
1787                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1788                                 rxfifosz, qmode);
1789                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1790                                 chan);
1791         }
1792
1793         for (chan = 0; chan < tx_channels_count; chan++) {
1794                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1795
1796                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1797                                 txfifosz, qmode);
1798         }
1799 }
1800
1801 /**
1802  * stmmac_tx_clean - to manage the transmission completion
1803  * @priv: driver private structure
1804  * @queue: TX queue index
1805  * Description: it reclaims the transmit resources after transmission completes.
1806  */
1807 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1808 {
1809         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1810         unsigned int bytes_compl = 0, pkts_compl = 0;
1811         unsigned int entry, count = 0;
1812
1813         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1814
1815         priv->xstats.tx_clean++;
1816
1817         entry = tx_q->dirty_tx;
1818         while ((entry != tx_q->cur_tx) && (count < budget)) {
1819                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1820                 struct dma_desc *p;
1821                 int status;
1822
1823                 if (priv->extend_desc)
1824                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1825                 else
1826                         p = tx_q->dma_tx + entry;
1827
1828                 status = stmmac_tx_status(priv, &priv->dev->stats,
1829                                 &priv->xstats, p, priv->ioaddr);
1830                 /* Check if the descriptor is owned by the DMA */
1831                 if (unlikely(status & tx_dma_own))
1832                         break;
1833
1834                 count++;
1835
1836                 /* Make sure descriptor fields are read after reading
1837                  * the own bit.
1838                  */
1839                 dma_rmb();
1840
1841                 /* Just consider the last segment and ...*/
1842                 if (likely(!(status & tx_not_ls))) {
1843                         /* ... verify the status error condition */
1844                         if (unlikely(status & tx_err)) {
1845                                 priv->dev->stats.tx_errors++;
1846                         } else {
1847                                 priv->dev->stats.tx_packets++;
1848                                 priv->xstats.tx_pkt_n++;
1849                         }
1850                         stmmac_get_tx_hwtstamp(priv, p, skb);
1851                 }
1852
1853                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1854                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
1855                                 dma_unmap_page(priv->device,
1856                                                tx_q->tx_skbuff_dma[entry].buf,
1857                                                tx_q->tx_skbuff_dma[entry].len,
1858                                                DMA_TO_DEVICE);
1859                         else
1860                                 dma_unmap_single(priv->device,
1861                                                  tx_q->tx_skbuff_dma[entry].buf,
1862                                                  tx_q->tx_skbuff_dma[entry].len,
1863                                                  DMA_TO_DEVICE);
1864                         tx_q->tx_skbuff_dma[entry].buf = 0;
1865                         tx_q->tx_skbuff_dma[entry].len = 0;
1866                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
1867                 }
1868
1869                 stmmac_clean_desc3(priv, tx_q, p);
1870
1871                 tx_q->tx_skbuff_dma[entry].last_segment = false;
1872                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1873
1874                 if (likely(skb != NULL)) {
1875                         pkts_compl++;
1876                         bytes_compl += skb->len;
1877                         dev_consume_skb_any(skb);
1878                         tx_q->tx_skbuff[entry] = NULL;
1879                 }
1880
1881                 stmmac_release_tx_desc(priv, p, priv->mode);
1882
1883                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1884         }
1885         tx_q->dirty_tx = entry;
1886
1887         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1888                                   pkts_compl, bytes_compl);
1889
1890         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1891                                                                 queue))) &&
1892             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1893
1894                 netif_dbg(priv, tx_done, priv->dev,
1895                           "%s: restart transmit\n", __func__);
1896                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1897         }
1898
1899         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1900                 stmmac_enable_eee_mode(priv);
1901                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1902         }
1903
1904         /* We still have pending packets, let's call for a new scheduling */
1905         if (tx_q->dirty_tx != tx_q->cur_tx)
1906                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1907
1908         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1909
1910         return count;
1911 }
1912
1913 /**
1914  * stmmac_tx_err - to manage the tx error
1915  * @priv: driver private structure
1916  * @chan: channel index
1917  * Description: it cleans the descriptors and restarts the transmission
1918  * in case of transmission errors.
1919  */
1920 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1921 {
1922         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1923         int i;
1924
1925         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1926
1927         stmmac_stop_tx_dma(priv, chan);
1928         dma_free_tx_skbufs(priv, chan);
1929         for (i = 0; i < DMA_TX_SIZE; i++)
1930                 if (priv->extend_desc)
1931                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1932                                         priv->mode, (i == DMA_TX_SIZE - 1));
1933                 else
1934                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1935                                         priv->mode, (i == DMA_TX_SIZE - 1));
1936         tx_q->dirty_tx = 0;
1937         tx_q->cur_tx = 0;
1938         tx_q->mss = 0;
1939         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1940         stmmac_start_tx_dma(priv, chan);
1941
1942         priv->dev->stats.tx_errors++;
1943         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1944 }
1945
1946 /**
1947  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1948  *  @priv: driver private structure
1949  *  @txmode: TX operating mode
1950  *  @rxmode: RX operating mode
1951  *  @chan: channel index
1952  *  Description: it is used for configuring of the DMA operation mode in
1953  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1954  *  mode.
1955  */
1956 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1957                                           u32 rxmode, u32 chan)
1958 {
1959         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1960         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1961         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1962         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1963         int rxfifosz = priv->plat->rx_fifo_size;
1964         int txfifosz = priv->plat->tx_fifo_size;
1965
1966         if (rxfifosz == 0)
1967                 rxfifosz = priv->dma_cap.rx_fifo_size;
1968         if (txfifosz == 0)
1969                 txfifosz = priv->dma_cap.tx_fifo_size;
1970
1971         /* Adjust for real per queue fifo size */
1972         rxfifosz /= rx_channels_count;
1973         txfifosz /= tx_channels_count;
1974
1975         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
1976         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
1977 }
1978
1979 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
1980 {
1981         int ret;
1982
1983         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
1984                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
1985         if (ret && (ret != -EINVAL)) {
1986                 stmmac_global_err(priv);
1987                 return true;
1988         }
1989
1990         return false;
1991 }
1992
1993 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
1994 {
1995         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
1996                                                  &priv->xstats, chan);
1997         struct stmmac_channel *ch = &priv->channel[chan];
1998
1999         if (status)
2000                 status |= handle_rx | handle_tx;
2001
2002         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2003                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2004                 napi_schedule_irqoff(&ch->rx_napi);
2005         }
2006
2007         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2008                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2009                 napi_schedule_irqoff(&ch->tx_napi);
2010         }
2011
2012         return status;
2013 }
2014
2015 /**
2016  * stmmac_dma_interrupt - DMA ISR
2017  * @priv: driver private structure
2018  * Description: this is the DMA ISR. It is called by the main ISR.
2019  * It calls the dwmac dma routine and schedule poll method in case of some
2020  * work can be done.
2021  */
2022 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2023 {
2024         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2025         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2026         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2027                                 tx_channel_count : rx_channel_count;
2028         u32 chan;
2029         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2030
2031         /* Make sure we never check beyond our status buffer. */
2032         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2033                 channels_to_check = ARRAY_SIZE(status);
2034
2035         for (chan = 0; chan < channels_to_check; chan++)
2036                 status[chan] = stmmac_napi_check(priv, chan);
2037
2038         for (chan = 0; chan < tx_channel_count; chan++) {
2039                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2040                         /* Try to bump up the dma threshold on this failure */
2041                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2042                             (tc <= 256)) {
2043                                 tc += 64;
2044                                 if (priv->plat->force_thresh_dma_mode)
2045                                         stmmac_set_dma_operation_mode(priv,
2046                                                                       tc,
2047                                                                       tc,
2048                                                                       chan);
2049                                 else
2050                                         stmmac_set_dma_operation_mode(priv,
2051                                                                     tc,
2052                                                                     SF_DMA_MODE,
2053                                                                     chan);
2054                                 priv->xstats.threshold = tc;
2055                         }
2056                 } else if (unlikely(status[chan] == tx_hard_error)) {
2057                         stmmac_tx_err(priv, chan);
2058                 }
2059         }
2060 }
2061
2062 /**
2063  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2064  * @priv: driver private structure
2065  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2066  */
2067 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2068 {
2069         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2070                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2071
2072         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2073
2074         if (priv->dma_cap.rmon) {
2075                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2076                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2077         } else
2078                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2079 }
2080
2081 /**
2082  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2083  * @priv: driver private structure
2084  * Description:
2085  *  new GMAC chip generations have a new register to indicate the
2086  *  presence of the optional feature/functions.
2087  *  This can be also used to override the value passed through the
2088  *  platform and necessary for old MAC10/100 and GMAC chips.
2089  */
2090 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2091 {
2092         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2093 }
2094
2095 /**
2096  * stmmac_check_ether_addr - check if the MAC addr is valid
2097  * @priv: driver private structure
2098  * Description:
2099  * it is to verify if the MAC address is valid, in case of failures it
2100  * generates a random MAC address
2101  */
2102 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2103 {
2104         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2105                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2106                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2107                         eth_hw_addr_random(priv->dev);
2108                 dev_info(priv->device, "device MAC address %pM\n",
2109                          priv->dev->dev_addr);
2110         }
2111 }
2112
2113 /**
2114  * stmmac_init_dma_engine - DMA init.
2115  * @priv: driver private structure
2116  * Description:
2117  * It inits the DMA invoking the specific MAC/GMAC callback.
2118  * Some DMA parameters can be passed from the platform;
2119  * in case of these are not passed a default is kept for the MAC or GMAC.
2120  */
2121 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2122 {
2123         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2124         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2125         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2126         struct stmmac_rx_queue *rx_q;
2127         struct stmmac_tx_queue *tx_q;
2128         u32 chan = 0;
2129         int atds = 0;
2130         int ret = 0;
2131
2132         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2133                 dev_err(priv->device, "Invalid DMA configuration\n");
2134                 return -EINVAL;
2135         }
2136
2137         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2138                 atds = 1;
2139
2140         ret = stmmac_reset(priv, priv->ioaddr);
2141         if (ret) {
2142                 dev_err(priv->device, "Failed to reset the dma\n");
2143                 return ret;
2144         }
2145
2146         /* DMA Configuration */
2147         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2148
2149         if (priv->plat->axi)
2150                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2151
2152         /* DMA CSR Channel configuration */
2153         for (chan = 0; chan < dma_csr_ch; chan++)
2154                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2155
2156         /* DMA RX Channel Configuration */
2157         for (chan = 0; chan < rx_channels_count; chan++) {
2158                 rx_q = &priv->rx_queue[chan];
2159
2160                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2161                                     rx_q->dma_rx_phy, chan);
2162
2163                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2164                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2165                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2166                                        rx_q->rx_tail_addr, chan);
2167         }
2168
2169         /* DMA TX Channel Configuration */
2170         for (chan = 0; chan < tx_channels_count; chan++) {
2171                 tx_q = &priv->tx_queue[chan];
2172
2173                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2174                                     tx_q->dma_tx_phy, chan);
2175
2176                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2177                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2178                                        tx_q->tx_tail_addr, chan);
2179         }
2180
2181         return ret;
2182 }
2183
2184 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2185 {
2186         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2187
2188         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2189 }
2190
2191 /**
2192  * stmmac_tx_timer - mitigation sw timer for tx.
2193  * @data: data pointer
2194  * Description:
2195  * This is the timer handler to directly invoke the stmmac_tx_clean.
2196  */
2197 static void stmmac_tx_timer(struct timer_list *t)
2198 {
2199         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2200         struct stmmac_priv *priv = tx_q->priv_data;
2201         struct stmmac_channel *ch;
2202
2203         ch = &priv->channel[tx_q->queue_index];
2204
2205         /*
2206          * If NAPI is already running we can miss some events. Let's rearm
2207          * the timer and try again.
2208          */
2209         if (likely(napi_schedule_prep(&ch->tx_napi)))
2210                 __napi_schedule(&ch->tx_napi);
2211         else
2212                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2213 }
2214
2215 /**
2216  * stmmac_init_tx_coalesce - init tx mitigation options.
2217  * @priv: driver private structure
2218  * Description:
2219  * This inits the transmit coalesce parameters: i.e. timer rate,
2220  * timer handler and default threshold used for enabling the
2221  * interrupt on completion bit.
2222  */
2223 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2224 {
2225         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2226         u32 chan;
2227
2228         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2229         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2230
2231         for (chan = 0; chan < tx_channel_count; chan++) {
2232                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2233
2234                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2235         }
2236 }
2237
2238 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2239 {
2240         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2241         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2242         u32 chan;
2243
2244         /* set TX ring length */
2245         for (chan = 0; chan < tx_channels_count; chan++)
2246                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2247                                 (DMA_TX_SIZE - 1), chan);
2248
2249         /* set RX ring length */
2250         for (chan = 0; chan < rx_channels_count; chan++)
2251                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2252                                 (DMA_RX_SIZE - 1), chan);
2253 }
2254
2255 /**
2256  *  stmmac_set_tx_queue_weight - Set TX queue weight
2257  *  @priv: driver private structure
2258  *  Description: It is used for setting TX queues weight
2259  */
2260 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2261 {
2262         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2263         u32 weight;
2264         u32 queue;
2265
2266         for (queue = 0; queue < tx_queues_count; queue++) {
2267                 weight = priv->plat->tx_queues_cfg[queue].weight;
2268                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2269         }
2270 }
2271
2272 /**
2273  *  stmmac_configure_cbs - Configure CBS in TX queue
2274  *  @priv: driver private structure
2275  *  Description: It is used for configuring CBS in AVB TX queues
2276  */
2277 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2278 {
2279         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2280         u32 mode_to_use;
2281         u32 queue;
2282
2283         /* queue 0 is reserved for legacy traffic */
2284         for (queue = 1; queue < tx_queues_count; queue++) {
2285                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2286                 if (mode_to_use == MTL_QUEUE_DCB)
2287                         continue;
2288
2289                 stmmac_config_cbs(priv, priv->hw,
2290                                 priv->plat->tx_queues_cfg[queue].send_slope,
2291                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2292                                 priv->plat->tx_queues_cfg[queue].high_credit,
2293                                 priv->plat->tx_queues_cfg[queue].low_credit,
2294                                 queue);
2295         }
2296 }
2297
2298 /**
2299  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2300  *  @priv: driver private structure
2301  *  Description: It is used for mapping RX queues to RX dma channels
2302  */
2303 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2304 {
2305         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2306         u32 queue;
2307         u32 chan;
2308
2309         for (queue = 0; queue < rx_queues_count; queue++) {
2310                 chan = priv->plat->rx_queues_cfg[queue].chan;
2311                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2312         }
2313 }
2314
2315 /**
2316  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2317  *  @priv: driver private structure
2318  *  Description: It is used for configuring the RX Queue Priority
2319  */
2320 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2321 {
2322         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2323         u32 queue;
2324         u32 prio;
2325
2326         for (queue = 0; queue < rx_queues_count; queue++) {
2327                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2328                         continue;
2329
2330                 prio = priv->plat->rx_queues_cfg[queue].prio;
2331                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2332         }
2333 }
2334
2335 /**
2336  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2337  *  @priv: driver private structure
2338  *  Description: It is used for configuring the TX Queue Priority
2339  */
2340 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2341 {
2342         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2343         u32 queue;
2344         u32 prio;
2345
2346         for (queue = 0; queue < tx_queues_count; queue++) {
2347                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2348                         continue;
2349
2350                 prio = priv->plat->tx_queues_cfg[queue].prio;
2351                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2352         }
2353 }
2354
2355 /**
2356  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2357  *  @priv: driver private structure
2358  *  Description: It is used for configuring the RX queue routing
2359  */
2360 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2361 {
2362         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2363         u32 queue;
2364         u8 packet;
2365
2366         for (queue = 0; queue < rx_queues_count; queue++) {
2367                 /* no specific packet type routing specified for the queue */
2368                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2369                         continue;
2370
2371                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2372                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2373         }
2374 }
2375
2376 /**
2377  *  stmmac_mtl_configuration - Configure MTL
2378  *  @priv: driver private structure
2379  *  Description: It is used for configurring MTL
2380  */
2381 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2382 {
2383         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2384         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2385
2386         if (tx_queues_count > 1)
2387                 stmmac_set_tx_queue_weight(priv);
2388
2389         /* Configure MTL RX algorithms */
2390         if (rx_queues_count > 1)
2391                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2392                                 priv->plat->rx_sched_algorithm);
2393
2394         /* Configure MTL TX algorithms */
2395         if (tx_queues_count > 1)
2396                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2397                                 priv->plat->tx_sched_algorithm);
2398
2399         /* Configure CBS in AVB TX queues */
2400         if (tx_queues_count > 1)
2401                 stmmac_configure_cbs(priv);
2402
2403         /* Map RX MTL to DMA channels */
2404         stmmac_rx_queue_dma_chan_map(priv);
2405
2406         /* Enable MAC RX Queues */
2407         stmmac_mac_enable_rx_queues(priv);
2408
2409         /* Set RX priorities */
2410         if (rx_queues_count > 1)
2411                 stmmac_mac_config_rx_queues_prio(priv);
2412
2413         /* Set TX priorities */
2414         if (tx_queues_count > 1)
2415                 stmmac_mac_config_tx_queues_prio(priv);
2416
2417         /* Set RX routing */
2418         if (rx_queues_count > 1)
2419                 stmmac_mac_config_rx_queues_routing(priv);
2420 }
2421
2422 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2423 {
2424         if (priv->dma_cap.asp) {
2425                 netdev_info(priv->dev, "Enabling Safety Features\n");
2426                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2427         } else {
2428                 netdev_info(priv->dev, "No Safety Features support found\n");
2429         }
2430 }
2431
2432 /**
2433  * stmmac_hw_setup - setup mac in a usable state.
2434  *  @dev : pointer to the device structure.
2435  *  Description:
2436  *  this is the main function to setup the HW in a usable state because the
2437  *  dma engine is reset, the core registers are configured (e.g. AXI,
2438  *  Checksum features, timers). The DMA is ready to start receiving and
2439  *  transmitting.
2440  *  Return value:
2441  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2442  *  file on failure.
2443  */
2444 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2445 {
2446         struct stmmac_priv *priv = netdev_priv(dev);
2447         u32 rx_cnt = priv->plat->rx_queues_to_use;
2448         u32 tx_cnt = priv->plat->tx_queues_to_use;
2449         u32 chan;
2450         int ret;
2451
2452         /* DMA initialization and SW reset */
2453         ret = stmmac_init_dma_engine(priv);
2454         if (ret < 0) {
2455                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2456                            __func__);
2457                 return ret;
2458         }
2459
2460         /* Copy the MAC addr into the HW  */
2461         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2462
2463         /* PS and related bits will be programmed according to the speed */
2464         if (priv->hw->pcs) {
2465                 int speed = priv->plat->mac_port_sel_speed;
2466
2467                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2468                     (speed == SPEED_1000)) {
2469                         priv->hw->ps = speed;
2470                 } else {
2471                         dev_warn(priv->device, "invalid port speed\n");
2472                         priv->hw->ps = 0;
2473                 }
2474         }
2475
2476         /* Initialize the MAC Core */
2477         stmmac_core_init(priv, priv->hw, dev);
2478
2479         /* Initialize MTL*/
2480         stmmac_mtl_configuration(priv);
2481
2482         /* Initialize Safety Features */
2483         stmmac_safety_feat_configuration(priv);
2484
2485         ret = stmmac_rx_ipc(priv, priv->hw);
2486         if (!ret) {
2487                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2488                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2489                 priv->hw->rx_csum = 0;
2490         }
2491
2492         /* Enable the MAC Rx/Tx */
2493         stmmac_mac_set(priv, priv->ioaddr, true);
2494
2495         /* Set the HW DMA mode and the COE */
2496         stmmac_dma_operation_mode(priv);
2497
2498         stmmac_mmc_setup(priv);
2499
2500         if (init_ptp) {
2501                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2502                 if (ret < 0)
2503                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2504
2505                 ret = stmmac_init_ptp(priv);
2506                 if (ret == -EOPNOTSUPP)
2507                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2508                 else if (ret)
2509                         netdev_warn(priv->dev, "PTP init failed\n");
2510         }
2511
2512         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2513
2514         if (priv->use_riwt) {
2515                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2516                 if (!ret)
2517                         priv->rx_riwt = MAX_DMA_RIWT;
2518         }
2519
2520         if (priv->hw->pcs)
2521                 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2522
2523         /* set TX and RX rings length */
2524         stmmac_set_rings_length(priv);
2525
2526         /* Enable TSO */
2527         if (priv->tso) {
2528                 for (chan = 0; chan < tx_cnt; chan++)
2529                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2530         }
2531
2532         /* Start the ball rolling... */
2533         stmmac_start_all_dma(priv);
2534
2535         return 0;
2536 }
2537
2538 static void stmmac_hw_teardown(struct net_device *dev)
2539 {
2540         struct stmmac_priv *priv = netdev_priv(dev);
2541
2542         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2543 }
2544
2545 /**
2546  *  stmmac_open - open entry point of the driver
2547  *  @dev : pointer to the device structure.
2548  *  Description:
2549  *  This function is the open entry point of the driver.
2550  *  Return value:
2551  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2552  *  file on failure.
2553  */
2554 static int stmmac_open(struct net_device *dev)
2555 {
2556         struct stmmac_priv *priv = netdev_priv(dev);
2557         u32 chan;
2558         int ret;
2559
2560         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2561             priv->hw->pcs != STMMAC_PCS_TBI &&
2562             priv->hw->pcs != STMMAC_PCS_RTBI) {
2563                 ret = stmmac_init_phy(dev);
2564                 if (ret) {
2565                         netdev_err(priv->dev,
2566                                    "%s: Cannot attach to PHY (error: %d)\n",
2567                                    __func__, ret);
2568                         return ret;
2569                 }
2570         }
2571
2572         /* Extra statistics */
2573         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2574         priv->xstats.threshold = tc;
2575
2576         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2577         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2578
2579         ret = alloc_dma_desc_resources(priv);
2580         if (ret < 0) {
2581                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2582                            __func__);
2583                 goto dma_desc_error;
2584         }
2585
2586         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2587         if (ret < 0) {
2588                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2589                            __func__);
2590                 goto init_error;
2591         }
2592
2593         ret = stmmac_hw_setup(dev, true);
2594         if (ret < 0) {
2595                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2596                 goto init_error;
2597         }
2598
2599         stmmac_init_tx_coalesce(priv);
2600
2601         phylink_start(priv->phylink);
2602
2603         /* Request the IRQ lines */
2604         ret = request_irq(dev->irq, stmmac_interrupt,
2605                           IRQF_SHARED, dev->name, dev);
2606         if (unlikely(ret < 0)) {
2607                 netdev_err(priv->dev,
2608                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2609                            __func__, dev->irq, ret);
2610                 goto irq_error;
2611         }
2612
2613         /* Request the Wake IRQ in case of another line is used for WoL */
2614         if (priv->wol_irq != dev->irq) {
2615                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2616                                   IRQF_SHARED, dev->name, dev);
2617                 if (unlikely(ret < 0)) {
2618                         netdev_err(priv->dev,
2619                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2620                                    __func__, priv->wol_irq, ret);
2621                         goto wolirq_error;
2622                 }
2623         }
2624
2625         /* Request the IRQ lines */
2626         if (priv->lpi_irq > 0) {
2627                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2628                                   dev->name, dev);
2629                 if (unlikely(ret < 0)) {
2630                         netdev_err(priv->dev,
2631                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2632                                    __func__, priv->lpi_irq, ret);
2633                         goto lpiirq_error;
2634                 }
2635         }
2636
2637         stmmac_enable_all_queues(priv);
2638         stmmac_start_all_queues(priv);
2639
2640         return 0;
2641
2642 lpiirq_error:
2643         if (priv->wol_irq != dev->irq)
2644                 free_irq(priv->wol_irq, dev);
2645 wolirq_error:
2646         free_irq(dev->irq, dev);
2647 irq_error:
2648         phylink_stop(priv->phylink);
2649
2650         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2651                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2652
2653         stmmac_hw_teardown(dev);
2654 init_error:
2655         free_dma_desc_resources(priv);
2656 dma_desc_error:
2657         phylink_disconnect_phy(priv->phylink);
2658         return ret;
2659 }
2660
2661 /**
2662  *  stmmac_release - close entry point of the driver
2663  *  @dev : device pointer.
2664  *  Description:
2665  *  This is the stop entry point of the driver.
2666  */
2667 static int stmmac_release(struct net_device *dev)
2668 {
2669         struct stmmac_priv *priv = netdev_priv(dev);
2670         u32 chan;
2671
2672         if (priv->eee_enabled)
2673                 del_timer_sync(&priv->eee_ctrl_timer);
2674
2675         /* Stop and disconnect the PHY */
2676         phylink_stop(priv->phylink);
2677         phylink_disconnect_phy(priv->phylink);
2678
2679         stmmac_stop_all_queues(priv);
2680
2681         stmmac_disable_all_queues(priv);
2682
2683         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2684                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2685
2686         /* Free the IRQ lines */
2687         free_irq(dev->irq, dev);
2688         if (priv->wol_irq != dev->irq)
2689                 free_irq(priv->wol_irq, dev);
2690         if (priv->lpi_irq > 0)
2691                 free_irq(priv->lpi_irq, dev);
2692
2693         /* Stop TX/RX DMA and clear the descriptors */
2694         stmmac_stop_all_dma(priv);
2695
2696         /* Release and free the Rx/Tx resources */
2697         free_dma_desc_resources(priv);
2698
2699         /* Disable the MAC Rx/Tx */
2700         stmmac_mac_set(priv, priv->ioaddr, false);
2701
2702         netif_carrier_off(dev);
2703
2704         stmmac_release_ptp(priv);
2705
2706         return 0;
2707 }
2708
2709 /**
2710  *  stmmac_tso_allocator - close entry point of the driver
2711  *  @priv: driver private structure
2712  *  @des: buffer start address
2713  *  @total_len: total length to fill in descriptors
2714  *  @last_segmant: condition for the last descriptor
2715  *  @queue: TX queue index
2716  *  Description:
2717  *  This function fills descriptor and request new descriptors according to
2718  *  buffer length to fill
2719  */
2720 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2721                                  int total_len, bool last_segment, u32 queue)
2722 {
2723         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2724         struct dma_desc *desc;
2725         u32 buff_size;
2726         int tmp_len;
2727
2728         tmp_len = total_len;
2729
2730         while (tmp_len > 0) {
2731                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2732                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2733                 desc = tx_q->dma_tx + tx_q->cur_tx;
2734
2735                 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2736                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2737                             TSO_MAX_BUFF_SIZE : tmp_len;
2738
2739                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2740                                 0, 1,
2741                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2742                                 0, 0);
2743
2744                 tmp_len -= TSO_MAX_BUFF_SIZE;
2745         }
2746 }
2747
2748 /**
2749  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2750  *  @skb : the socket buffer
2751  *  @dev : device pointer
2752  *  Description: this is the transmit function that is called on TSO frames
2753  *  (support available on GMAC4 and newer chips).
2754  *  Diagram below show the ring programming in case of TSO frames:
2755  *
2756  *  First Descriptor
2757  *   --------
2758  *   | DES0 |---> buffer1 = L2/L3/L4 header
2759  *   | DES1 |---> TCP Payload (can continue on next descr...)
2760  *   | DES2 |---> buffer 1 and 2 len
2761  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2762  *   --------
2763  *      |
2764  *     ...
2765  *      |
2766  *   --------
2767  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2768  *   | DES1 | --|
2769  *   | DES2 | --> buffer 1 and 2 len
2770  *   | DES3 |
2771  *   --------
2772  *
2773  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2774  */
2775 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2776 {
2777         struct dma_desc *desc, *first, *mss_desc = NULL;
2778         struct stmmac_priv *priv = netdev_priv(dev);
2779         int nfrags = skb_shinfo(skb)->nr_frags;
2780         u32 queue = skb_get_queue_mapping(skb);
2781         unsigned int first_entry, des;
2782         struct stmmac_tx_queue *tx_q;
2783         int tmp_pay_len = 0;
2784         u32 pay_len, mss;
2785         u8 proto_hdr_len;
2786         int i;
2787
2788         tx_q = &priv->tx_queue[queue];
2789
2790         /* Compute header lengths */
2791         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2792
2793         /* Desc availability based on threshold should be enough safe */
2794         if (unlikely(stmmac_tx_avail(priv, queue) <
2795                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2796                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2797                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2798                                                                 queue));
2799                         /* This is a hard error, log it. */
2800                         netdev_err(priv->dev,
2801                                    "%s: Tx Ring full when queue awake\n",
2802                                    __func__);
2803                 }
2804                 return NETDEV_TX_BUSY;
2805         }
2806
2807         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2808
2809         mss = skb_shinfo(skb)->gso_size;
2810
2811         /* set new MSS value if needed */
2812         if (mss != tx_q->mss) {
2813                 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2814                 stmmac_set_mss(priv, mss_desc, mss);
2815                 tx_q->mss = mss;
2816                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2817                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2818         }
2819
2820         if (netif_msg_tx_queued(priv)) {
2821                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2822                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2823                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2824                         skb->data_len);
2825         }
2826
2827         first_entry = tx_q->cur_tx;
2828         WARN_ON(tx_q->tx_skbuff[first_entry]);
2829
2830         desc = tx_q->dma_tx + first_entry;
2831         first = desc;
2832
2833         /* first descriptor: fill Headers on Buf1 */
2834         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2835                              DMA_TO_DEVICE);
2836         if (dma_mapping_error(priv->device, des))
2837                 goto dma_map_err;
2838
2839         tx_q->tx_skbuff_dma[first_entry].buf = des;
2840         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2841
2842         first->des0 = cpu_to_le32(des);
2843
2844         /* Fill start of payload in buff2 of first descriptor */
2845         if (pay_len)
2846                 first->des1 = cpu_to_le32(des + proto_hdr_len);
2847
2848         /* If needed take extra descriptors to fill the remaining payload */
2849         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2850
2851         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2852
2853         /* Prepare fragments */
2854         for (i = 0; i < nfrags; i++) {
2855                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2856
2857                 des = skb_frag_dma_map(priv->device, frag, 0,
2858                                        skb_frag_size(frag),
2859                                        DMA_TO_DEVICE);
2860                 if (dma_mapping_error(priv->device, des))
2861                         goto dma_map_err;
2862
2863                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2864                                      (i == nfrags - 1), queue);
2865
2866                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2867                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2868                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2869         }
2870
2871         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2872
2873         /* Only the last descriptor gets to point to the skb. */
2874         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2875
2876         /* We've used all descriptors we need for this skb, however,
2877          * advance cur_tx so that it references a fresh descriptor.
2878          * ndo_start_xmit will fill this descriptor the next time it's
2879          * called and stmmac_tx_clean may clean up to this descriptor.
2880          */
2881         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2882
2883         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2884                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2885                           __func__);
2886                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2887         }
2888
2889         dev->stats.tx_bytes += skb->len;
2890         priv->xstats.tx_tso_frames++;
2891         priv->xstats.tx_tso_nfrags += nfrags;
2892
2893         /* Manage tx mitigation */
2894         tx_q->tx_count_frames += nfrags + 1;
2895         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
2896             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
2897             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2898             priv->hwts_tx_en)) {
2899                 stmmac_tx_timer_arm(priv, queue);
2900         } else {
2901                 tx_q->tx_count_frames = 0;
2902                 stmmac_set_tx_ic(priv, desc);
2903                 priv->xstats.tx_set_ic_bit++;
2904         }
2905
2906         skb_tx_timestamp(skb);
2907
2908         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2909                      priv->hwts_tx_en)) {
2910                 /* declare that device is doing timestamping */
2911                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2912                 stmmac_enable_tx_timestamp(priv, first);
2913         }
2914
2915         /* Complete the first descriptor before granting the DMA */
2916         stmmac_prepare_tso_tx_desc(priv, first, 1,
2917                         proto_hdr_len,
2918                         pay_len,
2919                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2920                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2921
2922         /* If context desc is used to change MSS */
2923         if (mss_desc) {
2924                 /* Make sure that first descriptor has been completely
2925                  * written, including its own bit. This is because MSS is
2926                  * actually before first descriptor, so we need to make
2927                  * sure that MSS's own bit is the last thing written.
2928                  */
2929                 dma_wmb();
2930                 stmmac_set_tx_owner(priv, mss_desc);
2931         }
2932
2933         /* The own bit must be the latest setting done when prepare the
2934          * descriptor and then barrier is needed to make sure that
2935          * all is coherent before granting the DMA engine.
2936          */
2937         wmb();
2938
2939         if (netif_msg_pktdata(priv)) {
2940                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2941                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2942                         tx_q->cur_tx, first, nfrags);
2943
2944                 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
2945
2946                 pr_info(">>> frame to be transmitted: ");
2947                 print_pkt(skb->data, skb_headlen(skb));
2948         }
2949
2950         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2951
2952         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
2953         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
2954
2955         return NETDEV_TX_OK;
2956
2957 dma_map_err:
2958         dev_err(priv->device, "Tx dma map failed\n");
2959         dev_kfree_skb(skb);
2960         priv->dev->stats.tx_dropped++;
2961         return NETDEV_TX_OK;
2962 }
2963
2964 /**
2965  *  stmmac_xmit - Tx entry point of the driver
2966  *  @skb : the socket buffer
2967  *  @dev : device pointer
2968  *  Description : this is the tx entry point of the driver.
2969  *  It programs the chain or the ring and supports oversized frames
2970  *  and SG feature.
2971  */
2972 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2973 {
2974         struct stmmac_priv *priv = netdev_priv(dev);
2975         unsigned int nopaged_len = skb_headlen(skb);
2976         int i, csum_insertion = 0, is_jumbo = 0;
2977         u32 queue = skb_get_queue_mapping(skb);
2978         int nfrags = skb_shinfo(skb)->nr_frags;
2979         int entry;
2980         unsigned int first_entry;
2981         struct dma_desc *desc, *first;
2982         struct stmmac_tx_queue *tx_q;
2983         unsigned int enh_desc;
2984         unsigned int des;
2985
2986         tx_q = &priv->tx_queue[queue];
2987
2988         if (priv->tx_path_in_lpi_mode)
2989                 stmmac_disable_eee_mode(priv);
2990
2991         /* Manage oversized TCP frames for GMAC4 device */
2992         if (skb_is_gso(skb) && priv->tso) {
2993                 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
2994                         /*
2995                          * There is no way to determine the number of TSO
2996                          * capable Queues. Let's use always the Queue 0
2997                          * because if TSO is supported then at least this
2998                          * one will be capable.
2999                          */
3000                         skb_set_queue_mapping(skb, 0);
3001
3002                         return stmmac_tso_xmit(skb, dev);
3003                 }
3004         }
3005
3006         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3007                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3008                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3009                                                                 queue));
3010                         /* This is a hard error, log it. */
3011                         netdev_err(priv->dev,
3012                                    "%s: Tx Ring full when queue awake\n",
3013                                    __func__);
3014                 }
3015                 return NETDEV_TX_BUSY;
3016         }
3017
3018         entry = tx_q->cur_tx;
3019         first_entry = entry;
3020         WARN_ON(tx_q->tx_skbuff[first_entry]);
3021
3022         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3023
3024         if (likely(priv->extend_desc))
3025                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3026         else
3027                 desc = tx_q->dma_tx + entry;
3028
3029         first = desc;
3030
3031         enh_desc = priv->plat->enh_desc;
3032         /* To program the descriptors according to the size of the frame */
3033         if (enh_desc)
3034                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3035
3036         if (unlikely(is_jumbo)) {
3037                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3038                 if (unlikely(entry < 0) && (entry != -EINVAL))
3039                         goto dma_map_err;
3040         }
3041
3042         for (i = 0; i < nfrags; i++) {
3043                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3044                 int len = skb_frag_size(frag);
3045                 bool last_segment = (i == (nfrags - 1));
3046
3047                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3048                 WARN_ON(tx_q->tx_skbuff[entry]);
3049
3050                 if (likely(priv->extend_desc))
3051                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3052                 else
3053                         desc = tx_q->dma_tx + entry;
3054
3055                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3056                                        DMA_TO_DEVICE);
3057                 if (dma_mapping_error(priv->device, des))
3058                         goto dma_map_err; /* should reuse desc w/o issues */
3059
3060                 tx_q->tx_skbuff_dma[entry].buf = des;
3061
3062                 stmmac_set_desc_addr(priv, desc, des);
3063
3064                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3065                 tx_q->tx_skbuff_dma[entry].len = len;
3066                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3067
3068                 /* Prepare the descriptor and set the own bit too */
3069                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3070                                 priv->mode, 1, last_segment, skb->len);
3071         }
3072
3073         /* Only the last descriptor gets to point to the skb. */
3074         tx_q->tx_skbuff[entry] = skb;
3075
3076         /* We've used all descriptors we need for this skb, however,
3077          * advance cur_tx so that it references a fresh descriptor.
3078          * ndo_start_xmit will fill this descriptor the next time it's
3079          * called and stmmac_tx_clean may clean up to this descriptor.
3080          */
3081         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3082         tx_q->cur_tx = entry;
3083
3084         if (netif_msg_pktdata(priv)) {
3085                 void *tx_head;
3086
3087                 netdev_dbg(priv->dev,
3088                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3089                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3090                            entry, first, nfrags);
3091
3092                 if (priv->extend_desc)
3093                         tx_head = (void *)tx_q->dma_etx;
3094                 else
3095                         tx_head = (void *)tx_q->dma_tx;
3096
3097                 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3098
3099                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3100                 print_pkt(skb->data, skb->len);
3101         }
3102
3103         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3104                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3105                           __func__);
3106                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3107         }
3108
3109         dev->stats.tx_bytes += skb->len;
3110
3111         /* According to the coalesce parameter the IC bit for the latest
3112          * segment is reset and the timer re-started to clean the tx status.
3113          * This approach takes care about the fragments: desc is the first
3114          * element in case of no SG.
3115          */
3116         tx_q->tx_count_frames += nfrags + 1;
3117         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3118             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3119             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3120             priv->hwts_tx_en)) {
3121                 stmmac_tx_timer_arm(priv, queue);
3122         } else {
3123                 tx_q->tx_count_frames = 0;
3124                 stmmac_set_tx_ic(priv, desc);
3125                 priv->xstats.tx_set_ic_bit++;
3126         }
3127
3128         skb_tx_timestamp(skb);
3129
3130         /* Ready to fill the first descriptor and set the OWN bit w/o any
3131          * problems because all the descriptors are actually ready to be
3132          * passed to the DMA engine.
3133          */
3134         if (likely(!is_jumbo)) {
3135                 bool last_segment = (nfrags == 0);
3136
3137                 des = dma_map_single(priv->device, skb->data,
3138                                      nopaged_len, DMA_TO_DEVICE);
3139                 if (dma_mapping_error(priv->device, des))
3140                         goto dma_map_err;
3141
3142                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3143
3144                 stmmac_set_desc_addr(priv, first, des);
3145
3146                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3147                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3148
3149                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3150                              priv->hwts_tx_en)) {
3151                         /* declare that device is doing timestamping */
3152                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3153                         stmmac_enable_tx_timestamp(priv, first);
3154                 }
3155
3156                 /* Prepare the first descriptor setting the OWN bit too */
3157                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3158                                 csum_insertion, priv->mode, 1, last_segment,
3159                                 skb->len);
3160         } else {
3161                 stmmac_set_tx_owner(priv, first);
3162         }
3163
3164         /* The own bit must be the latest setting done when prepare the
3165          * descriptor and then barrier is needed to make sure that
3166          * all is coherent before granting the DMA engine.
3167          */
3168         wmb();
3169
3170         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3171
3172         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3173
3174         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3175         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3176
3177         return NETDEV_TX_OK;
3178
3179 dma_map_err:
3180         netdev_err(priv->dev, "Tx DMA map failed\n");
3181         dev_kfree_skb(skb);
3182         priv->dev->stats.tx_dropped++;
3183         return NETDEV_TX_OK;
3184 }
3185
3186 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3187 {
3188         struct vlan_ethhdr *veth;
3189         __be16 vlan_proto;
3190         u16 vlanid;
3191
3192         veth = (struct vlan_ethhdr *)skb->data;
3193         vlan_proto = veth->h_vlan_proto;
3194
3195         if ((vlan_proto == htons(ETH_P_8021Q) &&
3196              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3197             (vlan_proto == htons(ETH_P_8021AD) &&
3198              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3199                 /* pop the vlan tag */
3200                 vlanid = ntohs(veth->h_vlan_TCI);
3201                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3202                 skb_pull(skb, VLAN_HLEN);
3203                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3204         }
3205 }
3206
3207
3208 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3209 {
3210         if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3211                 return 0;
3212
3213         return 1;
3214 }
3215
3216 /**
3217  * stmmac_rx_refill - refill used skb preallocated buffers
3218  * @priv: driver private structure
3219  * @queue: RX queue index
3220  * Description : this is to reallocate the skb for the reception process
3221  * that is based on zero-copy.
3222  */
3223 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3224 {
3225         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3226         int dirty = stmmac_rx_dirty(priv, queue);
3227         unsigned int entry = rx_q->dirty_rx;
3228
3229         int bfsize = priv->dma_buf_sz;
3230
3231         while (dirty-- > 0) {
3232                 struct dma_desc *p;
3233
3234                 if (priv->extend_desc)
3235                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3236                 else
3237                         p = rx_q->dma_rx + entry;
3238
3239                 if (likely(!rx_q->rx_skbuff[entry])) {
3240                         struct sk_buff *skb;
3241
3242                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3243                         if (unlikely(!skb)) {
3244                                 /* so for a while no zero-copy! */
3245                                 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3246                                 if (unlikely(net_ratelimit()))
3247                                         dev_err(priv->device,
3248                                                 "fail to alloc skb entry %d\n",
3249                                                 entry);
3250                                 break;
3251                         }
3252
3253                         rx_q->rx_skbuff[entry] = skb;
3254                         rx_q->rx_skbuff_dma[entry] =
3255                             dma_map_single(priv->device, skb->data, bfsize,
3256                                            DMA_FROM_DEVICE);
3257                         if (dma_mapping_error(priv->device,
3258                                               rx_q->rx_skbuff_dma[entry])) {
3259                                 netdev_err(priv->dev, "Rx DMA map failed\n");
3260                                 dev_kfree_skb(skb);
3261                                 break;
3262                         }
3263
3264                         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3265                         stmmac_refill_desc3(priv, rx_q, p);
3266
3267                         if (rx_q->rx_zeroc_thresh > 0)
3268                                 rx_q->rx_zeroc_thresh--;
3269
3270                         netif_dbg(priv, rx_status, priv->dev,
3271                                   "refill entry #%d\n", entry);
3272                 }
3273                 dma_wmb();
3274
3275                 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3276
3277                 dma_wmb();
3278
3279                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3280         }
3281         rx_q->dirty_rx = entry;
3282         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3283 }
3284
3285 /**
3286  * stmmac_rx - manage the receive process
3287  * @priv: driver private structure
3288  * @limit: napi bugget
3289  * @queue: RX queue index.
3290  * Description :  this the function called by the napi poll method.
3291  * It gets all the frames inside the ring.
3292  */
3293 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3294 {
3295         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3296         struct stmmac_channel *ch = &priv->channel[queue];
3297         unsigned int next_entry = rx_q->cur_rx;
3298         int coe = priv->hw->rx_csum;
3299         unsigned int count = 0;
3300         bool xmac;
3301
3302         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3303
3304         if (netif_msg_rx_status(priv)) {
3305                 void *rx_head;
3306
3307                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3308                 if (priv->extend_desc)
3309                         rx_head = (void *)rx_q->dma_erx;
3310                 else
3311                         rx_head = (void *)rx_q->dma_rx;
3312
3313                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3314         }
3315         while (count < limit) {
3316                 int entry, status;
3317                 struct dma_desc *p;
3318                 struct dma_desc *np;
3319
3320                 entry = next_entry;
3321
3322                 if (priv->extend_desc)
3323                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3324                 else
3325                         p = rx_q->dma_rx + entry;
3326
3327                 /* read the status of the incoming frame */
3328                 status = stmmac_rx_status(priv, &priv->dev->stats,
3329                                 &priv->xstats, p);
3330                 /* check if managed by the DMA otherwise go ahead */
3331                 if (unlikely(status & dma_own))
3332                         break;
3333
3334                 count++;
3335
3336                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3337                 next_entry = rx_q->cur_rx;
3338
3339                 if (priv->extend_desc)
3340                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3341                 else
3342                         np = rx_q->dma_rx + next_entry;
3343
3344                 prefetch(np);
3345
3346                 if (priv->extend_desc)
3347                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3348                                         &priv->xstats, rx_q->dma_erx + entry);
3349                 if (unlikely(status == discard_frame)) {
3350                         priv->dev->stats.rx_errors++;
3351                         if (priv->hwts_rx_en && !priv->extend_desc) {
3352                                 /* DESC2 & DESC3 will be overwritten by device
3353                                  * with timestamp value, hence reinitialize
3354                                  * them in stmmac_rx_refill() function so that
3355                                  * device can reuse it.
3356                                  */
3357                                 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3358                                 rx_q->rx_skbuff[entry] = NULL;
3359                                 dma_unmap_single(priv->device,
3360                                                  rx_q->rx_skbuff_dma[entry],
3361                                                  priv->dma_buf_sz,
3362                                                  DMA_FROM_DEVICE);
3363                         }
3364                 } else {
3365                         struct sk_buff *skb;
3366                         int frame_len;
3367                         unsigned int des;
3368
3369                         stmmac_get_desc_addr(priv, p, &des);
3370                         frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3371
3372                         /*  If frame length is greater than skb buffer size
3373                          *  (preallocated during init) then the packet is
3374                          *  ignored
3375                          */
3376                         if (frame_len > priv->dma_buf_sz) {
3377                                 if (net_ratelimit())
3378                                         netdev_err(priv->dev,
3379                                                    "len %d larger than size (%d)\n",
3380                                                    frame_len, priv->dma_buf_sz);
3381                                 priv->dev->stats.rx_length_errors++;
3382                                 continue;
3383                         }
3384
3385                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3386                          * Type frames (LLC/LLC-SNAP)
3387                          *
3388                          * llc_snap is never checked in GMAC >= 4, so this ACS
3389                          * feature is always disabled and packets need to be
3390                          * stripped manually.
3391                          */
3392                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3393                             unlikely(status != llc_snap))
3394                                 frame_len -= ETH_FCS_LEN;
3395
3396                         if (netif_msg_rx_status(priv)) {
3397                                 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3398                                            p, entry, des);
3399                                 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3400                                            frame_len, status);
3401                         }
3402
3403                         /* The zero-copy is always used for all the sizes
3404                          * in case of GMAC4 because it needs
3405                          * to refill the used descriptors, always.
3406                          */
3407                         if (unlikely(!xmac &&
3408                                      ((frame_len < priv->rx_copybreak) ||
3409                                      stmmac_rx_threshold_count(rx_q)))) {
3410                                 skb = netdev_alloc_skb_ip_align(priv->dev,
3411                                                                 frame_len);
3412                                 if (unlikely(!skb)) {
3413                                         if (net_ratelimit())
3414                                                 dev_warn(priv->device,
3415                                                          "packet dropped\n");
3416                                         priv->dev->stats.rx_dropped++;
3417                                         continue;
3418                                 }
3419
3420                                 dma_sync_single_for_cpu(priv->device,
3421                                                         rx_q->rx_skbuff_dma
3422                                                         [entry], frame_len,
3423                                                         DMA_FROM_DEVICE);
3424                                 skb_copy_to_linear_data(skb,
3425                                                         rx_q->
3426                                                         rx_skbuff[entry]->data,
3427                                                         frame_len);
3428
3429                                 skb_put(skb, frame_len);
3430                                 dma_sync_single_for_device(priv->device,
3431                                                            rx_q->rx_skbuff_dma
3432                                                            [entry], frame_len,
3433                                                            DMA_FROM_DEVICE);
3434                         } else {
3435                                 skb = rx_q->rx_skbuff[entry];
3436                                 if (unlikely(!skb)) {
3437                                         if (net_ratelimit())
3438                                                 netdev_err(priv->dev,
3439                                                            "%s: Inconsistent Rx chain\n",
3440                                                            priv->dev->name);
3441                                         priv->dev->stats.rx_dropped++;
3442                                         continue;
3443                                 }
3444                                 prefetch(skb->data - NET_IP_ALIGN);
3445                                 rx_q->rx_skbuff[entry] = NULL;
3446                                 rx_q->rx_zeroc_thresh++;
3447
3448                                 skb_put(skb, frame_len);
3449                                 dma_unmap_single(priv->device,
3450                                                  rx_q->rx_skbuff_dma[entry],
3451                                                  priv->dma_buf_sz,
3452                                                  DMA_FROM_DEVICE);
3453                         }
3454
3455                         if (netif_msg_pktdata(priv)) {
3456                                 netdev_dbg(priv->dev, "frame received (%dbytes)",
3457                                            frame_len);
3458                                 print_pkt(skb->data, frame_len);
3459                         }
3460
3461                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
3462
3463                         stmmac_rx_vlan(priv->dev, skb);
3464
3465                         skb->protocol = eth_type_trans(skb, priv->dev);
3466
3467                         if (unlikely(!coe))
3468                                 skb_checksum_none_assert(skb);
3469                         else
3470                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3471
3472                         napi_gro_receive(&ch->rx_napi, skb);
3473
3474                         priv->dev->stats.rx_packets++;
3475                         priv->dev->stats.rx_bytes += frame_len;
3476                 }
3477         }
3478
3479         stmmac_rx_refill(priv, queue);
3480
3481         priv->xstats.rx_pkt_n += count;
3482
3483         return count;
3484 }
3485
3486 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3487 {
3488         struct stmmac_channel *ch =
3489                 container_of(napi, struct stmmac_channel, rx_napi);
3490         struct stmmac_priv *priv = ch->priv_data;
3491         u32 chan = ch->index;
3492         int work_done;
3493
3494         priv->xstats.napi_poll++;
3495
3496         work_done = stmmac_rx(priv, budget, chan);
3497         if (work_done < budget && napi_complete_done(napi, work_done))
3498                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3499         return work_done;
3500 }
3501
3502 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3503 {
3504         struct stmmac_channel *ch =
3505                 container_of(napi, struct stmmac_channel, tx_napi);
3506         struct stmmac_priv *priv = ch->priv_data;
3507         struct stmmac_tx_queue *tx_q;
3508         u32 chan = ch->index;
3509         int work_done;
3510
3511         priv->xstats.napi_poll++;
3512
3513         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3514         work_done = min(work_done, budget);
3515
3516         if (work_done < budget && napi_complete_done(napi, work_done))
3517                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3518
3519         /* Force transmission restart */
3520         tx_q = &priv->tx_queue[chan];
3521         if (tx_q->cur_tx != tx_q->dirty_tx) {
3522                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3523                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3524                                        chan);
3525         }
3526
3527         return work_done;
3528 }
3529
3530 /**
3531  *  stmmac_tx_timeout
3532  *  @dev : Pointer to net device structure
3533  *  Description: this function is called when a packet transmission fails to
3534  *   complete within a reasonable time. The driver will mark the error in the
3535  *   netdev structure and arrange for the device to be reset to a sane state
3536  *   in order to transmit a new packet.
3537  */
3538 static void stmmac_tx_timeout(struct net_device *dev)
3539 {
3540         struct stmmac_priv *priv = netdev_priv(dev);
3541
3542         stmmac_global_err(priv);
3543 }
3544
3545 /**
3546  *  stmmac_set_rx_mode - entry point for multicast addressing
3547  *  @dev : pointer to the device structure
3548  *  Description:
3549  *  This function is a driver entry point which gets called by the kernel
3550  *  whenever multicast addresses must be enabled/disabled.
3551  *  Return value:
3552  *  void.
3553  */
3554 static void stmmac_set_rx_mode(struct net_device *dev)
3555 {
3556         struct stmmac_priv *priv = netdev_priv(dev);
3557
3558         stmmac_set_filter(priv, priv->hw, dev);
3559 }
3560
3561 /**
3562  *  stmmac_change_mtu - entry point to change MTU size for the device.
3563  *  @dev : device pointer.
3564  *  @new_mtu : the new MTU size for the device.
3565  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3566  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3567  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3568  *  Return value:
3569  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3570  *  file on failure.
3571  */
3572 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3573 {
3574         struct stmmac_priv *priv = netdev_priv(dev);
3575
3576         if (netif_running(dev)) {
3577                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3578                 return -EBUSY;
3579         }
3580
3581         dev->mtu = new_mtu;
3582
3583         netdev_update_features(dev);
3584
3585         return 0;
3586 }
3587
3588 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3589                                              netdev_features_t features)
3590 {
3591         struct stmmac_priv *priv = netdev_priv(dev);
3592
3593         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3594                 features &= ~NETIF_F_RXCSUM;
3595
3596         if (!priv->plat->tx_coe)
3597                 features &= ~NETIF_F_CSUM_MASK;
3598
3599         /* Some GMAC devices have a bugged Jumbo frame support that
3600          * needs to have the Tx COE disabled for oversized frames
3601          * (due to limited buffer sizes). In this case we disable
3602          * the TX csum insertion in the TDES and not use SF.
3603          */
3604         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3605                 features &= ~NETIF_F_CSUM_MASK;
3606
3607         /* Disable tso if asked by ethtool */
3608         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3609                 if (features & NETIF_F_TSO)
3610                         priv->tso = true;
3611                 else
3612                         priv->tso = false;
3613         }
3614
3615         return features;
3616 }
3617
3618 static int stmmac_set_features(struct net_device *netdev,
3619                                netdev_features_t features)
3620 {
3621         struct stmmac_priv *priv = netdev_priv(netdev);
3622
3623         /* Keep the COE Type in case of csum is supporting */
3624         if (features & NETIF_F_RXCSUM)
3625                 priv->hw->rx_csum = priv->plat->rx_coe;
3626         else
3627                 priv->hw->rx_csum = 0;
3628         /* No check needed because rx_coe has been set before and it will be
3629          * fixed in case of issue.
3630          */
3631         stmmac_rx_ipc(priv, priv->hw);
3632
3633         return 0;
3634 }
3635
3636 /**
3637  *  stmmac_interrupt - main ISR
3638  *  @irq: interrupt number.
3639  *  @dev_id: to pass the net device pointer.
3640  *  Description: this is the main driver interrupt service routine.
3641  *  It can call:
3642  *  o DMA service routine (to manage incoming frame reception and transmission
3643  *    status)
3644  *  o Core interrupts to manage: remote wake-up, management counter, LPI
3645  *    interrupts.
3646  */
3647 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3648 {
3649         struct net_device *dev = (struct net_device *)dev_id;
3650         struct stmmac_priv *priv = netdev_priv(dev);
3651         u32 rx_cnt = priv->plat->rx_queues_to_use;
3652         u32 tx_cnt = priv->plat->tx_queues_to_use;
3653         u32 queues_count;
3654         u32 queue;
3655         bool xmac;
3656
3657         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3658         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3659
3660         if (priv->irq_wake)
3661                 pm_wakeup_event(priv->device, 0);
3662
3663         if (unlikely(!dev)) {
3664                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3665                 return IRQ_NONE;
3666         }
3667
3668         /* Check if adapter is up */
3669         if (test_bit(STMMAC_DOWN, &priv->state))
3670                 return IRQ_HANDLED;
3671         /* Check if a fatal error happened */
3672         if (stmmac_safety_feat_interrupt(priv))
3673                 return IRQ_HANDLED;
3674
3675         /* To handle GMAC own interrupts */
3676         if ((priv->plat->has_gmac) || xmac) {
3677                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3678                 int mtl_status;
3679
3680                 if (unlikely(status)) {
3681                         /* For LPI we need to save the tx status */
3682                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3683                                 priv->tx_path_in_lpi_mode = true;
3684                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3685                                 priv->tx_path_in_lpi_mode = false;
3686                 }
3687
3688                 for (queue = 0; queue < queues_count; queue++) {
3689                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3690
3691                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3692                                                                 queue);
3693                         if (mtl_status != -EINVAL)
3694                                 status |= mtl_status;
3695
3696                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3697                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3698                                                        rx_q->rx_tail_addr,
3699                                                        queue);
3700                 }
3701
3702                 /* PCS link status */
3703                 if (priv->hw->pcs) {
3704                         if (priv->xstats.pcs_link)
3705                                 netif_carrier_on(dev);
3706                         else
3707                                 netif_carrier_off(dev);
3708                 }
3709         }
3710
3711         /* To handle DMA interrupts */
3712         stmmac_dma_interrupt(priv);
3713
3714         return IRQ_HANDLED;
3715 }
3716
3717 #ifdef CONFIG_NET_POLL_CONTROLLER
3718 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3719  * to allow network I/O with interrupts disabled.
3720  */
3721 static void stmmac_poll_controller(struct net_device *dev)
3722 {
3723         disable_irq(dev->irq);
3724         stmmac_interrupt(dev->irq, dev);
3725         enable_irq(dev->irq);
3726 }
3727 #endif
3728
3729 /**
3730  *  stmmac_ioctl - Entry point for the Ioctl
3731  *  @dev: Device pointer.
3732  *  @rq: An IOCTL specefic structure, that can contain a pointer to
3733  *  a proprietary structure used to pass information to the driver.
3734  *  @cmd: IOCTL command
3735  *  Description:
3736  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3737  */
3738 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3739 {
3740         struct stmmac_priv *priv = netdev_priv (dev);
3741         int ret = -EOPNOTSUPP;
3742
3743         if (!netif_running(dev))
3744                 return -EINVAL;
3745
3746         switch (cmd) {
3747         case SIOCGMIIPHY:
3748         case SIOCGMIIREG:
3749         case SIOCSMIIREG:
3750                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3751                 break;
3752         case SIOCSHWTSTAMP:
3753                 ret = stmmac_hwtstamp_set(dev, rq);
3754                 break;
3755         case SIOCGHWTSTAMP:
3756                 ret = stmmac_hwtstamp_get(dev, rq);
3757                 break;
3758         default:
3759                 break;
3760         }
3761
3762         return ret;
3763 }
3764
3765 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3766                                     void *cb_priv)
3767 {
3768         struct stmmac_priv *priv = cb_priv;
3769         int ret = -EOPNOTSUPP;
3770
3771         stmmac_disable_all_queues(priv);
3772
3773         switch (type) {
3774         case TC_SETUP_CLSU32:
3775                 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3776                         ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3777                 break;
3778         default:
3779                 break;
3780         }
3781
3782         stmmac_enable_all_queues(priv);
3783         return ret;
3784 }
3785
3786 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3787                                  struct tc_block_offload *f)
3788 {
3789         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3790                 return -EOPNOTSUPP;
3791
3792         switch (f->command) {
3793         case TC_BLOCK_BIND:
3794                 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3795                                 priv, priv, f->extack);
3796         case TC_BLOCK_UNBIND:
3797                 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3798                 return 0;
3799         default:
3800                 return -EOPNOTSUPP;
3801         }
3802 }
3803
3804 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3805                            void *type_data)
3806 {
3807         struct stmmac_priv *priv = netdev_priv(ndev);
3808
3809         switch (type) {
3810         case TC_SETUP_BLOCK:
3811                 return stmmac_setup_tc_block(priv, type_data);
3812         case TC_SETUP_QDISC_CBS:
3813                 return stmmac_tc_setup_cbs(priv, priv, type_data);
3814         default:
3815                 return -EOPNOTSUPP;
3816         }
3817 }
3818
3819 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3820 {
3821         struct stmmac_priv *priv = netdev_priv(ndev);
3822         int ret = 0;
3823
3824         ret = eth_mac_addr(ndev, addr);
3825         if (ret)
3826                 return ret;
3827
3828         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3829
3830         return ret;
3831 }
3832
3833 #ifdef CONFIG_DEBUG_FS
3834 static struct dentry *stmmac_fs_dir;
3835
3836 static void sysfs_display_ring(void *head, int size, int extend_desc,
3837                                struct seq_file *seq)
3838 {
3839         int i;
3840         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3841         struct dma_desc *p = (struct dma_desc *)head;
3842
3843         for (i = 0; i < size; i++) {
3844                 if (extend_desc) {
3845                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3846                                    i, (unsigned int)virt_to_phys(ep),
3847                                    le32_to_cpu(ep->basic.des0),
3848                                    le32_to_cpu(ep->basic.des1),
3849                                    le32_to_cpu(ep->basic.des2),
3850                                    le32_to_cpu(ep->basic.des3));
3851                         ep++;
3852                 } else {
3853                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3854                                    i, (unsigned int)virt_to_phys(p),
3855                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3856                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3857                         p++;
3858                 }
3859                 seq_printf(seq, "\n");
3860         }
3861 }
3862
3863 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3864 {
3865         struct net_device *dev = seq->private;
3866         struct stmmac_priv *priv = netdev_priv(dev);
3867         u32 rx_count = priv->plat->rx_queues_to_use;
3868         u32 tx_count = priv->plat->tx_queues_to_use;
3869         u32 queue;
3870
3871         if ((dev->flags & IFF_UP) == 0)
3872                 return 0;
3873
3874         for (queue = 0; queue < rx_count; queue++) {
3875                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3876
3877                 seq_printf(seq, "RX Queue %d:\n", queue);
3878
3879                 if (priv->extend_desc) {
3880                         seq_printf(seq, "Extended descriptor ring:\n");
3881                         sysfs_display_ring((void *)rx_q->dma_erx,
3882                                            DMA_RX_SIZE, 1, seq);
3883                 } else {
3884                         seq_printf(seq, "Descriptor ring:\n");
3885                         sysfs_display_ring((void *)rx_q->dma_rx,
3886                                            DMA_RX_SIZE, 0, seq);
3887                 }
3888         }
3889
3890         for (queue = 0; queue < tx_count; queue++) {
3891                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3892
3893                 seq_printf(seq, "TX Queue %d:\n", queue);
3894
3895                 if (priv->extend_desc) {
3896                         seq_printf(seq, "Extended descriptor ring:\n");
3897                         sysfs_display_ring((void *)tx_q->dma_etx,
3898                                            DMA_TX_SIZE, 1, seq);
3899                 } else {
3900                         seq_printf(seq, "Descriptor ring:\n");
3901                         sysfs_display_ring((void *)tx_q->dma_tx,
3902                                            DMA_TX_SIZE, 0, seq);
3903                 }
3904         }
3905
3906         return 0;
3907 }
3908 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3909
3910 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3911 {
3912         struct net_device *dev = seq->private;
3913         struct stmmac_priv *priv = netdev_priv(dev);
3914
3915         if (!priv->hw_cap_support) {
3916                 seq_printf(seq, "DMA HW features not supported\n");
3917                 return 0;
3918         }
3919
3920         seq_printf(seq, "==============================\n");
3921         seq_printf(seq, "\tDMA HW features\n");
3922         seq_printf(seq, "==============================\n");
3923
3924         seq_printf(seq, "\t10/100 Mbps: %s\n",
3925                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3926         seq_printf(seq, "\t1000 Mbps: %s\n",
3927                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
3928         seq_printf(seq, "\tHalf duplex: %s\n",
3929                    (priv->dma_cap.half_duplex) ? "Y" : "N");
3930         seq_printf(seq, "\tHash Filter: %s\n",
3931                    (priv->dma_cap.hash_filter) ? "Y" : "N");
3932         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3933                    (priv->dma_cap.multi_addr) ? "Y" : "N");
3934         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3935                    (priv->dma_cap.pcs) ? "Y" : "N");
3936         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3937                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
3938         seq_printf(seq, "\tPMT Remote wake up: %s\n",
3939                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3940         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3941                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3942         seq_printf(seq, "\tRMON module: %s\n",
3943                    (priv->dma_cap.rmon) ? "Y" : "N");
3944         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3945                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3946         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3947                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3948         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3949                    (priv->dma_cap.eee) ? "Y" : "N");
3950         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3951         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3952                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3953         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3954                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3955                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3956         } else {
3957                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3958                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3959                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3960                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3961         }
3962         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3963                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3964         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3965                    priv->dma_cap.number_rx_channel);
3966         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3967                    priv->dma_cap.number_tx_channel);
3968         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3969                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3970
3971         return 0;
3972 }
3973 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
3974
3975 static int stmmac_init_fs(struct net_device *dev)
3976 {
3977         struct stmmac_priv *priv = netdev_priv(dev);
3978
3979         /* Create per netdev entries */
3980         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3981
3982         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3983                 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3984
3985                 return -ENOMEM;
3986         }
3987
3988         /* Entry to report DMA RX/TX rings */
3989         priv->dbgfs_rings_status =
3990                 debugfs_create_file("descriptors_status", 0444,
3991                                     priv->dbgfs_dir, dev,
3992                                     &stmmac_rings_status_fops);
3993
3994         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3995                 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3996                 debugfs_remove_recursive(priv->dbgfs_dir);
3997
3998                 return -ENOMEM;
3999         }
4000
4001         /* Entry to report the DMA HW features */
4002         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4003                                                   priv->dbgfs_dir,
4004                                                   dev, &stmmac_dma_cap_fops);
4005
4006         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4007                 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4008                 debugfs_remove_recursive(priv->dbgfs_dir);
4009
4010                 return -ENOMEM;
4011         }
4012
4013         return 0;
4014 }
4015
4016 static void stmmac_exit_fs(struct net_device *dev)
4017 {
4018         struct stmmac_priv *priv = netdev_priv(dev);
4019
4020         debugfs_remove_recursive(priv->dbgfs_dir);
4021 }
4022 #endif /* CONFIG_DEBUG_FS */
4023
4024 static const struct net_device_ops stmmac_netdev_ops = {
4025         .ndo_open = stmmac_open,
4026         .ndo_start_xmit = stmmac_xmit,
4027         .ndo_stop = stmmac_release,
4028         .ndo_change_mtu = stmmac_change_mtu,
4029         .ndo_fix_features = stmmac_fix_features,
4030         .ndo_set_features = stmmac_set_features,
4031         .ndo_set_rx_mode = stmmac_set_rx_mode,
4032         .ndo_tx_timeout = stmmac_tx_timeout,
4033         .ndo_do_ioctl = stmmac_ioctl,
4034         .ndo_setup_tc = stmmac_setup_tc,
4035 #ifdef CONFIG_NET_POLL_CONTROLLER
4036         .ndo_poll_controller = stmmac_poll_controller,
4037 #endif
4038         .ndo_set_mac_address = stmmac_set_mac_address,
4039 };
4040
4041 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4042 {
4043         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4044                 return;
4045         if (test_bit(STMMAC_DOWN, &priv->state))
4046                 return;
4047
4048         netdev_err(priv->dev, "Reset adapter.\n");
4049
4050         rtnl_lock();
4051         netif_trans_update(priv->dev);
4052         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4053                 usleep_range(1000, 2000);
4054
4055         set_bit(STMMAC_DOWN, &priv->state);
4056         dev_close(priv->dev);
4057         dev_open(priv->dev, NULL);
4058         clear_bit(STMMAC_DOWN, &priv->state);
4059         clear_bit(STMMAC_RESETING, &priv->state);
4060         rtnl_unlock();
4061 }
4062
4063 static void stmmac_service_task(struct work_struct *work)
4064 {
4065         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4066                         service_task);
4067
4068         stmmac_reset_subtask(priv);
4069         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4070 }
4071
4072 /**
4073  *  stmmac_hw_init - Init the MAC device
4074  *  @priv: driver private structure
4075  *  Description: this function is to configure the MAC device according to
4076  *  some platform parameters or the HW capability register. It prepares the
4077  *  driver to use either ring or chain modes and to setup either enhanced or
4078  *  normal descriptors.
4079  */
4080 static int stmmac_hw_init(struct stmmac_priv *priv)
4081 {
4082         int ret;
4083
4084         /* dwmac-sun8i only work in chain mode */
4085         if (priv->plat->has_sun8i)
4086                 chain_mode = 1;
4087         priv->chain_mode = chain_mode;
4088
4089         /* Initialize HW Interface */
4090         ret = stmmac_hwif_init(priv);
4091         if (ret)
4092                 return ret;
4093
4094         /* Get the HW capability (new GMAC newer than 3.50a) */
4095         priv->hw_cap_support = stmmac_get_hw_features(priv);
4096         if (priv->hw_cap_support) {
4097                 dev_info(priv->device, "DMA HW capability register supported\n");
4098
4099                 /* We can override some gmac/dma configuration fields: e.g.
4100                  * enh_desc, tx_coe (e.g. that are passed through the
4101                  * platform) with the values from the HW capability
4102                  * register (if supported).
4103                  */
4104                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4105                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4106                 priv->hw->pmt = priv->plat->pmt;
4107
4108                 /* TXCOE doesn't work in thresh DMA mode */
4109                 if (priv->plat->force_thresh_dma_mode)
4110                         priv->plat->tx_coe = 0;
4111                 else
4112                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4113
4114                 /* In case of GMAC4 rx_coe is from HW cap register. */
4115                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4116
4117                 if (priv->dma_cap.rx_coe_type2)
4118                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4119                 else if (priv->dma_cap.rx_coe_type1)
4120                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4121
4122         } else {
4123                 dev_info(priv->device, "No HW DMA feature register supported\n");
4124         }
4125
4126         if (priv->plat->rx_coe) {
4127                 priv->hw->rx_csum = priv->plat->rx_coe;
4128                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4129                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4130                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4131         }
4132         if (priv->plat->tx_coe)
4133                 dev_info(priv->device, "TX Checksum insertion supported\n");
4134
4135         if (priv->plat->pmt) {
4136                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4137                 device_set_wakeup_capable(priv->device, 1);
4138         }
4139
4140         if (priv->dma_cap.tsoen)
4141                 dev_info(priv->device, "TSO supported\n");
4142
4143         /* Run HW quirks, if any */
4144         if (priv->hwif_quirks) {
4145                 ret = priv->hwif_quirks(priv);
4146                 if (ret)
4147                         return ret;
4148         }
4149
4150         /* Rx Watchdog is available in the COREs newer than the 3.40.
4151          * In some case, for example on bugged HW this feature
4152          * has to be disable and this can be done by passing the
4153          * riwt_off field from the platform.
4154          */
4155         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4156             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4157                 priv->use_riwt = 1;
4158                 dev_info(priv->device,
4159                          "Enable RX Mitigation via HW Watchdog Timer\n");
4160         }
4161
4162         return 0;
4163 }
4164
4165 /**
4166  * stmmac_dvr_probe
4167  * @device: device pointer
4168  * @plat_dat: platform data pointer
4169  * @res: stmmac resource pointer
4170  * Description: this is the main probe function used to
4171  * call the alloc_etherdev, allocate the priv structure.
4172  * Return:
4173  * returns 0 on success, otherwise errno.
4174  */
4175 int stmmac_dvr_probe(struct device *device,
4176                      struct plat_stmmacenet_data *plat_dat,
4177                      struct stmmac_resources *res)
4178 {
4179         struct net_device *ndev = NULL;
4180         struct stmmac_priv *priv;
4181         u32 queue, maxq;
4182         int ret = 0;
4183
4184         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4185                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4186         if (!ndev)
4187                 return -ENOMEM;
4188
4189         SET_NETDEV_DEV(ndev, device);
4190
4191         priv = netdev_priv(ndev);
4192         priv->device = device;
4193         priv->dev = ndev;
4194
4195         stmmac_set_ethtool_ops(ndev);
4196         priv->pause = pause;
4197         priv->plat = plat_dat;
4198         priv->ioaddr = res->addr;
4199         priv->dev->base_addr = (unsigned long)res->addr;
4200
4201         priv->dev->irq = res->irq;
4202         priv->wol_irq = res->wol_irq;
4203         priv->lpi_irq = res->lpi_irq;
4204
4205         if (!IS_ERR_OR_NULL(res->mac))
4206                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4207
4208         dev_set_drvdata(device, priv->dev);
4209
4210         /* Verify driver arguments */
4211         stmmac_verify_args();
4212
4213         /* Allocate workqueue */
4214         priv->wq = create_singlethread_workqueue("stmmac_wq");
4215         if (!priv->wq) {
4216                 dev_err(priv->device, "failed to create workqueue\n");
4217                 return -ENOMEM;
4218         }
4219
4220         INIT_WORK(&priv->service_task, stmmac_service_task);
4221
4222         /* Override with kernel parameters if supplied XXX CRS XXX
4223          * this needs to have multiple instances
4224          */
4225         if ((phyaddr >= 0) && (phyaddr <= 31))
4226                 priv->plat->phy_addr = phyaddr;
4227
4228         if (priv->plat->stmmac_rst) {
4229                 ret = reset_control_assert(priv->plat->stmmac_rst);
4230                 reset_control_deassert(priv->plat->stmmac_rst);
4231                 /* Some reset controllers have only reset callback instead of
4232                  * assert + deassert callbacks pair.
4233                  */
4234                 if (ret == -ENOTSUPP)
4235                         reset_control_reset(priv->plat->stmmac_rst);
4236         }
4237
4238         /* Init MAC and get the capabilities */
4239         ret = stmmac_hw_init(priv);
4240         if (ret)
4241                 goto error_hw_init;
4242
4243         stmmac_check_ether_addr(priv);
4244
4245         /* Configure real RX and TX queues */
4246         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4247         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4248
4249         ndev->netdev_ops = &stmmac_netdev_ops;
4250
4251         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4252                             NETIF_F_RXCSUM;
4253
4254         ret = stmmac_tc_init(priv, priv);
4255         if (!ret) {
4256                 ndev->hw_features |= NETIF_F_HW_TC;
4257         }
4258
4259         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4260                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4261                 priv->tso = true;
4262                 dev_info(priv->device, "TSO feature enabled\n");
4263         }
4264         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4265         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4266 #ifdef STMMAC_VLAN_TAG_USED
4267         /* Both mac100 and gmac support receive VLAN tag detection */
4268         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4269 #endif
4270         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4271
4272         /* MTU range: 46 - hw-specific max */
4273         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4274         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4275                 ndev->max_mtu = JUMBO_LEN;
4276         else if (priv->plat->has_xgmac)
4277                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4278         else
4279                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4280         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4281          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4282          */
4283         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4284             (priv->plat->maxmtu >= ndev->min_mtu))
4285                 ndev->max_mtu = priv->plat->maxmtu;
4286         else if (priv->plat->maxmtu < ndev->min_mtu)
4287                 dev_warn(priv->device,
4288                          "%s: warning: maxmtu having invalid value (%d)\n",
4289                          __func__, priv->plat->maxmtu);
4290
4291         if (flow_ctrl)
4292                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4293
4294         /* Setup channels NAPI */
4295         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4296
4297         for (queue = 0; queue < maxq; queue++) {
4298                 struct stmmac_channel *ch = &priv->channel[queue];
4299
4300                 ch->priv_data = priv;
4301                 ch->index = queue;
4302
4303                 if (queue < priv->plat->rx_queues_to_use) {
4304                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4305                                        NAPI_POLL_WEIGHT);
4306                 }
4307                 if (queue < priv->plat->tx_queues_to_use) {
4308                         netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4309                                        NAPI_POLL_WEIGHT);
4310                 }
4311         }
4312
4313         mutex_init(&priv->lock);
4314
4315         /* If a specific clk_csr value is passed from the platform
4316          * this means that the CSR Clock Range selection cannot be
4317          * changed at run-time and it is fixed. Viceversa the driver'll try to
4318          * set the MDC clock dynamically according to the csr actual
4319          * clock input.
4320          */
4321         if (priv->plat->clk_csr >= 0)
4322                 priv->clk_csr = priv->plat->clk_csr;
4323         else
4324                 stmmac_clk_csr_set(priv);
4325
4326         stmmac_check_pcs_mode(priv);
4327
4328         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
4329             priv->hw->pcs != STMMAC_PCS_TBI &&
4330             priv->hw->pcs != STMMAC_PCS_RTBI) {
4331                 /* MDIO bus Registration */
4332                 ret = stmmac_mdio_register(ndev);
4333                 if (ret < 0) {
4334                         dev_err(priv->device,
4335                                 "%s: MDIO bus (id: %d) registration failed",
4336                                 __func__, priv->plat->bus_id);
4337                         goto error_mdio_register;
4338                 }
4339         }
4340
4341         ret = stmmac_phy_setup(priv);
4342         if (ret) {
4343                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4344                 goto error_phy_setup;
4345         }
4346
4347         ret = register_netdev(ndev);
4348         if (ret) {
4349                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4350                         __func__, ret);
4351                 goto error_netdev_register;
4352         }
4353
4354 #ifdef CONFIG_DEBUG_FS
4355         ret = stmmac_init_fs(ndev);
4356         if (ret < 0)
4357                 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4358                             __func__);
4359 #endif
4360
4361         return ret;
4362
4363 error_netdev_register:
4364         phylink_destroy(priv->phylink);
4365 error_phy_setup:
4366         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4367             priv->hw->pcs != STMMAC_PCS_TBI &&
4368             priv->hw->pcs != STMMAC_PCS_RTBI)
4369                 stmmac_mdio_unregister(ndev);
4370 error_mdio_register:
4371         for (queue = 0; queue < maxq; queue++) {
4372                 struct stmmac_channel *ch = &priv->channel[queue];
4373
4374                 if (queue < priv->plat->rx_queues_to_use)
4375                         netif_napi_del(&ch->rx_napi);
4376                 if (queue < priv->plat->tx_queues_to_use)
4377                         netif_napi_del(&ch->tx_napi);
4378         }
4379 error_hw_init:
4380         destroy_workqueue(priv->wq);
4381
4382         return ret;
4383 }
4384 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4385
4386 /**
4387  * stmmac_dvr_remove
4388  * @dev: device pointer
4389  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4390  * changes the link status, releases the DMA descriptor rings.
4391  */
4392 int stmmac_dvr_remove(struct device *dev)
4393 {
4394         struct net_device *ndev = dev_get_drvdata(dev);
4395         struct stmmac_priv *priv = netdev_priv(ndev);
4396
4397         netdev_info(priv->dev, "%s: removing driver", __func__);
4398
4399 #ifdef CONFIG_DEBUG_FS
4400         stmmac_exit_fs(ndev);
4401 #endif
4402         stmmac_stop_all_dma(priv);
4403
4404         stmmac_mac_set(priv, priv->ioaddr, false);
4405         netif_carrier_off(ndev);
4406         unregister_netdev(ndev);
4407         phylink_destroy(priv->phylink);
4408         if (priv->plat->stmmac_rst)
4409                 reset_control_assert(priv->plat->stmmac_rst);
4410         clk_disable_unprepare(priv->plat->pclk);
4411         clk_disable_unprepare(priv->plat->stmmac_clk);
4412         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4413             priv->hw->pcs != STMMAC_PCS_TBI &&
4414             priv->hw->pcs != STMMAC_PCS_RTBI)
4415                 stmmac_mdio_unregister(ndev);
4416         destroy_workqueue(priv->wq);
4417         mutex_destroy(&priv->lock);
4418
4419         return 0;
4420 }
4421 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4422
4423 /**
4424  * stmmac_suspend - suspend callback
4425  * @dev: device pointer
4426  * Description: this is the function to suspend the device and it is called
4427  * by the platform driver to stop the network queue, release the resources,
4428  * program the PMT register (for WoL), clean and release driver resources.
4429  */
4430 int stmmac_suspend(struct device *dev)
4431 {
4432         struct net_device *ndev = dev_get_drvdata(dev);
4433         struct stmmac_priv *priv = netdev_priv(ndev);
4434
4435         if (!ndev || !netif_running(ndev))
4436                 return 0;
4437
4438         phylink_stop(priv->phylink);
4439
4440         mutex_lock(&priv->lock);
4441
4442         netif_device_detach(ndev);
4443         stmmac_stop_all_queues(priv);
4444
4445         stmmac_disable_all_queues(priv);
4446
4447         /* Stop TX/RX DMA */
4448         stmmac_stop_all_dma(priv);
4449
4450         /* Enable Power down mode by programming the PMT regs */
4451         if (device_may_wakeup(priv->device)) {
4452                 stmmac_pmt(priv, priv->hw, priv->wolopts);
4453                 priv->irq_wake = 1;
4454         } else {
4455                 stmmac_mac_set(priv, priv->ioaddr, false);
4456                 pinctrl_pm_select_sleep_state(priv->device);
4457                 /* Disable clock in case of PWM is off */
4458                 clk_disable(priv->plat->pclk);
4459                 clk_disable(priv->plat->stmmac_clk);
4460         }
4461         mutex_unlock(&priv->lock);
4462
4463         priv->speed = SPEED_UNKNOWN;
4464         return 0;
4465 }
4466 EXPORT_SYMBOL_GPL(stmmac_suspend);
4467
4468 /**
4469  * stmmac_reset_queues_param - reset queue parameters
4470  * @dev: device pointer
4471  */
4472 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4473 {
4474         u32 rx_cnt = priv->plat->rx_queues_to_use;
4475         u32 tx_cnt = priv->plat->tx_queues_to_use;
4476         u32 queue;
4477
4478         for (queue = 0; queue < rx_cnt; queue++) {
4479                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4480
4481                 rx_q->cur_rx = 0;
4482                 rx_q->dirty_rx = 0;
4483         }
4484
4485         for (queue = 0; queue < tx_cnt; queue++) {
4486                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4487
4488                 tx_q->cur_tx = 0;
4489                 tx_q->dirty_tx = 0;
4490                 tx_q->mss = 0;
4491         }
4492 }
4493
4494 /**
4495  * stmmac_resume - resume callback
4496  * @dev: device pointer
4497  * Description: when resume this function is invoked to setup the DMA and CORE
4498  * in a usable state.
4499  */
4500 int stmmac_resume(struct device *dev)
4501 {
4502         struct net_device *ndev = dev_get_drvdata(dev);
4503         struct stmmac_priv *priv = netdev_priv(ndev);
4504
4505         if (!netif_running(ndev))
4506                 return 0;
4507
4508         /* Power Down bit, into the PM register, is cleared
4509          * automatically as soon as a magic packet or a Wake-up frame
4510          * is received. Anyway, it's better to manually clear
4511          * this bit because it can generate problems while resuming
4512          * from another devices (e.g. serial console).
4513          */
4514         if (device_may_wakeup(priv->device)) {
4515                 mutex_lock(&priv->lock);
4516                 stmmac_pmt(priv, priv->hw, 0);
4517                 mutex_unlock(&priv->lock);
4518                 priv->irq_wake = 0;
4519         } else {
4520                 pinctrl_pm_select_default_state(priv->device);
4521                 /* enable the clk previously disabled */
4522                 clk_enable(priv->plat->stmmac_clk);
4523                 clk_enable(priv->plat->pclk);
4524                 /* reset the phy so that it's ready */
4525                 if (priv->mii)
4526                         stmmac_mdio_reset(priv->mii);
4527         }
4528
4529         netif_device_attach(ndev);
4530
4531         mutex_lock(&priv->lock);
4532
4533         stmmac_reset_queues_param(priv);
4534
4535         stmmac_clear_descriptors(priv);
4536
4537         stmmac_hw_setup(ndev, false);
4538         stmmac_init_tx_coalesce(priv);
4539         stmmac_set_rx_mode(ndev);
4540
4541         stmmac_enable_all_queues(priv);
4542
4543         stmmac_start_all_queues(priv);
4544
4545         mutex_unlock(&priv->lock);
4546
4547         phylink_start(priv->phylink);
4548
4549         return 0;
4550 }
4551 EXPORT_SYMBOL_GPL(stmmac_resume);
4552
4553 #ifndef MODULE
4554 static int __init stmmac_cmdline_opt(char *str)
4555 {
4556         char *opt;
4557
4558         if (!str || !*str)
4559                 return -EINVAL;
4560         while ((opt = strsep(&str, ",")) != NULL) {
4561                 if (!strncmp(opt, "debug:", 6)) {
4562                         if (kstrtoint(opt + 6, 0, &debug))
4563                                 goto err;
4564                 } else if (!strncmp(opt, "phyaddr:", 8)) {
4565                         if (kstrtoint(opt + 8, 0, &phyaddr))
4566                                 goto err;
4567                 } else if (!strncmp(opt, "buf_sz:", 7)) {
4568                         if (kstrtoint(opt + 7, 0, &buf_sz))
4569                                 goto err;
4570                 } else if (!strncmp(opt, "tc:", 3)) {
4571                         if (kstrtoint(opt + 3, 0, &tc))
4572                                 goto err;
4573                 } else if (!strncmp(opt, "watchdog:", 9)) {
4574                         if (kstrtoint(opt + 9, 0, &watchdog))
4575                                 goto err;
4576                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4577                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
4578                                 goto err;
4579                 } else if (!strncmp(opt, "pause:", 6)) {
4580                         if (kstrtoint(opt + 6, 0, &pause))
4581                                 goto err;
4582                 } else if (!strncmp(opt, "eee_timer:", 10)) {
4583                         if (kstrtoint(opt + 10, 0, &eee_timer))
4584                                 goto err;
4585                 } else if (!strncmp(opt, "chain_mode:", 11)) {
4586                         if (kstrtoint(opt + 11, 0, &chain_mode))
4587                                 goto err;
4588                 }
4589         }
4590         return 0;
4591
4592 err:
4593         pr_err("%s: ERROR broken module parameter conversion", __func__);
4594         return -EINVAL;
4595 }
4596
4597 __setup("stmmaceth=", stmmac_cmdline_opt);
4598 #endif /* MODULE */
4599
4600 static int __init stmmac_init(void)
4601 {
4602 #ifdef CONFIG_DEBUG_FS
4603         /* Create debugfs main directory if it doesn't exist yet */
4604         if (!stmmac_fs_dir) {
4605                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4606
4607                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4608                         pr_err("ERROR %s, debugfs create directory failed\n",
4609                                STMMAC_RESOURCE_NAME);
4610
4611                         return -ENOMEM;
4612                 }
4613         }
4614 #endif
4615
4616         return 0;
4617 }
4618
4619 static void __exit stmmac_exit(void)
4620 {
4621 #ifdef CONFIG_DEBUG_FS
4622         debugfs_remove_recursive(stmmac_fs_dir);
4623 #endif
4624 }
4625
4626 module_init(stmmac_init)
4627 module_exit(stmmac_exit)
4628
4629 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4630 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4631 MODULE_LICENSE("GPL");