drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/prefetch.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #ifdef CONFIG_DEBUG_FS
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #endif /* CONFIG_DEBUG_FS */
  38 #include <linux/net_tstamp.h>
  39 #include <linux/phylink.h>
  40 #include <linux/udp.h>
  41 #include <linux/bpf_trace.h>
  42 #include <net/pkt_cls.h>
  43 #include <net/xdp_sock_drv.h>
  44 #include "stmmac_ptp.h"
  45 #include "stmmac.h"
  46 #include "stmmac_xdp.h"
  47 #include <linux/reset.h>
  48 #include <linux/of_mdio.h>
  49 #include "dwmac1000.h"
  50 #include "dwxgmac2.h"
  51 #include "hwif.h"
  52
  53 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  54 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  55
  56 /* Module parameters */
  57 #define TX_TIMEO        5000
  58 static int watchdog = TX_TIMEO;
  59 module_param(watchdog, int, 0644);
  60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  61
  62 static int debug = -1;
  63 module_param(debug, int, 0644);
  64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  65
  66 static int phyaddr = -1;
  67 module_param(phyaddr, int, 0444);
  68 MODULE_PARM_DESC(phyaddr, "Physical device address");
  69
  70 #define STMMAC_TX_THRESH(x)     ((x)->dma_tx_size / 4)
  71 #define STMMAC_RX_THRESH(x)     ((x)->dma_rx_size / 4)
  72
  73 /* Limit to make sure XDP TX and slow path can coexist */
  74 #define STMMAC_XSK_TX_BUDGET_MAX        256
  75 #define STMMAC_TX_XSK_AVAIL             16
  76 #define STMMAC_RX_FILL_BATCH            16
  77
  78 #define STMMAC_XDP_PASS         0
  79 #define STMMAC_XDP_CONSUMED     BIT(0)
  80 #define STMMAC_XDP_TX           BIT(1)
  81 #define STMMAC_XDP_REDIRECT     BIT(2)
  82
  83 static int flow_ctrl = FLOW_AUTO;
  84 module_param(flow_ctrl, int, 0644);
  85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  86
  87 static int pause = PAUSE_TIME;
  88 module_param(pause, int, 0644);
  89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  90
  91 #define TC_DEFAULT 64
  92 static int tc = TC_DEFAULT;
  93 module_param(tc, int, 0644);
  94 MODULE_PARM_DESC(tc, "DMA threshold control value");
  95
  96 #define DEFAULT_BUFSIZE 1536
  97 static int buf_sz = DEFAULT_BUFSIZE;
  98 module_param(buf_sz, int, 0644);
  99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 100
 101 #define STMMAC_RX_COPYBREAK     256
 102
 103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 104                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 105                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 106
 107 #define STMMAC_DEFAULT_LPI_TIMER        1000
 108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 109 module_param(eee_timer, int, 0644);
 110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
 112
 113 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 114  * but allow user to force to use the chain instead of the ring
 115  */
 116 static unsigned int chain_mode;
 117 module_param(chain_mode, int, 0444);
 118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 119
 120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 121 /* For MSI interrupts handling */
 122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
 123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
 124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
 125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
 126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
 127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
 128
 129 #ifdef CONFIG_DEBUG_FS
 130 static const struct net_device_ops stmmac_netdev_ops;
 131 static void stmmac_init_fs(struct net_device *dev);
 132 static void stmmac_exit_fs(struct net_device *dev);
 133 #endif
 134
 135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
 136
 137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
 138 {
 139         int ret = 0;
 140
 141         if (enabled) {
 142                 ret = clk_prepare_enable(priv->plat->stmmac_clk);
 143                 if (ret)
 144                         return ret;
 145                 ret = clk_prepare_enable(priv->plat->pclk);
 146                 if (ret) {
 147                         clk_disable_unprepare(priv->plat->stmmac_clk);
 148                         return ret;
 149                 }
 150                 if (priv->plat->clks_config) {
 151                         ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 152                         if (ret) {
 153                                 clk_disable_unprepare(priv->plat->stmmac_clk);
 154                                 clk_disable_unprepare(priv->plat->pclk);
 155                                 return ret;
 156                         }
 157                 }
 158         } else {
 159                 clk_disable_unprepare(priv->plat->stmmac_clk);
 160                 clk_disable_unprepare(priv->plat->pclk);
 161                 if (priv->plat->clks_config)
 162                         priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 163         }
 164
 165         return ret;
 166 }
 167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
 168
 169 /**
 170  * stmmac_verify_args - verify the driver parameters.
 171  * Description: it checks the driver parameters and set a default in case of
 172  * errors.
 173  */
 174 static void stmmac_verify_args(void)
 175 {
 176         if (unlikely(watchdog < 0))
 177                 watchdog = TX_TIMEO;
 178         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 179                 buf_sz = DEFAULT_BUFSIZE;
 180         if (unlikely(flow_ctrl > 1))
 181                 flow_ctrl = FLOW_AUTO;
 182         else if (likely(flow_ctrl < 0))
 183                 flow_ctrl = FLOW_OFF;
 184         if (unlikely((pause < 0) || (pause > 0xffff)))
 185                 pause = PAUSE_TIME;
 186         if (eee_timer < 0)
 187                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 188 }
 189
 190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
 191 {
 192         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 193         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 194         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 195         u32 queue;
 196
 197         for (queue = 0; queue < maxq; queue++) {
 198                 struct stmmac_channel *ch = &priv->channel[queue];
 199
 200                 if (stmmac_xdp_is_enabled(priv) &&
 201                     test_bit(queue, priv->af_xdp_zc_qps)) {
 202                         napi_disable(&ch->rxtx_napi);
 203                         continue;
 204                 }
 205
 206                 if (queue < rx_queues_cnt)
 207                         napi_disable(&ch->rx_napi);
 208                 if (queue < tx_queues_cnt)
 209                         napi_disable(&ch->tx_napi);
 210         }
 211 }
 212
 213 /**
 214  * stmmac_disable_all_queues - Disable all queues
 215  * @priv: driver private structure
 216  */
 217 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 218 {
 219         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 220         struct stmmac_rx_queue *rx_q;
 221         u32 queue;
 222
 223         /* synchronize_rcu() needed for pending XDP buffers to drain */
 224         for (queue = 0; queue < rx_queues_cnt; queue++) {
 225                 rx_q = &priv->rx_queue[queue];
 226                 if (rx_q->xsk_pool) {
 227                         synchronize_rcu();
 228                         break;
 229                 }
 230         }
 231
 232         __stmmac_disable_all_queues(priv);
 233 }
 234
 235 /**
 236  * stmmac_enable_all_queues - Enable all queues
 237  * @priv: driver private structure
 238  */
 239 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 240 {
 241         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 242         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 243         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 244         u32 queue;
 245
 246         for (queue = 0; queue < maxq; queue++) {
 247                 struct stmmac_channel *ch = &priv->channel[queue];
 248
 249                 if (stmmac_xdp_is_enabled(priv) &&
 250                     test_bit(queue, priv->af_xdp_zc_qps)) {
 251                         napi_enable(&ch->rxtx_napi);
 252                         continue;
 253                 }
 254
 255                 if (queue < rx_queues_cnt)
 256                         napi_enable(&ch->rx_napi);
 257                 if (queue < tx_queues_cnt)
 258                         napi_enable(&ch->tx_napi);
 259         }
 260 }
 261
 262 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 263 {
 264         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 265             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 266                 queue_work(priv->wq, &priv->service_task);
 267 }
 268
 269 static void stmmac_global_err(struct stmmac_priv *priv)
 270 {
 271         netif_carrier_off(priv->dev);
 272         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 273         stmmac_service_event_schedule(priv);
 274 }
 275
 276 /**
 277  * stmmac_clk_csr_set - dynamically set the MDC clock
 278  * @priv: driver private structure
 279  * Description: this is to dynamically set the MDC clock according to the csr
 280  * clock input.
 281  * Note:
 282  *      If a specific clk_csr value is passed from the platform
 283  *      this means that the CSR Clock Range selection cannot be
 284  *      changed at run-time and it is fixed (as reported in the driver
 285  *      documentation). Viceversa the driver will try to set the MDC
 286  *      clock dynamically according to the actual clock input.
 287  */
 288 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 289 {
 290         u32 clk_rate;
 291
 292         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 293
 294         /* Platform provided default clk_csr would be assumed valid
 295          * for all other cases except for the below mentioned ones.
 296          * For values higher than the IEEE 802.3 specified frequency
 297          * we can not estimate the proper divider as it is not known
 298          * the frequency of clk_csr_i. So we do not change the default
 299          * divider.
 300          */
 301         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 302                 if (clk_rate < CSR_F_35M)
 303                         priv->clk_csr = STMMAC_CSR_20_35M;
 304                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 305                         priv->clk_csr = STMMAC_CSR_35_60M;
 306                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 307                         priv->clk_csr = STMMAC_CSR_60_100M;
 308                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 309                         priv->clk_csr = STMMAC_CSR_100_150M;
 310                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 311                         priv->clk_csr = STMMAC_CSR_150_250M;
 312                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 313                         priv->clk_csr = STMMAC_CSR_250_300M;
 314         }
 315
 316         if (priv->plat->has_sun8i) {
 317                 if (clk_rate > 160000000)
 318                         priv->clk_csr = 0x03;
 319                 else if (clk_rate > 80000000)
 320                         priv->clk_csr = 0x02;
 321                 else if (clk_rate > 40000000)
 322                         priv->clk_csr = 0x01;
 323                 else
 324                         priv->clk_csr = 0;
 325         }
 326
 327         if (priv->plat->has_xgmac) {
 328                 if (clk_rate > 400000000)
 329                         priv->clk_csr = 0x5;
 330                 else if (clk_rate > 350000000)
 331                         priv->clk_csr = 0x4;
 332                 else if (clk_rate > 300000000)
 333                         priv->clk_csr = 0x3;
 334                 else if (clk_rate > 250000000)
 335                         priv->clk_csr = 0x2;
 336                 else if (clk_rate > 150000000)
 337                         priv->clk_csr = 0x1;
 338                 else
 339                         priv->clk_csr = 0x0;
 340         }
 341 }
 342
 343 static void print_pkt(unsigned char *buf, int len)
 344 {
 345         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 346         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 347 }
 348
 349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 350 {
 351         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 352         u32 avail;
 353
 354         if (tx_q->dirty_tx > tx_q->cur_tx)
 355                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 356         else
 357                 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
 358
 359         return avail;
 360 }
 361
 362 /**
 363  * stmmac_rx_dirty - Get RX queue dirty
 364  * @priv: driver private structure
 365  * @queue: RX queue index
 366  */
 367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 368 {
 369         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 370         u32 dirty;
 371
 372         if (rx_q->dirty_rx <= rx_q->cur_rx)
 373                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 374         else
 375                 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
 376
 377         return dirty;
 378 }
 379
 380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
 381 {
 382         int tx_lpi_timer;
 383
 384         /* Clear/set the SW EEE timer flag based on LPI ET enablement */
 385         priv->eee_sw_timer_en = en ? 0 : 1;
 386         tx_lpi_timer  = en ? priv->tx_lpi_timer : 0;
 387         stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
 388 }
 389
 390 /**
 391  * stmmac_enable_eee_mode - check and enter in LPI mode
 392  * @priv: driver private structure
 393  * Description: this function is to verify and enter in LPI mode in case of
 394  * EEE.
 395  */
 396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 397 {
 398         u32 tx_cnt = priv->plat->tx_queues_to_use;
 399         u32 queue;
 400
 401         /* check if all TX queues have the work finished */
 402         for (queue = 0; queue < tx_cnt; queue++) {
 403                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 404
 405                 if (tx_q->dirty_tx != tx_q->cur_tx)
 406                         return; /* still unfinished work */
 407         }
 408
 409         /* Check and enter in LPI mode */
 410         if (!priv->tx_path_in_lpi_mode)
 411                 stmmac_set_eee_mode(priv, priv->hw,
 412                                 priv->plat->en_tx_lpi_clockgating);
 413 }
 414
 415 /**
 416  * stmmac_disable_eee_mode - disable and exit from LPI mode
 417  * @priv: driver private structure
 418  * Description: this function is to exit and disable EEE in case of
 419  * LPI state is true. This is called by the xmit.
 420  */
 421 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 422 {
 423         if (!priv->eee_sw_timer_en) {
 424                 stmmac_lpi_entry_timer_config(priv, 0);
 425                 return;
 426         }
 427
 428         stmmac_reset_eee_mode(priv, priv->hw);
 429         del_timer_sync(&priv->eee_ctrl_timer);
 430         priv->tx_path_in_lpi_mode = false;
 431 }
 432
 433 /**
 434  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 435  * @t:  timer_list struct containing private info
 436  * Description:
 437  *  if there is no data transfer and if we are not in LPI state,
 438  *  then MAC Transmitter can be moved to LPI state.
 439  */
 440 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 441 {
 442         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 443
 444         stmmac_enable_eee_mode(priv);
 445         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
 446 }
 447
 448 /**
 449  * stmmac_eee_init - init EEE
 450  * @priv: driver private structure
 451  * Description:
 452  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 453  *  can also manage EEE, this function enable the LPI state and start related
 454  *  timer.
 455  */
 456 bool stmmac_eee_init(struct stmmac_priv *priv)
 457 {
 458         int eee_tw_timer = priv->eee_tw_timer;
 459
 460         /* Using PCS we cannot dial with the phy registers at this stage
 461          * so we do not support extra feature like EEE.
 462          */
 463         if (priv->hw->pcs == STMMAC_PCS_TBI ||
 464             priv->hw->pcs == STMMAC_PCS_RTBI)
 465                 return false;
 466
 467         /* Check if MAC core supports the EEE feature. */
 468         if (!priv->dma_cap.eee)
 469                 return false;
 470
 471         mutex_lock(&priv->lock);
 472
 473         /* Check if it needs to be deactivated */
 474         if (!priv->eee_active) {
 475                 if (priv->eee_enabled) {
 476                         netdev_dbg(priv->dev, "disable EEE\n");
 477                         stmmac_lpi_entry_timer_config(priv, 0);
 478                         del_timer_sync(&priv->eee_ctrl_timer);
 479                         stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
 480                 }
 481                 mutex_unlock(&priv->lock);
 482                 return false;
 483         }
 484
 485         if (priv->eee_active && !priv->eee_enabled) {
 486                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 487                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 488                                      eee_tw_timer);
 489                 if (priv->hw->xpcs)
 490                         xpcs_config_eee(priv->hw->xpcs,
 491                                         priv->plat->mult_fact_100ns,
 492                                         true);
 493         }
 494
 495         if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
 496                 del_timer_sync(&priv->eee_ctrl_timer);
 497                 priv->tx_path_in_lpi_mode = false;
 498                 stmmac_lpi_entry_timer_config(priv, 1);
 499         } else {
 500                 stmmac_lpi_entry_timer_config(priv, 0);
 501                 mod_timer(&priv->eee_ctrl_timer,
 502                           STMMAC_LPI_T(priv->tx_lpi_timer));
 503         }
 504
 505         mutex_unlock(&priv->lock);
 506         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 507         return true;
 508 }
 509
 510 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 511  * @priv: driver private structure
 512  * @p : descriptor pointer
 513  * @skb : the socket buffer
 514  * Description :
 515  * This function will read timestamp from the descriptor & pass it to stack.
 516  * and also perform some sanity checks.
 517  */
 518 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 519                                    struct dma_desc *p, struct sk_buff *skb)
 520 {
 521         struct skb_shared_hwtstamps shhwtstamp;
 522         bool found = false;
 523         s64 adjust = 0;
 524         u64 ns = 0;
 525
 526         if (!priv->hwts_tx_en)
 527                 return;
 528
 529         /* exit if skb doesn't support hw tstamp */
 530         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 531                 return;
 532
 533         /* check tx tstamp status */
 534         if (stmmac_get_tx_timestamp_status(priv, p)) {
 535                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 536                 found = true;
 537         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 538                 found = true;
 539         }
 540
 541         if (found) {
 542                 /* Correct the clk domain crossing(CDC) error */
 543                 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
 544                         adjust += -(2 * (NSEC_PER_SEC /
 545                                          priv->plat->clk_ptp_rate));
 546                         ns += adjust;
 547                 }
 548
 549                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 550                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 551
 552                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 553                 /* pass tstamp to stack */
 554                 skb_tstamp_tx(skb, &shhwtstamp);
 555         }
 556 }
 557
 558 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 559  * @priv: driver private structure
 560  * @p : descriptor pointer
 561  * @np : next descriptor pointer
 562  * @skb : the socket buffer
 563  * Description :
 564  * This function will read received packet's timestamp from the descriptor
 565  * and pass it to stack. It also perform some sanity checks.
 566  */
 567 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 568                                    struct dma_desc *np, struct sk_buff *skb)
 569 {
 570         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 571         struct dma_desc *desc = p;
 572         u64 adjust = 0;
 573         u64 ns = 0;
 574
 575         if (!priv->hwts_rx_en)
 576                 return;
 577         /* For GMAC4, the valid timestamp is from CTX next desc. */
 578         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 579                 desc = np;
 580
 581         /* Check if timestamp is available */
 582         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 583                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 584
 585                 /* Correct the clk domain crossing(CDC) error */
 586                 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
 587                         adjust += 2 * (NSEC_PER_SEC / priv->plat->clk_ptp_rate);
 588                         ns -= adjust;
 589                 }
 590
 591                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 592                 shhwtstamp = skb_hwtstamps(skb);
 593                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 594                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 595         } else  {
 596                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 597         }
 598 }
 599
 600 /**
 601  *  stmmac_hwtstamp_set - control hardware timestamping.
 602  *  @dev: device pointer.
 603  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 604  *  a proprietary structure used to pass information to the driver.
 605  *  Description:
 606  *  This function configures the MAC to enable/disable both outgoing(TX)
 607  *  and incoming(RX) packets time stamping based on user input.
 608  *  Return Value:
 609  *  0 on success and an appropriate -ve integer on failure.
 610  */
 611 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 612 {
 613         struct stmmac_priv *priv = netdev_priv(dev);
 614         struct hwtstamp_config config;
 615         struct timespec64 now;
 616         u64 temp = 0;
 617         u32 ptp_v2 = 0;
 618         u32 tstamp_all = 0;
 619         u32 ptp_over_ipv4_udp = 0;
 620         u32 ptp_over_ipv6_udp = 0;
 621         u32 ptp_over_ethernet = 0;
 622         u32 snap_type_sel = 0;
 623         u32 ts_master_en = 0;
 624         u32 ts_event_en = 0;
 625         u32 sec_inc = 0;
 626         u32 value = 0;
 627         bool xmac;
 628
 629         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 630
 631         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 632                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 633                 priv->hwts_tx_en = 0;
 634                 priv->hwts_rx_en = 0;
 635
 636                 return -EOPNOTSUPP;
 637         }
 638
 639         if (copy_from_user(&config, ifr->ifr_data,
 640                            sizeof(config)))
 641                 return -EFAULT;
 642
 643         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 644                    __func__, config.flags, config.tx_type, config.rx_filter);
 645
 646         /* reserved for future extensions */
 647         if (config.flags)
 648                 return -EINVAL;
 649
 650         if (config.tx_type != HWTSTAMP_TX_OFF &&
 651             config.tx_type != HWTSTAMP_TX_ON)
 652                 return -ERANGE;
 653
 654         if (priv->adv_ts) {
 655                 switch (config.rx_filter) {
 656                 case HWTSTAMP_FILTER_NONE:
 657                         /* time stamp no incoming packet at all */
 658                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 659                         break;
 660
 661                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 662                         /* PTP v1, UDP, any kind of event packet */
 663                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 664                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 665                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 666                          * This leaves Delay_Req timestamps out.
 667                          * Enable all events *and* general purpose message
 668                          * timestamping
 669                          */
 670                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 671                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 672                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 673                         break;
 674
 675                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 676                         /* PTP v1, UDP, Sync packet */
 677                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 678                         /* take time stamp for SYNC messages only */
 679                         ts_event_en = PTP_TCR_TSEVNTENA;
 680
 681                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 682                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 683                         break;
 684
 685                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 686                         /* PTP v1, UDP, Delay_req packet */
 687                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 688                         /* take time stamp for Delay_Req messages only */
 689                         ts_master_en = PTP_TCR_TSMSTRENA;
 690                         ts_event_en = PTP_TCR_TSEVNTENA;
 691
 692                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 693                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 694                         break;
 695
 696                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 697                         /* PTP v2, UDP, any kind of event packet */
 698                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 699                         ptp_v2 = PTP_TCR_TSVER2ENA;
 700                         /* take time stamp for all event messages */
 701                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 702
 703                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 704                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 705                         break;
 706
 707                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 708                         /* PTP v2, UDP, Sync packet */
 709                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 710                         ptp_v2 = PTP_TCR_TSVER2ENA;
 711                         /* take time stamp for SYNC messages only */
 712                         ts_event_en = PTP_TCR_TSEVNTENA;
 713
 714                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 715                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 716                         break;
 717
 718                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 719                         /* PTP v2, UDP, Delay_req packet */
 720                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 721                         ptp_v2 = PTP_TCR_TSVER2ENA;
 722                         /* take time stamp for Delay_Req messages only */
 723                         ts_master_en = PTP_TCR_TSMSTRENA;
 724                         ts_event_en = PTP_TCR_TSEVNTENA;
 725
 726                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 727                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 728                         break;
 729
 730                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 731                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 732                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 733                         ptp_v2 = PTP_TCR_TSVER2ENA;
 734                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 735                         if (priv->synopsys_id != DWMAC_CORE_5_10)
 736                                 ts_event_en = PTP_TCR_TSEVNTENA;
 737                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 738                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 739                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 740                         break;
 741
 742                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 743                         /* PTP v2/802.AS1, any layer, Sync packet */
 744                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 745                         ptp_v2 = PTP_TCR_TSVER2ENA;
 746                         /* take time stamp for SYNC messages only */
 747                         ts_event_en = PTP_TCR_TSEVNTENA;
 748
 749                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 750                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 751                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 752                         break;
 753
 754                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 755                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 756                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 757                         ptp_v2 = PTP_TCR_TSVER2ENA;
 758                         /* take time stamp for Delay_Req messages only */
 759                         ts_master_en = PTP_TCR_TSMSTRENA;
 760                         ts_event_en = PTP_TCR_TSEVNTENA;
 761
 762                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 763                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 764                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 765                         break;
 766
 767                 case HWTSTAMP_FILTER_NTP_ALL:
 768                 case HWTSTAMP_FILTER_ALL:
 769                         /* time stamp any incoming packet */
 770                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 771                         tstamp_all = PTP_TCR_TSENALL;
 772                         break;
 773
 774                 default:
 775                         return -ERANGE;
 776                 }
 777         } else {
 778                 switch (config.rx_filter) {
 779                 case HWTSTAMP_FILTER_NONE:
 780                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 781                         break;
 782                 default:
 783                         /* PTP v1, UDP, any kind of event packet */
 784                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 785                         break;
 786                 }
 787         }
 788         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 789         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 790
 791         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 792                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 793         else {
 794                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 795                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 796                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 797                          ts_master_en | snap_type_sel);
 798                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 799
 800                 /* program Sub Second Increment reg */
 801                 stmmac_config_sub_second_increment(priv,
 802                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 803                                 xmac, &sec_inc);
 804                 temp = div_u64(1000000000ULL, sec_inc);
 805
 806                 /* Store sub second increment and flags for later use */
 807                 priv->sub_second_inc = sec_inc;
 808                 priv->systime_flags = value;
 809
 810                 /* calculate default added value:
 811                  * formula is :
 812                  * addend = (2^32)/freq_div_ratio;
 813                  * where, freq_div_ratio = 1e9ns/sec_inc
 814                  */
 815                 temp = (u64)(temp << 32);
 816                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 817                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 818
 819                 /* initialize system time */
 820                 ktime_get_real_ts64(&now);
 821
 822                 /* lower 32 bits of tv_sec are safe until y2106 */
 823                 stmmac_init_systime(priv, priv->ptpaddr,
 824                                 (u32)now.tv_sec, now.tv_nsec);
 825         }
 826
 827         memcpy(&priv->tstamp_config, &config, sizeof(config));
 828
 829         return copy_to_user(ifr->ifr_data, &config,
 830                             sizeof(config)) ? -EFAULT : 0;
 831 }
 832
 833 /**
 834  *  stmmac_hwtstamp_get - read hardware timestamping.
 835  *  @dev: device pointer.
 836  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 837  *  a proprietary structure used to pass information to the driver.
 838  *  Description:
 839  *  This function obtain the current hardware timestamping settings
 840  *  as requested.
 841  */
 842 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 843 {
 844         struct stmmac_priv *priv = netdev_priv(dev);
 845         struct hwtstamp_config *config = &priv->tstamp_config;
 846
 847         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 848                 return -EOPNOTSUPP;
 849
 850         return copy_to_user(ifr->ifr_data, config,
 851                             sizeof(*config)) ? -EFAULT : 0;
 852 }
 853
 854 /**
 855  * stmmac_init_ptp - init PTP
 856  * @priv: driver private structure
 857  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 858  * This is done by looking at the HW cap. register.
 859  * This function also registers the ptp driver.
 860  */
 861 static int stmmac_init_ptp(struct stmmac_priv *priv)
 862 {
 863         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 864
 865         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 866                 return -EOPNOTSUPP;
 867
 868         priv->adv_ts = 0;
 869         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 870         if (xmac && priv->dma_cap.atime_stamp)
 871                 priv->adv_ts = 1;
 872         /* Dwmac 3.x core with extend_desc can support adv_ts */
 873         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 874                 priv->adv_ts = 1;
 875
 876         if (priv->dma_cap.time_stamp)
 877                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 878
 879         if (priv->adv_ts)
 880                 netdev_info(priv->dev,
 881                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 882
 883         priv->hwts_tx_en = 0;
 884         priv->hwts_rx_en = 0;
 885
 886         stmmac_ptp_register(priv);
 887
 888         return 0;
 889 }
 890
 891 static void stmmac_release_ptp(struct stmmac_priv *priv)
 892 {
 893         clk_disable_unprepare(priv->plat->clk_ptp_ref);
 894         stmmac_ptp_unregister(priv);
 895 }
 896
 897 /**
 898  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 899  *  @priv: driver private structure
 900  *  @duplex: duplex passed to the next function
 901  *  Description: It is used for configuring the flow control in all queues
 902  */
 903 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 904 {
 905         u32 tx_cnt = priv->plat->tx_queues_to_use;
 906
 907         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 908                         priv->pause, tx_cnt);
 909 }
 910
 911 static void stmmac_validate(struct phylink_config *config,
 912                             unsigned long *supported,
 913                             struct phylink_link_state *state)
 914 {
 915         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 916         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 917         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 918         int tx_cnt = priv->plat->tx_queues_to_use;
 919         int max_speed = priv->plat->max_speed;
 920
 921         phylink_set(mac_supported, 10baseT_Half);
 922         phylink_set(mac_supported, 10baseT_Full);
 923         phylink_set(mac_supported, 100baseT_Half);
 924         phylink_set(mac_supported, 100baseT_Full);
 925         phylink_set(mac_supported, 1000baseT_Half);
 926         phylink_set(mac_supported, 1000baseT_Full);
 927         phylink_set(mac_supported, 1000baseKX_Full);
 928
 929         phylink_set(mac_supported, Autoneg);
 930         phylink_set(mac_supported, Pause);
 931         phylink_set(mac_supported, Asym_Pause);
 932         phylink_set_port_modes(mac_supported);
 933
 934         /* Cut down 1G if asked to */
 935         if ((max_speed > 0) && (max_speed < 1000)) {
 936                 phylink_set(mask, 1000baseT_Full);
 937                 phylink_set(mask, 1000baseX_Full);
 938         } else if (priv->plat->has_gmac4) {
 939                 if (!max_speed || max_speed >= 2500) {
 940                         phylink_set(mac_supported, 2500baseT_Full);
 941                         phylink_set(mac_supported, 2500baseX_Full);
 942                 }
 943         } else if (priv->plat->has_xgmac) {
 944                 if (!max_speed || (max_speed >= 2500)) {
 945                         phylink_set(mac_supported, 2500baseT_Full);
 946                         phylink_set(mac_supported, 2500baseX_Full);
 947                 }
 948                 if (!max_speed || (max_speed >= 5000)) {
 949                         phylink_set(mac_supported, 5000baseT_Full);
 950                 }
 951                 if (!max_speed || (max_speed >= 10000)) {
 952                         phylink_set(mac_supported, 10000baseSR_Full);
 953                         phylink_set(mac_supported, 10000baseLR_Full);
 954                         phylink_set(mac_supported, 10000baseER_Full);
 955                         phylink_set(mac_supported, 10000baseLRM_Full);
 956                         phylink_set(mac_supported, 10000baseT_Full);
 957                         phylink_set(mac_supported, 10000baseKX4_Full);
 958                         phylink_set(mac_supported, 10000baseKR_Full);
 959                 }
 960                 if (!max_speed || (max_speed >= 25000)) {
 961                         phylink_set(mac_supported, 25000baseCR_Full);
 962                         phylink_set(mac_supported, 25000baseKR_Full);
 963                         phylink_set(mac_supported, 25000baseSR_Full);
 964                 }
 965                 if (!max_speed || (max_speed >= 40000)) {
 966                         phylink_set(mac_supported, 40000baseKR4_Full);
 967                         phylink_set(mac_supported, 40000baseCR4_Full);
 968                         phylink_set(mac_supported, 40000baseSR4_Full);
 969                         phylink_set(mac_supported, 40000baseLR4_Full);
 970                 }
 971                 if (!max_speed || (max_speed >= 50000)) {
 972                         phylink_set(mac_supported, 50000baseCR2_Full);
 973                         phylink_set(mac_supported, 50000baseKR2_Full);
 974                         phylink_set(mac_supported, 50000baseSR2_Full);
 975                         phylink_set(mac_supported, 50000baseKR_Full);
 976                         phylink_set(mac_supported, 50000baseSR_Full);
 977                         phylink_set(mac_supported, 50000baseCR_Full);
 978                         phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
 979                         phylink_set(mac_supported, 50000baseDR_Full);
 980                 }
 981                 if (!max_speed || (max_speed >= 100000)) {
 982                         phylink_set(mac_supported, 100000baseKR4_Full);
 983                         phylink_set(mac_supported, 100000baseSR4_Full);
 984                         phylink_set(mac_supported, 100000baseCR4_Full);
 985                         phylink_set(mac_supported, 100000baseLR4_ER4_Full);
 986                         phylink_set(mac_supported, 100000baseKR2_Full);
 987                         phylink_set(mac_supported, 100000baseSR2_Full);
 988                         phylink_set(mac_supported, 100000baseCR2_Full);
 989                         phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
 990                         phylink_set(mac_supported, 100000baseDR2_Full);
 991                 }
 992         }
 993
 994         /* Half-Duplex can only work with single queue */
 995         if (tx_cnt > 1) {
 996                 phylink_set(mask, 10baseT_Half);
 997                 phylink_set(mask, 100baseT_Half);
 998                 phylink_set(mask, 1000baseT_Half);
 999         }
1000
1001         linkmode_and(supported, supported, mac_supported);
1002         linkmode_andnot(supported, supported, mask);
1003
1004         linkmode_and(state->advertising, state->advertising, mac_supported);
1005         linkmode_andnot(state->advertising, state->advertising, mask);
1006
1007         /* If PCS is supported, check which modes it supports. */
1008         if (priv->hw->xpcs)
1009                 xpcs_validate(priv->hw->xpcs, supported, state);
1010 }
1011
1012 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
1013                               const struct phylink_link_state *state)
1014 {
1015         /* Nothing to do, xpcs_config() handles everything */
1016 }
1017
1018 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
1019 {
1020         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
1021         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
1022         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
1023         bool *hs_enable = &fpe_cfg->hs_enable;
1024
1025         if (is_up && *hs_enable) {
1026                 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
1027         } else {
1028                 *lo_state = FPE_STATE_OFF;
1029                 *lp_state = FPE_STATE_OFF;
1030         }
1031 }
1032
1033 static void stmmac_mac_link_down(struct phylink_config *config,
1034                                  unsigned int mode, phy_interface_t interface)
1035 {
1036         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1037
1038         stmmac_mac_set(priv, priv->ioaddr, false);
1039         priv->eee_active = false;
1040         priv->tx_lpi_enabled = false;
1041         stmmac_eee_init(priv);
1042         stmmac_set_eee_pls(priv, priv->hw, false);
1043
1044         if (priv->dma_cap.fpesel)
1045                 stmmac_fpe_link_state_handle(priv, false);
1046 }
1047
1048 static void stmmac_mac_link_up(struct phylink_config *config,
1049                                struct phy_device *phy,
1050                                unsigned int mode, phy_interface_t interface,
1051                                int speed, int duplex,
1052                                bool tx_pause, bool rx_pause)
1053 {
1054         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1055         u32 ctrl;
1056
1057         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
1058         ctrl &= ~priv->hw->link.speed_mask;
1059
1060         if (interface == PHY_INTERFACE_MODE_USXGMII) {
1061                 switch (speed) {
1062                 case SPEED_10000:
1063                         ctrl |= priv->hw->link.xgmii.speed10000;
1064                         break;
1065                 case SPEED_5000:
1066                         ctrl |= priv->hw->link.xgmii.speed5000;
1067                         break;
1068                 case SPEED_2500:
1069                         ctrl |= priv->hw->link.xgmii.speed2500;
1070                         break;
1071                 default:
1072                         return;
1073                 }
1074         } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1075                 switch (speed) {
1076                 case SPEED_100000:
1077                         ctrl |= priv->hw->link.xlgmii.speed100000;
1078                         break;
1079                 case SPEED_50000:
1080                         ctrl |= priv->hw->link.xlgmii.speed50000;
1081                         break;
1082                 case SPEED_40000:
1083                         ctrl |= priv->hw->link.xlgmii.speed40000;
1084                         break;
1085                 case SPEED_25000:
1086                         ctrl |= priv->hw->link.xlgmii.speed25000;
1087                         break;
1088                 case SPEED_10000:
1089                         ctrl |= priv->hw->link.xgmii.speed10000;
1090                         break;
1091                 case SPEED_2500:
1092                         ctrl |= priv->hw->link.speed2500;
1093                         break;
1094                 case SPEED_1000:
1095                         ctrl |= priv->hw->link.speed1000;
1096                         break;
1097                 default:
1098                         return;
1099                 }
1100         } else {
1101                 switch (speed) {
1102                 case SPEED_2500:
1103                         ctrl |= priv->hw->link.speed2500;
1104                         break;
1105                 case SPEED_1000:
1106                         ctrl |= priv->hw->link.speed1000;
1107                         break;
1108                 case SPEED_100:
1109                         ctrl |= priv->hw->link.speed100;
1110                         break;
1111                 case SPEED_10:
1112                         ctrl |= priv->hw->link.speed10;
1113                         break;
1114                 default:
1115                         return;
1116                 }
1117         }
1118
1119         priv->speed = speed;
1120
1121         if (priv->plat->fix_mac_speed)
1122                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1123
1124         if (!duplex)
1125                 ctrl &= ~priv->hw->link.duplex;
1126         else
1127                 ctrl |= priv->hw->link.duplex;
1128
1129         /* Flow Control operation */
1130         if (tx_pause && rx_pause)
1131                 stmmac_mac_flow_ctrl(priv, duplex);
1132
1133         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1134
1135         stmmac_mac_set(priv, priv->ioaddr, true);
1136         if (phy && priv->dma_cap.eee) {
1137                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1138                 priv->eee_enabled = stmmac_eee_init(priv);
1139                 priv->tx_lpi_enabled = priv->eee_enabled;
1140                 stmmac_set_eee_pls(priv, priv->hw, true);
1141         }
1142
1143         if (priv->dma_cap.fpesel)
1144                 stmmac_fpe_link_state_handle(priv, true);
1145 }
1146
1147 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1148         .validate = stmmac_validate,
1149         .mac_config = stmmac_mac_config,
1150         .mac_link_down = stmmac_mac_link_down,
1151         .mac_link_up = stmmac_mac_link_up,
1152 };
1153
1154 /**
1155  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1156  * @priv: driver private structure
1157  * Description: this is to verify if the HW supports the PCS.
1158  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1159  * configured for the TBI, RTBI, or SGMII PHY interface.
1160  */
1161 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1162 {
1163         int interface = priv->plat->interface;
1164
1165         if (priv->dma_cap.pcs) {
1166                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1167                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1168                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1169                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1170                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1171                         priv->hw->pcs = STMMAC_PCS_RGMII;
1172                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1173                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1174                         priv->hw->pcs = STMMAC_PCS_SGMII;
1175                 }
1176         }
1177 }
1178
1179 /**
1180  * stmmac_init_phy - PHY initialization
1181  * @dev: net device structure
1182  * Description: it initializes the driver's PHY state, and attaches the PHY
1183  * to the mac driver.
1184  *  Return value:
1185  *  0 on success
1186  */
1187 static int stmmac_init_phy(struct net_device *dev)
1188 {
1189         struct stmmac_priv *priv = netdev_priv(dev);
1190         struct device_node *node;
1191         int ret;
1192
1193         node = priv->plat->phylink_node;
1194
1195         if (node)
1196                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1197
1198         /* Some DT bindings do not set-up the PHY handle. Let's try to
1199          * manually parse it
1200          */
1201         if (!node || ret) {
1202                 int addr = priv->plat->phy_addr;
1203                 struct phy_device *phydev;
1204
1205                 phydev = mdiobus_get_phy(priv->mii, addr);
1206                 if (!phydev) {
1207                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1208                         return -ENODEV;
1209                 }
1210
1211                 ret = phylink_connect_phy(priv->phylink, phydev);
1212         }
1213
1214         if (!priv->plat->pmt) {
1215                 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1216
1217                 phylink_ethtool_get_wol(priv->phylink, &wol);
1218                 device_set_wakeup_capable(priv->device, !!wol.supported);
1219         }
1220
1221         return ret;
1222 }
1223
1224 static int stmmac_phy_setup(struct stmmac_priv *priv)
1225 {
1226         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1227         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1228         int mode = priv->plat->phy_interface;
1229         struct phylink *phylink;
1230
1231         priv->phylink_config.dev = &priv->dev->dev;
1232         priv->phylink_config.type = PHYLINK_NETDEV;
1233         priv->phylink_config.pcs_poll = true;
1234         if (priv->plat->mdio_bus_data)
1235                 priv->phylink_config.ovr_an_inband =
1236                         mdio_bus_data->xpcs_an_inband;
1237
1238         if (!fwnode)
1239                 fwnode = dev_fwnode(priv->device);
1240
1241         phylink = phylink_create(&priv->phylink_config, fwnode,
1242                                  mode, &stmmac_phylink_mac_ops);
1243         if (IS_ERR(phylink))
1244                 return PTR_ERR(phylink);
1245
1246         if (priv->hw->xpcs)
1247                 phylink_set_pcs(phylink, &priv->hw->xpcs->pcs);
1248
1249         priv->phylink = phylink;
1250         return 0;
1251 }
1252
1253 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1254 {
1255         u32 rx_cnt = priv->plat->rx_queues_to_use;
1256         unsigned int desc_size;
1257         void *head_rx;
1258         u32 queue;
1259
1260         /* Display RX rings */
1261         for (queue = 0; queue < rx_cnt; queue++) {
1262                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1263
1264                 pr_info("\tRX Queue %u rings\n", queue);
1265
1266                 if (priv->extend_desc) {
1267                         head_rx = (void *)rx_q->dma_erx;
1268                         desc_size = sizeof(struct dma_extended_desc);
1269                 } else {
1270                         head_rx = (void *)rx_q->dma_rx;
1271                         desc_size = sizeof(struct dma_desc);
1272                 }
1273
1274                 /* Display RX ring */
1275                 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
1276                                     rx_q->dma_rx_phy, desc_size);
1277         }
1278 }
1279
1280 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1281 {
1282         u32 tx_cnt = priv->plat->tx_queues_to_use;
1283         unsigned int desc_size;
1284         void *head_tx;
1285         u32 queue;
1286
1287         /* Display TX rings */
1288         for (queue = 0; queue < tx_cnt; queue++) {
1289                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1290
1291                 pr_info("\tTX Queue %d rings\n", queue);
1292
1293                 if (priv->extend_desc) {
1294                         head_tx = (void *)tx_q->dma_etx;
1295                         desc_size = sizeof(struct dma_extended_desc);
1296                 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1297                         head_tx = (void *)tx_q->dma_entx;
1298                         desc_size = sizeof(struct dma_edesc);
1299                 } else {
1300                         head_tx = (void *)tx_q->dma_tx;
1301                         desc_size = sizeof(struct dma_desc);
1302                 }
1303
1304                 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
1305                                     tx_q->dma_tx_phy, desc_size);
1306         }
1307 }
1308
1309 static void stmmac_display_rings(struct stmmac_priv *priv)
1310 {
1311         /* Display RX ring */
1312         stmmac_display_rx_rings(priv);
1313
1314         /* Display TX ring */
1315         stmmac_display_tx_rings(priv);
1316 }
1317
1318 static int stmmac_set_bfsize(int mtu, int bufsize)
1319 {
1320         int ret = bufsize;
1321
1322         if (mtu >= BUF_SIZE_8KiB)
1323                 ret = BUF_SIZE_16KiB;
1324         else if (mtu >= BUF_SIZE_4KiB)
1325                 ret = BUF_SIZE_8KiB;
1326         else if (mtu >= BUF_SIZE_2KiB)
1327                 ret = BUF_SIZE_4KiB;
1328         else if (mtu > DEFAULT_BUFSIZE)
1329                 ret = BUF_SIZE_2KiB;
1330         else
1331                 ret = DEFAULT_BUFSIZE;
1332
1333         return ret;
1334 }
1335
1336 /**
1337  * stmmac_clear_rx_descriptors - clear RX descriptors
1338  * @priv: driver private structure
1339  * @queue: RX queue index
1340  * Description: this function is called to clear the RX descriptors
1341  * in case of both basic and extended descriptors are used.
1342  */
1343 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1344 {
1345         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1346         int i;
1347
1348         /* Clear the RX descriptors */
1349         for (i = 0; i < priv->dma_rx_size; i++)
1350                 if (priv->extend_desc)
1351                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1352                                         priv->use_riwt, priv->mode,
1353                                         (i == priv->dma_rx_size - 1),
1354                                         priv->dma_buf_sz);
1355                 else
1356                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1357                                         priv->use_riwt, priv->mode,
1358                                         (i == priv->dma_rx_size - 1),
1359                                         priv->dma_buf_sz);
1360 }
1361
1362 /**
1363  * stmmac_clear_tx_descriptors - clear tx descriptors
1364  * @priv: driver private structure
1365  * @queue: TX queue index.
1366  * Description: this function is called to clear the TX descriptors
1367  * in case of both basic and extended descriptors are used.
1368  */
1369 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1370 {
1371         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1372         int i;
1373
1374         /* Clear the TX descriptors */
1375         for (i = 0; i < priv->dma_tx_size; i++) {
1376                 int last = (i == (priv->dma_tx_size - 1));
1377                 struct dma_desc *p;
1378
1379                 if (priv->extend_desc)
1380                         p = &tx_q->dma_etx[i].basic;
1381                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1382                         p = &tx_q->dma_entx[i].basic;
1383                 else
1384                         p = &tx_q->dma_tx[i];
1385
1386                 stmmac_init_tx_desc(priv, p, priv->mode, last);
1387         }
1388 }
1389
1390 /**
1391  * stmmac_clear_descriptors - clear descriptors
1392  * @priv: driver private structure
1393  * Description: this function is called to clear the TX and RX descriptors
1394  * in case of both basic and extended descriptors are used.
1395  */
1396 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1397 {
1398         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1399         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1400         u32 queue;
1401
1402         /* Clear the RX descriptors */
1403         for (queue = 0; queue < rx_queue_cnt; queue++)
1404                 stmmac_clear_rx_descriptors(priv, queue);
1405
1406         /* Clear the TX descriptors */
1407         for (queue = 0; queue < tx_queue_cnt; queue++)
1408                 stmmac_clear_tx_descriptors(priv, queue);
1409 }
1410
1411 /**
1412  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1413  * @priv: driver private structure
1414  * @p: descriptor pointer
1415  * @i: descriptor index
1416  * @flags: gfp flag
1417  * @queue: RX queue index
1418  * Description: this function is called to allocate a receive buffer, perform
1419  * the DMA mapping and init the descriptor.
1420  */
1421 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1422                                   int i, gfp_t flags, u32 queue)
1423 {
1424         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1425         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1426
1427         if (!buf->page) {
1428                 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1429                 if (!buf->page)
1430                         return -ENOMEM;
1431                 buf->page_offset = stmmac_rx_offset(priv);
1432         }
1433
1434         if (priv->sph && !buf->sec_page) {
1435                 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1436                 if (!buf->sec_page)
1437                         return -ENOMEM;
1438
1439                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1440                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1441         } else {
1442                 buf->sec_page = NULL;
1443                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1444         }
1445
1446         buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1447
1448         stmmac_set_desc_addr(priv, p, buf->addr);
1449         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1450                 stmmac_init_desc3(priv, p);
1451
1452         return 0;
1453 }
1454
1455 /**
1456  * stmmac_free_rx_buffer - free RX dma buffers
1457  * @priv: private structure
1458  * @queue: RX queue index
1459  * @i: buffer index.
1460  */
1461 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1462 {
1463         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1464         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1465
1466         if (buf->page)
1467                 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1468         buf->page = NULL;
1469
1470         if (buf->sec_page)
1471                 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1472         buf->sec_page = NULL;
1473 }
1474
1475 /**
1476  * stmmac_free_tx_buffer - free RX dma buffers
1477  * @priv: private structure
1478  * @queue: RX queue index
1479  * @i: buffer index.
1480  */
1481 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1482 {
1483         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1484
1485         if (tx_q->tx_skbuff_dma[i].buf &&
1486             tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1487                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1488                         dma_unmap_page(priv->device,
1489                                        tx_q->tx_skbuff_dma[i].buf,
1490                                        tx_q->tx_skbuff_dma[i].len,
1491                                        DMA_TO_DEVICE);
1492                 else
1493                         dma_unmap_single(priv->device,
1494                                          tx_q->tx_skbuff_dma[i].buf,
1495                                          tx_q->tx_skbuff_dma[i].len,
1496                                          DMA_TO_DEVICE);
1497         }
1498
1499         if (tx_q->xdpf[i] &&
1500             (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1501              tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1502                 xdp_return_frame(tx_q->xdpf[i]);
1503                 tx_q->xdpf[i] = NULL;
1504         }
1505
1506         if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1507                 tx_q->xsk_frames_done++;
1508
1509         if (tx_q->tx_skbuff[i] &&
1510             tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1511                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1512                 tx_q->tx_skbuff[i] = NULL;
1513         }
1514
1515         tx_q->tx_skbuff_dma[i].buf = 0;
1516         tx_q->tx_skbuff_dma[i].map_as_page = false;
1517 }
1518
1519 /**
1520  * dma_free_rx_skbufs - free RX dma buffers
1521  * @priv: private structure
1522  * @queue: RX queue index
1523  */
1524 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1525 {
1526         int i;
1527
1528         for (i = 0; i < priv->dma_rx_size; i++)
1529                 stmmac_free_rx_buffer(priv, queue, i);
1530 }
1531
1532 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
1533                                    gfp_t flags)
1534 {
1535         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1536         int i;
1537
1538         for (i = 0; i < priv->dma_rx_size; i++) {
1539                 struct dma_desc *p;
1540                 int ret;
1541
1542                 if (priv->extend_desc)
1543                         p = &((rx_q->dma_erx + i)->basic);
1544                 else
1545                         p = rx_q->dma_rx + i;
1546
1547                 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1548                                              queue);
1549                 if (ret)
1550                         return ret;
1551
1552                 rx_q->buf_alloc_num++;
1553         }
1554
1555         return 0;
1556 }
1557
1558 /**
1559  * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1560  * @priv: private structure
1561  * @queue: RX queue index
1562  */
1563 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
1564 {
1565         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1566         int i;
1567
1568         for (i = 0; i < priv->dma_rx_size; i++) {
1569                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1570
1571                 if (!buf->xdp)
1572                         continue;
1573
1574                 xsk_buff_free(buf->xdp);
1575                 buf->xdp = NULL;
1576         }
1577 }
1578
1579 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
1580 {
1581         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1582         int i;
1583
1584         for (i = 0; i < priv->dma_rx_size; i++) {
1585                 struct stmmac_rx_buffer *buf;
1586                 dma_addr_t dma_addr;
1587                 struct dma_desc *p;
1588
1589                 if (priv->extend_desc)
1590                         p = (struct dma_desc *)(rx_q->dma_erx + i);
1591                 else
1592                         p = rx_q->dma_rx + i;
1593
1594                 buf = &rx_q->buf_pool[i];
1595
1596                 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1597                 if (!buf->xdp)
1598                         return -ENOMEM;
1599
1600                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1601                 stmmac_set_desc_addr(priv, p, dma_addr);
1602                 rx_q->buf_alloc_num++;
1603         }
1604
1605         return 0;
1606 }
1607
1608 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1609 {
1610         if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1611                 return NULL;
1612
1613         return xsk_get_pool_from_qid(priv->dev, queue);
1614 }
1615
1616 /**
1617  * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1618  * @priv: driver private structure
1619  * @queue: RX queue index
1620  * @flags: gfp flag.
1621  * Description: this function initializes the DMA RX descriptors
1622  * and allocates the socket buffers. It supports the chained and ring
1623  * modes.
1624  */
1625 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
1626 {
1627         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1628         int ret;
1629
1630         netif_dbg(priv, probe, priv->dev,
1631                   "(%s) dma_rx_phy=0x%08x\n", __func__,
1632                   (u32)rx_q->dma_rx_phy);
1633
1634         stmmac_clear_rx_descriptors(priv, queue);
1635
1636         xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1637
1638         rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1639
1640         if (rx_q->xsk_pool) {
1641                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1642                                                    MEM_TYPE_XSK_BUFF_POOL,
1643                                                    NULL));
1644                 netdev_info(priv->dev,
1645                             "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1646                             rx_q->queue_index);
1647                 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1648         } else {
1649                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1650                                                    MEM_TYPE_PAGE_POOL,
1651                                                    rx_q->page_pool));
1652                 netdev_info(priv->dev,
1653                             "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1654                             rx_q->queue_index);
1655         }
1656
1657         if (rx_q->xsk_pool) {
1658                 /* RX XDP ZC buffer pool may not be populated, e.g.
1659                  * xdpsock TX-only.
1660                  */
1661                 stmmac_alloc_rx_buffers_zc(priv, queue);
1662         } else {
1663                 ret = stmmac_alloc_rx_buffers(priv, queue, flags);
1664                 if (ret < 0)
1665                         return -ENOMEM;
1666         }
1667
1668         rx_q->cur_rx = 0;
1669         rx_q->dirty_rx = 0;
1670
1671         /* Setup the chained descriptor addresses */
1672         if (priv->mode == STMMAC_CHAIN_MODE) {
1673                 if (priv->extend_desc)
1674                         stmmac_mode_init(priv, rx_q->dma_erx,
1675                                          rx_q->dma_rx_phy,
1676                                          priv->dma_rx_size, 1);
1677                 else
1678                         stmmac_mode_init(priv, rx_q->dma_rx,
1679                                          rx_q->dma_rx_phy,
1680                                          priv->dma_rx_size, 0);
1681         }
1682
1683         return 0;
1684 }
1685
1686 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1687 {
1688         struct stmmac_priv *priv = netdev_priv(dev);
1689         u32 rx_count = priv->plat->rx_queues_to_use;
1690         u32 queue;
1691         int ret;
1692
1693         /* RX INITIALIZATION */
1694         netif_dbg(priv, probe, priv->dev,
1695                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1696
1697         for (queue = 0; queue < rx_count; queue++) {
1698                 ret = __init_dma_rx_desc_rings(priv, queue, flags);
1699                 if (ret)
1700                         goto err_init_rx_buffers;
1701         }
1702
1703         return 0;
1704
1705 err_init_rx_buffers:
1706         while (queue >= 0) {
1707                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1708
1709                 if (rx_q->xsk_pool)
1710                         dma_free_rx_xskbufs(priv, queue);
1711                 else
1712                         dma_free_rx_skbufs(priv, queue);
1713
1714                 rx_q->buf_alloc_num = 0;
1715                 rx_q->xsk_pool = NULL;
1716
1717                 if (queue == 0)
1718                         break;
1719
1720                 queue--;
1721         }
1722
1723         return ret;
1724 }
1725
1726 /**
1727  * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1728  * @priv: driver private structure
1729  * @queue : TX queue index
1730  * Description: this function initializes the DMA TX descriptors
1731  * and allocates the socket buffers. It supports the chained and ring
1732  * modes.
1733  */
1734 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
1735 {
1736         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1737         int i;
1738
1739         netif_dbg(priv, probe, priv->dev,
1740                   "(%s) dma_tx_phy=0x%08x\n", __func__,
1741                   (u32)tx_q->dma_tx_phy);
1742
1743         /* Setup the chained descriptor addresses */
1744         if (priv->mode == STMMAC_CHAIN_MODE) {
1745                 if (priv->extend_desc)
1746                         stmmac_mode_init(priv, tx_q->dma_etx,
1747                                          tx_q->dma_tx_phy,
1748                                          priv->dma_tx_size, 1);
1749                 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1750                         stmmac_mode_init(priv, tx_q->dma_tx,
1751                                          tx_q->dma_tx_phy,
1752                                          priv->dma_tx_size, 0);
1753         }
1754
1755         tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1756
1757         for (i = 0; i < priv->dma_tx_size; i++) {
1758                 struct dma_desc *p;
1759
1760                 if (priv->extend_desc)
1761                         p = &((tx_q->dma_etx + i)->basic);
1762                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1763                         p = &((tx_q->dma_entx + i)->basic);
1764                 else
1765                         p = tx_q->dma_tx + i;
1766
1767                 stmmac_clear_desc(priv, p);
1768
1769                 tx_q->tx_skbuff_dma[i].buf = 0;
1770                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1771                 tx_q->tx_skbuff_dma[i].len = 0;
1772                 tx_q->tx_skbuff_dma[i].last_segment = false;
1773                 tx_q->tx_skbuff[i] = NULL;
1774         }
1775
1776         tx_q->dirty_tx = 0;
1777         tx_q->cur_tx = 0;
1778         tx_q->mss = 0;
1779
1780         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1781
1782         return 0;
1783 }
1784
1785 static int init_dma_tx_desc_rings(struct net_device *dev)
1786 {
1787         struct stmmac_priv *priv = netdev_priv(dev);
1788         u32 tx_queue_cnt;
1789         u32 queue;
1790
1791         tx_queue_cnt = priv->plat->tx_queues_to_use;
1792
1793         for (queue = 0; queue < tx_queue_cnt; queue++)
1794                 __init_dma_tx_desc_rings(priv, queue);
1795
1796         return 0;
1797 }
1798
1799 /**
1800  * init_dma_desc_rings - init the RX/TX descriptor rings
1801  * @dev: net device structure
1802  * @flags: gfp flag.
1803  * Description: this function initializes the DMA RX/TX descriptors
1804  * and allocates the socket buffers. It supports the chained and ring
1805  * modes.
1806  */
1807 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1808 {
1809         struct stmmac_priv *priv = netdev_priv(dev);
1810         int ret;
1811
1812         ret = init_dma_rx_desc_rings(dev, flags);
1813         if (ret)
1814                 return ret;
1815
1816         ret = init_dma_tx_desc_rings(dev);
1817
1818         stmmac_clear_descriptors(priv);
1819
1820         if (netif_msg_hw(priv))
1821                 stmmac_display_rings(priv);
1822
1823         return ret;
1824 }
1825
1826 /**
1827  * dma_free_tx_skbufs - free TX dma buffers
1828  * @priv: private structure
1829  * @queue: TX queue index
1830  */
1831 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1832 {
1833         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1834         int i;
1835
1836         tx_q->xsk_frames_done = 0;
1837
1838         for (i = 0; i < priv->dma_tx_size; i++)
1839                 stmmac_free_tx_buffer(priv, queue, i);
1840
1841         if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1842                 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1843                 tx_q->xsk_frames_done = 0;
1844                 tx_q->xsk_pool = NULL;
1845         }
1846 }
1847
1848 /**
1849  * stmmac_free_tx_skbufs - free TX skb buffers
1850  * @priv: private structure
1851  */
1852 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1853 {
1854         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1855         u32 queue;
1856
1857         for (queue = 0; queue < tx_queue_cnt; queue++)
1858                 dma_free_tx_skbufs(priv, queue);
1859 }
1860
1861 /**
1862  * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1863  * @priv: private structure
1864  * @queue: RX queue index
1865  */
1866 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1867 {
1868         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1869
1870         /* Release the DMA RX socket buffers */
1871         if (rx_q->xsk_pool)
1872                 dma_free_rx_xskbufs(priv, queue);
1873         else
1874                 dma_free_rx_skbufs(priv, queue);
1875
1876         rx_q->buf_alloc_num = 0;
1877         rx_q->xsk_pool = NULL;
1878
1879         /* Free DMA regions of consistent memory previously allocated */
1880         if (!priv->extend_desc)
1881                 dma_free_coherent(priv->device, priv->dma_rx_size *
1882                                   sizeof(struct dma_desc),
1883                                   rx_q->dma_rx, rx_q->dma_rx_phy);
1884         else
1885                 dma_free_coherent(priv->device, priv->dma_rx_size *
1886                                   sizeof(struct dma_extended_desc),
1887                                   rx_q->dma_erx, rx_q->dma_rx_phy);
1888
1889         if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1890                 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1891
1892         kfree(rx_q->buf_pool);
1893         if (rx_q->page_pool)
1894                 page_pool_destroy(rx_q->page_pool);
1895 }
1896
1897 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1898 {
1899         u32 rx_count = priv->plat->rx_queues_to_use;
1900         u32 queue;
1901
1902         /* Free RX queue resources */
1903         for (queue = 0; queue < rx_count; queue++)
1904                 __free_dma_rx_desc_resources(priv, queue);
1905 }
1906
1907 /**
1908  * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1909  * @priv: private structure
1910  * @queue: TX queue index
1911  */
1912 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
1913 {
1914         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1915         size_t size;
1916         void *addr;
1917
1918         /* Release the DMA TX socket buffers */
1919         dma_free_tx_skbufs(priv, queue);
1920
1921         if (priv->extend_desc) {
1922                 size = sizeof(struct dma_extended_desc);
1923                 addr = tx_q->dma_etx;
1924         } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1925                 size = sizeof(struct dma_edesc);
1926                 addr = tx_q->dma_entx;
1927         } else {
1928                 size = sizeof(struct dma_desc);
1929                 addr = tx_q->dma_tx;
1930         }
1931
1932         size *= priv->dma_tx_size;
1933
1934         dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1935
1936         kfree(tx_q->tx_skbuff_dma);
1937         kfree(tx_q->tx_skbuff);
1938 }
1939
1940 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1941 {
1942         u32 tx_count = priv->plat->tx_queues_to_use;
1943         u32 queue;
1944
1945         /* Free TX queue resources */
1946         for (queue = 0; queue < tx_count; queue++)
1947                 __free_dma_tx_desc_resources(priv, queue);
1948 }
1949
1950 /**
1951  * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
1952  * @priv: private structure
1953  * @queue: RX queue index
1954  * Description: according to which descriptor can be used (extend or basic)
1955  * this function allocates the resources for TX and RX paths. In case of
1956  * reception, for example, it pre-allocated the RX socket buffer in order to
1957  * allow zero-copy mechanism.
1958  */
1959 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1960 {
1961         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1962         struct stmmac_channel *ch = &priv->channel[queue];
1963         bool xdp_prog = stmmac_xdp_is_enabled(priv);
1964         struct page_pool_params pp_params = { 0 };
1965         unsigned int num_pages;
1966         unsigned int napi_id;
1967         int ret;
1968
1969         rx_q->queue_index = queue;
1970         rx_q->priv_data = priv;
1971
1972         pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
1973         pp_params.pool_size = priv->dma_rx_size;
1974         num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1975         pp_params.order = ilog2(num_pages);
1976         pp_params.nid = dev_to_node(priv->device);
1977         pp_params.dev = priv->device;
1978         pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
1979         pp_params.offset = stmmac_rx_offset(priv);
1980         pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
1981
1982         rx_q->page_pool = page_pool_create(&pp_params);
1983         if (IS_ERR(rx_q->page_pool)) {
1984                 ret = PTR_ERR(rx_q->page_pool);
1985                 rx_q->page_pool = NULL;
1986                 return ret;
1987         }
1988
1989         rx_q->buf_pool = kcalloc(priv->dma_rx_size,
1990                                  sizeof(*rx_q->buf_pool),
1991                                  GFP_KERNEL);
1992         if (!rx_q->buf_pool)
1993                 return -ENOMEM;
1994
1995         if (priv->extend_desc) {
1996                 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1997                                                    priv->dma_rx_size *
1998                                                    sizeof(struct dma_extended_desc),
1999                                                    &rx_q->dma_rx_phy,
2000                                                    GFP_KERNEL);
2001                 if (!rx_q->dma_erx)
2002                         return -ENOMEM;
2003
2004         } else {
2005                 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2006                                                   priv->dma_rx_size *
2007                                                   sizeof(struct dma_desc),
2008                                                   &rx_q->dma_rx_phy,
2009                                                   GFP_KERNEL);
2010                 if (!rx_q->dma_rx)
2011                         return -ENOMEM;
2012         }
2013
2014         if (stmmac_xdp_is_enabled(priv) &&
2015             test_bit(queue, priv->af_xdp_zc_qps))
2016                 napi_id = ch->rxtx_napi.napi_id;
2017         else
2018                 napi_id = ch->rx_napi.napi_id;
2019
2020         ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2021                                rx_q->queue_index,
2022                                napi_id);
2023         if (ret) {
2024                 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2025                 return -EINVAL;
2026         }
2027
2028         return 0;
2029 }
2030
2031 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
2032 {
2033         u32 rx_count = priv->plat->rx_queues_to_use;
2034         u32 queue;
2035         int ret;
2036
2037         /* RX queues buffers and DMA */
2038         for (queue = 0; queue < rx_count; queue++) {
2039                 ret = __alloc_dma_rx_desc_resources(priv, queue);
2040                 if (ret)
2041                         goto err_dma;
2042         }
2043
2044         return 0;
2045
2046 err_dma:
2047         free_dma_rx_desc_resources(priv);
2048
2049         return ret;
2050 }
2051
2052 /**
2053  * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2054  * @priv: private structure
2055  * @queue: TX queue index
2056  * Description: according to which descriptor can be used (extend or basic)
2057  * this function allocates the resources for TX and RX paths. In case of
2058  * reception, for example, it pre-allocated the RX socket buffer in order to
2059  * allow zero-copy mechanism.
2060  */
2061 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
2062 {
2063         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2064         size_t size;
2065         void *addr;
2066
2067         tx_q->queue_index = queue;
2068         tx_q->priv_data = priv;
2069
2070         tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
2071                                       sizeof(*tx_q->tx_skbuff_dma),
2072                                       GFP_KERNEL);
2073         if (!tx_q->tx_skbuff_dma)
2074                 return -ENOMEM;
2075
2076         tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
2077                                   sizeof(struct sk_buff *),
2078                                   GFP_KERNEL);
2079         if (!tx_q->tx_skbuff)
2080                 return -ENOMEM;
2081
2082         if (priv->extend_desc)
2083                 size = sizeof(struct dma_extended_desc);
2084         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2085                 size = sizeof(struct dma_edesc);
2086         else
2087                 size = sizeof(struct dma_desc);
2088
2089         size *= priv->dma_tx_size;
2090
2091         addr = dma_alloc_coherent(priv->device, size,
2092                                   &tx_q->dma_tx_phy, GFP_KERNEL);
2093         if (!addr)
2094                 return -ENOMEM;
2095
2096         if (priv->extend_desc)
2097                 tx_q->dma_etx = addr;
2098         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2099                 tx_q->dma_entx = addr;
2100         else
2101                 tx_q->dma_tx = addr;
2102
2103         return 0;
2104 }
2105
2106 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
2107 {
2108         u32 tx_count = priv->plat->tx_queues_to_use;
2109         u32 queue;
2110         int ret;
2111
2112         /* TX queues buffers and DMA */
2113         for (queue = 0; queue < tx_count; queue++) {
2114                 ret = __alloc_dma_tx_desc_resources(priv, queue);
2115                 if (ret)
2116                         goto err_dma;
2117         }
2118
2119         return 0;
2120
2121 err_dma:
2122         free_dma_tx_desc_resources(priv);
2123         return ret;
2124 }
2125
2126 /**
2127  * alloc_dma_desc_resources - alloc TX/RX resources.
2128  * @priv: private structure
2129  * Description: according to which descriptor can be used (extend or basic)
2130  * this function allocates the resources for TX and RX paths. In case of
2131  * reception, for example, it pre-allocated the RX socket buffer in order to
2132  * allow zero-copy mechanism.
2133  */
2134 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
2135 {
2136         /* RX Allocation */
2137         int ret = alloc_dma_rx_desc_resources(priv);
2138
2139         if (ret)
2140                 return ret;
2141
2142         ret = alloc_dma_tx_desc_resources(priv);
2143
2144         return ret;
2145 }
2146
2147 /**
2148  * free_dma_desc_resources - free dma desc resources
2149  * @priv: private structure
2150  */
2151 static void free_dma_desc_resources(struct stmmac_priv *priv)
2152 {
2153         /* Release the DMA TX socket buffers */
2154         free_dma_tx_desc_resources(priv);
2155
2156         /* Release the DMA RX socket buffers later
2157          * to ensure all pending XDP_TX buffers are returned.
2158          */
2159         free_dma_rx_desc_resources(priv);
2160 }
2161
2162 /**
2163  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
2164  *  @priv: driver private structure
2165  *  Description: It is used for enabling the rx queues in the MAC
2166  */
2167 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2168 {
2169         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2170         int queue;
2171         u8 mode;
2172
2173         for (queue = 0; queue < rx_queues_count; queue++) {
2174                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2175                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2176         }
2177 }
2178
2179 /**
2180  * stmmac_start_rx_dma - start RX DMA channel
2181  * @priv: driver private structure
2182  * @chan: RX channel index
2183  * Description:
2184  * This starts a RX DMA channel
2185  */
2186 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2187 {
2188         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2189         stmmac_start_rx(priv, priv->ioaddr, chan);
2190 }
2191
2192 /**
2193  * stmmac_start_tx_dma - start TX DMA channel
2194  * @priv: driver private structure
2195  * @chan: TX channel index
2196  * Description:
2197  * This starts a TX DMA channel
2198  */
2199 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2200 {
2201         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2202         stmmac_start_tx(priv, priv->ioaddr, chan);
2203 }
2204
2205 /**
2206  * stmmac_stop_rx_dma - stop RX DMA channel
2207  * @priv: driver private structure
2208  * @chan: RX channel index
2209  * Description:
2210  * This stops a RX DMA channel
2211  */
2212 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2213 {
2214         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2215         stmmac_stop_rx(priv, priv->ioaddr, chan);
2216 }
2217
2218 /**
2219  * stmmac_stop_tx_dma - stop TX DMA channel
2220  * @priv: driver private structure
2221  * @chan: TX channel index
2222  * Description:
2223  * This stops a TX DMA channel
2224  */
2225 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2226 {
2227         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2228         stmmac_stop_tx(priv, priv->ioaddr, chan);
2229 }
2230
2231 /**
2232  * stmmac_start_all_dma - start all RX and TX DMA channels
2233  * @priv: driver private structure
2234  * Description:
2235  * This starts all the RX and TX DMA channels
2236  */
2237 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2238 {
2239         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2240         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2241         u32 chan = 0;
2242
2243         for (chan = 0; chan < rx_channels_count; chan++)
2244                 stmmac_start_rx_dma(priv, chan);
2245
2246         for (chan = 0; chan < tx_channels_count; chan++)
2247                 stmmac_start_tx_dma(priv, chan);
2248 }
2249
2250 /**
2251  * stmmac_stop_all_dma - stop all RX and TX DMA channels
2252  * @priv: driver private structure
2253  * Description:
2254  * This stops the RX and TX DMA channels
2255  */
2256 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2257 {
2258         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2259         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2260         u32 chan = 0;
2261
2262         for (chan = 0; chan < rx_channels_count; chan++)
2263                 stmmac_stop_rx_dma(priv, chan);
2264
2265         for (chan = 0; chan < tx_channels_count; chan++)
2266                 stmmac_stop_tx_dma(priv, chan);
2267 }
2268
2269 /**
2270  *  stmmac_dma_operation_mode - HW DMA operation mode
2271  *  @priv: driver private structure
2272  *  Description: it is used for configuring the DMA operation mode register in
2273  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2274  */
2275 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2276 {
2277         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2278         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2279         int rxfifosz = priv->plat->rx_fifo_size;
2280         int txfifosz = priv->plat->tx_fifo_size;
2281         u32 txmode = 0;
2282         u32 rxmode = 0;
2283         u32 chan = 0;
2284         u8 qmode = 0;
2285
2286         if (rxfifosz == 0)
2287                 rxfifosz = priv->dma_cap.rx_fifo_size;
2288         if (txfifosz == 0)
2289                 txfifosz = priv->dma_cap.tx_fifo_size;
2290
2291         /* Adjust for real per queue fifo size */
2292         rxfifosz /= rx_channels_count;
2293         txfifosz /= tx_channels_count;
2294
2295         if (priv->plat->force_thresh_dma_mode) {
2296                 txmode = tc;
2297                 rxmode = tc;
2298         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2299                 /*
2300                  * In case of GMAC, SF mode can be enabled
2301                  * to perform the TX COE in HW. This depends on:
2302                  * 1) TX COE if actually supported
2303                  * 2) There is no bugged Jumbo frame support
2304                  *    that needs to not insert csum in the TDES.
2305                  */
2306                 txmode = SF_DMA_MODE;
2307                 rxmode = SF_DMA_MODE;
2308                 priv->xstats.threshold = SF_DMA_MODE;
2309         } else {
2310                 txmode = tc;
2311                 rxmode = SF_DMA_MODE;
2312         }
2313
2314         /* configure all channels */
2315         for (chan = 0; chan < rx_channels_count; chan++) {
2316                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2317                 u32 buf_size;
2318
2319                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2320
2321                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2322                                 rxfifosz, qmode);
2323
2324                 if (rx_q->xsk_pool) {
2325                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2326                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2327                                               buf_size,
2328                                               chan);
2329                 } else {
2330                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2331                                               priv->dma_buf_sz,
2332                                               chan);
2333                 }
2334         }
2335
2336         for (chan = 0; chan < tx_channels_count; chan++) {
2337                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2338
2339                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2340                                 txfifosz, qmode);
2341         }
2342 }
2343
2344 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2345 {
2346         struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2347         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2348         struct xsk_buff_pool *pool = tx_q->xsk_pool;
2349         unsigned int entry = tx_q->cur_tx;
2350         struct dma_desc *tx_desc = NULL;
2351         struct xdp_desc xdp_desc;
2352         bool work_done = true;
2353
2354         /* Avoids TX time-out as we are sharing with slow path */
2355         nq->trans_start = jiffies;
2356
2357         budget = min(budget, stmmac_tx_avail(priv, queue));
2358
2359         while (budget-- > 0) {
2360                 dma_addr_t dma_addr;
2361                 bool set_ic;
2362
2363                 /* We are sharing with slow path and stop XSK TX desc submission when
2364                  * available TX ring is less than threshold.
2365                  */
2366                 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2367                     !netif_carrier_ok(priv->dev)) {
2368                         work_done = false;
2369                         break;
2370                 }
2371
2372                 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2373                         break;
2374
2375                 if (likely(priv->extend_desc))
2376                         tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2377                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2378                         tx_desc = &tx_q->dma_entx[entry].basic;
2379                 else
2380                         tx_desc = tx_q->dma_tx + entry;
2381
2382                 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2383                 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2384
2385                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2386
2387                 /* To return XDP buffer to XSK pool, we simple call
2388                  * xsk_tx_completed(), so we don't need to fill up
2389                  * 'buf' and 'xdpf'.
2390                  */
2391                 tx_q->tx_skbuff_dma[entry].buf = 0;
2392                 tx_q->xdpf[entry] = NULL;
2393
2394                 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2395                 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2396                 tx_q->tx_skbuff_dma[entry].last_segment = true;
2397                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2398
2399                 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2400
2401                 tx_q->tx_count_frames++;
2402
2403                 if (!priv->tx_coal_frames[queue])
2404                         set_ic = false;
2405                 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2406                         set_ic = true;
2407                 else
2408                         set_ic = false;
2409
2410                 if (set_ic) {
2411                         tx_q->tx_count_frames = 0;
2412                         stmmac_set_tx_ic(priv, tx_desc);
2413                         priv->xstats.tx_set_ic_bit++;
2414                 }
2415
2416                 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2417                                        true, priv->mode, true, true,
2418                                        xdp_desc.len);
2419
2420                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2421
2422                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
2423                 entry = tx_q->cur_tx;
2424         }
2425
2426         if (tx_desc) {
2427                 stmmac_flush_tx_descriptors(priv, queue);
2428                 xsk_tx_release(pool);
2429         }
2430
2431         /* Return true if all of the 3 conditions are met
2432          *  a) TX Budget is still available
2433          *  b) work_done = true when XSK TX desc peek is empty (no more
2434          *     pending XSK TX for transmission)
2435          */
2436         return !!budget && work_done;
2437 }
2438
2439 /**
2440  * stmmac_tx_clean - to manage the transmission completion
2441  * @priv: driver private structure
2442  * @budget: napi budget limiting this functions packet handling
2443  * @queue: TX queue index
2444  * Description: it reclaims the transmit resources after transmission completes.
2445  */
2446 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2447 {
2448         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2449         unsigned int bytes_compl = 0, pkts_compl = 0;
2450         unsigned int entry, xmits = 0, count = 0;
2451
2452         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2453
2454         priv->xstats.tx_clean++;
2455
2456         tx_q->xsk_frames_done = 0;
2457
2458         entry = tx_q->dirty_tx;
2459
2460         /* Try to clean all TX complete frame in 1 shot */
2461         while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
2462                 struct xdp_frame *xdpf;
2463                 struct sk_buff *skb;
2464                 struct dma_desc *p;
2465                 int status;
2466
2467                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2468                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2469                         xdpf = tx_q->xdpf[entry];
2470                         skb = NULL;
2471                 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2472                         xdpf = NULL;
2473                         skb = tx_q->tx_skbuff[entry];
2474                 } else {
2475                         xdpf = NULL;
2476                         skb = NULL;
2477                 }
2478
2479                 if (priv->extend_desc)
2480                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
2481                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2482                         p = &tx_q->dma_entx[entry].basic;
2483                 else
2484                         p = tx_q->dma_tx + entry;
2485
2486                 status = stmmac_tx_status(priv, &priv->dev->stats,
2487                                 &priv->xstats, p, priv->ioaddr);
2488                 /* Check if the descriptor is owned by the DMA */
2489                 if (unlikely(status & tx_dma_own))
2490                         break;
2491
2492                 count++;
2493
2494                 /* Make sure descriptor fields are read after reading
2495                  * the own bit.
2496                  */
2497                 dma_rmb();
2498
2499                 /* Just consider the last segment and ...*/
2500                 if (likely(!(status & tx_not_ls))) {
2501                         /* ... verify the status error condition */
2502                         if (unlikely(status & tx_err)) {
2503                                 priv->dev->stats.tx_errors++;
2504                         } else {
2505                                 priv->dev->stats.tx_packets++;
2506                                 priv->xstats.tx_pkt_n++;
2507                                 priv->xstats.txq_stats[queue].tx_pkt_n++;
2508                         }
2509                         if (skb)
2510                                 stmmac_get_tx_hwtstamp(priv, p, skb);
2511                 }
2512
2513                 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2514                            tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2515                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
2516                                 dma_unmap_page(priv->device,
2517                                                tx_q->tx_skbuff_dma[entry].buf,
2518                                                tx_q->tx_skbuff_dma[entry].len,
2519                                                DMA_TO_DEVICE);
2520                         else
2521                                 dma_unmap_single(priv->device,
2522                                                  tx_q->tx_skbuff_dma[entry].buf,
2523                                                  tx_q->tx_skbuff_dma[entry].len,
2524                                                  DMA_TO_DEVICE);
2525                         tx_q->tx_skbuff_dma[entry].buf = 0;
2526                         tx_q->tx_skbuff_dma[entry].len = 0;
2527                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
2528                 }
2529
2530                 stmmac_clean_desc3(priv, tx_q, p);
2531
2532                 tx_q->tx_skbuff_dma[entry].last_segment = false;
2533                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2534
2535                 if (xdpf &&
2536                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2537                         xdp_return_frame_rx_napi(xdpf);
2538                         tx_q->xdpf[entry] = NULL;
2539                 }
2540
2541                 if (xdpf &&
2542                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2543                         xdp_return_frame(xdpf);
2544                         tx_q->xdpf[entry] = NULL;
2545                 }
2546
2547                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2548                         tx_q->xsk_frames_done++;
2549
2550                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2551                         if (likely(skb)) {
2552                                 pkts_compl++;
2553                                 bytes_compl += skb->len;
2554                                 dev_consume_skb_any(skb);
2555                                 tx_q->tx_skbuff[entry] = NULL;
2556                         }
2557                 }
2558
2559                 stmmac_release_tx_desc(priv, p, priv->mode);
2560
2561                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
2562         }
2563         tx_q->dirty_tx = entry;
2564
2565         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2566                                   pkts_compl, bytes_compl);
2567
2568         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2569                                                                 queue))) &&
2570             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2571
2572                 netif_dbg(priv, tx_done, priv->dev,
2573                           "%s: restart transmit\n", __func__);
2574                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2575         }
2576
2577         if (tx_q->xsk_pool) {
2578                 bool work_done;
2579
2580                 if (tx_q->xsk_frames_done)
2581                         xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2582
2583                 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2584                         xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2585
2586                 /* For XSK TX, we try to send as many as possible.
2587                  * If XSK work done (XSK TX desc empty and budget still
2588                  * available), return "budget - 1" to reenable TX IRQ.
2589                  * Else, return "budget" to make NAPI continue polling.
2590                  */
2591                 work_done = stmmac_xdp_xmit_zc(priv, queue,
2592                                                STMMAC_XSK_TX_BUDGET_MAX);
2593                 if (work_done)
2594                         xmits = budget - 1;
2595                 else
2596                         xmits = budget;
2597         }
2598
2599         if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2600             priv->eee_sw_timer_en) {
2601                 stmmac_enable_eee_mode(priv);
2602                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2603         }
2604
2605         /* We still have pending packets, let's call for a new scheduling */
2606         if (tx_q->dirty_tx != tx_q->cur_tx)
2607                 hrtimer_start(&tx_q->txtimer,
2608                               STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2609                               HRTIMER_MODE_REL);
2610
2611         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2612
2613         /* Combine decisions from TX clean and XSK TX */
2614         return max(count, xmits);
2615 }
2616
2617 /**
2618  * stmmac_tx_err - to manage the tx error
2619  * @priv: driver private structure
2620  * @chan: channel index
2621  * Description: it cleans the descriptors and restarts the transmission
2622  * in case of transmission errors.
2623  */
2624 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2625 {
2626         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2627
2628         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2629
2630         stmmac_stop_tx_dma(priv, chan);
2631         dma_free_tx_skbufs(priv, chan);
2632         stmmac_clear_tx_descriptors(priv, chan);
2633         tx_q->dirty_tx = 0;
2634         tx_q->cur_tx = 0;
2635         tx_q->mss = 0;
2636         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2637         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2638                             tx_q->dma_tx_phy, chan);
2639         stmmac_start_tx_dma(priv, chan);
2640
2641         priv->dev->stats.tx_errors++;
2642         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2643 }
2644
2645 /**
2646  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2647  *  @priv: driver private structure
2648  *  @txmode: TX operating mode
2649  *  @rxmode: RX operating mode
2650  *  @chan: channel index
2651  *  Description: it is used for configuring of the DMA operation mode in
2652  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2653  *  mode.
2654  */
2655 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2656                                           u32 rxmode, u32 chan)
2657 {
2658         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2659         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2660         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2661         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2662         int rxfifosz = priv->plat->rx_fifo_size;
2663         int txfifosz = priv->plat->tx_fifo_size;
2664
2665         if (rxfifosz == 0)
2666                 rxfifosz = priv->dma_cap.rx_fifo_size;
2667         if (txfifosz == 0)
2668                 txfifosz = priv->dma_cap.tx_fifo_size;
2669
2670         /* Adjust for real per queue fifo size */
2671         rxfifosz /= rx_channels_count;
2672         txfifosz /= tx_channels_count;
2673
2674         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2675         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2676 }
2677
2678 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2679 {
2680         int ret;
2681
2682         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2683                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2684         if (ret && (ret != -EINVAL)) {
2685                 stmmac_global_err(priv);
2686                 return true;
2687         }
2688
2689         return false;
2690 }
2691
2692 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2693 {
2694         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2695                                                  &priv->xstats, chan, dir);
2696         struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2697         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2698         struct stmmac_channel *ch = &priv->channel[chan];
2699         struct napi_struct *rx_napi;
2700         struct napi_struct *tx_napi;
2701         unsigned long flags;
2702
2703         rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2704         tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2705
2706         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2707                 if (napi_schedule_prep(rx_napi)) {
2708                         spin_lock_irqsave(&ch->lock, flags);
2709                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2710                         spin_unlock_irqrestore(&ch->lock, flags);
2711                         __napi_schedule(rx_napi);
2712                 }
2713         }
2714
2715         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2716                 if (napi_schedule_prep(tx_napi)) {
2717                         spin_lock_irqsave(&ch->lock, flags);
2718                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2719                         spin_unlock_irqrestore(&ch->lock, flags);
2720                         __napi_schedule(tx_napi);
2721                 }
2722         }
2723
2724         return status;
2725 }
2726
2727 /**
2728  * stmmac_dma_interrupt - DMA ISR
2729  * @priv: driver private structure
2730  * Description: this is the DMA ISR. It is called by the main ISR.
2731  * It calls the dwmac dma routine and schedule poll method in case of some
2732  * work can be done.
2733  */
2734 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2735 {
2736         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2737         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2738         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2739                                 tx_channel_count : rx_channel_count;
2740         u32 chan;
2741         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2742
2743         /* Make sure we never check beyond our status buffer. */
2744         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2745                 channels_to_check = ARRAY_SIZE(status);
2746
2747         for (chan = 0; chan < channels_to_check; chan++)
2748                 status[chan] = stmmac_napi_check(priv, chan,
2749                                                  DMA_DIR_RXTX);
2750
2751         for (chan = 0; chan < tx_channel_count; chan++) {
2752                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2753                         /* Try to bump up the dma threshold on this failure */
2754                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2755                             (tc <= 256)) {
2756                                 tc += 64;
2757                                 if (priv->plat->force_thresh_dma_mode)
2758                                         stmmac_set_dma_operation_mode(priv,
2759                                                                       tc,
2760                                                                       tc,
2761                                                                       chan);
2762                                 else
2763                                         stmmac_set_dma_operation_mode(priv,
2764                                                                     tc,
2765                                                                     SF_DMA_MODE,
2766                                                                     chan);
2767                                 priv->xstats.threshold = tc;
2768                         }
2769                 } else if (unlikely(status[chan] == tx_hard_error)) {
2770                         stmmac_tx_err(priv, chan);
2771                 }
2772         }
2773 }
2774
2775 /**
2776  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2777  * @priv: driver private structure
2778  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2779  */
2780 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2781 {
2782         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2783                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2784
2785         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2786
2787         if (priv->dma_cap.rmon) {
2788                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2789                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2790         } else
2791                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2792 }
2793
2794 /**
2795  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2796  * @priv: driver private structure
2797  * Description:
2798  *  new GMAC chip generations have a new register to indicate the
2799  *  presence of the optional feature/functions.
2800  *  This can be also used to override the value passed through the
2801  *  platform and necessary for old MAC10/100 and GMAC chips.
2802  */
2803 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2804 {
2805         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2806 }
2807
2808 /**
2809  * stmmac_check_ether_addr - check if the MAC addr is valid
2810  * @priv: driver private structure
2811  * Description:
2812  * it is to verify if the MAC address is valid, in case of failures it
2813  * generates a random MAC address
2814  */
2815 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2816 {
2817         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2818                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2819                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2820                         eth_hw_addr_random(priv->dev);
2821                 dev_info(priv->device, "device MAC address %pM\n",
2822                          priv->dev->dev_addr);
2823         }
2824 }
2825
2826 /**
2827  * stmmac_init_dma_engine - DMA init.
2828  * @priv: driver private structure
2829  * Description:
2830  * It inits the DMA invoking the specific MAC/GMAC callback.
2831  * Some DMA parameters can be passed from the platform;
2832  * in case of these are not passed a default is kept for the MAC or GMAC.
2833  */
2834 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2835 {
2836         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2837         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2838         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2839         struct stmmac_rx_queue *rx_q;
2840         struct stmmac_tx_queue *tx_q;
2841         u32 chan = 0;
2842         int atds = 0;
2843         int ret = 0;
2844
2845         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2846                 dev_err(priv->device, "Invalid DMA configuration\n");
2847                 return -EINVAL;
2848         }
2849
2850         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2851                 atds = 1;
2852
2853         ret = stmmac_reset(priv, priv->ioaddr);
2854         if (ret) {
2855                 dev_err(priv->device, "Failed to reset the dma\n");
2856                 return ret;
2857         }
2858
2859         /* DMA Configuration */
2860         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2861
2862         if (priv->plat->axi)
2863                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2864
2865         /* DMA CSR Channel configuration */
2866         for (chan = 0; chan < dma_csr_ch; chan++)
2867                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2868
2869         /* DMA RX Channel Configuration */
2870         for (chan = 0; chan < rx_channels_count; chan++) {
2871                 rx_q = &priv->rx_queue[chan];
2872
2873                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2874                                     rx_q->dma_rx_phy, chan);
2875
2876                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2877                                      (rx_q->buf_alloc_num *
2878                                       sizeof(struct dma_desc));
2879                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2880                                        rx_q->rx_tail_addr, chan);
2881         }
2882
2883         /* DMA TX Channel Configuration */
2884         for (chan = 0; chan < tx_channels_count; chan++) {
2885                 tx_q = &priv->tx_queue[chan];
2886
2887                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2888                                     tx_q->dma_tx_phy, chan);
2889
2890                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2891                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2892                                        tx_q->tx_tail_addr, chan);
2893         }
2894
2895         return ret;
2896 }
2897
2898 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2899 {
2900         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2901
2902         hrtimer_start(&tx_q->txtimer,
2903                       STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2904                       HRTIMER_MODE_REL);
2905 }
2906
2907 /**
2908  * stmmac_tx_timer - mitigation sw timer for tx.
2909  * @t: data pointer
2910  * Description:
2911  * This is the timer handler to directly invoke the stmmac_tx_clean.
2912  */
2913 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
2914 {
2915         struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
2916         struct stmmac_priv *priv = tx_q->priv_data;
2917         struct stmmac_channel *ch;
2918         struct napi_struct *napi;
2919
2920         ch = &priv->channel[tx_q->queue_index];
2921         napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2922
2923         if (likely(napi_schedule_prep(napi))) {
2924                 unsigned long flags;
2925
2926                 spin_lock_irqsave(&ch->lock, flags);
2927                 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2928                 spin_unlock_irqrestore(&ch->lock, flags);
2929                 __napi_schedule(napi);
2930         }
2931
2932         return HRTIMER_NORESTART;
2933 }
2934
2935 /**
2936  * stmmac_init_coalesce - init mitigation options.
2937  * @priv: driver private structure
2938  * Description:
2939  * This inits the coalesce parameters: i.e. timer rate,
2940  * timer handler and default threshold used for enabling the
2941  * interrupt on completion bit.
2942  */
2943 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2944 {
2945         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2946         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2947         u32 chan;
2948
2949         for (chan = 0; chan < tx_channel_count; chan++) {
2950                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2951
2952                 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
2953                 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
2954
2955                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2956                 tx_q->txtimer.function = stmmac_tx_timer;
2957         }
2958
2959         for (chan = 0; chan < rx_channel_count; chan++)
2960                 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
2961 }
2962
2963 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2964 {
2965         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2966         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2967         u32 chan;
2968
2969         /* set TX ring length */
2970         for (chan = 0; chan < tx_channels_count; chan++)
2971                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2972                                        (priv->dma_tx_size - 1), chan);
2973
2974         /* set RX ring length */
2975         for (chan = 0; chan < rx_channels_count; chan++)
2976                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2977                                        (priv->dma_rx_size - 1), chan);
2978 }
2979
2980 /**
2981  *  stmmac_set_tx_queue_weight - Set TX queue weight
2982  *  @priv: driver private structure
2983  *  Description: It is used for setting TX queues weight
2984  */
2985 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2986 {
2987         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2988         u32 weight;
2989         u32 queue;
2990
2991         for (queue = 0; queue < tx_queues_count; queue++) {
2992                 weight = priv->plat->tx_queues_cfg[queue].weight;
2993                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2994         }
2995 }
2996
2997 /**
2998  *  stmmac_configure_cbs - Configure CBS in TX queue
2999  *  @priv: driver private structure
3000  *  Description: It is used for configuring CBS in AVB TX queues
3001  */
3002 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3003 {
3004         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3005         u32 mode_to_use;
3006         u32 queue;
3007
3008         /* queue 0 is reserved for legacy traffic */
3009         for (queue = 1; queue < tx_queues_count; queue++) {
3010                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3011                 if (mode_to_use == MTL_QUEUE_DCB)
3012                         continue;
3013
3014                 stmmac_config_cbs(priv, priv->hw,
3015                                 priv->plat->tx_queues_cfg[queue].send_slope,
3016                                 priv->plat->tx_queues_cfg[queue].idle_slope,
3017                                 priv->plat->tx_queues_cfg[queue].high_credit,
3018                                 priv->plat->tx_queues_cfg[queue].low_credit,
3019                                 queue);
3020         }
3021 }
3022
3023 /**
3024  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3025  *  @priv: driver private structure
3026  *  Description: It is used for mapping RX queues to RX dma channels
3027  */
3028 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3029 {
3030         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3031         u32 queue;
3032         u32 chan;
3033
3034         for (queue = 0; queue < rx_queues_count; queue++) {
3035                 chan = priv->plat->rx_queues_cfg[queue].chan;
3036                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3037         }
3038 }
3039
3040 /**
3041  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3042  *  @priv: driver private structure
3043  *  Description: It is used for configuring the RX Queue Priority
3044  */
3045 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3046 {
3047         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3048         u32 queue;
3049         u32 prio;
3050
3051         for (queue = 0; queue < rx_queues_count; queue++) {
3052                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3053                         continue;
3054
3055                 prio = priv->plat->rx_queues_cfg[queue].prio;
3056                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3057         }
3058 }
3059
3060 /**
3061  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3062  *  @priv: driver private structure
3063  *  Description: It is used for configuring the TX Queue Priority
3064  */
3065 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3066 {
3067         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3068         u32 queue;
3069         u32 prio;
3070
3071         for (queue = 0; queue < tx_queues_count; queue++) {
3072                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3073                         continue;
3074
3075                 prio = priv->plat->tx_queues_cfg[queue].prio;
3076                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3077         }
3078 }
3079
3080 /**
3081  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3082  *  @priv: driver private structure
3083  *  Description: It is used for configuring the RX queue routing
3084  */
3085 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3086 {
3087         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3088         u32 queue;
3089         u8 packet;
3090
3091         for (queue = 0; queue < rx_queues_count; queue++) {
3092                 /* no specific packet type routing specified for the queue */
3093                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3094                         continue;
3095
3096                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3097                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3098         }
3099 }
3100
3101 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3102 {
3103         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3104                 priv->rss.enable = false;
3105                 return;
3106         }
3107
3108         if (priv->dev->features & NETIF_F_RXHASH)
3109                 priv->rss.enable = true;
3110         else
3111                 priv->rss.enable = false;
3112
3113         stmmac_rss_configure(priv, priv->hw, &priv->rss,
3114                              priv->plat->rx_queues_to_use);
3115 }
3116
3117 /**
3118  *  stmmac_mtl_configuration - Configure MTL
3119  *  @priv: driver private structure
3120  *  Description: It is used for configurring MTL
3121  */
3122 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3123 {
3124         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3125         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3126
3127         if (tx_queues_count > 1)
3128                 stmmac_set_tx_queue_weight(priv);
3129
3130         /* Configure MTL RX algorithms */
3131         if (rx_queues_count > 1)
3132                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3133                                 priv->plat->rx_sched_algorithm);
3134
3135         /* Configure MTL TX algorithms */
3136         if (tx_queues_count > 1)
3137                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3138                                 priv->plat->tx_sched_algorithm);
3139
3140         /* Configure CBS in AVB TX queues */
3141         if (tx_queues_count > 1)
3142                 stmmac_configure_cbs(priv);
3143
3144         /* Map RX MTL to DMA channels */
3145         stmmac_rx_queue_dma_chan_map(priv);
3146
3147         /* Enable MAC RX Queues */
3148         stmmac_mac_enable_rx_queues(priv);
3149
3150         /* Set RX priorities */
3151         if (rx_queues_count > 1)
3152                 stmmac_mac_config_rx_queues_prio(priv);
3153
3154         /* Set TX priorities */
3155         if (tx_queues_count > 1)
3156                 stmmac_mac_config_tx_queues_prio(priv);
3157
3158         /* Set RX routing */
3159         if (rx_queues_count > 1)
3160                 stmmac_mac_config_rx_queues_routing(priv);
3161
3162         /* Receive Side Scaling */
3163         if (rx_queues_count > 1)
3164                 stmmac_mac_config_rss(priv);
3165 }
3166
3167 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3168 {
3169         if (priv->dma_cap.asp) {
3170                 netdev_info(priv->dev, "Enabling Safety Features\n");
3171                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3172                                           priv->plat->safety_feat_cfg);
3173         } else {
3174                 netdev_info(priv->dev, "No Safety Features support found\n");
3175         }
3176 }
3177
3178 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3179 {
3180         char *name;
3181
3182         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3183         clear_bit(__FPE_REMOVING,  &priv->fpe_task_state);
3184
3185         name = priv->wq_name;
3186         sprintf(name, "%s-fpe", priv->dev->name);
3187
3188         priv->fpe_wq = create_singlethread_workqueue(name);
3189         if (!priv->fpe_wq) {
3190                 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3191
3192                 return -ENOMEM;
3193         }
3194         netdev_info(priv->dev, "FPE workqueue start");
3195
3196         return 0;
3197 }
3198
3199 /**
3200  * stmmac_hw_setup - setup mac in a usable state.
3201  *  @dev : pointer to the device structure.
3202  *  @init_ptp: initialize PTP if set
3203  *  Description:
3204  *  this is the main function to setup the HW in a usable state because the
3205  *  dma engine is reset, the core registers are configured (e.g. AXI,
3206  *  Checksum features, timers). The DMA is ready to start receiving and
3207  *  transmitting.
3208  *  Return value:
3209  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3210  *  file on failure.
3211  */
3212 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
3213 {
3214         struct stmmac_priv *priv = netdev_priv(dev);
3215         u32 rx_cnt = priv->plat->rx_queues_to_use;
3216         u32 tx_cnt = priv->plat->tx_queues_to_use;
3217         bool sph_en;
3218         u32 chan;
3219         int ret;
3220
3221         /* DMA initialization and SW reset */
3222         ret = stmmac_init_dma_engine(priv);
3223         if (ret < 0) {
3224                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3225                            __func__);
3226                 return ret;
3227         }
3228
3229         /* Copy the MAC addr into the HW  */
3230         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3231
3232         /* PS and related bits will be programmed according to the speed */
3233         if (priv->hw->pcs) {
3234                 int speed = priv->plat->mac_port_sel_speed;
3235
3236                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3237                     (speed == SPEED_1000)) {
3238                         priv->hw->ps = speed;
3239                 } else {
3240                         dev_warn(priv->device, "invalid port speed\n");
3241                         priv->hw->ps = 0;
3242                 }
3243         }
3244
3245         /* Initialize the MAC Core */
3246         stmmac_core_init(priv, priv->hw, dev);
3247
3248         /* Initialize MTL*/
3249         stmmac_mtl_configuration(priv);
3250
3251         /* Initialize Safety Features */
3252         stmmac_safety_feat_configuration(priv);
3253
3254         ret = stmmac_rx_ipc(priv, priv->hw);
3255         if (!ret) {
3256                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3257                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3258                 priv->hw->rx_csum = 0;
3259         }
3260
3261         /* Enable the MAC Rx/Tx */
3262         stmmac_mac_set(priv, priv->ioaddr, true);
3263
3264         /* Set the HW DMA mode and the COE */
3265         stmmac_dma_operation_mode(priv);
3266
3267         stmmac_mmc_setup(priv);
3268
3269         if (init_ptp) {
3270                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3271                 if (ret < 0)
3272                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
3273
3274                 ret = stmmac_init_ptp(priv);
3275                 if (ret == -EOPNOTSUPP)
3276                         netdev_warn(priv->dev, "PTP not supported by HW\n");
3277                 else if (ret)
3278                         netdev_warn(priv->dev, "PTP init failed\n");
3279         }
3280
3281         priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3282
3283         /* Convert the timer from msec to usec */
3284         if (!priv->tx_lpi_timer)
3285                 priv->tx_lpi_timer = eee_timer * 1000;
3286
3287         if (priv->use_riwt) {
3288                 u32 queue;
3289
3290                 for (queue = 0; queue < rx_cnt; queue++) {
3291                         if (!priv->rx_riwt[queue])
3292                                 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3293
3294                         stmmac_rx_watchdog(priv, priv->ioaddr,
3295                                            priv->rx_riwt[queue], queue);
3296                 }
3297         }
3298
3299         if (priv->hw->pcs)
3300                 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3301
3302         /* set TX and RX rings length */
3303         stmmac_set_rings_length(priv);
3304
3305         /* Enable TSO */
3306         if (priv->tso) {
3307                 for (chan = 0; chan < tx_cnt; chan++) {
3308                         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3309
3310                         /* TSO and TBS cannot co-exist */
3311                         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3312                                 continue;
3313
3314                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3315                 }
3316         }
3317
3318         /* Enable Split Header */
3319         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3320         for (chan = 0; chan < rx_cnt; chan++)
3321                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3322
3323
3324         /* VLAN Tag Insertion */
3325         if (priv->dma_cap.vlins)
3326                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3327
3328         /* TBS */
3329         for (chan = 0; chan < tx_cnt; chan++) {
3330                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3331                 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3332
3333                 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3334         }
3335
3336         /* Configure real RX and TX queues */
3337         netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3338         netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3339
3340         /* Start the ball rolling... */
3341         stmmac_start_all_dma(priv);
3342
3343         if (priv->dma_cap.fpesel) {
3344                 stmmac_fpe_start_wq(priv);
3345
3346                 if (priv->plat->fpe_cfg->enable)
3347                         stmmac_fpe_handshake(priv, true);
3348         }
3349
3350         return 0;
3351 }
3352
3353 static void stmmac_hw_teardown(struct net_device *dev)
3354 {
3355         struct stmmac_priv *priv = netdev_priv(dev);
3356
3357         clk_disable_unprepare(priv->plat->clk_ptp_ref);
3358 }
3359
3360 static void stmmac_free_irq(struct net_device *dev,
3361                             enum request_irq_err irq_err, int irq_idx)
3362 {
3363         struct stmmac_priv *priv = netdev_priv(dev);
3364         int j;
3365
3366         switch (irq_err) {
3367         case REQ_IRQ_ERR_ALL:
3368                 irq_idx = priv->plat->tx_queues_to_use;
3369                 fallthrough;
3370         case REQ_IRQ_ERR_TX:
3371                 for (j = irq_idx - 1; j >= 0; j--) {
3372                         if (priv->tx_irq[j] > 0) {
3373                                 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3374                                 free_irq(priv->tx_irq[j], &priv->tx_queue[j]);
3375                         }
3376                 }
3377                 irq_idx = priv->plat->rx_queues_to_use;
3378                 fallthrough;
3379         case REQ_IRQ_ERR_RX:
3380                 for (j = irq_idx - 1; j >= 0; j--) {
3381                         if (priv->rx_irq[j] > 0) {
3382                                 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3383                                 free_irq(priv->rx_irq[j], &priv->rx_queue[j]);
3384                         }
3385                 }
3386
3387                 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3388                         free_irq(priv->sfty_ue_irq, dev);
3389                 fallthrough;
3390         case REQ_IRQ_ERR_SFTY_UE:
3391                 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3392                         free_irq(priv->sfty_ce_irq, dev);
3393                 fallthrough;
3394         case REQ_IRQ_ERR_SFTY_CE:
3395                 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3396                         free_irq(priv->lpi_irq, dev);
3397                 fallthrough;
3398         case REQ_IRQ_ERR_LPI:
3399                 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3400                         free_irq(priv->wol_irq, dev);
3401                 fallthrough;
3402         case REQ_IRQ_ERR_WOL:
3403                 free_irq(dev->irq, dev);
3404                 fallthrough;
3405         case REQ_IRQ_ERR_MAC:
3406         case REQ_IRQ_ERR_NO:
3407                 /* If MAC IRQ request error, no more IRQ to free */
3408                 break;
3409         }
3410 }
3411
3412 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3413 {
3414         struct stmmac_priv *priv = netdev_priv(dev);
3415         enum request_irq_err irq_err;
3416         cpumask_t cpu_mask;
3417         int irq_idx = 0;
3418         char *int_name;
3419         int ret;
3420         int i;
3421
3422         /* For common interrupt */
3423         int_name = priv->int_name_mac;
3424         sprintf(int_name, "%s:%s", dev->name, "mac");
3425         ret = request_irq(dev->irq, stmmac_mac_interrupt,
3426                           0, int_name, dev);
3427         if (unlikely(ret < 0)) {
3428                 netdev_err(priv->dev,
3429                            "%s: alloc mac MSI %d (error: %d)\n",
3430                            __func__, dev->irq, ret);
3431                 irq_err = REQ_IRQ_ERR_MAC;
3432                 goto irq_error;
3433         }
3434
3435         /* Request the Wake IRQ in case of another line
3436          * is used for WoL
3437          */
3438         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3439                 int_name = priv->int_name_wol;
3440                 sprintf(int_name, "%s:%s", dev->name, "wol");
3441                 ret = request_irq(priv->wol_irq,
3442                                   stmmac_mac_interrupt,
3443                                   0, int_name, dev);
3444                 if (unlikely(ret < 0)) {
3445                         netdev_err(priv->dev,
3446                                    "%s: alloc wol MSI %d (error: %d)\n",
3447                                    __func__, priv->wol_irq, ret);
3448                         irq_err = REQ_IRQ_ERR_WOL;
3449                         goto irq_error;
3450                 }
3451         }
3452
3453         /* Request the LPI IRQ in case of another line
3454          * is used for LPI
3455          */
3456         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3457                 int_name = priv->int_name_lpi;
3458                 sprintf(int_name, "%s:%s", dev->name, "lpi");
3459                 ret = request_irq(priv->lpi_irq,
3460                                   stmmac_mac_interrupt,
3461                                   0, int_name, dev);
3462                 if (unlikely(ret < 0)) {
3463                         netdev_err(priv->dev,
3464                                    "%s: alloc lpi MSI %d (error: %d)\n",
3465                                    __func__, priv->lpi_irq, ret);
3466                         irq_err = REQ_IRQ_ERR_LPI;
3467                         goto irq_error;
3468                 }
3469         }
3470
3471         /* Request the Safety Feature Correctible Error line in
3472          * case of another line is used
3473          */
3474         if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3475                 int_name = priv->int_name_sfty_ce;
3476                 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3477                 ret = request_irq(priv->sfty_ce_irq,
3478                                   stmmac_safety_interrupt,
3479                                   0, int_name, dev);
3480                 if (unlikely(ret < 0)) {
3481                         netdev_err(priv->dev,
3482                                    "%s: alloc sfty ce MSI %d (error: %d)\n",
3483                                    __func__, priv->sfty_ce_irq, ret);
3484                         irq_err = REQ_IRQ_ERR_SFTY_CE;
3485                         goto irq_error;
3486                 }
3487         }
3488
3489         /* Request the Safety Feature Uncorrectible Error line in
3490          * case of another line is used
3491          */
3492         if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3493                 int_name = priv->int_name_sfty_ue;
3494                 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3495                 ret = request_irq(priv->sfty_ue_irq,
3496                                   stmmac_safety_interrupt,
3497                                   0, int_name, dev);
3498                 if (unlikely(ret < 0)) {
3499                         netdev_err(priv->dev,
3500                                    "%s: alloc sfty ue MSI %d (error: %d)\n",
3501                                    __func__, priv->sfty_ue_irq, ret);
3502                         irq_err = REQ_IRQ_ERR_SFTY_UE;
3503                         goto irq_error;
3504                 }
3505         }
3506
3507         /* Request Rx MSI irq */
3508         for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3509                 if (priv->rx_irq[i] == 0)
3510                         continue;
3511
3512                 int_name = priv->int_name_rx_irq[i];
3513                 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3514                 ret = request_irq(priv->rx_irq[i],
3515                                   stmmac_msi_intr_rx,
3516                                   0, int_name, &priv->rx_queue[i]);
3517                 if (unlikely(ret < 0)) {
3518                         netdev_err(priv->dev,
3519                                    "%s: alloc rx-%d  MSI %d (error: %d)\n",
3520                                    __func__, i, priv->rx_irq[i], ret);
3521                         irq_err = REQ_IRQ_ERR_RX;
3522                         irq_idx = i;
3523                         goto irq_error;
3524                 }
3525                 cpumask_clear(&cpu_mask);
3526                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3527                 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3528         }
3529
3530         /* Request Tx MSI irq */
3531         for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3532                 if (priv->tx_irq[i] == 0)
3533                         continue;
3534
3535                 int_name = priv->int_name_tx_irq[i];
3536                 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3537                 ret = request_irq(priv->tx_irq[i],
3538                                   stmmac_msi_intr_tx,
3539                                   0, int_name, &priv->tx_queue[i]);
3540                 if (unlikely(ret < 0)) {
3541                         netdev_err(priv->dev,
3542                                    "%s: alloc tx-%d  MSI %d (error: %d)\n",
3543                                    __func__, i, priv->tx_irq[i], ret);
3544                         irq_err = REQ_IRQ_ERR_TX;
3545                         irq_idx = i;
3546                         goto irq_error;
3547                 }
3548                 cpumask_clear(&cpu_mask);
3549                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3550                 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3551         }
3552
3553         return 0;
3554
3555 irq_error:
3556         stmmac_free_irq(dev, irq_err, irq_idx);
3557         return ret;
3558 }
3559
3560 static int stmmac_request_irq_single(struct net_device *dev)
3561 {
3562         struct stmmac_priv *priv = netdev_priv(dev);
3563         enum request_irq_err irq_err;
3564         int ret;
3565
3566         ret = request_irq(dev->irq, stmmac_interrupt,
3567                           IRQF_SHARED, dev->name, dev);
3568         if (unlikely(ret < 0)) {
3569                 netdev_err(priv->dev,
3570                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3571                            __func__, dev->irq, ret);
3572                 irq_err = REQ_IRQ_ERR_MAC;
3573                 goto irq_error;
3574         }
3575
3576         /* Request the Wake IRQ in case of another line
3577          * is used for WoL
3578          */
3579         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3580                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3581                                   IRQF_SHARED, dev->name, dev);
3582                 if (unlikely(ret < 0)) {
3583                         netdev_err(priv->dev,
3584                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3585                                    __func__, priv->wol_irq, ret);
3586                         irq_err = REQ_IRQ_ERR_WOL;
3587                         goto irq_error;
3588                 }
3589         }
3590
3591         /* Request the IRQ lines */
3592         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3593                 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3594                                   IRQF_SHARED, dev->name, dev);
3595                 if (unlikely(ret < 0)) {
3596                         netdev_err(priv->dev,
3597                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3598                                    __func__, priv->lpi_irq, ret);
3599                         irq_err = REQ_IRQ_ERR_LPI;
3600                         goto irq_error;
3601                 }
3602         }
3603
3604         return 0;
3605
3606 irq_error:
3607         stmmac_free_irq(dev, irq_err, 0);
3608         return ret;
3609 }
3610
3611 static int stmmac_request_irq(struct net_device *dev)
3612 {
3613         struct stmmac_priv *priv = netdev_priv(dev);
3614         int ret;
3615
3616         /* Request the IRQ lines */
3617         if (priv->plat->multi_msi_en)
3618                 ret = stmmac_request_irq_multi_msi(dev);
3619         else
3620                 ret = stmmac_request_irq_single(dev);
3621
3622         return ret;
3623 }
3624
3625 /**
3626  *  stmmac_open - open entry point of the driver
3627  *  @dev : pointer to the device structure.
3628  *  Description:
3629  *  This function is the open entry point of the driver.
3630  *  Return value:
3631  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3632  *  file on failure.
3633  */
3634 int stmmac_open(struct net_device *dev)
3635 {
3636         struct stmmac_priv *priv = netdev_priv(dev);
3637         int mode = priv->plat->phy_interface;
3638         int bfsize = 0;
3639         u32 chan;
3640         int ret;
3641
3642         ret = pm_runtime_get_sync(priv->device);
3643         if (ret < 0) {
3644                 pm_runtime_put_noidle(priv->device);
3645                 return ret;
3646         }
3647
3648         if (priv->hw->pcs != STMMAC_PCS_TBI &&
3649             priv->hw->pcs != STMMAC_PCS_RTBI &&
3650             (!priv->hw->xpcs ||
3651              xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3652                 ret = stmmac_init_phy(dev);
3653                 if (ret) {
3654                         netdev_err(priv->dev,
3655                                    "%s: Cannot attach to PHY (error: %d)\n",
3656                                    __func__, ret);
3657                         goto init_phy_error;
3658                 }
3659         }
3660
3661         /* Extra statistics */
3662         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3663         priv->xstats.threshold = tc;
3664
3665         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
3666         if (bfsize < 0)
3667                 bfsize = 0;
3668
3669         if (bfsize < BUF_SIZE_16KiB)
3670                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
3671
3672         priv->dma_buf_sz = bfsize;
3673         buf_sz = bfsize;
3674
3675         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3676
3677         if (!priv->dma_tx_size)
3678                 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3679         if (!priv->dma_rx_size)
3680                 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3681
3682         /* Earlier check for TBS */
3683         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3684                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3685                 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3686
3687                 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3688                 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3689         }
3690
3691         ret = alloc_dma_desc_resources(priv);
3692         if (ret < 0) {
3693                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3694                            __func__);
3695                 goto dma_desc_error;
3696         }
3697
3698         ret = init_dma_desc_rings(dev, GFP_KERNEL);
3699         if (ret < 0) {
3700                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3701                            __func__);
3702                 goto init_error;
3703         }
3704
3705         ret = stmmac_hw_setup(dev, true);
3706         if (ret < 0) {
3707                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3708                 goto init_error;
3709         }
3710
3711         stmmac_init_coalesce(priv);
3712
3713         phylink_start(priv->phylink);
3714         /* We may have called phylink_speed_down before */
3715         phylink_speed_up(priv->phylink);
3716
3717         ret = stmmac_request_irq(dev);
3718         if (ret)
3719                 goto irq_error;
3720
3721         stmmac_enable_all_queues(priv);
3722         netif_tx_start_all_queues(priv->dev);
3723
3724         return 0;
3725
3726 irq_error:
3727         phylink_stop(priv->phylink);
3728
3729         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3730                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3731
3732         stmmac_hw_teardown(dev);
3733 init_error:
3734         free_dma_desc_resources(priv);
3735 dma_desc_error:
3736         phylink_disconnect_phy(priv->phylink);
3737 init_phy_error:
3738         pm_runtime_put(priv->device);
3739         return ret;
3740 }
3741
3742 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3743 {
3744         set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3745
3746         if (priv->fpe_wq)
3747                 destroy_workqueue(priv->fpe_wq);
3748
3749         netdev_info(priv->dev, "FPE workqueue stop");
3750 }
3751
3752 /**
3753  *  stmmac_release - close entry point of the driver
3754  *  @dev : device pointer.
3755  *  Description:
3756  *  This is the stop entry point of the driver.
3757  */
3758 int stmmac_release(struct net_device *dev)
3759 {
3760         struct stmmac_priv *priv = netdev_priv(dev);
3761         u32 chan;
3762
3763         if (device_may_wakeup(priv->device))
3764                 phylink_speed_down(priv->phylink, false);
3765         /* Stop and disconnect the PHY */
3766         phylink_stop(priv->phylink);
3767         phylink_disconnect_phy(priv->phylink);
3768
3769         stmmac_disable_all_queues(priv);
3770
3771         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3772                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3773
3774         /* Free the IRQ lines */
3775         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3776
3777         if (priv->eee_enabled) {
3778                 priv->tx_path_in_lpi_mode = false;
3779                 del_timer_sync(&priv->eee_ctrl_timer);
3780         }
3781
3782         /* Stop TX/RX DMA and clear the descriptors */
3783         stmmac_stop_all_dma(priv);
3784
3785         /* Release and free the Rx/Tx resources */
3786         free_dma_desc_resources(priv);
3787
3788         /* Disable the MAC Rx/Tx */
3789         stmmac_mac_set(priv, priv->ioaddr, false);
3790
3791         netif_carrier_off(dev);
3792
3793         stmmac_release_ptp(priv);
3794
3795         pm_runtime_put(priv->device);
3796
3797         if (priv->dma_cap.fpesel)
3798                 stmmac_fpe_stop_wq(priv);
3799
3800         return 0;
3801 }
3802
3803 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3804                                struct stmmac_tx_queue *tx_q)
3805 {
3806         u16 tag = 0x0, inner_tag = 0x0;
3807         u32 inner_type = 0x0;
3808         struct dma_desc *p;
3809
3810         if (!priv->dma_cap.vlins)
3811                 return false;
3812         if (!skb_vlan_tag_present(skb))
3813                 return false;
3814         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3815                 inner_tag = skb_vlan_tag_get(skb);
3816                 inner_type = STMMAC_VLAN_INSERT;
3817         }
3818
3819         tag = skb_vlan_tag_get(skb);
3820
3821         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3822                 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3823         else
3824                 p = &tx_q->dma_tx[tx_q->cur_tx];
3825
3826         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3827                 return false;
3828
3829         stmmac_set_tx_owner(priv, p);
3830         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
3831         return true;
3832 }
3833
3834 /**
3835  *  stmmac_tso_allocator - close entry point of the driver
3836  *  @priv: driver private structure
3837  *  @des: buffer start address
3838  *  @total_len: total length to fill in descriptors
3839  *  @last_segment: condition for the last descriptor
3840  *  @queue: TX queue index
3841  *  Description:
3842  *  This function fills descriptor and request new descriptors according to
3843  *  buffer length to fill
3844  */
3845 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
3846                                  int total_len, bool last_segment, u32 queue)
3847 {
3848         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3849         struct dma_desc *desc;
3850         u32 buff_size;
3851         int tmp_len;
3852
3853         tmp_len = total_len;
3854
3855         while (tmp_len > 0) {
3856                 dma_addr_t curr_addr;
3857
3858                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3859                                                 priv->dma_tx_size);
3860                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3861
3862                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3863                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3864                 else
3865                         desc = &tx_q->dma_tx[tx_q->cur_tx];
3866
3867                 curr_addr = des + (total_len - tmp_len);
3868                 if (priv->dma_cap.addr64 <= 32)
3869                         desc->des0 = cpu_to_le32(curr_addr);
3870                 else
3871                         stmmac_set_desc_addr(priv, desc, curr_addr);
3872
3873                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
3874                             TSO_MAX_BUFF_SIZE : tmp_len;
3875
3876                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3877                                 0, 1,
3878                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3879                                 0, 0);
3880
3881                 tmp_len -= TSO_MAX_BUFF_SIZE;
3882         }
3883 }
3884
3885 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
3886 {
3887         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3888         int desc_size;
3889
3890         if (likely(priv->extend_desc))
3891                 desc_size = sizeof(struct dma_extended_desc);
3892         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3893                 desc_size = sizeof(struct dma_edesc);
3894         else
3895                 desc_size = sizeof(struct dma_desc);
3896
3897         /* The own bit must be the latest setting done when prepare the
3898          * descriptor and then barrier is needed to make sure that
3899          * all is coherent before granting the DMA engine.
3900          */
3901         wmb();
3902
3903         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3904         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3905 }
3906
3907 /**
3908  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3909  *  @skb : the socket buffer
3910  *  @dev : device pointer
3911  *  Description: this is the transmit function that is called on TSO frames
3912  *  (support available on GMAC4 and newer chips).
3913  *  Diagram below show the ring programming in case of TSO frames:
3914  *
3915  *  First Descriptor
3916  *   --------
3917  *   | DES0 |---> buffer1 = L2/L3/L4 header
3918  *   | DES1 |---> TCP Payload (can continue on next descr...)
3919  *   | DES2 |---> buffer 1 and 2 len
3920  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3921  *   --------
3922  *      |
3923  *     ...
3924  *      |
3925  *   --------
3926  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
3927  *   | DES1 | --|
3928  *   | DES2 | --> buffer 1 and 2 len
3929  *   | DES3 |
3930  *   --------
3931  *
3932  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3933  */
3934 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3935 {
3936         struct dma_desc *desc, *first, *mss_desc = NULL;
3937         struct stmmac_priv *priv = netdev_priv(dev);
3938         int nfrags = skb_shinfo(skb)->nr_frags;
3939         u32 queue = skb_get_queue_mapping(skb);
3940         unsigned int first_entry, tx_packets;
3941         int tmp_pay_len = 0, first_tx;
3942         struct stmmac_tx_queue *tx_q;
3943         bool has_vlan, set_ic;
3944         u8 proto_hdr_len, hdr;
3945         u32 pay_len, mss;
3946         dma_addr_t des;
3947         int i;
3948
3949         tx_q = &priv->tx_queue[queue];
3950         first_tx = tx_q->cur_tx;
3951
3952         /* Compute header lengths */
3953         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3954                 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3955                 hdr = sizeof(struct udphdr);
3956         } else {
3957                 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3958                 hdr = tcp_hdrlen(skb);
3959         }
3960
3961         /* Desc availability based on threshold should be enough safe */
3962         if (unlikely(stmmac_tx_avail(priv, queue) <
3963                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
3964                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3965                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3966                                                                 queue));
3967                         /* This is a hard error, log it. */
3968                         netdev_err(priv->dev,
3969                                    "%s: Tx Ring full when queue awake\n",
3970                                    __func__);
3971                 }
3972                 return NETDEV_TX_BUSY;
3973         }
3974
3975         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
3976
3977         mss = skb_shinfo(skb)->gso_size;
3978
3979         /* set new MSS value if needed */
3980         if (mss != tx_q->mss) {
3981                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3982                         mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3983                 else
3984                         mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
3985
3986                 stmmac_set_mss(priv, mss_desc, mss);
3987                 tx_q->mss = mss;
3988                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3989                                                 priv->dma_tx_size);
3990                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3991         }
3992
3993         if (netif_msg_tx_queued(priv)) {
3994                 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
3995                         __func__, hdr, proto_hdr_len, pay_len, mss);
3996                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
3997                         skb->data_len);
3998         }
3999
4000         /* Check if VLAN can be inserted by HW */
4001         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4002
4003         first_entry = tx_q->cur_tx;
4004         WARN_ON(tx_q->tx_skbuff[first_entry]);
4005
4006         if (tx_q->tbs & STMMAC_TBS_AVAIL)
4007                 desc = &tx_q->dma_entx[first_entry].basic;
4008         else
4009                 desc = &tx_q->dma_tx[first_entry];
4010         first = desc;
4011
4012         if (has_vlan)
4013                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4014
4015         /* first descriptor: fill Headers on Buf1 */
4016         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4017                              DMA_TO_DEVICE);
4018         if (dma_mapping_error(priv->device, des))
4019                 goto dma_map_err;
4020
4021         tx_q->tx_skbuff_dma[first_entry].buf = des;
4022         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4023         tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4024         tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4025
4026         if (priv->dma_cap.addr64 <= 32) {
4027                 first->des0 = cpu_to_le32(des);
4028
4029                 /* Fill start of payload in buff2 of first descriptor */
4030                 if (pay_len)
4031                         first->des1 = cpu_to_le32(des + proto_hdr_len);
4032
4033                 /* If needed take extra descriptors to fill the remaining payload */
4034                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4035         } else {
4036                 stmmac_set_desc_addr(priv, first, des);
4037                 tmp_pay_len = pay_len;
4038                 des += proto_hdr_len;
4039                 pay_len = 0;
4040         }
4041
4042         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4043
4044         /* Prepare fragments */
4045         for (i = 0; i < nfrags; i++) {
4046                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4047
4048                 des = skb_frag_dma_map(priv->device, frag, 0,
4049                                        skb_frag_size(frag),
4050                                        DMA_TO_DEVICE);
4051                 if (dma_mapping_error(priv->device, des))
4052                         goto dma_map_err;
4053
4054                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4055                                      (i == nfrags - 1), queue);
4056
4057                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4058                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4059                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4060                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4061         }
4062
4063         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4064
4065         /* Only the last descriptor gets to point to the skb. */
4066         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4067         tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4068
4069         /* Manage tx mitigation */
4070         tx_packets = (tx_q->cur_tx + 1) - first_tx;
4071         tx_q->tx_count_frames += tx_packets;
4072
4073         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4074                 set_ic = true;
4075         else if (!priv->tx_coal_frames[queue])
4076                 set_ic = false;
4077         else if (tx_packets > priv->tx_coal_frames[queue])
4078                 set_ic = true;
4079         else if ((tx_q->tx_count_frames %
4080                   priv->tx_coal_frames[queue]) < tx_packets)
4081                 set_ic = true;
4082         else
4083                 set_ic = false;
4084
4085         if (set_ic) {
4086                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4087                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4088                 else
4089                         desc = &tx_q->dma_tx[tx_q->cur_tx];
4090
4091                 tx_q->tx_count_frames = 0;
4092                 stmmac_set_tx_ic(priv, desc);
4093                 priv->xstats.tx_set_ic_bit++;
4094         }
4095
4096         /* We've used all descriptors we need for this skb, however,
4097          * advance cur_tx so that it references a fresh descriptor.
4098          * ndo_start_xmit will fill this descriptor the next time it's
4099          * called and stmmac_tx_clean may clean up to this descriptor.
4100          */
4101         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
4102
4103         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4104                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4105                           __func__);
4106                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4107         }
4108
4109         dev->stats.tx_bytes += skb->len;
4110         priv->xstats.tx_tso_frames++;
4111         priv->xstats.tx_tso_nfrags += nfrags;
4112
4113         if (priv->sarc_type)
4114                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4115
4116         skb_tx_timestamp(skb);
4117
4118         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4119                      priv->hwts_tx_en)) {
4120                 /* declare that device is doing timestamping */
4121                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4122                 stmmac_enable_tx_timestamp(priv, first);
4123         }
4124
4125         /* Complete the first descriptor before granting the DMA */
4126         stmmac_prepare_tso_tx_desc(priv, first, 1,
4127                         proto_hdr_len,
4128                         pay_len,
4129                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4130                         hdr / 4, (skb->len - proto_hdr_len));
4131
4132         /* If context desc is used to change MSS */
4133         if (mss_desc) {
4134                 /* Make sure that first descriptor has been completely
4135                  * written, including its own bit. This is because MSS is
4136                  * actually before first descriptor, so we need to make
4137                  * sure that MSS's own bit is the last thing written.
4138                  */
4139                 dma_wmb();
4140                 stmmac_set_tx_owner(priv, mss_desc);
4141         }
4142
4143         if (netif_msg_pktdata(priv)) {
4144                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4145                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4146                         tx_q->cur_tx, first, nfrags);
4147                 pr_info(">>> frame to be transmitted: ");
4148                 print_pkt(skb->data, skb_headlen(skb));
4149         }
4150
4151         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4152
4153         stmmac_flush_tx_descriptors(priv, queue);
4154         stmmac_tx_timer_arm(priv, queue);
4155
4156         return NETDEV_TX_OK;
4157
4158 dma_map_err:
4159         dev_err(priv->device, "Tx dma map failed\n");
4160         dev_kfree_skb(skb);
4161         priv->dev->stats.tx_dropped++;
4162         return NETDEV_TX_OK;
4163 }
4164
4165 /**
4166  *  stmmac_xmit - Tx entry point of the driver
4167  *  @skb : the socket buffer
4168  *  @dev : device pointer
4169  *  Description : this is the tx entry point of the driver.
4170  *  It programs the chain or the ring and supports oversized frames
4171  *  and SG feature.
4172  */
4173 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4174 {
4175         unsigned int first_entry, tx_packets, enh_desc;
4176         struct stmmac_priv *priv = netdev_priv(dev);
4177         unsigned int nopaged_len = skb_headlen(skb);
4178         int i, csum_insertion = 0, is_jumbo = 0;
4179         u32 queue = skb_get_queue_mapping(skb);
4180         int nfrags = skb_shinfo(skb)->nr_frags;
4181         int gso = skb_shinfo(skb)->gso_type;
4182         struct dma_edesc *tbs_desc = NULL;
4183         struct dma_desc *desc, *first;
4184         struct stmmac_tx_queue *tx_q;
4185         bool has_vlan, set_ic;
4186         int entry, first_tx;
4187         dma_addr_t des;
4188
4189         tx_q = &priv->tx_queue[queue];
4190         first_tx = tx_q->cur_tx;
4191
4192         if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4193                 stmmac_disable_eee_mode(priv);
4194
4195         /* Manage oversized TCP frames for GMAC4 device */
4196         if (skb_is_gso(skb) && priv->tso) {
4197                 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4198                         return stmmac_tso_xmit(skb, dev);
4199                 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4200                         return stmmac_tso_xmit(skb, dev);
4201         }
4202
4203         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4204                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4205                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4206                                                                 queue));
4207                         /* This is a hard error, log it. */
4208                         netdev_err(priv->dev,
4209                                    "%s: Tx Ring full when queue awake\n",
4210                                    __func__);
4211                 }
4212                 return NETDEV_TX_BUSY;
4213         }
4214
4215         /* Check if VLAN can be inserted by HW */
4216         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4217
4218         entry = tx_q->cur_tx;
4219         first_entry = entry;
4220         WARN_ON(tx_q->tx_skbuff[first_entry]);
4221
4222         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4223
4224         if (likely(priv->extend_desc))
4225                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4226         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4227                 desc = &tx_q->dma_entx[entry].basic;
4228         else
4229                 desc = tx_q->dma_tx + entry;
4230
4231         first = desc;
4232
4233         if (has_vlan)
4234                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4235
4236         enh_desc = priv->plat->enh_desc;
4237         /* To program the descriptors according to the size of the frame */
4238         if (enh_desc)
4239                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4240
4241         if (unlikely(is_jumbo)) {
4242                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4243                 if (unlikely(entry < 0) && (entry != -EINVAL))
4244                         goto dma_map_err;
4245         }
4246
4247         for (i = 0; i < nfrags; i++) {
4248                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4249                 int len = skb_frag_size(frag);
4250                 bool last_segment = (i == (nfrags - 1));
4251
4252                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4253                 WARN_ON(tx_q->tx_skbuff[entry]);
4254
4255                 if (likely(priv->extend_desc))
4256                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4257                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4258                         desc = &tx_q->dma_entx[entry].basic;
4259                 else
4260                         desc = tx_q->dma_tx + entry;
4261
4262                 des = skb_frag_dma_map(priv->device, frag, 0, len,
4263                                        DMA_TO_DEVICE);
4264                 if (dma_mapping_error(priv->device, des))
4265                         goto dma_map_err; /* should reuse desc w/o issues */
4266
4267                 tx_q->tx_skbuff_dma[entry].buf = des;
4268
4269                 stmmac_set_desc_addr(priv, desc, des);
4270
4271                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4272                 tx_q->tx_skbuff_dma[entry].len = len;
4273                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4274                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4275
4276                 /* Prepare the descriptor and set the own bit too */
4277                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4278                                 priv->mode, 1, last_segment, skb->len);
4279         }
4280
4281         /* Only the last descriptor gets to point to the skb. */
4282         tx_q->tx_skbuff[entry] = skb;
4283         tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4284
4285         /* According to the coalesce parameter the IC bit for the latest
4286          * segment is reset and the timer re-started to clean the tx status.
4287          * This approach takes care about the fragments: desc is the first
4288          * element in case of no SG.
4289          */
4290         tx_packets = (entry + 1) - first_tx;
4291         tx_q->tx_count_frames += tx_packets;
4292
4293         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4294                 set_ic = true;
4295         else if (!priv->tx_coal_frames[queue])
4296                 set_ic = false;
4297         else if (tx_packets > priv->tx_coal_frames[queue])
4298                 set_ic = true;
4299         else if ((tx_q->tx_count_frames %
4300                   priv->tx_coal_frames[queue]) < tx_packets)
4301                 set_ic = true;
4302         else
4303                 set_ic = false;
4304
4305         if (set_ic) {
4306                 if (likely(priv->extend_desc))
4307                         desc = &tx_q->dma_etx[entry].basic;
4308                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4309                         desc = &tx_q->dma_entx[entry].basic;
4310                 else
4311                         desc = &tx_q->dma_tx[entry];
4312
4313                 tx_q->tx_count_frames = 0;
4314                 stmmac_set_tx_ic(priv, desc);
4315                 priv->xstats.tx_set_ic_bit++;
4316         }
4317
4318         /* We've used all descriptors we need for this skb, however,
4319          * advance cur_tx so that it references a fresh descriptor.
4320          * ndo_start_xmit will fill this descriptor the next time it's
4321          * called and stmmac_tx_clean may clean up to this descriptor.
4322          */
4323         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4324         tx_q->cur_tx = entry;
4325
4326         if (netif_msg_pktdata(priv)) {
4327                 netdev_dbg(priv->dev,
4328                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4329                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4330                            entry, first, nfrags);
4331
4332                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4333                 print_pkt(skb->data, skb->len);
4334         }
4335
4336         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4337                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4338                           __func__);
4339                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4340         }
4341
4342         dev->stats.tx_bytes += skb->len;
4343
4344         if (priv->sarc_type)
4345                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4346
4347         skb_tx_timestamp(skb);
4348
4349         /* Ready to fill the first descriptor and set the OWN bit w/o any
4350          * problems because all the descriptors are actually ready to be
4351          * passed to the DMA engine.
4352          */
4353         if (likely(!is_jumbo)) {
4354                 bool last_segment = (nfrags == 0);
4355
4356                 des = dma_map_single(priv->device, skb->data,
4357                                      nopaged_len, DMA_TO_DEVICE);
4358                 if (dma_mapping_error(priv->device, des))
4359                         goto dma_map_err;
4360
4361                 tx_q->tx_skbuff_dma[first_entry].buf = des;
4362                 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4363                 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4364
4365                 stmmac_set_desc_addr(priv, first, des);
4366
4367                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4368                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4369
4370                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4371                              priv->hwts_tx_en)) {
4372                         /* declare that device is doing timestamping */
4373                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4374                         stmmac_enable_tx_timestamp(priv, first);
4375                 }
4376
4377                 /* Prepare the first descriptor setting the OWN bit too */
4378                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4379                                 csum_insertion, priv->mode, 0, last_segment,
4380                                 skb->len);
4381         }
4382
4383         if (tx_q->tbs & STMMAC_TBS_EN) {
4384                 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4385
4386                 tbs_desc = &tx_q->dma_entx[first_entry];
4387                 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4388         }
4389
4390         stmmac_set_tx_owner(priv, first);
4391
4392         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4393
4394         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4395
4396         stmmac_flush_tx_descriptors(priv, queue);
4397         stmmac_tx_timer_arm(priv, queue);
4398
4399         return NETDEV_TX_OK;
4400
4401 dma_map_err:
4402         netdev_err(priv->dev, "Tx DMA map failed\n");
4403         dev_kfree_skb(skb);
4404         priv->dev->stats.tx_dropped++;
4405         return NETDEV_TX_OK;
4406 }
4407
4408 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4409 {
4410         struct vlan_ethhdr *veth;
4411         __be16 vlan_proto;
4412         u16 vlanid;
4413
4414         veth = (struct vlan_ethhdr *)skb->data;
4415         vlan_proto = veth->h_vlan_proto;
4416
4417         if ((vlan_proto == htons(ETH_P_8021Q) &&
4418              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4419             (vlan_proto == htons(ETH_P_8021AD) &&
4420              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4421                 /* pop the vlan tag */
4422                 vlanid = ntohs(veth->h_vlan_TCI);
4423                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4424                 skb_pull(skb, VLAN_HLEN);
4425                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4426         }
4427 }
4428
4429 /**
4430  * stmmac_rx_refill - refill used skb preallocated buffers
4431  * @priv: driver private structure
4432  * @queue: RX queue index
4433  * Description : this is to reallocate the skb for the reception process
4434  * that is based on zero-copy.
4435  */
4436 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4437 {
4438         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4439         int dirty = stmmac_rx_dirty(priv, queue);
4440         unsigned int entry = rx_q->dirty_rx;
4441
4442         while (dirty-- > 0) {
4443                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4444                 struct dma_desc *p;
4445                 bool use_rx_wd;
4446
4447                 if (priv->extend_desc)
4448                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4449                 else
4450                         p = rx_q->dma_rx + entry;
4451
4452                 if (!buf->page) {
4453                         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
4454                         if (!buf->page)
4455                                 break;
4456                 }
4457
4458                 if (priv->sph && !buf->sec_page) {
4459                         buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
4460                         if (!buf->sec_page)
4461                                 break;
4462
4463                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4464                 }
4465
4466                 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4467
4468                 stmmac_set_desc_addr(priv, p, buf->addr);
4469                 if (priv->sph)
4470                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4471                 else
4472                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4473                 stmmac_refill_desc3(priv, rx_q, p);
4474
4475                 rx_q->rx_count_frames++;
4476                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4477                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4478                         rx_q->rx_count_frames = 0;
4479
4480                 use_rx_wd = !priv->rx_coal_frames[queue];
4481                 use_rx_wd |= rx_q->rx_count_frames > 0;
4482                 if (!priv->use_riwt)
4483                         use_rx_wd = false;
4484
4485                 dma_wmb();
4486                 stmmac_set_rx_owner(priv, p, use_rx_wd);
4487
4488                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4489         }
4490         rx_q->dirty_rx = entry;
4491         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4492                             (rx_q->dirty_rx * sizeof(struct dma_desc));
4493         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4494 }
4495
4496 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4497                                        struct dma_desc *p,
4498                                        int status, unsigned int len)
4499 {
4500         unsigned int plen = 0, hlen = 0;
4501         int coe = priv->hw->rx_csum;
4502
4503         /* Not first descriptor, buffer is always zero */
4504         if (priv->sph && len)
4505                 return 0;
4506
4507         /* First descriptor, get split header length */
4508         stmmac_get_rx_header_len(priv, p, &hlen);
4509         if (priv->sph && hlen) {
4510                 priv->xstats.rx_split_hdr_pkt_n++;
4511                 return hlen;
4512         }
4513
4514         /* First descriptor, not last descriptor and not split header */
4515         if (status & rx_not_ls)
4516                 return priv->dma_buf_sz;
4517
4518         plen = stmmac_get_rx_frame_len(priv, p, coe);
4519
4520         /* First descriptor and last descriptor and not split header */
4521         return min_t(unsigned int, priv->dma_buf_sz, plen);
4522 }
4523
4524 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4525                                        struct dma_desc *p,
4526                                        int status, unsigned int len)
4527 {
4528         int coe = priv->hw->rx_csum;
4529         unsigned int plen = 0;
4530
4531         /* Not split header, buffer is not available */
4532         if (!priv->sph)
4533                 return 0;
4534
4535         /* Not last descriptor */
4536         if (status & rx_not_ls)
4537                 return priv->dma_buf_sz;
4538
4539         plen = stmmac_get_rx_frame_len(priv, p, coe);
4540
4541         /* Last descriptor */
4542         return plen - len;
4543 }
4544
4545 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4546                                 struct xdp_frame *xdpf, bool dma_map)
4547 {
4548         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4549         unsigned int entry = tx_q->cur_tx;
4550         struct dma_desc *tx_desc;
4551         dma_addr_t dma_addr;
4552         bool set_ic;
4553
4554         if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4555                 return STMMAC_XDP_CONSUMED;
4556
4557         if (likely(priv->extend_desc))
4558                 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4559         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4560                 tx_desc = &tx_q->dma_entx[entry].basic;
4561         else
4562                 tx_desc = tx_q->dma_tx + entry;
4563
4564         if (dma_map) {
4565                 dma_addr = dma_map_single(priv->device, xdpf->data,
4566                                           xdpf->len, DMA_TO_DEVICE);
4567                 if (dma_mapping_error(priv->device, dma_addr))
4568                         return STMMAC_XDP_CONSUMED;
4569
4570                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4571         } else {
4572                 struct page *page = virt_to_page(xdpf->data);
4573
4574                 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4575                            xdpf->headroom;
4576                 dma_sync_single_for_device(priv->device, dma_addr,
4577                                            xdpf->len, DMA_BIDIRECTIONAL);
4578
4579                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4580         }
4581
4582         tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4583         tx_q->tx_skbuff_dma[entry].map_as_page = false;
4584         tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4585         tx_q->tx_skbuff_dma[entry].last_segment = true;
4586         tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4587
4588         tx_q->xdpf[entry] = xdpf;
4589
4590         stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4591
4592         stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4593                                true, priv->mode, true, true,
4594                                xdpf->len);
4595
4596         tx_q->tx_count_frames++;
4597
4598         if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4599                 set_ic = true;
4600         else
4601                 set_ic = false;
4602
4603         if (set_ic) {
4604                 tx_q->tx_count_frames = 0;
4605                 stmmac_set_tx_ic(priv, tx_desc);
4606                 priv->xstats.tx_set_ic_bit++;
4607         }
4608
4609         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4610
4611         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4612         tx_q->cur_tx = entry;
4613
4614         return STMMAC_XDP_TX;
4615 }
4616
4617 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4618                                    int cpu)
4619 {
4620         int index = cpu;
4621
4622         if (unlikely(index < 0))
4623                 index = 0;
4624
4625         while (index >= priv->plat->tx_queues_to_use)
4626                 index -= priv->plat->tx_queues_to_use;
4627
4628         return index;
4629 }
4630
4631 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4632                                 struct xdp_buff *xdp)
4633 {
4634         struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4635         int cpu = smp_processor_id();
4636         struct netdev_queue *nq;
4637         int queue;
4638         int res;
4639
4640         if (unlikely(!xdpf))
4641                 return STMMAC_XDP_CONSUMED;
4642
4643         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4644         nq = netdev_get_tx_queue(priv->dev, queue);
4645
4646         __netif_tx_lock(nq, cpu);
4647         /* Avoids TX time-out as we are sharing with slow path */
4648         nq->trans_start = jiffies;
4649
4650         res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4651         if (res == STMMAC_XDP_TX)
4652                 stmmac_flush_tx_descriptors(priv, queue);
4653
4654         __netif_tx_unlock(nq);
4655
4656         return res;
4657 }
4658
4659 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4660                                  struct bpf_prog *prog,
4661                                  struct xdp_buff *xdp)
4662 {
4663         u32 act;
4664         int res;
4665
4666         act = bpf_prog_run_xdp(prog, xdp);
4667         switch (act) {
4668         case XDP_PASS:
4669                 res = STMMAC_XDP_PASS;
4670                 break;
4671         case XDP_TX:
4672                 res = stmmac_xdp_xmit_back(priv, xdp);
4673                 break;
4674         case XDP_REDIRECT:
4675                 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4676                         res = STMMAC_XDP_CONSUMED;
4677                 else
4678                         res = STMMAC_XDP_REDIRECT;
4679                 break;
4680         default:
4681                 bpf_warn_invalid_xdp_action(act);
4682                 fallthrough;
4683         case XDP_ABORTED:
4684                 trace_xdp_exception(priv->dev, prog, act);
4685                 fallthrough;
4686         case XDP_DROP:
4687                 res = STMMAC_XDP_CONSUMED;
4688                 break;
4689         }
4690
4691         return res;
4692 }
4693
4694 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4695                                            struct xdp_buff *xdp)
4696 {
4697         struct bpf_prog *prog;
4698         int res;
4699
4700         prog = READ_ONCE(priv->xdp_prog);
4701         if (!prog) {
4702                 res = STMMAC_XDP_PASS;
4703                 goto out;
4704         }
4705
4706         res = __stmmac_xdp_run_prog(priv, prog, xdp);
4707 out:
4708         return ERR_PTR(-res);
4709 }
4710
4711 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4712                                    int xdp_status)
4713 {
4714         int cpu = smp_processor_id();
4715         int queue;
4716
4717         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4718
4719         if (xdp_status & STMMAC_XDP_TX)
4720                 stmmac_tx_timer_arm(priv, queue);
4721
4722         if (xdp_status & STMMAC_XDP_REDIRECT)
4723                 xdp_do_flush();
4724 }
4725
4726 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4727                                                struct xdp_buff *xdp)
4728 {
4729         unsigned int metasize = xdp->data - xdp->data_meta;
4730         unsigned int datasize = xdp->data_end - xdp->data;
4731         struct sk_buff *skb;
4732
4733         skb = __napi_alloc_skb(&ch->rxtx_napi,
4734                                xdp->data_end - xdp->data_hard_start,
4735                                GFP_ATOMIC | __GFP_NOWARN);
4736         if (unlikely(!skb))
4737                 return NULL;
4738
4739         skb_reserve(skb, xdp->data - xdp->data_hard_start);
4740         memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4741         if (metasize)
4742                 skb_metadata_set(skb, metasize);
4743
4744         return skb;
4745 }
4746
4747 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4748                                    struct dma_desc *p, struct dma_desc *np,
4749                                    struct xdp_buff *xdp)
4750 {
4751         struct stmmac_channel *ch = &priv->channel[queue];
4752         unsigned int len = xdp->data_end - xdp->data;
4753         enum pkt_hash_types hash_type;
4754         int coe = priv->hw->rx_csum;
4755         struct sk_buff *skb;
4756         u32 hash;
4757
4758         skb = stmmac_construct_skb_zc(ch, xdp);
4759         if (!skb) {
4760                 priv->dev->stats.rx_dropped++;
4761                 return;
4762         }
4763
4764         stmmac_get_rx_hwtstamp(priv, p, np, skb);
4765         stmmac_rx_vlan(priv->dev, skb);
4766         skb->protocol = eth_type_trans(skb, priv->dev);
4767
4768         if (unlikely(!coe))
4769                 skb_checksum_none_assert(skb);
4770         else
4771                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4772
4773         if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4774                 skb_set_hash(skb, hash, hash_type);
4775
4776         skb_record_rx_queue(skb, queue);
4777         napi_gro_receive(&ch->rxtx_napi, skb);
4778
4779         priv->dev->stats.rx_packets++;
4780         priv->dev->stats.rx_bytes += len;
4781 }
4782
4783 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4784 {
4785         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4786         unsigned int entry = rx_q->dirty_rx;
4787         struct dma_desc *rx_desc = NULL;
4788         bool ret = true;
4789
4790         budget = min(budget, stmmac_rx_dirty(priv, queue));
4791
4792         while (budget-- > 0 && entry != rx_q->cur_rx) {
4793                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4794                 dma_addr_t dma_addr;
4795                 bool use_rx_wd;
4796
4797                 if (!buf->xdp) {
4798                         buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4799                         if (!buf->xdp) {
4800                                 ret = false;
4801                                 break;
4802                         }
4803                 }
4804
4805                 if (priv->extend_desc)
4806                         rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4807                 else
4808                         rx_desc = rx_q->dma_rx + entry;
4809
4810                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4811                 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4812                 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4813                 stmmac_refill_desc3(priv, rx_q, rx_desc);
4814
4815                 rx_q->rx_count_frames++;
4816                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4817                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4818                         rx_q->rx_count_frames = 0;
4819
4820                 use_rx_wd = !priv->rx_coal_frames[queue];
4821                 use_rx_wd |= rx_q->rx_count_frames > 0;
4822                 if (!priv->use_riwt)
4823                         use_rx_wd = false;
4824
4825                 dma_wmb();
4826                 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4827
4828                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4829         }
4830
4831         if (rx_desc) {
4832                 rx_q->dirty_rx = entry;
4833                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4834                                      (rx_q->dirty_rx * sizeof(struct dma_desc));
4835                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4836         }
4837
4838         return ret;
4839 }
4840
4841 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
4842 {
4843         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4844         unsigned int count = 0, error = 0, len = 0;
4845         int dirty = stmmac_rx_dirty(priv, queue);
4846         unsigned int next_entry = rx_q->cur_rx;
4847         unsigned int desc_size;
4848         struct bpf_prog *prog;
4849         bool failure = false;
4850         int xdp_status = 0;
4851         int status = 0;
4852
4853         if (netif_msg_rx_status(priv)) {
4854                 void *rx_head;
4855
4856                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
4857                 if (priv->extend_desc) {
4858                         rx_head = (void *)rx_q->dma_erx;
4859                         desc_size = sizeof(struct dma_extended_desc);
4860                 } else {
4861                         rx_head = (void *)rx_q->dma_rx;
4862                         desc_size = sizeof(struct dma_desc);
4863                 }
4864
4865                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
4866                                     rx_q->dma_rx_phy, desc_size);
4867         }
4868         while (count < limit) {
4869                 struct stmmac_rx_buffer *buf;
4870                 unsigned int buf1_len = 0;
4871                 struct dma_desc *np, *p;
4872                 int entry;
4873                 int res;
4874
4875                 if (!count && rx_q->state_saved) {
4876                         error = rx_q->state.error;
4877                         len = rx_q->state.len;
4878                 } else {
4879                         rx_q->state_saved = false;
4880                         error = 0;
4881                         len = 0;
4882                 }
4883
4884                 if (count >= limit)
4885                         break;
4886
4887 read_again:
4888                 buf1_len = 0;
4889                 entry = next_entry;
4890                 buf = &rx_q->buf_pool[entry];
4891
4892                 if (dirty >= STMMAC_RX_FILL_BATCH) {
4893                         failure = failure ||
4894                                   !stmmac_rx_refill_zc(priv, queue, dirty);
4895                         dirty = 0;
4896                 }
4897
4898                 if (priv->extend_desc)
4899                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4900                 else
4901                         p = rx_q->dma_rx + entry;
4902
4903                 /* read the status of the incoming frame */
4904                 status = stmmac_rx_status(priv, &priv->dev->stats,
4905                                           &priv->xstats, p);
4906                 /* check if managed by the DMA otherwise go ahead */
4907                 if (unlikely(status & dma_own))
4908                         break;
4909
4910                 /* Prefetch the next RX descriptor */
4911                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
4912                                                 priv->dma_rx_size);
4913                 next_entry = rx_q->cur_rx;
4914
4915                 if (priv->extend_desc)
4916                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
4917                 else
4918                         np = rx_q->dma_rx + next_entry;
4919
4920                 prefetch(np);
4921
4922                 /* Ensure a valid XSK buffer before proceed */
4923                 if (!buf->xdp)
4924                         break;
4925
4926                 if (priv->extend_desc)
4927                         stmmac_rx_extended_status(priv, &priv->dev->stats,
4928                                                   &priv->xstats,
4929                                                   rx_q->dma_erx + entry);
4930                 if (unlikely(status == discard_frame)) {
4931                         xsk_buff_free(buf->xdp);
4932                         buf->xdp = NULL;
4933                         dirty++;
4934                         error = 1;
4935                         if (!priv->hwts_rx_en)
4936                                 priv->dev->stats.rx_errors++;
4937                 }
4938
4939                 if (unlikely(error && (status & rx_not_ls)))
4940                         goto read_again;
4941                 if (unlikely(error)) {
4942                         count++;
4943                         continue;
4944                 }
4945
4946                 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
4947                 if (likely(status & rx_not_ls)) {
4948                         xsk_buff_free(buf->xdp);
4949                         buf->xdp = NULL;
4950                         dirty++;
4951                         count++;
4952                         goto read_again;
4953                 }
4954
4955                 /* XDP ZC Frame only support primary buffers for now */
4956                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
4957                 len += buf1_len;
4958
4959                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
4960                  * Type frames (LLC/LLC-SNAP)
4961                  *
4962                  * llc_snap is never checked in GMAC >= 4, so this ACS
4963                  * feature is always disabled and packets need to be
4964                  * stripped manually.
4965                  */
4966                 if (likely(!(status & rx_not_ls)) &&
4967                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
4968                      unlikely(status != llc_snap))) {
4969                         buf1_len -= ETH_FCS_LEN;
4970                         len -= ETH_FCS_LEN;
4971                 }
4972
4973                 /* RX buffer is good and fit into a XSK pool buffer */
4974                 buf->xdp->data_end = buf->xdp->data + buf1_len;
4975                 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
4976
4977                 prog = READ_ONCE(priv->xdp_prog);
4978                 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
4979
4980                 switch (res) {
4981                 case STMMAC_XDP_PASS:
4982                         stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
4983                         xsk_buff_free(buf->xdp);
4984                         break;
4985                 case STMMAC_XDP_CONSUMED:
4986                         xsk_buff_free(buf->xdp);
4987                         priv->dev->stats.rx_dropped++;
4988                         break;
4989                 case STMMAC_XDP_TX:
4990                 case STMMAC_XDP_REDIRECT:
4991                         xdp_status |= res;
4992                         break;
4993                 }
4994
4995                 buf->xdp = NULL;
4996                 dirty++;
4997                 count++;
4998         }
4999
5000         if (status & rx_not_ls) {
5001                 rx_q->state_saved = true;
5002                 rx_q->state.error = error;
5003                 rx_q->state.len = len;
5004         }
5005
5006         stmmac_finalize_xdp_rx(priv, xdp_status);
5007
5008         priv->xstats.rx_pkt_n += count;
5009         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5010
5011         if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5012                 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5013                         xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5014                 else
5015                         xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5016
5017                 return (int)count;
5018         }
5019
5020         return failure ? limit : (int)count;
5021 }
5022
5023 /**
5024  * stmmac_rx - manage the receive process
5025  * @priv: driver private structure
5026  * @limit: napi bugget
5027  * @queue: RX queue index.
5028  * Description :  this the function called by the napi poll method.
5029  * It gets all the frames inside the ring.
5030  */
5031 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5032 {
5033         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5034         struct stmmac_channel *ch = &priv->channel[queue];
5035         unsigned int count = 0, error = 0, len = 0;
5036         int status = 0, coe = priv->hw->rx_csum;
5037         unsigned int next_entry = rx_q->cur_rx;
5038         enum dma_data_direction dma_dir;
5039         unsigned int desc_size;
5040         struct sk_buff *skb = NULL;
5041         struct xdp_buff xdp;
5042         int xdp_status = 0;
5043         int buf_sz;
5044
5045         dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5046         buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5047
5048         if (netif_msg_rx_status(priv)) {
5049                 void *rx_head;
5050
5051                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5052                 if (priv->extend_desc) {
5053                         rx_head = (void *)rx_q->dma_erx;
5054                         desc_size = sizeof(struct dma_extended_desc);
5055                 } else {
5056                         rx_head = (void *)rx_q->dma_rx;
5057                         desc_size = sizeof(struct dma_desc);
5058                 }
5059
5060                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
5061                                     rx_q->dma_rx_phy, desc_size);
5062         }
5063         while (count < limit) {
5064                 unsigned int buf1_len = 0, buf2_len = 0;
5065                 enum pkt_hash_types hash_type;
5066                 struct stmmac_rx_buffer *buf;
5067                 struct dma_desc *np, *p;
5068                 int entry;
5069                 u32 hash;
5070
5071                 if (!count && rx_q->state_saved) {
5072                         skb = rx_q->state.skb;
5073                         error = rx_q->state.error;
5074                         len = rx_q->state.len;
5075                 } else {
5076                         rx_q->state_saved = false;
5077                         skb = NULL;
5078                         error = 0;
5079                         len = 0;
5080                 }
5081
5082                 if (count >= limit)
5083                         break;
5084
5085 read_again:
5086                 buf1_len = 0;
5087                 buf2_len = 0;
5088                 entry = next_entry;
5089                 buf = &rx_q->buf_pool[entry];
5090
5091                 if (priv->extend_desc)
5092                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
5093                 else
5094                         p = rx_q->dma_rx + entry;
5095
5096                 /* read the status of the incoming frame */
5097                 status = stmmac_rx_status(priv, &priv->dev->stats,
5098                                 &priv->xstats, p);
5099                 /* check if managed by the DMA otherwise go ahead */
5100                 if (unlikely(status & dma_own))
5101                         break;
5102
5103                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5104                                                 priv->dma_rx_size);
5105                 next_entry = rx_q->cur_rx;
5106
5107                 if (priv->extend_desc)
5108                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5109                 else
5110                         np = rx_q->dma_rx + next_entry;
5111
5112                 prefetch(np);
5113
5114                 if (priv->extend_desc)
5115                         stmmac_rx_extended_status(priv, &priv->dev->stats,
5116                                         &priv->xstats, rx_q->dma_erx + entry);
5117                 if (unlikely(status == discard_frame)) {
5118                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5119                         buf->page = NULL;
5120                         error = 1;
5121                         if (!priv->hwts_rx_en)
5122                                 priv->dev->stats.rx_errors++;
5123                 }
5124
5125                 if (unlikely(error && (status & rx_not_ls)))
5126                         goto read_again;
5127                 if (unlikely(error)) {
5128                         dev_kfree_skb(skb);
5129                         skb = NULL;
5130                         count++;
5131                         continue;
5132                 }
5133
5134                 /* Buffer is good. Go on. */
5135
5136                 prefetch(page_address(buf->page) + buf->page_offset);
5137                 if (buf->sec_page)
5138                         prefetch(page_address(buf->sec_page));
5139
5140                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5141                 len += buf1_len;
5142                 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5143                 len += buf2_len;
5144
5145                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5146                  * Type frames (LLC/LLC-SNAP)
5147                  *
5148                  * llc_snap is never checked in GMAC >= 4, so this ACS
5149                  * feature is always disabled and packets need to be
5150                  * stripped manually.
5151                  */
5152                 if (likely(!(status & rx_not_ls)) &&
5153                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5154                      unlikely(status != llc_snap))) {
5155                         if (buf2_len)
5156                                 buf2_len -= ETH_FCS_LEN;
5157                         else
5158                                 buf1_len -= ETH_FCS_LEN;
5159
5160                         len -= ETH_FCS_LEN;
5161                 }
5162
5163                 if (!skb) {
5164                         unsigned int pre_len, sync_len;
5165
5166                         dma_sync_single_for_cpu(priv->device, buf->addr,
5167                                                 buf1_len, dma_dir);
5168
5169                         xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq);
5170                         xdp_prepare_buff(&xdp, page_address(buf->page),
5171                                          buf->page_offset, buf1_len, false);
5172
5173                         pre_len = xdp.data_end - xdp.data_hard_start -
5174                                   buf->page_offset;
5175                         skb = stmmac_xdp_run_prog(priv, &xdp);
5176                         /* Due xdp_adjust_tail: DMA sync for_device
5177                          * cover max len CPU touch
5178                          */
5179                         sync_len = xdp.data_end - xdp.data_hard_start -
5180                                    buf->page_offset;
5181                         sync_len = max(sync_len, pre_len);
5182
5183                         /* For Not XDP_PASS verdict */
5184                         if (IS_ERR(skb)) {
5185                                 unsigned int xdp_res = -PTR_ERR(skb);
5186
5187                                 if (xdp_res & STMMAC_XDP_CONSUMED) {
5188                                         page_pool_put_page(rx_q->page_pool,
5189                                                            virt_to_head_page(xdp.data),
5190                                                            sync_len, true);
5191                                         buf->page = NULL;
5192                                         priv->dev->stats.rx_dropped++;
5193
5194                                         /* Clear skb as it was set as
5195                                          * status by XDP program.
5196                                          */
5197                                         skb = NULL;
5198
5199                                         if (unlikely((status & rx_not_ls)))
5200                                                 goto read_again;
5201
5202                                         count++;
5203                                         continue;
5204                                 } else if (xdp_res & (STMMAC_XDP_TX |
5205                                                       STMMAC_XDP_REDIRECT)) {
5206                                         xdp_status |= xdp_res;
5207                                         buf->page = NULL;
5208                                         skb = NULL;
5209                                         count++;
5210                                         continue;
5211                                 }
5212                         }
5213                 }
5214
5215                 if (!skb) {
5216                         /* XDP program may expand or reduce tail */
5217                         buf1_len = xdp.data_end - xdp.data;
5218
5219                         skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5220                         if (!skb) {
5221                                 priv->dev->stats.rx_dropped++;
5222                                 count++;
5223                                 goto drain_data;
5224                         }
5225
5226                         /* XDP program may adjust header */
5227                         skb_copy_to_linear_data(skb, xdp.data, buf1_len);
5228                         skb_put(skb, buf1_len);
5229
5230                         /* Data payload copied into SKB, page ready for recycle */
5231                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5232                         buf->page = NULL;
5233                 } else if (buf1_len) {
5234                         dma_sync_single_for_cpu(priv->device, buf->addr,
5235                                                 buf1_len, dma_dir);
5236                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5237                                         buf->page, buf->page_offset, buf1_len,
5238                                         priv->dma_buf_sz);
5239
5240                         /* Data payload appended into SKB */
5241                         page_pool_release_page(rx_q->page_pool, buf->page);
5242                         buf->page = NULL;
5243                 }
5244
5245                 if (buf2_len) {
5246                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5247                                                 buf2_len, dma_dir);
5248                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5249                                         buf->sec_page, 0, buf2_len,
5250                                         priv->dma_buf_sz);
5251
5252                         /* Data payload appended into SKB */
5253                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
5254                         buf->sec_page = NULL;
5255                 }
5256
5257 drain_data:
5258                 if (likely(status & rx_not_ls))
5259                         goto read_again;
5260                 if (!skb)
5261                         continue;
5262
5263                 /* Got entire packet into SKB. Finish it. */
5264
5265                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5266                 stmmac_rx_vlan(priv->dev, skb);
5267                 skb->protocol = eth_type_trans(skb, priv->dev);
5268
5269                 if (unlikely(!coe))
5270                         skb_checksum_none_assert(skb);
5271                 else
5272                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5273
5274                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5275                         skb_set_hash(skb, hash, hash_type);
5276
5277                 skb_record_rx_queue(skb, queue);
5278                 napi_gro_receive(&ch->rx_napi, skb);
5279                 skb = NULL;
5280
5281                 priv->dev->stats.rx_packets++;
5282                 priv->dev->stats.rx_bytes += len;
5283                 count++;
5284         }
5285
5286         if (status & rx_not_ls || skb) {
5287                 rx_q->state_saved = true;
5288                 rx_q->state.skb = skb;
5289                 rx_q->state.error = error;
5290                 rx_q->state.len = len;
5291         }
5292
5293         stmmac_finalize_xdp_rx(priv, xdp_status);
5294
5295         stmmac_rx_refill(priv, queue);
5296
5297         priv->xstats.rx_pkt_n += count;
5298         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5299
5300         return count;
5301 }
5302
5303 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5304 {
5305         struct stmmac_channel *ch =
5306                 container_of(napi, struct stmmac_channel, rx_napi);
5307         struct stmmac_priv *priv = ch->priv_data;
5308         u32 chan = ch->index;
5309         int work_done;
5310
5311         priv->xstats.napi_poll++;
5312
5313         work_done = stmmac_rx(priv, budget, chan);
5314         if (work_done < budget && napi_complete_done(napi, work_done)) {
5315                 unsigned long flags;
5316
5317                 spin_lock_irqsave(&ch->lock, flags);
5318                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5319                 spin_unlock_irqrestore(&ch->lock, flags);
5320         }
5321
5322         return work_done;
5323 }
5324
5325 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5326 {
5327         struct stmmac_channel *ch =
5328                 container_of(napi, struct stmmac_channel, tx_napi);
5329         struct stmmac_priv *priv = ch->priv_data;
5330         u32 chan = ch->index;
5331         int work_done;
5332
5333         priv->xstats.napi_poll++;
5334
5335         work_done = stmmac_tx_clean(priv, budget, chan);
5336         work_done = min(work_done, budget);
5337
5338         if (work_done < budget && napi_complete_done(napi, work_done)) {
5339                 unsigned long flags;
5340
5341                 spin_lock_irqsave(&ch->lock, flags);
5342                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5343                 spin_unlock_irqrestore(&ch->lock, flags);
5344         }
5345
5346         return work_done;
5347 }
5348
5349 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5350 {
5351         struct stmmac_channel *ch =
5352                 container_of(napi, struct stmmac_channel, rxtx_napi);
5353         struct stmmac_priv *priv = ch->priv_data;
5354         int rx_done, tx_done, rxtx_done;
5355         u32 chan = ch->index;
5356
5357         priv->xstats.napi_poll++;
5358
5359         tx_done = stmmac_tx_clean(priv, budget, chan);
5360         tx_done = min(tx_done, budget);
5361
5362         rx_done = stmmac_rx_zc(priv, budget, chan);
5363
5364         rxtx_done = max(tx_done, rx_done);
5365
5366         /* If either TX or RX work is not complete, return budget
5367          * and keep pooling
5368          */
5369         if (rxtx_done >= budget)
5370                 return budget;
5371
5372         /* all work done, exit the polling mode */
5373         if (napi_complete_done(napi, rxtx_done)) {
5374                 unsigned long flags;
5375
5376                 spin_lock_irqsave(&ch->lock, flags);
5377                 /* Both RX and TX work done are compelte,
5378                  * so enable both RX & TX IRQs.
5379                  */
5380                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5381                 spin_unlock_irqrestore(&ch->lock, flags);
5382         }
5383
5384         return min(rxtx_done, budget - 1);
5385 }
5386
5387 /**
5388  *  stmmac_tx_timeout
5389  *  @dev : Pointer to net device structure
5390  *  @txqueue: the index of the hanging transmit queue
5391  *  Description: this function is called when a packet transmission fails to
5392  *   complete within a reasonable time. The driver will mark the error in the
5393  *   netdev structure and arrange for the device to be reset to a sane state
5394  *   in order to transmit a new packet.
5395  */
5396 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5397 {
5398         struct stmmac_priv *priv = netdev_priv(dev);
5399
5400         stmmac_global_err(priv);
5401 }
5402
5403 /**
5404  *  stmmac_set_rx_mode - entry point for multicast addressing
5405  *  @dev : pointer to the device structure
5406  *  Description:
5407  *  This function is a driver entry point which gets called by the kernel
5408  *  whenever multicast addresses must be enabled/disabled.
5409  *  Return value:
5410  *  void.
5411  */
5412 static void stmmac_set_rx_mode(struct net_device *dev)
5413 {
5414         struct stmmac_priv *priv = netdev_priv(dev);
5415
5416         stmmac_set_filter(priv, priv->hw, dev);
5417 }
5418
5419 /**
5420  *  stmmac_change_mtu - entry point to change MTU size for the device.
5421  *  @dev : device pointer.
5422  *  @new_mtu : the new MTU size for the device.
5423  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
5424  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
5425  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
5426  *  Return value:
5427  *  0 on success and an appropriate (-)ve integer as defined in errno.h
5428  *  file on failure.
5429  */
5430 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5431 {
5432         struct stmmac_priv *priv = netdev_priv(dev);
5433         int txfifosz = priv->plat->tx_fifo_size;
5434         const int mtu = new_mtu;
5435
5436         if (txfifosz == 0)
5437                 txfifosz = priv->dma_cap.tx_fifo_size;
5438
5439         txfifosz /= priv->plat->tx_queues_to_use;
5440
5441         if (netif_running(dev)) {
5442                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
5443                 return -EBUSY;
5444         }
5445
5446         if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5447                 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5448                 return -EINVAL;
5449         }
5450
5451         new_mtu = STMMAC_ALIGN(new_mtu);
5452
5453         /* If condition true, FIFO is too small or MTU too large */
5454         if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5455                 return -EINVAL;
5456
5457         dev->mtu = mtu;
5458
5459         netdev_update_features(dev);
5460
5461         return 0;
5462 }
5463
5464 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5465                                              netdev_features_t features)
5466 {
5467         struct stmmac_priv *priv = netdev_priv(dev);
5468
5469         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5470                 features &= ~NETIF_F_RXCSUM;
5471
5472         if (!priv->plat->tx_coe)
5473                 features &= ~NETIF_F_CSUM_MASK;
5474
5475         /* Some GMAC devices have a bugged Jumbo frame support that
5476          * needs to have the Tx COE disabled for oversized frames
5477          * (due to limited buffer sizes). In this case we disable
5478          * the TX csum insertion in the TDES and not use SF.
5479          */
5480         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5481                 features &= ~NETIF_F_CSUM_MASK;
5482
5483         /* Disable tso if asked by ethtool */
5484         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
5485                 if (features & NETIF_F_TSO)
5486                         priv->tso = true;
5487                 else
5488                         priv->tso = false;
5489         }
5490
5491         return features;
5492 }
5493
5494 static int stmmac_set_features(struct net_device *netdev,
5495                                netdev_features_t features)
5496 {
5497         struct stmmac_priv *priv = netdev_priv(netdev);
5498         bool sph_en;
5499         u32 chan;
5500
5501         /* Keep the COE Type in case of csum is supporting */
5502         if (features & NETIF_F_RXCSUM)
5503                 priv->hw->rx_csum = priv->plat->rx_coe;
5504         else
5505                 priv->hw->rx_csum = 0;
5506         /* No check needed because rx_coe has been set before and it will be
5507          * fixed in case of issue.
5508          */
5509         stmmac_rx_ipc(priv, priv->hw);
5510
5511         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5512
5513         for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5514                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5515
5516         return 0;
5517 }
5518
5519 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5520 {
5521         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5522         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5523         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5524         bool *hs_enable = &fpe_cfg->hs_enable;
5525
5526         if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5527                 return;
5528
5529         /* If LP has sent verify mPacket, LP is FPE capable */
5530         if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5531                 if (*lp_state < FPE_STATE_CAPABLE)
5532                         *lp_state = FPE_STATE_CAPABLE;
5533
5534                 /* If user has requested FPE enable, quickly response */
5535                 if (*hs_enable)
5536                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5537                                                 MPACKET_RESPONSE);
5538         }
5539
5540         /* If Local has sent verify mPacket, Local is FPE capable */
5541         if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5542                 if (*lo_state < FPE_STATE_CAPABLE)
5543                         *lo_state = FPE_STATE_CAPABLE;
5544         }
5545
5546         /* If LP has sent response mPacket, LP is entering FPE ON */
5547         if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5548                 *lp_state = FPE_STATE_ENTERING_ON;
5549
5550         /* If Local has sent response mPacket, Local is entering FPE ON */
5551         if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5552                 *lo_state = FPE_STATE_ENTERING_ON;
5553
5554         if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5555             !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5556             priv->fpe_wq) {
5557                 queue_work(priv->fpe_wq, &priv->fpe_task);
5558         }
5559 }
5560
5561 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5562 {
5563         u32 rx_cnt = priv->plat->rx_queues_to_use;
5564         u32 tx_cnt = priv->plat->tx_queues_to_use;
5565         u32 queues_count;
5566         u32 queue;
5567         bool xmac;
5568
5569         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5570         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5571
5572         if (priv->irq_wake)
5573                 pm_wakeup_event(priv->device, 0);
5574
5575         if (priv->dma_cap.estsel)
5576                 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5577                                       &priv->xstats, tx_cnt);
5578
5579         if (priv->dma_cap.fpesel) {
5580                 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5581                                                    priv->dev);
5582
5583                 stmmac_fpe_event_status(priv, status);
5584         }
5585
5586         /* To handle GMAC own interrupts */
5587         if ((priv->plat->has_gmac) || xmac) {
5588                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5589
5590                 if (unlikely(status)) {
5591                         /* For LPI we need to save the tx status */
5592                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5593                                 priv->tx_path_in_lpi_mode = true;
5594                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5595                                 priv->tx_path_in_lpi_mode = false;
5596                 }
5597
5598                 for (queue = 0; queue < queues_count; queue++) {
5599                         status = stmmac_host_mtl_irq_status(priv, priv->hw,
5600                                                             queue);
5601                 }
5602
5603                 /* PCS link status */
5604                 if (priv->hw->pcs) {
5605                         if (priv->xstats.pcs_link)
5606                                 netif_carrier_on(priv->dev);
5607                         else
5608                                 netif_carrier_off(priv->dev);
5609                 }
5610
5611                 stmmac_timestamp_interrupt(priv, priv);
5612         }
5613 }
5614
5615 /**
5616  *  stmmac_interrupt - main ISR
5617  *  @irq: interrupt number.
5618  *  @dev_id: to pass the net device pointer.
5619  *  Description: this is the main driver interrupt service routine.
5620  *  It can call:
5621  *  o DMA service routine (to manage incoming frame reception and transmission
5622  *    status)
5623  *  o Core interrupts to manage: remote wake-up, management counter, LPI
5624  *    interrupts.
5625  */
5626 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5627 {
5628         struct net_device *dev = (struct net_device *)dev_id;
5629         struct stmmac_priv *priv = netdev_priv(dev);
5630
5631         /* Check if adapter is up */
5632         if (test_bit(STMMAC_DOWN, &priv->state))
5633                 return IRQ_HANDLED;
5634
5635         /* Check if a fatal error happened */
5636         if (stmmac_safety_feat_interrupt(priv))
5637                 return IRQ_HANDLED;
5638
5639         /* To handle Common interrupts */
5640         stmmac_common_interrupt(priv);
5641
5642         /* To handle DMA interrupts */
5643         stmmac_dma_interrupt(priv);
5644
5645         return IRQ_HANDLED;
5646 }
5647
5648 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5649 {
5650         struct net_device *dev = (struct net_device *)dev_id;
5651         struct stmmac_priv *priv = netdev_priv(dev);
5652
5653         if (unlikely(!dev)) {
5654                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5655                 return IRQ_NONE;
5656         }
5657
5658         /* Check if adapter is up */
5659         if (test_bit(STMMAC_DOWN, &priv->state))
5660                 return IRQ_HANDLED;
5661
5662         /* To handle Common interrupts */
5663         stmmac_common_interrupt(priv);
5664
5665         return IRQ_HANDLED;
5666 }
5667
5668 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5669 {
5670         struct net_device *dev = (struct net_device *)dev_id;
5671         struct stmmac_priv *priv = netdev_priv(dev);
5672
5673         if (unlikely(!dev)) {
5674                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5675                 return IRQ_NONE;
5676         }
5677
5678         /* Check if adapter is up */
5679         if (test_bit(STMMAC_DOWN, &priv->state))
5680                 return IRQ_HANDLED;
5681
5682         /* Check if a fatal error happened */
5683         stmmac_safety_feat_interrupt(priv);
5684
5685         return IRQ_HANDLED;
5686 }
5687
5688 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5689 {
5690         struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5691         int chan = tx_q->queue_index;
5692         struct stmmac_priv *priv;
5693         int status;
5694
5695         priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]);
5696
5697         if (unlikely(!data)) {
5698                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5699                 return IRQ_NONE;
5700         }
5701
5702         /* Check if adapter is up */
5703         if (test_bit(STMMAC_DOWN, &priv->state))
5704                 return IRQ_HANDLED;
5705
5706         status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5707
5708         if (unlikely(status & tx_hard_error_bump_tc)) {
5709                 /* Try to bump up the dma threshold on this failure */
5710                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
5711                     tc <= 256) {
5712                         tc += 64;
5713                         if (priv->plat->force_thresh_dma_mode)
5714                                 stmmac_set_dma_operation_mode(priv,
5715                                                               tc,
5716                                                               tc,
5717                                                               chan);
5718                         else
5719                                 stmmac_set_dma_operation_mode(priv,
5720                                                               tc,
5721                                                               SF_DMA_MODE,
5722                                                               chan);
5723                         priv->xstats.threshold = tc;
5724                 }
5725         } else if (unlikely(status == tx_hard_error)) {
5726                 stmmac_tx_err(priv, chan);
5727         }
5728
5729         return IRQ_HANDLED;
5730 }
5731
5732 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5733 {
5734         struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5735         int chan = rx_q->queue_index;
5736         struct stmmac_priv *priv;
5737
5738         priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]);
5739
5740         if (unlikely(!data)) {
5741                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5742                 return IRQ_NONE;
5743         }
5744
5745         /* Check if adapter is up */
5746         if (test_bit(STMMAC_DOWN, &priv->state))
5747                 return IRQ_HANDLED;
5748
5749         stmmac_napi_check(priv, chan, DMA_DIR_RX);
5750
5751         return IRQ_HANDLED;
5752 }
5753
5754 #ifdef CONFIG_NET_POLL_CONTROLLER
5755 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5756  * to allow network I/O with interrupts disabled.
5757  */
5758 static void stmmac_poll_controller(struct net_device *dev)
5759 {
5760         struct stmmac_priv *priv = netdev_priv(dev);
5761         int i;
5762
5763         /* If adapter is down, do nothing */
5764         if (test_bit(STMMAC_DOWN, &priv->state))
5765                 return;
5766
5767         if (priv->plat->multi_msi_en) {
5768                 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5769                         stmmac_msi_intr_rx(0, &priv->rx_queue[i]);
5770
5771                 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5772                         stmmac_msi_intr_tx(0, &priv->tx_queue[i]);
5773         } else {
5774                 disable_irq(dev->irq);
5775                 stmmac_interrupt(dev->irq, dev);
5776                 enable_irq(dev->irq);
5777         }
5778 }
5779 #endif
5780
5781 /**
5782  *  stmmac_ioctl - Entry point for the Ioctl
5783  *  @dev: Device pointer.
5784  *  @rq: An IOCTL specefic structure, that can contain a pointer to
5785  *  a proprietary structure used to pass information to the driver.
5786  *  @cmd: IOCTL command
5787  *  Description:
5788  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5789  */
5790 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5791 {
5792         struct stmmac_priv *priv = netdev_priv (dev);
5793         int ret = -EOPNOTSUPP;
5794
5795         if (!netif_running(dev))
5796                 return -EINVAL;
5797
5798         switch (cmd) {
5799         case SIOCGMIIPHY:
5800         case SIOCGMIIREG:
5801         case SIOCSMIIREG:
5802                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5803                 break;
5804         case SIOCSHWTSTAMP:
5805                 ret = stmmac_hwtstamp_set(dev, rq);
5806                 break;
5807         case SIOCGHWTSTAMP:
5808                 ret = stmmac_hwtstamp_get(dev, rq);
5809                 break;
5810         default:
5811                 break;
5812         }
5813
5814         return ret;
5815 }
5816
5817 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5818                                     void *cb_priv)
5819 {
5820         struct stmmac_priv *priv = cb_priv;
5821         int ret = -EOPNOTSUPP;
5822
5823         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
5824                 return ret;
5825
5826         __stmmac_disable_all_queues(priv);
5827
5828         switch (type) {
5829         case TC_SETUP_CLSU32:
5830                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
5831                 break;
5832         case TC_SETUP_CLSFLOWER:
5833                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
5834                 break;
5835         default:
5836                 break;
5837         }
5838
5839         stmmac_enable_all_queues(priv);
5840         return ret;
5841 }
5842
5843 static LIST_HEAD(stmmac_block_cb_list);
5844
5845 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
5846                            void *type_data)
5847 {
5848         struct stmmac_priv *priv = netdev_priv(ndev);
5849
5850         switch (type) {
5851         case TC_SETUP_BLOCK:
5852                 return flow_block_cb_setup_simple(type_data,
5853                                                   &stmmac_block_cb_list,
5854                                                   stmmac_setup_tc_block_cb,
5855                                                   priv, priv, true);
5856         case TC_SETUP_QDISC_CBS:
5857                 return stmmac_tc_setup_cbs(priv, priv, type_data);
5858         case TC_SETUP_QDISC_TAPRIO:
5859                 return stmmac_tc_setup_taprio(priv, priv, type_data);
5860         case TC_SETUP_QDISC_ETF:
5861                 return stmmac_tc_setup_etf(priv, priv, type_data);
5862         default:
5863                 return -EOPNOTSUPP;
5864         }
5865 }
5866
5867 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
5868                                struct net_device *sb_dev)
5869 {
5870         int gso = skb_shinfo(skb)->gso_type;
5871
5872         if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
5873                 /*
5874                  * There is no way to determine the number of TSO/USO
5875                  * capable Queues. Let's use always the Queue 0
5876                  * because if TSO/USO is supported then at least this
5877                  * one will be capable.
5878                  */
5879                 return 0;
5880         }
5881
5882         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
5883 }
5884
5885 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
5886 {
5887         struct stmmac_priv *priv = netdev_priv(ndev);
5888         int ret = 0;
5889
5890         ret = pm_runtime_get_sync(priv->device);
5891         if (ret < 0) {
5892                 pm_runtime_put_noidle(priv->device);
5893                 return ret;
5894         }
5895
5896         ret = eth_mac_addr(ndev, addr);
5897         if (ret)
5898                 goto set_mac_error;
5899
5900         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
5901
5902 set_mac_error:
5903         pm_runtime_put(priv->device);
5904
5905         return ret;
5906 }
5907
5908 #ifdef CONFIG_DEBUG_FS
5909 static struct dentry *stmmac_fs_dir;
5910
5911 static void sysfs_display_ring(void *head, int size, int extend_desc,
5912                                struct seq_file *seq, dma_addr_t dma_phy_addr)
5913 {
5914         int i;
5915         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
5916         struct dma_desc *p = (struct dma_desc *)head;
5917         dma_addr_t dma_addr;
5918
5919         for (i = 0; i < size; i++) {
5920                 if (extend_desc) {
5921                         dma_addr = dma_phy_addr + i * sizeof(*ep);
5922                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5923                                    i, &dma_addr,
5924                                    le32_to_cpu(ep->basic.des0),
5925                                    le32_to_cpu(ep->basic.des1),
5926                                    le32_to_cpu(ep->basic.des2),
5927                                    le32_to_cpu(ep->basic.des3));
5928                         ep++;
5929                 } else {
5930                         dma_addr = dma_phy_addr + i * sizeof(*p);
5931                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5932                                    i, &dma_addr,
5933                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
5934                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
5935                         p++;
5936                 }
5937                 seq_printf(seq, "\n");
5938         }
5939 }
5940
5941 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
5942 {
5943         struct net_device *dev = seq->private;
5944         struct stmmac_priv *priv = netdev_priv(dev);
5945         u32 rx_count = priv->plat->rx_queues_to_use;
5946         u32 tx_count = priv->plat->tx_queues_to_use;
5947         u32 queue;
5948
5949         if ((dev->flags & IFF_UP) == 0)
5950                 return 0;
5951
5952         for (queue = 0; queue < rx_count; queue++) {
5953                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5954
5955                 seq_printf(seq, "RX Queue %d:\n", queue);
5956
5957                 if (priv->extend_desc) {
5958                         seq_printf(seq, "Extended descriptor ring:\n");
5959                         sysfs_display_ring((void *)rx_q->dma_erx,
5960                                            priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy);
5961                 } else {
5962                         seq_printf(seq, "Descriptor ring:\n");
5963                         sysfs_display_ring((void *)rx_q->dma_rx,
5964                                            priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy);
5965                 }
5966         }
5967
5968         for (queue = 0; queue < tx_count; queue++) {
5969                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5970
5971                 seq_printf(seq, "TX Queue %d:\n", queue);
5972
5973                 if (priv->extend_desc) {
5974                         seq_printf(seq, "Extended descriptor ring:\n");
5975                         sysfs_display_ring((void *)tx_q->dma_etx,
5976                                            priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy);
5977                 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
5978                         seq_printf(seq, "Descriptor ring:\n");
5979                         sysfs_display_ring((void *)tx_q->dma_tx,
5980                                            priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy);
5981                 }
5982         }
5983
5984         return 0;
5985 }
5986 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
5987
5988 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
5989 {
5990         struct net_device *dev = seq->private;
5991         struct stmmac_priv *priv = netdev_priv(dev);
5992
5993         if (!priv->hw_cap_support) {
5994                 seq_printf(seq, "DMA HW features not supported\n");
5995                 return 0;
5996         }
5997
5998         seq_printf(seq, "==============================\n");
5999         seq_printf(seq, "\tDMA HW features\n");
6000         seq_printf(seq, "==============================\n");
6001
6002         seq_printf(seq, "\t10/100 Mbps: %s\n",
6003                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6004         seq_printf(seq, "\t1000 Mbps: %s\n",
6005                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
6006         seq_printf(seq, "\tHalf duplex: %s\n",
6007                    (priv->dma_cap.half_duplex) ? "Y" : "N");
6008         seq_printf(seq, "\tHash Filter: %s\n",
6009                    (priv->dma_cap.hash_filter) ? "Y" : "N");
6010         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6011                    (priv->dma_cap.multi_addr) ? "Y" : "N");
6012         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6013                    (priv->dma_cap.pcs) ? "Y" : "N");
6014         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6015                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
6016         seq_printf(seq, "\tPMT Remote wake up: %s\n",
6017                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6018         seq_printf(seq, "\tPMT Magic Frame: %s\n",
6019                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6020         seq_printf(seq, "\tRMON module: %s\n",
6021                    (priv->dma_cap.rmon) ? "Y" : "N");
6022         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6023                    (priv->dma_cap.time_stamp) ? "Y" : "N");
6024         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6025                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
6026         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6027                    (priv->dma_cap.eee) ? "Y" : "N");
6028         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6029         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6030                    (priv->dma_cap.tx_coe) ? "Y" : "N");
6031         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6032                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6033                            (priv->dma_cap.rx_coe) ? "Y" : "N");
6034         } else {
6035                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6036                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6037                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6038                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6039         }
6040         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6041                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6042         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6043                    priv->dma_cap.number_rx_channel);
6044         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6045                    priv->dma_cap.number_tx_channel);
6046         seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6047                    priv->dma_cap.number_rx_queues);
6048         seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6049                    priv->dma_cap.number_tx_queues);
6050         seq_printf(seq, "\tEnhanced descriptors: %s\n",
6051                    (priv->dma_cap.enh_desc) ? "Y" : "N");
6052         seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6053         seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6054         seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6055         seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6056         seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6057                    priv->dma_cap.pps_out_num);
6058         seq_printf(seq, "\tSafety Features: %s\n",
6059                    priv->dma_cap.asp ? "Y" : "N");
6060         seq_printf(seq, "\tFlexible RX Parser: %s\n",
6061                    priv->dma_cap.frpsel ? "Y" : "N");
6062         seq_printf(seq, "\tEnhanced Addressing: %d\n",
6063                    priv->dma_cap.addr64);
6064         seq_printf(seq, "\tReceive Side Scaling: %s\n",
6065                    priv->dma_cap.rssen ? "Y" : "N");
6066         seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6067                    priv->dma_cap.vlhash ? "Y" : "N");
6068         seq_printf(seq, "\tSplit Header: %s\n",
6069                    priv->dma_cap.sphen ? "Y" : "N");
6070         seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6071                    priv->dma_cap.vlins ? "Y" : "N");
6072         seq_printf(seq, "\tDouble VLAN: %s\n",
6073                    priv->dma_cap.dvlan ? "Y" : "N");
6074         seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6075                    priv->dma_cap.l3l4fnum);
6076         seq_printf(seq, "\tARP Offloading: %s\n",
6077                    priv->dma_cap.arpoffsel ? "Y" : "N");
6078         seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6079                    priv->dma_cap.estsel ? "Y" : "N");
6080         seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6081                    priv->dma_cap.fpesel ? "Y" : "N");
6082         seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6083                    priv->dma_cap.tbssel ? "Y" : "N");
6084         return 0;
6085 }
6086 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6087
6088 /* Use network device events to rename debugfs file entries.
6089  */
6090 static int stmmac_device_event(struct notifier_block *unused,
6091                                unsigned long event, void *ptr)
6092 {
6093         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6094         struct stmmac_priv *priv = netdev_priv(dev);
6095
6096         if (dev->netdev_ops != &stmmac_netdev_ops)
6097                 goto done;
6098
6099         switch (event) {
6100         case NETDEV_CHANGENAME:
6101                 if (priv->dbgfs_dir)
6102                         priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6103                                                          priv->dbgfs_dir,
6104                                                          stmmac_fs_dir,
6105                                                          dev->name);
6106                 break;
6107         }
6108 done:
6109         return NOTIFY_DONE;
6110 }
6111
6112 static struct notifier_block stmmac_notifier = {
6113         .notifier_call = stmmac_device_event,
6114 };
6115
6116 static void stmmac_init_fs(struct net_device *dev)
6117 {
6118         struct stmmac_priv *priv = netdev_priv(dev);
6119
6120         rtnl_lock();
6121
6122         /* Create per netdev entries */
6123         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6124
6125         /* Entry to report DMA RX/TX rings */
6126         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6127                             &stmmac_rings_status_fops);
6128
6129         /* Entry to report the DMA HW features */
6130         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6131                             &stmmac_dma_cap_fops);
6132
6133         rtnl_unlock();
6134 }
6135
6136 static void stmmac_exit_fs(struct net_device *dev)
6137 {
6138         struct stmmac_priv *priv = netdev_priv(dev);
6139
6140         debugfs_remove_recursive(priv->dbgfs_dir);
6141 }
6142 #endif /* CONFIG_DEBUG_FS */
6143
6144 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6145 {
6146         unsigned char *data = (unsigned char *)&vid_le;
6147         unsigned char data_byte = 0;
6148         u32 crc = ~0x0;
6149         u32 temp = 0;
6150         int i, bits;
6151
6152         bits = get_bitmask_order(VLAN_VID_MASK);
6153         for (i = 0; i < bits; i++) {
6154                 if ((i % 8) == 0)
6155                         data_byte = data[i / 8];
6156
6157                 temp = ((crc & 1) ^ data_byte) & 1;
6158                 crc >>= 1;
6159                 data_byte >>= 1;
6160
6161                 if (temp)
6162                         crc ^= 0xedb88320;
6163         }
6164
6165         return crc;
6166 }
6167
6168 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6169 {
6170         u32 crc, hash = 0;
6171         __le16 pmatch = 0;
6172         int count = 0;
6173         u16 vid = 0;
6174
6175         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6176                 __le16 vid_le = cpu_to_le16(vid);
6177                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6178                 hash |= (1 << crc);
6179                 count++;
6180         }
6181
6182         if (!priv->dma_cap.vlhash) {
6183                 if (count > 2) /* VID = 0 always passes filter */
6184                         return -EOPNOTSUPP;
6185
6186                 pmatch = cpu_to_le16(vid);
6187                 hash = 0;
6188         }
6189
6190         return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6191 }
6192
6193 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6194 {
6195         struct stmmac_priv *priv = netdev_priv(ndev);
6196         bool is_double = false;
6197         int ret;
6198
6199         if (be16_to_cpu(proto) == ETH_P_8021AD)
6200                 is_double = true;
6201
6202         set_bit(vid, priv->active_vlans);
6203         ret = stmmac_vlan_update(priv, is_double);
6204         if (ret) {
6205                 clear_bit(vid, priv->active_vlans);
6206                 return ret;
6207         }
6208
6209         if (priv->hw->num_vlan) {
6210                 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6211                 if (ret)
6212                         return ret;
6213         }
6214
6215         return 0;
6216 }
6217
6218 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6219 {
6220         struct stmmac_priv *priv = netdev_priv(ndev);
6221         bool is_double = false;
6222         int ret;
6223
6224         ret = pm_runtime_get_sync(priv->device);
6225         if (ret < 0) {
6226                 pm_runtime_put_noidle(priv->device);
6227                 return ret;
6228         }
6229
6230         if (be16_to_cpu(proto) == ETH_P_8021AD)
6231                 is_double = true;
6232
6233         clear_bit(vid, priv->active_vlans);
6234
6235         if (priv->hw->num_vlan) {
6236                 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6237                 if (ret)
6238                         goto del_vlan_error;
6239         }
6240
6241         ret = stmmac_vlan_update(priv, is_double);
6242
6243 del_vlan_error:
6244         pm_runtime_put(priv->device);
6245
6246         return ret;
6247 }
6248
6249 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6250 {
6251         struct stmmac_priv *priv = netdev_priv(dev);
6252
6253         switch (bpf->command) {
6254         case XDP_SETUP_PROG:
6255                 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6256         case XDP_SETUP_XSK_POOL:
6257                 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6258                                              bpf->xsk.queue_id);
6259         default:
6260                 return -EOPNOTSUPP;
6261         }
6262 }
6263
6264 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6265                            struct xdp_frame **frames, u32 flags)
6266 {
6267         struct stmmac_priv *priv = netdev_priv(dev);
6268         int cpu = smp_processor_id();
6269         struct netdev_queue *nq;
6270         int i, nxmit = 0;
6271         int queue;
6272
6273         if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6274                 return -ENETDOWN;
6275
6276         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6277                 return -EINVAL;
6278
6279         queue = stmmac_xdp_get_tx_queue(priv, cpu);
6280         nq = netdev_get_tx_queue(priv->dev, queue);
6281
6282         __netif_tx_lock(nq, cpu);
6283         /* Avoids TX time-out as we are sharing with slow path */
6284         nq->trans_start = jiffies;
6285
6286         for (i = 0; i < num_frames; i++) {
6287                 int res;
6288
6289                 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6290                 if (res == STMMAC_XDP_CONSUMED)
6291                         break;
6292
6293                 nxmit++;
6294         }
6295
6296         if (flags & XDP_XMIT_FLUSH) {
6297                 stmmac_flush_tx_descriptors(priv, queue);
6298                 stmmac_tx_timer_arm(priv, queue);
6299         }
6300
6301         __netif_tx_unlock(nq);
6302
6303         return nxmit;
6304 }
6305
6306 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6307 {
6308         struct stmmac_channel *ch = &priv->channel[queue];
6309         unsigned long flags;
6310
6311         spin_lock_irqsave(&ch->lock, flags);
6312         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6313         spin_unlock_irqrestore(&ch->lock, flags);
6314
6315         stmmac_stop_rx_dma(priv, queue);
6316         __free_dma_rx_desc_resources(priv, queue);
6317 }
6318
6319 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6320 {
6321         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
6322         struct stmmac_channel *ch = &priv->channel[queue];
6323         unsigned long flags;
6324         u32 buf_size;
6325         int ret;
6326
6327         ret = __alloc_dma_rx_desc_resources(priv, queue);
6328         if (ret) {
6329                 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6330                 return;
6331         }
6332
6333         ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL);
6334         if (ret) {
6335                 __free_dma_rx_desc_resources(priv, queue);
6336                 netdev_err(priv->dev, "Failed to init RX desc.\n");
6337                 return;
6338         }
6339
6340         stmmac_clear_rx_descriptors(priv, queue);
6341
6342         stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6343                             rx_q->dma_rx_phy, rx_q->queue_index);
6344
6345         rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6346                              sizeof(struct dma_desc));
6347         stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6348                                rx_q->rx_tail_addr, rx_q->queue_index);
6349
6350         if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6351                 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6352                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6353                                       buf_size,
6354                                       rx_q->queue_index);
6355         } else {
6356                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6357                                       priv->dma_buf_sz,
6358                                       rx_q->queue_index);
6359         }
6360
6361         stmmac_start_rx_dma(priv, queue);
6362
6363         spin_lock_irqsave(&ch->lock, flags);
6364         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6365         spin_unlock_irqrestore(&ch->lock, flags);
6366 }
6367
6368 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6369 {
6370         struct stmmac_channel *ch = &priv->channel[queue];
6371         unsigned long flags;
6372
6373         spin_lock_irqsave(&ch->lock, flags);
6374         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6375         spin_unlock_irqrestore(&ch->lock, flags);
6376
6377         stmmac_stop_tx_dma(priv, queue);
6378         __free_dma_tx_desc_resources(priv, queue);
6379 }
6380
6381 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6382 {
6383         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6384         struct stmmac_channel *ch = &priv->channel[queue];
6385         unsigned long flags;
6386         int ret;
6387
6388         ret = __alloc_dma_tx_desc_resources(priv, queue);
6389         if (ret) {
6390                 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6391                 return;
6392         }
6393
6394         ret = __init_dma_tx_desc_rings(priv, queue);
6395         if (ret) {
6396                 __free_dma_tx_desc_resources(priv, queue);
6397                 netdev_err(priv->dev, "Failed to init TX desc.\n");
6398                 return;
6399         }
6400
6401         stmmac_clear_tx_descriptors(priv, queue);
6402
6403         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6404                             tx_q->dma_tx_phy, tx_q->queue_index);
6405
6406         if (tx_q->tbs & STMMAC_TBS_AVAIL)
6407                 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6408
6409         tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6410         stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6411                                tx_q->tx_tail_addr, tx_q->queue_index);
6412
6413         stmmac_start_tx_dma(priv, queue);
6414
6415         spin_lock_irqsave(&ch->lock, flags);
6416         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6417         spin_unlock_irqrestore(&ch->lock, flags);
6418 }
6419
6420 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6421 {
6422         struct stmmac_priv *priv = netdev_priv(dev);
6423         struct stmmac_rx_queue *rx_q;
6424         struct stmmac_tx_queue *tx_q;
6425         struct stmmac_channel *ch;
6426
6427         if (test_bit(STMMAC_DOWN, &priv->state) ||
6428             !netif_carrier_ok(priv->dev))
6429                 return -ENETDOWN;
6430
6431         if (!stmmac_xdp_is_enabled(priv))
6432                 return -ENXIO;
6433
6434         if (queue >= priv->plat->rx_queues_to_use ||
6435             queue >= priv->plat->tx_queues_to_use)
6436                 return -EINVAL;
6437
6438         rx_q = &priv->rx_queue[queue];
6439         tx_q = &priv->tx_queue[queue];
6440         ch = &priv->channel[queue];
6441
6442         if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6443                 return -ENXIO;
6444
6445         if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6446                 /* EQoS does not have per-DMA channel SW interrupt,
6447                  * so we schedule RX Napi straight-away.
6448                  */
6449                 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6450                         __napi_schedule(&ch->rxtx_napi);
6451         }
6452
6453         return 0;
6454 }
6455
6456 static const struct net_device_ops stmmac_netdev_ops = {
6457         .ndo_open = stmmac_open,
6458         .ndo_start_xmit = stmmac_xmit,
6459         .ndo_stop = stmmac_release,
6460         .ndo_change_mtu = stmmac_change_mtu,
6461         .ndo_fix_features = stmmac_fix_features,
6462         .ndo_set_features = stmmac_set_features,
6463         .ndo_set_rx_mode = stmmac_set_rx_mode,
6464         .ndo_tx_timeout = stmmac_tx_timeout,
6465         .ndo_eth_ioctl = stmmac_ioctl,
6466         .ndo_setup_tc = stmmac_setup_tc,
6467         .ndo_select_queue = stmmac_select_queue,
6468 #ifdef CONFIG_NET_POLL_CONTROLLER
6469         .ndo_poll_controller = stmmac_poll_controller,
6470 #endif
6471         .ndo_set_mac_address = stmmac_set_mac_address,
6472         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6473         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6474         .ndo_bpf = stmmac_bpf,
6475         .ndo_xdp_xmit = stmmac_xdp_xmit,
6476         .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6477 };
6478
6479 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6480 {
6481         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6482                 return;
6483         if (test_bit(STMMAC_DOWN, &priv->state))
6484                 return;
6485
6486         netdev_err(priv->dev, "Reset adapter.\n");
6487
6488         rtnl_lock();
6489         netif_trans_update(priv->dev);
6490         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6491                 usleep_range(1000, 2000);
6492
6493         set_bit(STMMAC_DOWN, &priv->state);
6494         dev_close(priv->dev);
6495         dev_open(priv->dev, NULL);
6496         clear_bit(STMMAC_DOWN, &priv->state);
6497         clear_bit(STMMAC_RESETING, &priv->state);
6498         rtnl_unlock();
6499 }
6500
6501 static void stmmac_service_task(struct work_struct *work)
6502 {
6503         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6504                         service_task);
6505
6506         stmmac_reset_subtask(priv);
6507         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6508 }
6509
6510 /**
6511  *  stmmac_hw_init - Init the MAC device
6512  *  @priv: driver private structure
6513  *  Description: this function is to configure the MAC device according to
6514  *  some platform parameters or the HW capability register. It prepares the
6515  *  driver to use either ring or chain modes and to setup either enhanced or
6516  *  normal descriptors.
6517  */
6518 static int stmmac_hw_init(struct stmmac_priv *priv)
6519 {
6520         int ret;
6521
6522         /* dwmac-sun8i only work in chain mode */
6523         if (priv->plat->has_sun8i)
6524                 chain_mode = 1;
6525         priv->chain_mode = chain_mode;
6526
6527         /* Initialize HW Interface */
6528         ret = stmmac_hwif_init(priv);
6529         if (ret)
6530                 return ret;
6531
6532         /* Get the HW capability (new GMAC newer than 3.50a) */
6533         priv->hw_cap_support = stmmac_get_hw_features(priv);
6534         if (priv->hw_cap_support) {
6535                 dev_info(priv->device, "DMA HW capability register supported\n");
6536
6537                 /* We can override some gmac/dma configuration fields: e.g.
6538                  * enh_desc, tx_coe (e.g. that are passed through the
6539                  * platform) with the values from the HW capability
6540                  * register (if supported).
6541                  */
6542                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6543                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6544                                 !priv->plat->use_phy_wol;
6545                 priv->hw->pmt = priv->plat->pmt;
6546                 if (priv->dma_cap.hash_tb_sz) {
6547                         priv->hw->multicast_filter_bins =
6548                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
6549                         priv->hw->mcast_bits_log2 =
6550                                         ilog2(priv->hw->multicast_filter_bins);
6551                 }
6552
6553                 /* TXCOE doesn't work in thresh DMA mode */
6554                 if (priv->plat->force_thresh_dma_mode)
6555                         priv->plat->tx_coe = 0;
6556                 else
6557                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
6558
6559                 /* In case of GMAC4 rx_coe is from HW cap register. */
6560                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6561
6562                 if (priv->dma_cap.rx_coe_type2)
6563                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6564                 else if (priv->dma_cap.rx_coe_type1)
6565                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6566
6567         } else {
6568                 dev_info(priv->device, "No HW DMA feature register supported\n");
6569         }
6570
6571         if (priv->plat->rx_coe) {
6572                 priv->hw->rx_csum = priv->plat->rx_coe;
6573                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6574                 if (priv->synopsys_id < DWMAC_CORE_4_00)
6575                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6576         }
6577         if (priv->plat->tx_coe)
6578                 dev_info(priv->device, "TX Checksum insertion supported\n");
6579
6580         if (priv->plat->pmt) {
6581                 dev_info(priv->device, "Wake-Up On Lan supported\n");
6582                 device_set_wakeup_capable(priv->device, 1);
6583         }
6584
6585         if (priv->dma_cap.tsoen)
6586                 dev_info(priv->device, "TSO supported\n");
6587
6588         priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6589         priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6590
6591         /* Run HW quirks, if any */
6592         if (priv->hwif_quirks) {
6593                 ret = priv->hwif_quirks(priv);
6594                 if (ret)
6595                         return ret;
6596         }
6597
6598         /* Rx Watchdog is available in the COREs newer than the 3.40.
6599          * In some case, for example on bugged HW this feature
6600          * has to be disable and this can be done by passing the
6601          * riwt_off field from the platform.
6602          */
6603         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6604             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6605                 priv->use_riwt = 1;
6606                 dev_info(priv->device,
6607                          "Enable RX Mitigation via HW Watchdog Timer\n");
6608         }
6609
6610         return 0;
6611 }
6612
6613 static void stmmac_napi_add(struct net_device *dev)
6614 {
6615         struct stmmac_priv *priv = netdev_priv(dev);
6616         u32 queue, maxq;
6617
6618         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6619
6620         for (queue = 0; queue < maxq; queue++) {
6621                 struct stmmac_channel *ch = &priv->channel[queue];
6622
6623                 ch->priv_data = priv;
6624                 ch->index = queue;
6625                 spin_lock_init(&ch->lock);
6626
6627                 if (queue < priv->plat->rx_queues_to_use) {
6628                         netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
6629                                        NAPI_POLL_WEIGHT);
6630                 }
6631                 if (queue < priv->plat->tx_queues_to_use) {
6632                         netif_tx_napi_add(dev, &ch->tx_napi,
6633                                           stmmac_napi_poll_tx,
6634                                           NAPI_POLL_WEIGHT);
6635                 }
6636                 if (queue < priv->plat->rx_queues_to_use &&
6637                     queue < priv->plat->tx_queues_to_use) {
6638                         netif_napi_add(dev, &ch->rxtx_napi,
6639                                        stmmac_napi_poll_rxtx,
6640                                        NAPI_POLL_WEIGHT);
6641                 }
6642         }
6643 }
6644
6645 static void stmmac_napi_del(struct net_device *dev)
6646 {
6647         struct stmmac_priv *priv = netdev_priv(dev);
6648         u32 queue, maxq;
6649
6650         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6651
6652         for (queue = 0; queue < maxq; queue++) {
6653                 struct stmmac_channel *ch = &priv->channel[queue];
6654
6655                 if (queue < priv->plat->rx_queues_to_use)
6656                         netif_napi_del(&ch->rx_napi);
6657                 if (queue < priv->plat->tx_queues_to_use)
6658                         netif_napi_del(&ch->tx_napi);
6659                 if (queue < priv->plat->rx_queues_to_use &&
6660                     queue < priv->plat->tx_queues_to_use) {
6661                         netif_napi_del(&ch->rxtx_napi);
6662                 }
6663         }
6664 }
6665
6666 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
6667 {
6668         struct stmmac_priv *priv = netdev_priv(dev);
6669         int ret = 0;
6670
6671         if (netif_running(dev))
6672                 stmmac_release(dev);
6673
6674         stmmac_napi_del(dev);
6675
6676         priv->plat->rx_queues_to_use = rx_cnt;
6677         priv->plat->tx_queues_to_use = tx_cnt;
6678
6679         stmmac_napi_add(dev);
6680
6681         if (netif_running(dev))
6682                 ret = stmmac_open(dev);
6683
6684         return ret;
6685 }
6686
6687 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
6688 {
6689         struct stmmac_priv *priv = netdev_priv(dev);
6690         int ret = 0;
6691
6692         if (netif_running(dev))
6693                 stmmac_release(dev);
6694
6695         priv->dma_rx_size = rx_size;
6696         priv->dma_tx_size = tx_size;
6697
6698         if (netif_running(dev))
6699                 ret = stmmac_open(dev);
6700
6701         return ret;
6702 }
6703
6704 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
6705 static void stmmac_fpe_lp_task(struct work_struct *work)
6706 {
6707         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6708                                                 fpe_task);
6709         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
6710         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
6711         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
6712         bool *hs_enable = &fpe_cfg->hs_enable;
6713         bool *enable = &fpe_cfg->enable;
6714         int retries = 20;
6715
6716         while (retries-- > 0) {
6717                 /* Bail out immediately if FPE handshake is OFF */
6718                 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
6719                         break;
6720
6721                 if (*lo_state == FPE_STATE_ENTERING_ON &&
6722                     *lp_state == FPE_STATE_ENTERING_ON) {
6723                         stmmac_fpe_configure(priv, priv->ioaddr,
6724                                              priv->plat->tx_queues_to_use,
6725                                              priv->plat->rx_queues_to_use,
6726                                              *enable);
6727
6728                         netdev_info(priv->dev, "configured FPE\n");
6729
6730                         *lo_state = FPE_STATE_ON;
6731                         *lp_state = FPE_STATE_ON;
6732                         netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
6733                         break;
6734                 }
6735
6736                 if ((*lo_state == FPE_STATE_CAPABLE ||
6737                      *lo_state == FPE_STATE_ENTERING_ON) &&
6738                      *lp_state != FPE_STATE_ON) {
6739                         netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
6740                                     *lo_state, *lp_state);
6741                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6742                                                 MPACKET_VERIFY);
6743                 }
6744                 /* Sleep then retry */
6745                 msleep(500);
6746         }
6747
6748         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
6749 }
6750
6751 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
6752 {
6753         if (priv->plat->fpe_cfg->hs_enable != enable) {
6754                 if (enable) {
6755                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6756                                                 MPACKET_VERIFY);
6757                 } else {
6758                         priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
6759                         priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
6760                 }
6761
6762                 priv->plat->fpe_cfg->hs_enable = enable;
6763         }
6764 }
6765
6766 /**
6767  * stmmac_dvr_probe
6768  * @device: device pointer
6769  * @plat_dat: platform data pointer
6770  * @res: stmmac resource pointer
6771  * Description: this is the main probe function used to
6772  * call the alloc_etherdev, allocate the priv structure.
6773  * Return:
6774  * returns 0 on success, otherwise errno.
6775  */
6776 int stmmac_dvr_probe(struct device *device,
6777                      struct plat_stmmacenet_data *plat_dat,
6778                      struct stmmac_resources *res)
6779 {
6780         struct net_device *ndev = NULL;
6781         struct stmmac_priv *priv;
6782         u32 rxq;
6783         int i, ret = 0;
6784
6785         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
6786                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
6787         if (!ndev)
6788                 return -ENOMEM;
6789
6790         SET_NETDEV_DEV(ndev, device);
6791
6792         priv = netdev_priv(ndev);
6793         priv->device = device;
6794         priv->dev = ndev;
6795
6796         stmmac_set_ethtool_ops(ndev);
6797         priv->pause = pause;
6798         priv->plat = plat_dat;
6799         priv->ioaddr = res->addr;
6800         priv->dev->base_addr = (unsigned long)res->addr;
6801         priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
6802
6803         priv->dev->irq = res->irq;
6804         priv->wol_irq = res->wol_irq;
6805         priv->lpi_irq = res->lpi_irq;
6806         priv->sfty_ce_irq = res->sfty_ce_irq;
6807         priv->sfty_ue_irq = res->sfty_ue_irq;
6808         for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
6809                 priv->rx_irq[i] = res->rx_irq[i];
6810         for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
6811                 priv->tx_irq[i] = res->tx_irq[i];
6812
6813         if (!is_zero_ether_addr(res->mac))
6814                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
6815
6816         dev_set_drvdata(device, priv->dev);
6817
6818         /* Verify driver arguments */
6819         stmmac_verify_args();
6820
6821         priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
6822         if (!priv->af_xdp_zc_qps)
6823                 return -ENOMEM;
6824
6825         /* Allocate workqueue */
6826         priv->wq = create_singlethread_workqueue("stmmac_wq");
6827         if (!priv->wq) {
6828                 dev_err(priv->device, "failed to create workqueue\n");
6829                 return -ENOMEM;
6830         }
6831
6832         INIT_WORK(&priv->service_task, stmmac_service_task);
6833
6834         /* Initialize Link Partner FPE workqueue */
6835         INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
6836
6837         /* Override with kernel parameters if supplied XXX CRS XXX
6838          * this needs to have multiple instances
6839          */
6840         if ((phyaddr >= 0) && (phyaddr <= 31))
6841                 priv->plat->phy_addr = phyaddr;
6842
6843         if (priv->plat->stmmac_rst) {
6844                 ret = reset_control_assert(priv->plat->stmmac_rst);
6845                 reset_control_deassert(priv->plat->stmmac_rst);
6846                 /* Some reset controllers have only reset callback instead of
6847                  * assert + deassert callbacks pair.
6848                  */
6849                 if (ret == -ENOTSUPP)
6850                         reset_control_reset(priv->plat->stmmac_rst);
6851         }
6852
6853         ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
6854         if (ret == -ENOTSUPP)
6855                 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
6856                         ERR_PTR(ret));
6857
6858         /* Init MAC and get the capabilities */
6859         ret = stmmac_hw_init(priv);
6860         if (ret)
6861                 goto error_hw_init;
6862
6863         /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
6864          */
6865         if (priv->synopsys_id < DWMAC_CORE_5_20)
6866                 priv->plat->dma_cfg->dche = false;
6867
6868         stmmac_check_ether_addr(priv);
6869
6870         ndev->netdev_ops = &stmmac_netdev_ops;
6871
6872         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6873                             NETIF_F_RXCSUM;
6874
6875         ret = stmmac_tc_init(priv, priv);
6876         if (!ret) {
6877                 ndev->hw_features |= NETIF_F_HW_TC;
6878         }
6879
6880         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
6881                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
6882                 if (priv->plat->has_gmac4)
6883                         ndev->hw_features |= NETIF_F_GSO_UDP_L4;
6884                 priv->tso = true;
6885                 dev_info(priv->device, "TSO feature enabled\n");
6886         }
6887
6888         if (priv->dma_cap.sphen) {
6889                 ndev->hw_features |= NETIF_F_GRO;
6890                 priv->sph_cap = true;
6891                 priv->sph = priv->sph_cap;
6892                 dev_info(priv->device, "SPH feature enabled\n");
6893         }
6894
6895         /* The current IP register MAC_HW_Feature1[ADDR64] only define
6896          * 32/40/64 bit width, but some SOC support others like i.MX8MP
6897          * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
6898          * So overwrite dma_cap.addr64 according to HW real design.
6899          */
6900         if (priv->plat->addr64)
6901                 priv->dma_cap.addr64 = priv->plat->addr64;
6902
6903         if (priv->dma_cap.addr64) {
6904                 ret = dma_set_mask_and_coherent(device,
6905                                 DMA_BIT_MASK(priv->dma_cap.addr64));
6906                 if (!ret) {
6907                         dev_info(priv->device, "Using %d bits DMA width\n",
6908                                  priv->dma_cap.addr64);
6909
6910                         /*
6911                          * If more than 32 bits can be addressed, make sure to
6912                          * enable enhanced addressing mode.
6913                          */
6914                         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
6915                                 priv->plat->dma_cfg->eame = true;
6916                 } else {
6917                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
6918                         if (ret) {
6919                                 dev_err(priv->device, "Failed to set DMA Mask\n");
6920                                 goto error_hw_init;
6921                         }
6922
6923                         priv->dma_cap.addr64 = 32;
6924                 }
6925         }
6926
6927         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
6928         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
6929 #ifdef STMMAC_VLAN_TAG_USED
6930         /* Both mac100 and gmac support receive VLAN tag detection */
6931         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
6932         if (priv->dma_cap.vlhash) {
6933                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
6934                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
6935         }
6936         if (priv->dma_cap.vlins) {
6937                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
6938                 if (priv->dma_cap.dvlan)
6939                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
6940         }
6941 #endif
6942         priv->msg_enable = netif_msg_init(debug, default_msg_level);
6943
6944         /* Initialize RSS */
6945         rxq = priv->plat->rx_queues_to_use;
6946         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
6947         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
6948                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
6949
6950         if (priv->dma_cap.rssen && priv->plat->rss_en)
6951                 ndev->features |= NETIF_F_RXHASH;
6952
6953         /* MTU range: 46 - hw-specific max */
6954         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
6955         if (priv->plat->has_xgmac)
6956                 ndev->max_mtu = XGMAC_JUMBO_LEN;
6957         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
6958                 ndev->max_mtu = JUMBO_LEN;
6959         else
6960                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
6961         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
6962          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
6963          */
6964         if ((priv->plat->maxmtu < ndev->max_mtu) &&
6965             (priv->plat->maxmtu >= ndev->min_mtu))
6966                 ndev->max_mtu = priv->plat->maxmtu;
6967         else if (priv->plat->maxmtu < ndev->min_mtu)
6968                 dev_warn(priv->device,
6969                          "%s: warning: maxmtu having invalid value (%d)\n",
6970                          __func__, priv->plat->maxmtu);
6971
6972         if (flow_ctrl)
6973                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
6974
6975         /* Setup channels NAPI */
6976         stmmac_napi_add(ndev);
6977
6978         mutex_init(&priv->lock);
6979
6980         /* If a specific clk_csr value is passed from the platform
6981          * this means that the CSR Clock Range selection cannot be
6982          * changed at run-time and it is fixed. Viceversa the driver'll try to
6983          * set the MDC clock dynamically according to the csr actual
6984          * clock input.
6985          */
6986         if (priv->plat->clk_csr >= 0)
6987                 priv->clk_csr = priv->plat->clk_csr;
6988         else
6989                 stmmac_clk_csr_set(priv);
6990
6991         stmmac_check_pcs_mode(priv);
6992
6993         pm_runtime_get_noresume(device);
6994         pm_runtime_set_active(device);
6995         pm_runtime_enable(device);
6996
6997         if (priv->hw->pcs != STMMAC_PCS_TBI &&
6998             priv->hw->pcs != STMMAC_PCS_RTBI) {
6999                 /* MDIO bus Registration */
7000                 ret = stmmac_mdio_register(ndev);
7001                 if (ret < 0) {
7002                         dev_err(priv->device,
7003                                 "%s: MDIO bus (id: %d) registration failed",
7004                                 __func__, priv->plat->bus_id);
7005                         goto error_mdio_register;
7006                 }
7007         }
7008
7009         if (priv->plat->speed_mode_2500)
7010                 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7011
7012         if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7013                 ret = stmmac_xpcs_setup(priv->mii);
7014                 if (ret)
7015                         goto error_xpcs_setup;
7016         }
7017
7018         ret = stmmac_phy_setup(priv);
7019         if (ret) {
7020                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7021                 goto error_phy_setup;
7022         }
7023
7024         ret = register_netdev(ndev);
7025         if (ret) {
7026                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7027                         __func__, ret);
7028                 goto error_netdev_register;
7029         }
7030
7031         if (priv->plat->serdes_powerup) {
7032                 ret = priv->plat->serdes_powerup(ndev,
7033                                                  priv->plat->bsp_priv);
7034
7035                 if (ret < 0)
7036                         goto error_serdes_powerup;
7037         }
7038
7039 #ifdef CONFIG_DEBUG_FS
7040         stmmac_init_fs(ndev);
7041 #endif
7042
7043         /* Let pm_runtime_put() disable the clocks.
7044          * If CONFIG_PM is not enabled, the clocks will stay powered.
7045          */
7046         pm_runtime_put(device);
7047
7048         return ret;
7049
7050 error_serdes_powerup:
7051         unregister_netdev(ndev);
7052 error_netdev_register:
7053         phylink_destroy(priv->phylink);
7054 error_xpcs_setup:
7055 error_phy_setup:
7056         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7057             priv->hw->pcs != STMMAC_PCS_RTBI)
7058                 stmmac_mdio_unregister(ndev);
7059 error_mdio_register:
7060         stmmac_napi_del(ndev);
7061 error_hw_init:
7062         destroy_workqueue(priv->wq);
7063         bitmap_free(priv->af_xdp_zc_qps);
7064
7065         return ret;
7066 }
7067 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7068
7069 /**
7070  * stmmac_dvr_remove
7071  * @dev: device pointer
7072  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7073  * changes the link status, releases the DMA descriptor rings.
7074  */
7075 int stmmac_dvr_remove(struct device *dev)
7076 {
7077         struct net_device *ndev = dev_get_drvdata(dev);
7078         struct stmmac_priv *priv = netdev_priv(ndev);
7079
7080         netdev_info(priv->dev, "%s: removing driver", __func__);
7081
7082         stmmac_stop_all_dma(priv);
7083         stmmac_mac_set(priv, priv->ioaddr, false);
7084         netif_carrier_off(ndev);
7085         unregister_netdev(ndev);
7086
7087         /* Serdes power down needs to happen after VLAN filter
7088          * is deleted that is triggered by unregister_netdev().
7089          */
7090         if (priv->plat->serdes_powerdown)
7091                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7092
7093 #ifdef CONFIG_DEBUG_FS
7094         stmmac_exit_fs(ndev);
7095 #endif
7096         phylink_destroy(priv->phylink);
7097         if (priv->plat->stmmac_rst)
7098                 reset_control_assert(priv->plat->stmmac_rst);
7099         reset_control_assert(priv->plat->stmmac_ahb_rst);
7100         pm_runtime_put(dev);
7101         pm_runtime_disable(dev);
7102         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7103             priv->hw->pcs != STMMAC_PCS_RTBI)
7104                 stmmac_mdio_unregister(ndev);
7105         destroy_workqueue(priv->wq);
7106         mutex_destroy(&priv->lock);
7107         bitmap_free(priv->af_xdp_zc_qps);
7108
7109         return 0;
7110 }
7111 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7112
7113 /**
7114  * stmmac_suspend - suspend callback
7115  * @dev: device pointer
7116  * Description: this is the function to suspend the device and it is called
7117  * by the platform driver to stop the network queue, release the resources,
7118  * program the PMT register (for WoL), clean and release driver resources.
7119  */
7120 int stmmac_suspend(struct device *dev)
7121 {
7122         struct net_device *ndev = dev_get_drvdata(dev);
7123         struct stmmac_priv *priv = netdev_priv(ndev);
7124         u32 chan;
7125
7126         if (!ndev || !netif_running(ndev))
7127                 return 0;
7128
7129         mutex_lock(&priv->lock);
7130
7131         netif_device_detach(ndev);
7132
7133         stmmac_disable_all_queues(priv);
7134
7135         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7136                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
7137
7138         if (priv->eee_enabled) {
7139                 priv->tx_path_in_lpi_mode = false;
7140                 del_timer_sync(&priv->eee_ctrl_timer);
7141         }
7142
7143         /* Stop TX/RX DMA */
7144         stmmac_stop_all_dma(priv);
7145
7146         if (priv->plat->serdes_powerdown)
7147                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7148
7149         /* Enable Power down mode by programming the PMT regs */
7150         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7151                 stmmac_pmt(priv, priv->hw, priv->wolopts);
7152                 priv->irq_wake = 1;
7153         } else {
7154                 stmmac_mac_set(priv, priv->ioaddr, false);
7155                 pinctrl_pm_select_sleep_state(priv->device);
7156         }
7157
7158         mutex_unlock(&priv->lock);
7159
7160         rtnl_lock();
7161         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7162                 phylink_suspend(priv->phylink, true);
7163         } else {
7164                 if (device_may_wakeup(priv->device))
7165                         phylink_speed_down(priv->phylink, false);
7166                 phylink_suspend(priv->phylink, false);
7167         }
7168         rtnl_unlock();
7169
7170         if (priv->dma_cap.fpesel) {
7171                 /* Disable FPE */
7172                 stmmac_fpe_configure(priv, priv->ioaddr,
7173                                      priv->plat->tx_queues_to_use,
7174                                      priv->plat->rx_queues_to_use, false);
7175
7176                 stmmac_fpe_handshake(priv, false);
7177                 stmmac_fpe_stop_wq(priv);
7178         }
7179
7180         priv->speed = SPEED_UNKNOWN;
7181         return 0;
7182 }
7183 EXPORT_SYMBOL_GPL(stmmac_suspend);
7184
7185 /**
7186  * stmmac_reset_queues_param - reset queue parameters
7187  * @priv: device pointer
7188  */
7189 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7190 {
7191         u32 rx_cnt = priv->plat->rx_queues_to_use;
7192         u32 tx_cnt = priv->plat->tx_queues_to_use;
7193         u32 queue;
7194
7195         for (queue = 0; queue < rx_cnt; queue++) {
7196                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
7197
7198                 rx_q->cur_rx = 0;
7199                 rx_q->dirty_rx = 0;
7200         }
7201
7202         for (queue = 0; queue < tx_cnt; queue++) {
7203                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
7204
7205                 tx_q->cur_tx = 0;
7206                 tx_q->dirty_tx = 0;
7207                 tx_q->mss = 0;
7208
7209                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7210         }
7211 }
7212
7213 /**
7214  * stmmac_resume - resume callback
7215  * @dev: device pointer
7216  * Description: when resume this function is invoked to setup the DMA and CORE
7217  * in a usable state.
7218  */
7219 int stmmac_resume(struct device *dev)
7220 {
7221         struct net_device *ndev = dev_get_drvdata(dev);
7222         struct stmmac_priv *priv = netdev_priv(ndev);
7223         int ret;
7224
7225         if (!netif_running(ndev))
7226                 return 0;
7227
7228         /* Power Down bit, into the PM register, is cleared
7229          * automatically as soon as a magic packet or a Wake-up frame
7230          * is received. Anyway, it's better to manually clear
7231          * this bit because it can generate problems while resuming
7232          * from another devices (e.g. serial console).
7233          */
7234         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7235                 mutex_lock(&priv->lock);
7236                 stmmac_pmt(priv, priv->hw, 0);
7237                 mutex_unlock(&priv->lock);
7238                 priv->irq_wake = 0;
7239         } else {
7240                 pinctrl_pm_select_default_state(priv->device);
7241                 /* reset the phy so that it's ready */
7242                 if (priv->mii)
7243                         stmmac_mdio_reset(priv->mii);
7244         }
7245
7246         if (priv->plat->serdes_powerup) {
7247                 ret = priv->plat->serdes_powerup(ndev,
7248                                                  priv->plat->bsp_priv);
7249
7250                 if (ret < 0)
7251                         return ret;
7252         }
7253
7254         rtnl_lock();
7255         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7256                 phylink_resume(priv->phylink);
7257         } else {
7258                 phylink_resume(priv->phylink);
7259                 if (device_may_wakeup(priv->device))
7260                         phylink_speed_up(priv->phylink);
7261         }
7262         rtnl_unlock();
7263
7264         rtnl_lock();
7265         mutex_lock(&priv->lock);
7266
7267         stmmac_reset_queues_param(priv);
7268
7269         stmmac_free_tx_skbufs(priv);
7270         stmmac_clear_descriptors(priv);
7271
7272         stmmac_hw_setup(ndev, false);
7273         stmmac_init_coalesce(priv);
7274         stmmac_set_rx_mode(ndev);
7275
7276         stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7277
7278         stmmac_enable_all_queues(priv);
7279
7280         mutex_unlock(&priv->lock);
7281         rtnl_unlock();
7282
7283         netif_device_attach(ndev);
7284
7285         return 0;
7286 }
7287 EXPORT_SYMBOL_GPL(stmmac_resume);
7288
7289 #ifndef MODULE
7290 static int __init stmmac_cmdline_opt(char *str)
7291 {
7292         char *opt;
7293
7294         if (!str || !*str)
7295                 return -EINVAL;
7296         while ((opt = strsep(&str, ",")) != NULL) {
7297                 if (!strncmp(opt, "debug:", 6)) {
7298                         if (kstrtoint(opt + 6, 0, &debug))
7299                                 goto err;
7300                 } else if (!strncmp(opt, "phyaddr:", 8)) {
7301                         if (kstrtoint(opt + 8, 0, &phyaddr))
7302                                 goto err;
7303                 } else if (!strncmp(opt, "buf_sz:", 7)) {
7304                         if (kstrtoint(opt + 7, 0, &buf_sz))
7305                                 goto err;
7306                 } else if (!strncmp(opt, "tc:", 3)) {
7307                         if (kstrtoint(opt + 3, 0, &tc))
7308                                 goto err;
7309                 } else if (!strncmp(opt, "watchdog:", 9)) {
7310                         if (kstrtoint(opt + 9, 0, &watchdog))
7311                                 goto err;
7312                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7313                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
7314                                 goto err;
7315                 } else if (!strncmp(opt, "pause:", 6)) {
7316                         if (kstrtoint(opt + 6, 0, &pause))
7317                                 goto err;
7318                 } else if (!strncmp(opt, "eee_timer:", 10)) {
7319                         if (kstrtoint(opt + 10, 0, &eee_timer))
7320                                 goto err;
7321                 } else if (!strncmp(opt, "chain_mode:", 11)) {
7322                         if (kstrtoint(opt + 11, 0, &chain_mode))
7323                                 goto err;
7324                 }
7325         }
7326         return 0;
7327
7328 err:
7329         pr_err("%s: ERROR broken module parameter conversion", __func__);
7330         return -EINVAL;
7331 }
7332
7333 __setup("stmmaceth=", stmmac_cmdline_opt);
7334 #endif /* MODULE */
7335
7336 static int __init stmmac_init(void)
7337 {
7338 #ifdef CONFIG_DEBUG_FS
7339         /* Create debugfs main directory if it doesn't exist yet */
7340         if (!stmmac_fs_dir)
7341                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7342         register_netdevice_notifier(&stmmac_notifier);
7343 #endif
7344
7345         return 0;
7346 }
7347
7348 static void __exit stmmac_exit(void)
7349 {
7350 #ifdef CONFIG_DEBUG_FS
7351         unregister_netdevice_notifier(&stmmac_notifier);
7352         debugfs_remove_recursive(stmmac_fs_dir);
7353 #endif
7354 }
7355
7356 module_init(stmmac_init)
7357 module_exit(stmmac_exit)
7358
7359 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7360 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7361 MODULE_LICENSE("GPL");