1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/prefetch.h>
32 #include <linux/pinctrl/consumer.h>
33 #ifdef CONFIG_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/seq_file.h>
36 #endif /* CONFIG_DEBUG_FS */
37 #include <linux/net_tstamp.h>
38 #include <linux/phylink.h>
39 #include <net/pkt_cls.h>
40 #include "stmmac_ptp.h"
42 #include <linux/reset.h>
43 #include <linux/of_mdio.h>
44 #include "dwmac1000.h"
48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
51 /* Module parameters */
53 static int watchdog = TX_TIMEO;
54 module_param(watchdog, int, 0644);
55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
57 static int debug = -1;
58 module_param(debug, int, 0644);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static int phyaddr = -1;
62 module_param(phyaddr, int, 0444);
63 MODULE_PARM_DESC(phyaddr, "Physical device address");
65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
68 static int flow_ctrl = FLOW_AUTO;
69 module_param(flow_ctrl, int, 0644);
70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
72 static int pause = PAUSE_TIME;
73 module_param(pause, int, 0644);
74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
77 static int tc = TC_DEFAULT;
78 module_param(tc, int, 0644);
79 MODULE_PARM_DESC(tc, "DMA threshold control value");
81 #define DEFAULT_BUFSIZE 1536
82 static int buf_sz = DEFAULT_BUFSIZE;
83 module_param(buf_sz, int, 0644);
84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
86 #define STMMAC_RX_COPYBREAK 256
88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
89 NETIF_MSG_LINK | NETIF_MSG_IFUP |
90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
92 #define STMMAC_DEFAULT_LPI_TIMER 1000
93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
94 module_param(eee_timer, int, 0644);
95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
99 * but allow user to force to use the chain instead of the ring
101 static unsigned int chain_mode;
102 module_param(chain_mode, int, 0444);
103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
107 #ifdef CONFIG_DEBUG_FS
108 static int stmmac_init_fs(struct net_device *dev);
109 static void stmmac_exit_fs(struct net_device *dev);
112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
115 * stmmac_verify_args - verify the driver parameters.
116 * Description: it checks the driver parameters and set a default in case of
119 static void stmmac_verify_args(void)
121 if (unlikely(watchdog < 0))
123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
124 buf_sz = DEFAULT_BUFSIZE;
125 if (unlikely(flow_ctrl > 1))
126 flow_ctrl = FLOW_AUTO;
127 else if (likely(flow_ctrl < 0))
128 flow_ctrl = FLOW_OFF;
129 if (unlikely((pause < 0) || (pause > 0xffff)))
132 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
136 * stmmac_disable_all_queues - Disable all queues
137 * @priv: driver private structure
139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
146 for (queue = 0; queue < maxq; queue++) {
147 struct stmmac_channel *ch = &priv->channel[queue];
149 if (queue < rx_queues_cnt)
150 napi_disable(&ch->rx_napi);
151 if (queue < tx_queues_cnt)
152 napi_disable(&ch->tx_napi);
157 * stmmac_enable_all_queues - Enable all queues
158 * @priv: driver private structure
160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
167 for (queue = 0; queue < maxq; queue++) {
168 struct stmmac_channel *ch = &priv->channel[queue];
170 if (queue < rx_queues_cnt)
171 napi_enable(&ch->rx_napi);
172 if (queue < tx_queues_cnt)
173 napi_enable(&ch->tx_napi);
178 * stmmac_stop_all_queues - Stop all queues
179 * @priv: driver private structure
181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
186 for (queue = 0; queue < tx_queues_cnt; queue++)
187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
191 * stmmac_start_all_queues - Start all queues
192 * @priv: driver private structure
194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
199 for (queue = 0; queue < tx_queues_cnt; queue++)
200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
205 if (!test_bit(STMMAC_DOWN, &priv->state) &&
206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
207 queue_work(priv->wq, &priv->service_task);
210 static void stmmac_global_err(struct stmmac_priv *priv)
212 netif_carrier_off(priv->dev);
213 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
214 stmmac_service_event_schedule(priv);
218 * stmmac_clk_csr_set - dynamically set the MDC clock
219 * @priv: driver private structure
220 * Description: this is to dynamically set the MDC clock according to the csr
223 * If a specific clk_csr value is passed from the platform
224 * this means that the CSR Clock Range selection cannot be
225 * changed at run-time and it is fixed (as reported in the driver
226 * documentation). Viceversa the driver will try to set the MDC
227 * clock dynamically according to the actual clock input.
229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
233 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
235 /* Platform provided default clk_csr would be assumed valid
236 * for all other cases except for the below mentioned ones.
237 * For values higher than the IEEE 802.3 specified frequency
238 * we can not estimate the proper divider as it is not known
239 * the frequency of clk_csr_i. So we do not change the default
242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
243 if (clk_rate < CSR_F_35M)
244 priv->clk_csr = STMMAC_CSR_20_35M;
245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
246 priv->clk_csr = STMMAC_CSR_35_60M;
247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
248 priv->clk_csr = STMMAC_CSR_60_100M;
249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
250 priv->clk_csr = STMMAC_CSR_100_150M;
251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
252 priv->clk_csr = STMMAC_CSR_150_250M;
253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
254 priv->clk_csr = STMMAC_CSR_250_300M;
257 if (priv->plat->has_sun8i) {
258 if (clk_rate > 160000000)
259 priv->clk_csr = 0x03;
260 else if (clk_rate > 80000000)
261 priv->clk_csr = 0x02;
262 else if (clk_rate > 40000000)
263 priv->clk_csr = 0x01;
268 if (priv->plat->has_xgmac) {
269 if (clk_rate > 400000000)
271 else if (clk_rate > 350000000)
273 else if (clk_rate > 300000000)
275 else if (clk_rate > 250000000)
277 else if (clk_rate > 150000000)
284 static void print_pkt(unsigned char *buf, int len)
286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
295 if (tx_q->dirty_tx > tx_q->cur_tx)
296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
304 * stmmac_rx_dirty - Get RX queue dirty
305 * @priv: driver private structure
306 * @queue: RX queue index
308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
313 if (rx_q->dirty_rx <= rx_q->cur_rx)
314 dirty = rx_q->cur_rx - rx_q->dirty_rx;
316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
322 * stmmac_enable_eee_mode - check and enter in LPI mode
323 * @priv: driver private structure
324 * Description: this function is to verify and enter in LPI mode in case of
327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
329 u32 tx_cnt = priv->plat->tx_queues_to_use;
332 /* check if all TX queues have the work finished */
333 for (queue = 0; queue < tx_cnt; queue++) {
334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
336 if (tx_q->dirty_tx != tx_q->cur_tx)
337 return; /* still unfinished work */
340 /* Check and enter in LPI mode */
341 if (!priv->tx_path_in_lpi_mode)
342 stmmac_set_eee_mode(priv, priv->hw,
343 priv->plat->en_tx_lpi_clockgating);
347 * stmmac_disable_eee_mode - disable and exit from LPI mode
348 * @priv: driver private structure
349 * Description: this function is to exit and disable EEE in case of
350 * LPI state is true. This is called by the xmit.
352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
354 stmmac_reset_eee_mode(priv, priv->hw);
355 del_timer_sync(&priv->eee_ctrl_timer);
356 priv->tx_path_in_lpi_mode = false;
360 * stmmac_eee_ctrl_timer - EEE TX SW timer.
363 * if there is no data transfer and if we are not in LPI state,
364 * then MAC Transmitter can be moved to LPI state.
366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
370 stmmac_enable_eee_mode(priv);
371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
375 * stmmac_eee_init - init EEE
376 * @priv: driver private structure
378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
379 * can also manage EEE, this function enable the LPI state and start related
382 bool stmmac_eee_init(struct stmmac_priv *priv)
384 int tx_lpi_timer = priv->tx_lpi_timer;
386 /* Using PCS we cannot dial with the phy registers at this stage
387 * so we do not support extra feature like EEE.
389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
390 (priv->hw->pcs == STMMAC_PCS_TBI) ||
391 (priv->hw->pcs == STMMAC_PCS_RTBI))
394 /* Check if MAC core supports the EEE feature. */
395 if (!priv->dma_cap.eee)
398 mutex_lock(&priv->lock);
400 /* Check if it needs to be deactivated */
401 if (!priv->eee_active) {
402 if (priv->eee_enabled) {
403 netdev_dbg(priv->dev, "disable EEE\n");
404 del_timer_sync(&priv->eee_ctrl_timer);
405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
407 mutex_unlock(&priv->lock);
411 if (priv->eee_active && !priv->eee_enabled) {
412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
418 mutex_unlock(&priv->lock);
419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
424 * @priv: driver private structure
425 * @p : descriptor pointer
426 * @skb : the socket buffer
428 * This function will read timestamp from the descriptor & pass it to stack.
429 * and also perform some sanity checks.
431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
432 struct dma_desc *p, struct sk_buff *skb)
434 struct skb_shared_hwtstamps shhwtstamp;
437 if (!priv->hwts_tx_en)
440 /* exit if skb doesn't support hw tstamp */
441 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
444 /* check tx tstamp status */
445 if (stmmac_get_tx_timestamp_status(priv, p)) {
446 /* get the valid tstamp */
447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
449 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
450 shhwtstamp.hwtstamp = ns_to_ktime(ns);
452 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
453 /* pass tstamp to stack */
454 skb_tstamp_tx(skb, &shhwtstamp);
460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
461 * @priv: driver private structure
462 * @p : descriptor pointer
463 * @np : next descriptor pointer
464 * @skb : the socket buffer
466 * This function will read received packet's timestamp from the descriptor
467 * and pass it to stack. It also perform some sanity checks.
469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
470 struct dma_desc *np, struct sk_buff *skb)
472 struct skb_shared_hwtstamps *shhwtstamp = NULL;
473 struct dma_desc *desc = p;
476 if (!priv->hwts_rx_en)
478 /* For GMAC4, the valid timestamp is from CTX next desc. */
479 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
482 /* Check if timestamp is available */
483 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
484 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
485 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
486 shhwtstamp = skb_hwtstamps(skb);
487 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
488 shhwtstamp->hwtstamp = ns_to_ktime(ns);
490 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
495 * stmmac_hwtstamp_set - control hardware timestamping.
496 * @dev: device pointer.
497 * @ifr: An IOCTL specific structure, that can contain a pointer to
498 * a proprietary structure used to pass information to the driver.
500 * This function configures the MAC to enable/disable both outgoing(TX)
501 * and incoming(RX) packets time stamping based on user input.
503 * 0 on success and an appropriate -ve integer on failure.
505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
507 struct stmmac_priv *priv = netdev_priv(dev);
508 struct hwtstamp_config config;
509 struct timespec64 now;
513 u32 ptp_over_ipv4_udp = 0;
514 u32 ptp_over_ipv6_udp = 0;
515 u32 ptp_over_ethernet = 0;
516 u32 snap_type_sel = 0;
517 u32 ts_master_en = 0;
523 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
525 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
526 netdev_alert(priv->dev, "No support for HW time stamping\n");
527 priv->hwts_tx_en = 0;
528 priv->hwts_rx_en = 0;
533 if (copy_from_user(&config, ifr->ifr_data,
537 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
538 __func__, config.flags, config.tx_type, config.rx_filter);
540 /* reserved for future extensions */
544 if (config.tx_type != HWTSTAMP_TX_OFF &&
545 config.tx_type != HWTSTAMP_TX_ON)
549 switch (config.rx_filter) {
550 case HWTSTAMP_FILTER_NONE:
551 /* time stamp no incoming packet at all */
552 config.rx_filter = HWTSTAMP_FILTER_NONE;
555 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
556 /* PTP v1, UDP, any kind of event packet */
557 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
558 /* 'xmac' hardware can support Sync, Pdelay_Req and
559 * Pdelay_resp by setting bit14 and bits17/16 to 01
560 * This leaves Delay_Req timestamps out.
561 * Enable all events *and* general purpose message
564 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
565 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
566 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
569 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
570 /* PTP v1, UDP, Sync packet */
571 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
572 /* take time stamp for SYNC messages only */
573 ts_event_en = PTP_TCR_TSEVNTENA;
575 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
576 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
579 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
580 /* PTP v1, UDP, Delay_req packet */
581 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
582 /* take time stamp for Delay_Req messages only */
583 ts_master_en = PTP_TCR_TSMSTRENA;
584 ts_event_en = PTP_TCR_TSEVNTENA;
586 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
587 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
590 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
591 /* PTP v2, UDP, any kind of event packet */
592 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
593 ptp_v2 = PTP_TCR_TSVER2ENA;
594 /* take time stamp for all event messages */
595 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
597 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
598 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
601 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
602 /* PTP v2, UDP, Sync packet */
603 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
604 ptp_v2 = PTP_TCR_TSVER2ENA;
605 /* take time stamp for SYNC messages only */
606 ts_event_en = PTP_TCR_TSEVNTENA;
608 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
609 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
612 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
613 /* PTP v2, UDP, Delay_req packet */
614 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
615 ptp_v2 = PTP_TCR_TSVER2ENA;
616 /* take time stamp for Delay_Req messages only */
617 ts_master_en = PTP_TCR_TSMSTRENA;
618 ts_event_en = PTP_TCR_TSEVNTENA;
620 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
621 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
624 case HWTSTAMP_FILTER_PTP_V2_EVENT:
625 /* PTP v2/802.AS1 any layer, any kind of event packet */
626 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
627 ptp_v2 = PTP_TCR_TSVER2ENA;
628 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
629 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
630 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
631 ptp_over_ethernet = PTP_TCR_TSIPENA;
634 case HWTSTAMP_FILTER_PTP_V2_SYNC:
635 /* PTP v2/802.AS1, any layer, Sync packet */
636 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
637 ptp_v2 = PTP_TCR_TSVER2ENA;
638 /* take time stamp for SYNC messages only */
639 ts_event_en = PTP_TCR_TSEVNTENA;
641 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
642 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
643 ptp_over_ethernet = PTP_TCR_TSIPENA;
646 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
647 /* PTP v2/802.AS1, any layer, Delay_req packet */
648 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
649 ptp_v2 = PTP_TCR_TSVER2ENA;
650 /* take time stamp for Delay_Req messages only */
651 ts_master_en = PTP_TCR_TSMSTRENA;
652 ts_event_en = PTP_TCR_TSEVNTENA;
654 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
655 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
656 ptp_over_ethernet = PTP_TCR_TSIPENA;
659 case HWTSTAMP_FILTER_NTP_ALL:
660 case HWTSTAMP_FILTER_ALL:
661 /* time stamp any incoming packet */
662 config.rx_filter = HWTSTAMP_FILTER_ALL;
663 tstamp_all = PTP_TCR_TSENALL;
670 switch (config.rx_filter) {
671 case HWTSTAMP_FILTER_NONE:
672 config.rx_filter = HWTSTAMP_FILTER_NONE;
675 /* PTP v1, UDP, any kind of event packet */
676 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
680 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
681 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
683 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
684 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
686 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
687 tstamp_all | ptp_v2 | ptp_over_ethernet |
688 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
689 ts_master_en | snap_type_sel);
690 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
692 /* program Sub Second Increment reg */
693 stmmac_config_sub_second_increment(priv,
694 priv->ptpaddr, priv->plat->clk_ptp_rate,
696 temp = div_u64(1000000000ULL, sec_inc);
698 /* Store sub second increment and flags for later use */
699 priv->sub_second_inc = sec_inc;
700 priv->systime_flags = value;
702 /* calculate default added value:
704 * addend = (2^32)/freq_div_ratio;
705 * where, freq_div_ratio = 1e9ns/sec_inc
707 temp = (u64)(temp << 32);
708 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
709 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
711 /* initialize system time */
712 ktime_get_real_ts64(&now);
714 /* lower 32 bits of tv_sec are safe until y2106 */
715 stmmac_init_systime(priv, priv->ptpaddr,
716 (u32)now.tv_sec, now.tv_nsec);
719 memcpy(&priv->tstamp_config, &config, sizeof(config));
721 return copy_to_user(ifr->ifr_data, &config,
722 sizeof(config)) ? -EFAULT : 0;
726 * stmmac_hwtstamp_get - read hardware timestamping.
727 * @dev: device pointer.
728 * @ifr: An IOCTL specific structure, that can contain a pointer to
729 * a proprietary structure used to pass information to the driver.
731 * This function obtain the current hardware timestamping settings
734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
736 struct stmmac_priv *priv = netdev_priv(dev);
737 struct hwtstamp_config *config = &priv->tstamp_config;
739 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
742 return copy_to_user(ifr->ifr_data, config,
743 sizeof(*config)) ? -EFAULT : 0;
747 * stmmac_init_ptp - init PTP
748 * @priv: driver private structure
749 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
750 * This is done by looking at the HW cap. register.
751 * This function also registers the ptp driver.
753 static int stmmac_init_ptp(struct stmmac_priv *priv)
755 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
757 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
761 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
762 if (xmac && priv->dma_cap.atime_stamp)
764 /* Dwmac 3.x core with extend_desc can support adv_ts */
765 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
768 if (priv->dma_cap.time_stamp)
769 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
772 netdev_info(priv->dev,
773 "IEEE 1588-2008 Advanced Timestamp supported\n");
775 priv->hwts_tx_en = 0;
776 priv->hwts_rx_en = 0;
778 stmmac_ptp_register(priv);
783 static void stmmac_release_ptp(struct stmmac_priv *priv)
785 if (priv->plat->clk_ptp_ref)
786 clk_disable_unprepare(priv->plat->clk_ptp_ref);
787 stmmac_ptp_unregister(priv);
791 * stmmac_mac_flow_ctrl - Configure flow control in all queues
792 * @priv: driver private structure
793 * Description: It is used for configuring the flow control in all queues
795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
797 u32 tx_cnt = priv->plat->tx_queues_to_use;
799 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
800 priv->pause, tx_cnt);
803 static void stmmac_validate(struct phylink_config *config,
804 unsigned long *supported,
805 struct phylink_link_state *state)
807 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
808 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
809 int tx_cnt = priv->plat->tx_queues_to_use;
810 int max_speed = priv->plat->max_speed;
812 /* Cut down 1G if asked to */
813 if ((max_speed > 0) && (max_speed < 1000)) {
814 phylink_set(mask, 1000baseT_Full);
815 phylink_set(mask, 1000baseX_Full);
818 /* Half-Duplex can only work with single queue */
820 phylink_set(mask, 10baseT_Half);
821 phylink_set(mask, 100baseT_Half);
822 phylink_set(mask, 1000baseT_Half);
825 bitmap_andnot(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
826 bitmap_andnot(state->advertising, state->advertising, mask,
827 __ETHTOOL_LINK_MODE_MASK_NBITS);
830 static int stmmac_mac_link_state(struct phylink_config *config,
831 struct phylink_link_state *state)
836 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
837 const struct phylink_link_state *state)
839 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
842 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
843 ctrl &= ~priv->hw->link.speed_mask;
845 switch (state->speed) {
847 ctrl |= priv->hw->link.speed1000;
850 ctrl |= priv->hw->link.speed100;
853 ctrl |= priv->hw->link.speed10;
859 priv->speed = state->speed;
861 if (priv->plat->fix_mac_speed)
862 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
865 ctrl &= ~priv->hw->link.duplex;
867 ctrl |= priv->hw->link.duplex;
869 /* Flow Control operation */
871 stmmac_mac_flow_ctrl(priv, state->duplex);
873 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
876 static void stmmac_mac_an_restart(struct phylink_config *config)
881 static void stmmac_mac_link_down(struct phylink_config *config,
882 unsigned int mode, phy_interface_t interface)
884 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
886 stmmac_mac_set(priv, priv->ioaddr, false);
887 priv->eee_active = false;
888 stmmac_eee_init(priv);
889 stmmac_set_eee_pls(priv, priv->hw, false);
892 static void stmmac_mac_link_up(struct phylink_config *config,
893 unsigned int mode, phy_interface_t interface,
894 struct phy_device *phy)
896 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
898 stmmac_mac_set(priv, priv->ioaddr, true);
900 priv->eee_active = phy_init_eee(phy, 1) >= 0;
901 priv->eee_enabled = stmmac_eee_init(priv);
902 stmmac_set_eee_pls(priv, priv->hw, true);
906 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
907 .validate = stmmac_validate,
908 .mac_link_state = stmmac_mac_link_state,
909 .mac_config = stmmac_mac_config,
910 .mac_an_restart = stmmac_mac_an_restart,
911 .mac_link_down = stmmac_mac_link_down,
912 .mac_link_up = stmmac_mac_link_up,
916 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
917 * @priv: driver private structure
918 * Description: this is to verify if the HW supports the PCS.
919 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
920 * configured for the TBI, RTBI, or SGMII PHY interface.
922 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
924 int interface = priv->plat->interface;
926 if (priv->dma_cap.pcs) {
927 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
928 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
929 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
930 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
931 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
932 priv->hw->pcs = STMMAC_PCS_RGMII;
933 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
934 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
935 priv->hw->pcs = STMMAC_PCS_SGMII;
941 * stmmac_init_phy - PHY initialization
942 * @dev: net device structure
943 * Description: it initializes the driver's PHY state, and attaches the PHY
948 static int stmmac_init_phy(struct net_device *dev)
950 struct stmmac_priv *priv = netdev_priv(dev);
951 struct device_node *node;
954 node = priv->plat->phylink_node;
957 ret = phylink_of_phy_connect(priv->phylink, node, 0);
959 int addr = priv->plat->phy_addr;
960 struct phy_device *phydev;
962 phydev = mdiobus_get_phy(priv->mii, addr);
964 netdev_err(priv->dev, "no phy at addr %d\n", addr);
968 ret = phylink_connect_phy(priv->phylink, phydev);
974 static int stmmac_phy_setup(struct stmmac_priv *priv)
976 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
977 int mode = priv->plat->interface;
978 struct phylink *phylink;
980 priv->phylink_config.dev = &priv->dev->dev;
981 priv->phylink_config.type = PHYLINK_NETDEV;
983 phylink = phylink_create(&priv->phylink_config, fwnode,
984 mode, &stmmac_phylink_mac_ops);
986 return PTR_ERR(phylink);
988 priv->phylink = phylink;
992 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
994 u32 rx_cnt = priv->plat->rx_queues_to_use;
998 /* Display RX rings */
999 for (queue = 0; queue < rx_cnt; queue++) {
1000 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1002 pr_info("\tRX Queue %u rings\n", queue);
1004 if (priv->extend_desc)
1005 head_rx = (void *)rx_q->dma_erx;
1007 head_rx = (void *)rx_q->dma_rx;
1009 /* Display RX ring */
1010 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1014 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1016 u32 tx_cnt = priv->plat->tx_queues_to_use;
1020 /* Display TX rings */
1021 for (queue = 0; queue < tx_cnt; queue++) {
1022 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1024 pr_info("\tTX Queue %d rings\n", queue);
1026 if (priv->extend_desc)
1027 head_tx = (void *)tx_q->dma_etx;
1029 head_tx = (void *)tx_q->dma_tx;
1031 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1035 static void stmmac_display_rings(struct stmmac_priv *priv)
1037 /* Display RX ring */
1038 stmmac_display_rx_rings(priv);
1040 /* Display TX ring */
1041 stmmac_display_tx_rings(priv);
1044 static int stmmac_set_bfsize(int mtu, int bufsize)
1048 if (mtu >= BUF_SIZE_4KiB)
1049 ret = BUF_SIZE_8KiB;
1050 else if (mtu >= BUF_SIZE_2KiB)
1051 ret = BUF_SIZE_4KiB;
1052 else if (mtu > DEFAULT_BUFSIZE)
1053 ret = BUF_SIZE_2KiB;
1055 ret = DEFAULT_BUFSIZE;
1061 * stmmac_clear_rx_descriptors - clear RX descriptors
1062 * @priv: driver private structure
1063 * @queue: RX queue index
1064 * Description: this function is called to clear the RX descriptors
1065 * in case of both basic and extended descriptors are used.
1067 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1069 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1072 /* Clear the RX descriptors */
1073 for (i = 0; i < DMA_RX_SIZE; i++)
1074 if (priv->extend_desc)
1075 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1076 priv->use_riwt, priv->mode,
1077 (i == DMA_RX_SIZE - 1),
1080 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1081 priv->use_riwt, priv->mode,
1082 (i == DMA_RX_SIZE - 1),
1087 * stmmac_clear_tx_descriptors - clear tx descriptors
1088 * @priv: driver private structure
1089 * @queue: TX queue index.
1090 * Description: this function is called to clear the TX descriptors
1091 * in case of both basic and extended descriptors are used.
1093 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1095 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1098 /* Clear the TX descriptors */
1099 for (i = 0; i < DMA_TX_SIZE; i++)
1100 if (priv->extend_desc)
1101 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1102 priv->mode, (i == DMA_TX_SIZE - 1));
1104 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1105 priv->mode, (i == DMA_TX_SIZE - 1));
1109 * stmmac_clear_descriptors - clear descriptors
1110 * @priv: driver private structure
1111 * Description: this function is called to clear the TX and RX descriptors
1112 * in case of both basic and extended descriptors are used.
1114 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1116 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1117 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1120 /* Clear the RX descriptors */
1121 for (queue = 0; queue < rx_queue_cnt; queue++)
1122 stmmac_clear_rx_descriptors(priv, queue);
1124 /* Clear the TX descriptors */
1125 for (queue = 0; queue < tx_queue_cnt; queue++)
1126 stmmac_clear_tx_descriptors(priv, queue);
1130 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1131 * @priv: driver private structure
1132 * @p: descriptor pointer
1133 * @i: descriptor index
1135 * @queue: RX queue index
1136 * Description: this function is called to allocate a receive buffer, perform
1137 * the DMA mapping and init the descriptor.
1139 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1140 int i, gfp_t flags, u32 queue)
1142 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1143 struct sk_buff *skb;
1145 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1147 netdev_err(priv->dev,
1148 "%s: Rx init fails; skb is NULL\n", __func__);
1151 rx_q->rx_skbuff[i] = skb;
1152 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1155 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1156 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1157 dev_kfree_skb_any(skb);
1161 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1163 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1164 stmmac_init_desc3(priv, p);
1170 * stmmac_free_rx_buffer - free RX dma buffers
1171 * @priv: private structure
1172 * @queue: RX queue index
1175 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1177 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1179 if (rx_q->rx_skbuff[i]) {
1180 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1181 priv->dma_buf_sz, DMA_FROM_DEVICE);
1182 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1184 rx_q->rx_skbuff[i] = NULL;
1188 * stmmac_free_tx_buffer - free RX dma buffers
1189 * @priv: private structure
1190 * @queue: RX queue index
1193 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1195 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1197 if (tx_q->tx_skbuff_dma[i].buf) {
1198 if (tx_q->tx_skbuff_dma[i].map_as_page)
1199 dma_unmap_page(priv->device,
1200 tx_q->tx_skbuff_dma[i].buf,
1201 tx_q->tx_skbuff_dma[i].len,
1204 dma_unmap_single(priv->device,
1205 tx_q->tx_skbuff_dma[i].buf,
1206 tx_q->tx_skbuff_dma[i].len,
1210 if (tx_q->tx_skbuff[i]) {
1211 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1212 tx_q->tx_skbuff[i] = NULL;
1213 tx_q->tx_skbuff_dma[i].buf = 0;
1214 tx_q->tx_skbuff_dma[i].map_as_page = false;
1219 * init_dma_rx_desc_rings - init the RX descriptor rings
1220 * @dev: net device structure
1222 * Description: this function initializes the DMA RX descriptors
1223 * and allocates the socket buffers. It supports the chained and ring
1226 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1228 struct stmmac_priv *priv = netdev_priv(dev);
1229 u32 rx_count = priv->plat->rx_queues_to_use;
1235 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1239 if (bfsize < BUF_SIZE_16KiB)
1240 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1242 priv->dma_buf_sz = bfsize;
1244 /* RX INITIALIZATION */
1245 netif_dbg(priv, probe, priv->dev,
1246 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1248 for (queue = 0; queue < rx_count; queue++) {
1249 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1251 netif_dbg(priv, probe, priv->dev,
1252 "(%s) dma_rx_phy=0x%08x\n", __func__,
1253 (u32)rx_q->dma_rx_phy);
1255 for (i = 0; i < DMA_RX_SIZE; i++) {
1258 if (priv->extend_desc)
1259 p = &((rx_q->dma_erx + i)->basic);
1261 p = rx_q->dma_rx + i;
1263 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1266 goto err_init_rx_buffers;
1268 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1269 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1270 (unsigned int)rx_q->rx_skbuff_dma[i]);
1274 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1276 stmmac_clear_rx_descriptors(priv, queue);
1278 /* Setup the chained descriptor addresses */
1279 if (priv->mode == STMMAC_CHAIN_MODE) {
1280 if (priv->extend_desc)
1281 stmmac_mode_init(priv, rx_q->dma_erx,
1282 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1284 stmmac_mode_init(priv, rx_q->dma_rx,
1285 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1293 err_init_rx_buffers:
1294 while (queue >= 0) {
1296 stmmac_free_rx_buffer(priv, queue, i);
1309 * init_dma_tx_desc_rings - init the TX descriptor rings
1310 * @dev: net device structure.
1311 * Description: this function initializes the DMA TX descriptors
1312 * and allocates the socket buffers. It supports the chained and ring
1315 static int init_dma_tx_desc_rings(struct net_device *dev)
1317 struct stmmac_priv *priv = netdev_priv(dev);
1318 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1322 for (queue = 0; queue < tx_queue_cnt; queue++) {
1323 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1325 netif_dbg(priv, probe, priv->dev,
1326 "(%s) dma_tx_phy=0x%08x\n", __func__,
1327 (u32)tx_q->dma_tx_phy);
1329 /* Setup the chained descriptor addresses */
1330 if (priv->mode == STMMAC_CHAIN_MODE) {
1331 if (priv->extend_desc)
1332 stmmac_mode_init(priv, tx_q->dma_etx,
1333 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1335 stmmac_mode_init(priv, tx_q->dma_tx,
1336 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1339 for (i = 0; i < DMA_TX_SIZE; i++) {
1341 if (priv->extend_desc)
1342 p = &((tx_q->dma_etx + i)->basic);
1344 p = tx_q->dma_tx + i;
1346 stmmac_clear_desc(priv, p);
1348 tx_q->tx_skbuff_dma[i].buf = 0;
1349 tx_q->tx_skbuff_dma[i].map_as_page = false;
1350 tx_q->tx_skbuff_dma[i].len = 0;
1351 tx_q->tx_skbuff_dma[i].last_segment = false;
1352 tx_q->tx_skbuff[i] = NULL;
1359 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1366 * init_dma_desc_rings - init the RX/TX descriptor rings
1367 * @dev: net device structure
1369 * Description: this function initializes the DMA RX/TX descriptors
1370 * and allocates the socket buffers. It supports the chained and ring
1373 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1375 struct stmmac_priv *priv = netdev_priv(dev);
1378 ret = init_dma_rx_desc_rings(dev, flags);
1382 ret = init_dma_tx_desc_rings(dev);
1384 stmmac_clear_descriptors(priv);
1386 if (netif_msg_hw(priv))
1387 stmmac_display_rings(priv);
1393 * dma_free_rx_skbufs - free RX dma buffers
1394 * @priv: private structure
1395 * @queue: RX queue index
1397 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1401 for (i = 0; i < DMA_RX_SIZE; i++)
1402 stmmac_free_rx_buffer(priv, queue, i);
1406 * dma_free_tx_skbufs - free TX dma buffers
1407 * @priv: private structure
1408 * @queue: TX queue index
1410 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1414 for (i = 0; i < DMA_TX_SIZE; i++)
1415 stmmac_free_tx_buffer(priv, queue, i);
1419 * free_dma_rx_desc_resources - free RX dma desc resources
1420 * @priv: private structure
1422 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1424 u32 rx_count = priv->plat->rx_queues_to_use;
1427 /* Free RX queue resources */
1428 for (queue = 0; queue < rx_count; queue++) {
1429 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1431 /* Release the DMA RX socket buffers */
1432 dma_free_rx_skbufs(priv, queue);
1434 /* Free DMA regions of consistent memory previously allocated */
1435 if (!priv->extend_desc)
1436 dma_free_coherent(priv->device,
1437 DMA_RX_SIZE * sizeof(struct dma_desc),
1438 rx_q->dma_rx, rx_q->dma_rx_phy);
1440 dma_free_coherent(priv->device, DMA_RX_SIZE *
1441 sizeof(struct dma_extended_desc),
1442 rx_q->dma_erx, rx_q->dma_rx_phy);
1444 kfree(rx_q->rx_skbuff_dma);
1445 kfree(rx_q->rx_skbuff);
1450 * free_dma_tx_desc_resources - free TX dma desc resources
1451 * @priv: private structure
1453 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1455 u32 tx_count = priv->plat->tx_queues_to_use;
1458 /* Free TX queue resources */
1459 for (queue = 0; queue < tx_count; queue++) {
1460 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1462 /* Release the DMA TX socket buffers */
1463 dma_free_tx_skbufs(priv, queue);
1465 /* Free DMA regions of consistent memory previously allocated */
1466 if (!priv->extend_desc)
1467 dma_free_coherent(priv->device,
1468 DMA_TX_SIZE * sizeof(struct dma_desc),
1469 tx_q->dma_tx, tx_q->dma_tx_phy);
1471 dma_free_coherent(priv->device, DMA_TX_SIZE *
1472 sizeof(struct dma_extended_desc),
1473 tx_q->dma_etx, tx_q->dma_tx_phy);
1475 kfree(tx_q->tx_skbuff_dma);
1476 kfree(tx_q->tx_skbuff);
1481 * alloc_dma_rx_desc_resources - alloc RX resources.
1482 * @priv: private structure
1483 * Description: according to which descriptor can be used (extend or basic)
1484 * this function allocates the resources for TX and RX paths. In case of
1485 * reception, for example, it pre-allocated the RX socket buffer in order to
1486 * allow zero-copy mechanism.
1488 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1490 u32 rx_count = priv->plat->rx_queues_to_use;
1494 /* RX queues buffers and DMA */
1495 for (queue = 0; queue < rx_count; queue++) {
1496 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1498 rx_q->queue_index = queue;
1499 rx_q->priv_data = priv;
1501 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1504 if (!rx_q->rx_skbuff_dma)
1507 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1508 sizeof(struct sk_buff *),
1510 if (!rx_q->rx_skbuff)
1513 if (priv->extend_desc) {
1514 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1515 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1522 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1523 DMA_RX_SIZE * sizeof(struct dma_desc),
1534 free_dma_rx_desc_resources(priv);
1540 * alloc_dma_tx_desc_resources - alloc TX resources.
1541 * @priv: private structure
1542 * Description: according to which descriptor can be used (extend or basic)
1543 * this function allocates the resources for TX and RX paths. In case of
1544 * reception, for example, it pre-allocated the RX socket buffer in order to
1545 * allow zero-copy mechanism.
1547 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1549 u32 tx_count = priv->plat->tx_queues_to_use;
1553 /* TX queues buffers and DMA */
1554 for (queue = 0; queue < tx_count; queue++) {
1555 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1557 tx_q->queue_index = queue;
1558 tx_q->priv_data = priv;
1560 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1561 sizeof(*tx_q->tx_skbuff_dma),
1563 if (!tx_q->tx_skbuff_dma)
1566 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1567 sizeof(struct sk_buff *),
1569 if (!tx_q->tx_skbuff)
1572 if (priv->extend_desc) {
1573 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1574 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1580 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1581 DMA_TX_SIZE * sizeof(struct dma_desc),
1592 free_dma_tx_desc_resources(priv);
1598 * alloc_dma_desc_resources - alloc TX/RX resources.
1599 * @priv: private structure
1600 * Description: according to which descriptor can be used (extend or basic)
1601 * this function allocates the resources for TX and RX paths. In case of
1602 * reception, for example, it pre-allocated the RX socket buffer in order to
1603 * allow zero-copy mechanism.
1605 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1608 int ret = alloc_dma_rx_desc_resources(priv);
1613 ret = alloc_dma_tx_desc_resources(priv);
1619 * free_dma_desc_resources - free dma desc resources
1620 * @priv: private structure
1622 static void free_dma_desc_resources(struct stmmac_priv *priv)
1624 /* Release the DMA RX socket buffers */
1625 free_dma_rx_desc_resources(priv);
1627 /* Release the DMA TX socket buffers */
1628 free_dma_tx_desc_resources(priv);
1632 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1633 * @priv: driver private structure
1634 * Description: It is used for enabling the rx queues in the MAC
1636 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1638 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1642 for (queue = 0; queue < rx_queues_count; queue++) {
1643 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1644 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1649 * stmmac_start_rx_dma - start RX DMA channel
1650 * @priv: driver private structure
1651 * @chan: RX channel index
1653 * This starts a RX DMA channel
1655 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1657 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1658 stmmac_start_rx(priv, priv->ioaddr, chan);
1662 * stmmac_start_tx_dma - start TX DMA channel
1663 * @priv: driver private structure
1664 * @chan: TX channel index
1666 * This starts a TX DMA channel
1668 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1670 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1671 stmmac_start_tx(priv, priv->ioaddr, chan);
1675 * stmmac_stop_rx_dma - stop RX DMA channel
1676 * @priv: driver private structure
1677 * @chan: RX channel index
1679 * This stops a RX DMA channel
1681 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1683 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1684 stmmac_stop_rx(priv, priv->ioaddr, chan);
1688 * stmmac_stop_tx_dma - stop TX DMA channel
1689 * @priv: driver private structure
1690 * @chan: TX channel index
1692 * This stops a TX DMA channel
1694 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1696 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1697 stmmac_stop_tx(priv, priv->ioaddr, chan);
1701 * stmmac_start_all_dma - start all RX and TX DMA channels
1702 * @priv: driver private structure
1704 * This starts all the RX and TX DMA channels
1706 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1708 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1709 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1712 for (chan = 0; chan < rx_channels_count; chan++)
1713 stmmac_start_rx_dma(priv, chan);
1715 for (chan = 0; chan < tx_channels_count; chan++)
1716 stmmac_start_tx_dma(priv, chan);
1720 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1721 * @priv: driver private structure
1723 * This stops the RX and TX DMA channels
1725 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1727 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1728 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1731 for (chan = 0; chan < rx_channels_count; chan++)
1732 stmmac_stop_rx_dma(priv, chan);
1734 for (chan = 0; chan < tx_channels_count; chan++)
1735 stmmac_stop_tx_dma(priv, chan);
1739 * stmmac_dma_operation_mode - HW DMA operation mode
1740 * @priv: driver private structure
1741 * Description: it is used for configuring the DMA operation mode register in
1742 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1744 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1746 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1747 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1748 int rxfifosz = priv->plat->rx_fifo_size;
1749 int txfifosz = priv->plat->tx_fifo_size;
1756 rxfifosz = priv->dma_cap.rx_fifo_size;
1758 txfifosz = priv->dma_cap.tx_fifo_size;
1760 /* Adjust for real per queue fifo size */
1761 rxfifosz /= rx_channels_count;
1762 txfifosz /= tx_channels_count;
1764 if (priv->plat->force_thresh_dma_mode) {
1767 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1769 * In case of GMAC, SF mode can be enabled
1770 * to perform the TX COE in HW. This depends on:
1771 * 1) TX COE if actually supported
1772 * 2) There is no bugged Jumbo frame support
1773 * that needs to not insert csum in the TDES.
1775 txmode = SF_DMA_MODE;
1776 rxmode = SF_DMA_MODE;
1777 priv->xstats.threshold = SF_DMA_MODE;
1780 rxmode = SF_DMA_MODE;
1783 /* configure all channels */
1784 for (chan = 0; chan < rx_channels_count; chan++) {
1785 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1787 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1789 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1793 for (chan = 0; chan < tx_channels_count; chan++) {
1794 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1796 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1802 * stmmac_tx_clean - to manage the transmission completion
1803 * @priv: driver private structure
1804 * @queue: TX queue index
1805 * Description: it reclaims the transmit resources after transmission completes.
1807 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1809 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1810 unsigned int bytes_compl = 0, pkts_compl = 0;
1811 unsigned int entry, count = 0;
1813 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1815 priv->xstats.tx_clean++;
1817 entry = tx_q->dirty_tx;
1818 while ((entry != tx_q->cur_tx) && (count < budget)) {
1819 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1823 if (priv->extend_desc)
1824 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1826 p = tx_q->dma_tx + entry;
1828 status = stmmac_tx_status(priv, &priv->dev->stats,
1829 &priv->xstats, p, priv->ioaddr);
1830 /* Check if the descriptor is owned by the DMA */
1831 if (unlikely(status & tx_dma_own))
1836 /* Make sure descriptor fields are read after reading
1841 /* Just consider the last segment and ...*/
1842 if (likely(!(status & tx_not_ls))) {
1843 /* ... verify the status error condition */
1844 if (unlikely(status & tx_err)) {
1845 priv->dev->stats.tx_errors++;
1847 priv->dev->stats.tx_packets++;
1848 priv->xstats.tx_pkt_n++;
1850 stmmac_get_tx_hwtstamp(priv, p, skb);
1853 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1854 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1855 dma_unmap_page(priv->device,
1856 tx_q->tx_skbuff_dma[entry].buf,
1857 tx_q->tx_skbuff_dma[entry].len,
1860 dma_unmap_single(priv->device,
1861 tx_q->tx_skbuff_dma[entry].buf,
1862 tx_q->tx_skbuff_dma[entry].len,
1864 tx_q->tx_skbuff_dma[entry].buf = 0;
1865 tx_q->tx_skbuff_dma[entry].len = 0;
1866 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1869 stmmac_clean_desc3(priv, tx_q, p);
1871 tx_q->tx_skbuff_dma[entry].last_segment = false;
1872 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1874 if (likely(skb != NULL)) {
1876 bytes_compl += skb->len;
1877 dev_consume_skb_any(skb);
1878 tx_q->tx_skbuff[entry] = NULL;
1881 stmmac_release_tx_desc(priv, p, priv->mode);
1883 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1885 tx_q->dirty_tx = entry;
1887 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1888 pkts_compl, bytes_compl);
1890 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1892 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1894 netif_dbg(priv, tx_done, priv->dev,
1895 "%s: restart transmit\n", __func__);
1896 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1899 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1900 stmmac_enable_eee_mode(priv);
1901 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1904 /* We still have pending packets, let's call for a new scheduling */
1905 if (tx_q->dirty_tx != tx_q->cur_tx)
1906 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1908 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1914 * stmmac_tx_err - to manage the tx error
1915 * @priv: driver private structure
1916 * @chan: channel index
1917 * Description: it cleans the descriptors and restarts the transmission
1918 * in case of transmission errors.
1920 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1922 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1925 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1927 stmmac_stop_tx_dma(priv, chan);
1928 dma_free_tx_skbufs(priv, chan);
1929 for (i = 0; i < DMA_TX_SIZE; i++)
1930 if (priv->extend_desc)
1931 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1932 priv->mode, (i == DMA_TX_SIZE - 1));
1934 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1935 priv->mode, (i == DMA_TX_SIZE - 1));
1939 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1940 stmmac_start_tx_dma(priv, chan);
1942 priv->dev->stats.tx_errors++;
1943 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1947 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1948 * @priv: driver private structure
1949 * @txmode: TX operating mode
1950 * @rxmode: RX operating mode
1951 * @chan: channel index
1952 * Description: it is used for configuring of the DMA operation mode in
1953 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1956 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1957 u32 rxmode, u32 chan)
1959 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1960 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1961 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1962 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1963 int rxfifosz = priv->plat->rx_fifo_size;
1964 int txfifosz = priv->plat->tx_fifo_size;
1967 rxfifosz = priv->dma_cap.rx_fifo_size;
1969 txfifosz = priv->dma_cap.tx_fifo_size;
1971 /* Adjust for real per queue fifo size */
1972 rxfifosz /= rx_channels_count;
1973 txfifosz /= tx_channels_count;
1975 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
1976 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
1979 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
1983 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
1984 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
1985 if (ret && (ret != -EINVAL)) {
1986 stmmac_global_err(priv);
1993 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
1995 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
1996 &priv->xstats, chan);
1997 struct stmmac_channel *ch = &priv->channel[chan];
2000 status |= handle_rx | handle_tx;
2002 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2003 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2004 napi_schedule_irqoff(&ch->rx_napi);
2007 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2008 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2009 napi_schedule_irqoff(&ch->tx_napi);
2016 * stmmac_dma_interrupt - DMA ISR
2017 * @priv: driver private structure
2018 * Description: this is the DMA ISR. It is called by the main ISR.
2019 * It calls the dwmac dma routine and schedule poll method in case of some
2022 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2024 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2025 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2026 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2027 tx_channel_count : rx_channel_count;
2029 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2031 /* Make sure we never check beyond our status buffer. */
2032 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2033 channels_to_check = ARRAY_SIZE(status);
2035 for (chan = 0; chan < channels_to_check; chan++)
2036 status[chan] = stmmac_napi_check(priv, chan);
2038 for (chan = 0; chan < tx_channel_count; chan++) {
2039 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2040 /* Try to bump up the dma threshold on this failure */
2041 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2044 if (priv->plat->force_thresh_dma_mode)
2045 stmmac_set_dma_operation_mode(priv,
2050 stmmac_set_dma_operation_mode(priv,
2054 priv->xstats.threshold = tc;
2056 } else if (unlikely(status[chan] == tx_hard_error)) {
2057 stmmac_tx_err(priv, chan);
2063 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2064 * @priv: driver private structure
2065 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2067 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2069 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2070 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2072 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2074 if (priv->dma_cap.rmon) {
2075 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2076 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2078 netdev_info(priv->dev, "No MAC Management Counters available\n");
2082 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2083 * @priv: driver private structure
2085 * new GMAC chip generations have a new register to indicate the
2086 * presence of the optional feature/functions.
2087 * This can be also used to override the value passed through the
2088 * platform and necessary for old MAC10/100 and GMAC chips.
2090 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2092 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2096 * stmmac_check_ether_addr - check if the MAC addr is valid
2097 * @priv: driver private structure
2099 * it is to verify if the MAC address is valid, in case of failures it
2100 * generates a random MAC address
2102 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2104 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2105 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2106 if (!is_valid_ether_addr(priv->dev->dev_addr))
2107 eth_hw_addr_random(priv->dev);
2108 dev_info(priv->device, "device MAC address %pM\n",
2109 priv->dev->dev_addr);
2114 * stmmac_init_dma_engine - DMA init.
2115 * @priv: driver private structure
2117 * It inits the DMA invoking the specific MAC/GMAC callback.
2118 * Some DMA parameters can be passed from the platform;
2119 * in case of these are not passed a default is kept for the MAC or GMAC.
2121 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2123 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2124 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2125 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2126 struct stmmac_rx_queue *rx_q;
2127 struct stmmac_tx_queue *tx_q;
2132 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2133 dev_err(priv->device, "Invalid DMA configuration\n");
2137 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2140 ret = stmmac_reset(priv, priv->ioaddr);
2142 dev_err(priv->device, "Failed to reset the dma\n");
2146 /* DMA Configuration */
2147 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2149 if (priv->plat->axi)
2150 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2152 /* DMA CSR Channel configuration */
2153 for (chan = 0; chan < dma_csr_ch; chan++)
2154 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2156 /* DMA RX Channel Configuration */
2157 for (chan = 0; chan < rx_channels_count; chan++) {
2158 rx_q = &priv->rx_queue[chan];
2160 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2161 rx_q->dma_rx_phy, chan);
2163 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2164 (DMA_RX_SIZE * sizeof(struct dma_desc));
2165 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2166 rx_q->rx_tail_addr, chan);
2169 /* DMA TX Channel Configuration */
2170 for (chan = 0; chan < tx_channels_count; chan++) {
2171 tx_q = &priv->tx_queue[chan];
2173 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2174 tx_q->dma_tx_phy, chan);
2176 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2177 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2178 tx_q->tx_tail_addr, chan);
2184 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2186 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2188 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2192 * stmmac_tx_timer - mitigation sw timer for tx.
2193 * @data: data pointer
2195 * This is the timer handler to directly invoke the stmmac_tx_clean.
2197 static void stmmac_tx_timer(struct timer_list *t)
2199 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2200 struct stmmac_priv *priv = tx_q->priv_data;
2201 struct stmmac_channel *ch;
2203 ch = &priv->channel[tx_q->queue_index];
2206 * If NAPI is already running we can miss some events. Let's rearm
2207 * the timer and try again.
2209 if (likely(napi_schedule_prep(&ch->tx_napi)))
2210 __napi_schedule(&ch->tx_napi);
2212 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2216 * stmmac_init_tx_coalesce - init tx mitigation options.
2217 * @priv: driver private structure
2219 * This inits the transmit coalesce parameters: i.e. timer rate,
2220 * timer handler and default threshold used for enabling the
2221 * interrupt on completion bit.
2223 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2225 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2228 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2229 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2231 for (chan = 0; chan < tx_channel_count; chan++) {
2232 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2234 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2238 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2240 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2241 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2244 /* set TX ring length */
2245 for (chan = 0; chan < tx_channels_count; chan++)
2246 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2247 (DMA_TX_SIZE - 1), chan);
2249 /* set RX ring length */
2250 for (chan = 0; chan < rx_channels_count; chan++)
2251 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2252 (DMA_RX_SIZE - 1), chan);
2256 * stmmac_set_tx_queue_weight - Set TX queue weight
2257 * @priv: driver private structure
2258 * Description: It is used for setting TX queues weight
2260 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2262 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2266 for (queue = 0; queue < tx_queues_count; queue++) {
2267 weight = priv->plat->tx_queues_cfg[queue].weight;
2268 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2273 * stmmac_configure_cbs - Configure CBS in TX queue
2274 * @priv: driver private structure
2275 * Description: It is used for configuring CBS in AVB TX queues
2277 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2279 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2283 /* queue 0 is reserved for legacy traffic */
2284 for (queue = 1; queue < tx_queues_count; queue++) {
2285 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2286 if (mode_to_use == MTL_QUEUE_DCB)
2289 stmmac_config_cbs(priv, priv->hw,
2290 priv->plat->tx_queues_cfg[queue].send_slope,
2291 priv->plat->tx_queues_cfg[queue].idle_slope,
2292 priv->plat->tx_queues_cfg[queue].high_credit,
2293 priv->plat->tx_queues_cfg[queue].low_credit,
2299 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2300 * @priv: driver private structure
2301 * Description: It is used for mapping RX queues to RX dma channels
2303 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2305 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2309 for (queue = 0; queue < rx_queues_count; queue++) {
2310 chan = priv->plat->rx_queues_cfg[queue].chan;
2311 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2316 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2317 * @priv: driver private structure
2318 * Description: It is used for configuring the RX Queue Priority
2320 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2322 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2326 for (queue = 0; queue < rx_queues_count; queue++) {
2327 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2330 prio = priv->plat->rx_queues_cfg[queue].prio;
2331 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2336 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2337 * @priv: driver private structure
2338 * Description: It is used for configuring the TX Queue Priority
2340 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2342 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2346 for (queue = 0; queue < tx_queues_count; queue++) {
2347 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2350 prio = priv->plat->tx_queues_cfg[queue].prio;
2351 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2356 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2357 * @priv: driver private structure
2358 * Description: It is used for configuring the RX queue routing
2360 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2362 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2366 for (queue = 0; queue < rx_queues_count; queue++) {
2367 /* no specific packet type routing specified for the queue */
2368 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2371 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2372 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2377 * stmmac_mtl_configuration - Configure MTL
2378 * @priv: driver private structure
2379 * Description: It is used for configurring MTL
2381 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2383 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2384 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2386 if (tx_queues_count > 1)
2387 stmmac_set_tx_queue_weight(priv);
2389 /* Configure MTL RX algorithms */
2390 if (rx_queues_count > 1)
2391 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2392 priv->plat->rx_sched_algorithm);
2394 /* Configure MTL TX algorithms */
2395 if (tx_queues_count > 1)
2396 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2397 priv->plat->tx_sched_algorithm);
2399 /* Configure CBS in AVB TX queues */
2400 if (tx_queues_count > 1)
2401 stmmac_configure_cbs(priv);
2403 /* Map RX MTL to DMA channels */
2404 stmmac_rx_queue_dma_chan_map(priv);
2406 /* Enable MAC RX Queues */
2407 stmmac_mac_enable_rx_queues(priv);
2409 /* Set RX priorities */
2410 if (rx_queues_count > 1)
2411 stmmac_mac_config_rx_queues_prio(priv);
2413 /* Set TX priorities */
2414 if (tx_queues_count > 1)
2415 stmmac_mac_config_tx_queues_prio(priv);
2417 /* Set RX routing */
2418 if (rx_queues_count > 1)
2419 stmmac_mac_config_rx_queues_routing(priv);
2422 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2424 if (priv->dma_cap.asp) {
2425 netdev_info(priv->dev, "Enabling Safety Features\n");
2426 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2428 netdev_info(priv->dev, "No Safety Features support found\n");
2433 * stmmac_hw_setup - setup mac in a usable state.
2434 * @dev : pointer to the device structure.
2436 * this is the main function to setup the HW in a usable state because the
2437 * dma engine is reset, the core registers are configured (e.g. AXI,
2438 * Checksum features, timers). The DMA is ready to start receiving and
2441 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2444 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2446 struct stmmac_priv *priv = netdev_priv(dev);
2447 u32 rx_cnt = priv->plat->rx_queues_to_use;
2448 u32 tx_cnt = priv->plat->tx_queues_to_use;
2452 /* DMA initialization and SW reset */
2453 ret = stmmac_init_dma_engine(priv);
2455 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2460 /* Copy the MAC addr into the HW */
2461 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2463 /* PS and related bits will be programmed according to the speed */
2464 if (priv->hw->pcs) {
2465 int speed = priv->plat->mac_port_sel_speed;
2467 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2468 (speed == SPEED_1000)) {
2469 priv->hw->ps = speed;
2471 dev_warn(priv->device, "invalid port speed\n");
2476 /* Initialize the MAC Core */
2477 stmmac_core_init(priv, priv->hw, dev);
2480 stmmac_mtl_configuration(priv);
2482 /* Initialize Safety Features */
2483 stmmac_safety_feat_configuration(priv);
2485 ret = stmmac_rx_ipc(priv, priv->hw);
2487 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2488 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2489 priv->hw->rx_csum = 0;
2492 /* Enable the MAC Rx/Tx */
2493 stmmac_mac_set(priv, priv->ioaddr, true);
2495 /* Set the HW DMA mode and the COE */
2496 stmmac_dma_operation_mode(priv);
2498 stmmac_mmc_setup(priv);
2501 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2503 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2505 ret = stmmac_init_ptp(priv);
2506 if (ret == -EOPNOTSUPP)
2507 netdev_warn(priv->dev, "PTP not supported by HW\n");
2509 netdev_warn(priv->dev, "PTP init failed\n");
2512 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2514 if (priv->use_riwt) {
2515 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2517 priv->rx_riwt = MAX_DMA_RIWT;
2521 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2523 /* set TX and RX rings length */
2524 stmmac_set_rings_length(priv);
2528 for (chan = 0; chan < tx_cnt; chan++)
2529 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2532 /* Start the ball rolling... */
2533 stmmac_start_all_dma(priv);
2538 static void stmmac_hw_teardown(struct net_device *dev)
2540 struct stmmac_priv *priv = netdev_priv(dev);
2542 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2546 * stmmac_open - open entry point of the driver
2547 * @dev : pointer to the device structure.
2549 * This function is the open entry point of the driver.
2551 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2554 static int stmmac_open(struct net_device *dev)
2556 struct stmmac_priv *priv = netdev_priv(dev);
2560 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2561 priv->hw->pcs != STMMAC_PCS_TBI &&
2562 priv->hw->pcs != STMMAC_PCS_RTBI) {
2563 ret = stmmac_init_phy(dev);
2565 netdev_err(priv->dev,
2566 "%s: Cannot attach to PHY (error: %d)\n",
2572 /* Extra statistics */
2573 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2574 priv->xstats.threshold = tc;
2576 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2577 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2579 ret = alloc_dma_desc_resources(priv);
2581 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2583 goto dma_desc_error;
2586 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2588 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2593 ret = stmmac_hw_setup(dev, true);
2595 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2599 stmmac_init_tx_coalesce(priv);
2601 phylink_start(priv->phylink);
2603 /* Request the IRQ lines */
2604 ret = request_irq(dev->irq, stmmac_interrupt,
2605 IRQF_SHARED, dev->name, dev);
2606 if (unlikely(ret < 0)) {
2607 netdev_err(priv->dev,
2608 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2609 __func__, dev->irq, ret);
2613 /* Request the Wake IRQ in case of another line is used for WoL */
2614 if (priv->wol_irq != dev->irq) {
2615 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2616 IRQF_SHARED, dev->name, dev);
2617 if (unlikely(ret < 0)) {
2618 netdev_err(priv->dev,
2619 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2620 __func__, priv->wol_irq, ret);
2625 /* Request the IRQ lines */
2626 if (priv->lpi_irq > 0) {
2627 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2629 if (unlikely(ret < 0)) {
2630 netdev_err(priv->dev,
2631 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2632 __func__, priv->lpi_irq, ret);
2637 stmmac_enable_all_queues(priv);
2638 stmmac_start_all_queues(priv);
2643 if (priv->wol_irq != dev->irq)
2644 free_irq(priv->wol_irq, dev);
2646 free_irq(dev->irq, dev);
2648 phylink_stop(priv->phylink);
2650 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2651 del_timer_sync(&priv->tx_queue[chan].txtimer);
2653 stmmac_hw_teardown(dev);
2655 free_dma_desc_resources(priv);
2657 phylink_disconnect_phy(priv->phylink);
2662 * stmmac_release - close entry point of the driver
2663 * @dev : device pointer.
2665 * This is the stop entry point of the driver.
2667 static int stmmac_release(struct net_device *dev)
2669 struct stmmac_priv *priv = netdev_priv(dev);
2672 if (priv->eee_enabled)
2673 del_timer_sync(&priv->eee_ctrl_timer);
2675 /* Stop and disconnect the PHY */
2676 phylink_stop(priv->phylink);
2677 phylink_disconnect_phy(priv->phylink);
2679 stmmac_stop_all_queues(priv);
2681 stmmac_disable_all_queues(priv);
2683 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2684 del_timer_sync(&priv->tx_queue[chan].txtimer);
2686 /* Free the IRQ lines */
2687 free_irq(dev->irq, dev);
2688 if (priv->wol_irq != dev->irq)
2689 free_irq(priv->wol_irq, dev);
2690 if (priv->lpi_irq > 0)
2691 free_irq(priv->lpi_irq, dev);
2693 /* Stop TX/RX DMA and clear the descriptors */
2694 stmmac_stop_all_dma(priv);
2696 /* Release and free the Rx/Tx resources */
2697 free_dma_desc_resources(priv);
2699 /* Disable the MAC Rx/Tx */
2700 stmmac_mac_set(priv, priv->ioaddr, false);
2702 netif_carrier_off(dev);
2704 stmmac_release_ptp(priv);
2710 * stmmac_tso_allocator - close entry point of the driver
2711 * @priv: driver private structure
2712 * @des: buffer start address
2713 * @total_len: total length to fill in descriptors
2714 * @last_segmant: condition for the last descriptor
2715 * @queue: TX queue index
2717 * This function fills descriptor and request new descriptors according to
2718 * buffer length to fill
2720 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2721 int total_len, bool last_segment, u32 queue)
2723 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2724 struct dma_desc *desc;
2728 tmp_len = total_len;
2730 while (tmp_len > 0) {
2731 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2732 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2733 desc = tx_q->dma_tx + tx_q->cur_tx;
2735 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2736 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2737 TSO_MAX_BUFF_SIZE : tmp_len;
2739 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2741 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2744 tmp_len -= TSO_MAX_BUFF_SIZE;
2749 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2750 * @skb : the socket buffer
2751 * @dev : device pointer
2752 * Description: this is the transmit function that is called on TSO frames
2753 * (support available on GMAC4 and newer chips).
2754 * Diagram below show the ring programming in case of TSO frames:
2758 * | DES0 |---> buffer1 = L2/L3/L4 header
2759 * | DES1 |---> TCP Payload (can continue on next descr...)
2760 * | DES2 |---> buffer 1 and 2 len
2761 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2767 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2769 * | DES2 | --> buffer 1 and 2 len
2773 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2775 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2777 struct dma_desc *desc, *first, *mss_desc = NULL;
2778 struct stmmac_priv *priv = netdev_priv(dev);
2779 int nfrags = skb_shinfo(skb)->nr_frags;
2780 u32 queue = skb_get_queue_mapping(skb);
2781 unsigned int first_entry, des;
2782 struct stmmac_tx_queue *tx_q;
2783 int tmp_pay_len = 0;
2788 tx_q = &priv->tx_queue[queue];
2790 /* Compute header lengths */
2791 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2793 /* Desc availability based on threshold should be enough safe */
2794 if (unlikely(stmmac_tx_avail(priv, queue) <
2795 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2796 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2797 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2799 /* This is a hard error, log it. */
2800 netdev_err(priv->dev,
2801 "%s: Tx Ring full when queue awake\n",
2804 return NETDEV_TX_BUSY;
2807 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2809 mss = skb_shinfo(skb)->gso_size;
2811 /* set new MSS value if needed */
2812 if (mss != tx_q->mss) {
2813 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2814 stmmac_set_mss(priv, mss_desc, mss);
2816 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2817 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2820 if (netif_msg_tx_queued(priv)) {
2821 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2822 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2823 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2827 first_entry = tx_q->cur_tx;
2828 WARN_ON(tx_q->tx_skbuff[first_entry]);
2830 desc = tx_q->dma_tx + first_entry;
2833 /* first descriptor: fill Headers on Buf1 */
2834 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2836 if (dma_mapping_error(priv->device, des))
2839 tx_q->tx_skbuff_dma[first_entry].buf = des;
2840 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2842 first->des0 = cpu_to_le32(des);
2844 /* Fill start of payload in buff2 of first descriptor */
2846 first->des1 = cpu_to_le32(des + proto_hdr_len);
2848 /* If needed take extra descriptors to fill the remaining payload */
2849 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2851 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2853 /* Prepare fragments */
2854 for (i = 0; i < nfrags; i++) {
2855 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2857 des = skb_frag_dma_map(priv->device, frag, 0,
2858 skb_frag_size(frag),
2860 if (dma_mapping_error(priv->device, des))
2863 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2864 (i == nfrags - 1), queue);
2866 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2867 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2868 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2871 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2873 /* Only the last descriptor gets to point to the skb. */
2874 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2876 /* We've used all descriptors we need for this skb, however,
2877 * advance cur_tx so that it references a fresh descriptor.
2878 * ndo_start_xmit will fill this descriptor the next time it's
2879 * called and stmmac_tx_clean may clean up to this descriptor.
2881 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2883 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2884 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2886 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2889 dev->stats.tx_bytes += skb->len;
2890 priv->xstats.tx_tso_frames++;
2891 priv->xstats.tx_tso_nfrags += nfrags;
2893 /* Manage tx mitigation */
2894 tx_q->tx_count_frames += nfrags + 1;
2895 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
2896 stmmac_set_tx_ic(priv, desc);
2897 priv->xstats.tx_set_ic_bit++;
2898 tx_q->tx_count_frames = 0;
2900 stmmac_tx_timer_arm(priv, queue);
2903 skb_tx_timestamp(skb);
2905 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2906 priv->hwts_tx_en)) {
2907 /* declare that device is doing timestamping */
2908 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2909 stmmac_enable_tx_timestamp(priv, first);
2912 /* Complete the first descriptor before granting the DMA */
2913 stmmac_prepare_tso_tx_desc(priv, first, 1,
2916 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2917 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2919 /* If context desc is used to change MSS */
2921 /* Make sure that first descriptor has been completely
2922 * written, including its own bit. This is because MSS is
2923 * actually before first descriptor, so we need to make
2924 * sure that MSS's own bit is the last thing written.
2927 stmmac_set_tx_owner(priv, mss_desc);
2930 /* The own bit must be the latest setting done when prepare the
2931 * descriptor and then barrier is needed to make sure that
2932 * all is coherent before granting the DMA engine.
2936 if (netif_msg_pktdata(priv)) {
2937 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2938 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2939 tx_q->cur_tx, first, nfrags);
2941 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
2943 pr_info(">>> frame to be transmitted: ");
2944 print_pkt(skb->data, skb_headlen(skb));
2947 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2949 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
2950 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
2952 return NETDEV_TX_OK;
2955 dev_err(priv->device, "Tx dma map failed\n");
2957 priv->dev->stats.tx_dropped++;
2958 return NETDEV_TX_OK;
2962 * stmmac_xmit - Tx entry point of the driver
2963 * @skb : the socket buffer
2964 * @dev : device pointer
2965 * Description : this is the tx entry point of the driver.
2966 * It programs the chain or the ring and supports oversized frames
2969 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2971 struct stmmac_priv *priv = netdev_priv(dev);
2972 unsigned int nopaged_len = skb_headlen(skb);
2973 int i, csum_insertion = 0, is_jumbo = 0;
2974 u32 queue = skb_get_queue_mapping(skb);
2975 int nfrags = skb_shinfo(skb)->nr_frags;
2977 unsigned int first_entry;
2978 struct dma_desc *desc, *first;
2979 struct stmmac_tx_queue *tx_q;
2980 unsigned int enh_desc;
2983 tx_q = &priv->tx_queue[queue];
2985 if (priv->tx_path_in_lpi_mode)
2986 stmmac_disable_eee_mode(priv);
2988 /* Manage oversized TCP frames for GMAC4 device */
2989 if (skb_is_gso(skb) && priv->tso) {
2990 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
2992 * There is no way to determine the number of TSO
2993 * capable Queues. Let's use always the Queue 0
2994 * because if TSO is supported then at least this
2995 * one will be capable.
2997 skb_set_queue_mapping(skb, 0);
2999 return stmmac_tso_xmit(skb, dev);
3003 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3004 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3005 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3007 /* This is a hard error, log it. */
3008 netdev_err(priv->dev,
3009 "%s: Tx Ring full when queue awake\n",
3012 return NETDEV_TX_BUSY;
3015 entry = tx_q->cur_tx;
3016 first_entry = entry;
3017 WARN_ON(tx_q->tx_skbuff[first_entry]);
3019 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3021 if (likely(priv->extend_desc))
3022 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3024 desc = tx_q->dma_tx + entry;
3028 enh_desc = priv->plat->enh_desc;
3029 /* To program the descriptors according to the size of the frame */
3031 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3033 if (unlikely(is_jumbo)) {
3034 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3035 if (unlikely(entry < 0) && (entry != -EINVAL))
3039 for (i = 0; i < nfrags; i++) {
3040 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3041 int len = skb_frag_size(frag);
3042 bool last_segment = (i == (nfrags - 1));
3044 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3045 WARN_ON(tx_q->tx_skbuff[entry]);
3047 if (likely(priv->extend_desc))
3048 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3050 desc = tx_q->dma_tx + entry;
3052 des = skb_frag_dma_map(priv->device, frag, 0, len,
3054 if (dma_mapping_error(priv->device, des))
3055 goto dma_map_err; /* should reuse desc w/o issues */
3057 tx_q->tx_skbuff_dma[entry].buf = des;
3059 stmmac_set_desc_addr(priv, desc, des);
3061 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3062 tx_q->tx_skbuff_dma[entry].len = len;
3063 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3065 /* Prepare the descriptor and set the own bit too */
3066 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3067 priv->mode, 1, last_segment, skb->len);
3070 /* Only the last descriptor gets to point to the skb. */
3071 tx_q->tx_skbuff[entry] = skb;
3073 /* We've used all descriptors we need for this skb, however,
3074 * advance cur_tx so that it references a fresh descriptor.
3075 * ndo_start_xmit will fill this descriptor the next time it's
3076 * called and stmmac_tx_clean may clean up to this descriptor.
3078 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3079 tx_q->cur_tx = entry;
3081 if (netif_msg_pktdata(priv)) {
3084 netdev_dbg(priv->dev,
3085 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3086 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3087 entry, first, nfrags);
3089 if (priv->extend_desc)
3090 tx_head = (void *)tx_q->dma_etx;
3092 tx_head = (void *)tx_q->dma_tx;
3094 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3096 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3097 print_pkt(skb->data, skb->len);
3100 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3101 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3103 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3106 dev->stats.tx_bytes += skb->len;
3108 /* According to the coalesce parameter the IC bit for the latest
3109 * segment is reset and the timer re-started to clean the tx status.
3110 * This approach takes care about the fragments: desc is the first
3111 * element in case of no SG.
3113 tx_q->tx_count_frames += nfrags + 1;
3114 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
3115 stmmac_set_tx_ic(priv, desc);
3116 priv->xstats.tx_set_ic_bit++;
3117 tx_q->tx_count_frames = 0;
3119 stmmac_tx_timer_arm(priv, queue);
3122 skb_tx_timestamp(skb);
3124 /* Ready to fill the first descriptor and set the OWN bit w/o any
3125 * problems because all the descriptors are actually ready to be
3126 * passed to the DMA engine.
3128 if (likely(!is_jumbo)) {
3129 bool last_segment = (nfrags == 0);
3131 des = dma_map_single(priv->device, skb->data,
3132 nopaged_len, DMA_TO_DEVICE);
3133 if (dma_mapping_error(priv->device, des))
3136 tx_q->tx_skbuff_dma[first_entry].buf = des;
3138 stmmac_set_desc_addr(priv, first, des);
3140 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3141 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3143 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3144 priv->hwts_tx_en)) {
3145 /* declare that device is doing timestamping */
3146 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3147 stmmac_enable_tx_timestamp(priv, first);
3150 /* Prepare the first descriptor setting the OWN bit too */
3151 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3152 csum_insertion, priv->mode, 1, last_segment,
3155 stmmac_set_tx_owner(priv, first);
3158 /* The own bit must be the latest setting done when prepare the
3159 * descriptor and then barrier is needed to make sure that
3160 * all is coherent before granting the DMA engine.
3164 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3166 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3168 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3169 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3171 return NETDEV_TX_OK;
3174 netdev_err(priv->dev, "Tx DMA map failed\n");
3176 priv->dev->stats.tx_dropped++;
3177 return NETDEV_TX_OK;
3180 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3182 struct vlan_ethhdr *veth;
3186 veth = (struct vlan_ethhdr *)skb->data;
3187 vlan_proto = veth->h_vlan_proto;
3189 if ((vlan_proto == htons(ETH_P_8021Q) &&
3190 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3191 (vlan_proto == htons(ETH_P_8021AD) &&
3192 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3193 /* pop the vlan tag */
3194 vlanid = ntohs(veth->h_vlan_TCI);
3195 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3196 skb_pull(skb, VLAN_HLEN);
3197 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3202 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3204 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3211 * stmmac_rx_refill - refill used skb preallocated buffers
3212 * @priv: driver private structure
3213 * @queue: RX queue index
3214 * Description : this is to reallocate the skb for the reception process
3215 * that is based on zero-copy.
3217 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3219 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3220 int dirty = stmmac_rx_dirty(priv, queue);
3221 unsigned int entry = rx_q->dirty_rx;
3223 int bfsize = priv->dma_buf_sz;
3225 while (dirty-- > 0) {
3228 if (priv->extend_desc)
3229 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3231 p = rx_q->dma_rx + entry;
3233 if (likely(!rx_q->rx_skbuff[entry])) {
3234 struct sk_buff *skb;
3236 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3237 if (unlikely(!skb)) {
3238 /* so for a while no zero-copy! */
3239 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3240 if (unlikely(net_ratelimit()))
3241 dev_err(priv->device,
3242 "fail to alloc skb entry %d\n",
3247 rx_q->rx_skbuff[entry] = skb;
3248 rx_q->rx_skbuff_dma[entry] =
3249 dma_map_single(priv->device, skb->data, bfsize,
3251 if (dma_mapping_error(priv->device,
3252 rx_q->rx_skbuff_dma[entry])) {
3253 netdev_err(priv->dev, "Rx DMA map failed\n");
3258 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3259 stmmac_refill_desc3(priv, rx_q, p);
3261 if (rx_q->rx_zeroc_thresh > 0)
3262 rx_q->rx_zeroc_thresh--;
3264 netif_dbg(priv, rx_status, priv->dev,
3265 "refill entry #%d\n", entry);
3269 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3273 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3275 rx_q->dirty_rx = entry;
3276 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3280 * stmmac_rx - manage the receive process
3281 * @priv: driver private structure
3282 * @limit: napi bugget
3283 * @queue: RX queue index.
3284 * Description : this the function called by the napi poll method.
3285 * It gets all the frames inside the ring.
3287 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3289 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3290 struct stmmac_channel *ch = &priv->channel[queue];
3291 unsigned int next_entry = rx_q->cur_rx;
3292 int coe = priv->hw->rx_csum;
3293 unsigned int count = 0;
3296 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3298 if (netif_msg_rx_status(priv)) {
3301 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3302 if (priv->extend_desc)
3303 rx_head = (void *)rx_q->dma_erx;
3305 rx_head = (void *)rx_q->dma_rx;
3307 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3309 while (count < limit) {
3312 struct dma_desc *np;
3316 if (priv->extend_desc)
3317 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3319 p = rx_q->dma_rx + entry;
3321 /* read the status of the incoming frame */
3322 status = stmmac_rx_status(priv, &priv->dev->stats,
3324 /* check if managed by the DMA otherwise go ahead */
3325 if (unlikely(status & dma_own))
3330 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3331 next_entry = rx_q->cur_rx;
3333 if (priv->extend_desc)
3334 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3336 np = rx_q->dma_rx + next_entry;
3340 if (priv->extend_desc)
3341 stmmac_rx_extended_status(priv, &priv->dev->stats,
3342 &priv->xstats, rx_q->dma_erx + entry);
3343 if (unlikely(status == discard_frame)) {
3344 priv->dev->stats.rx_errors++;
3345 if (priv->hwts_rx_en && !priv->extend_desc) {
3346 /* DESC2 & DESC3 will be overwritten by device
3347 * with timestamp value, hence reinitialize
3348 * them in stmmac_rx_refill() function so that
3349 * device can reuse it.
3351 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3352 rx_q->rx_skbuff[entry] = NULL;
3353 dma_unmap_single(priv->device,
3354 rx_q->rx_skbuff_dma[entry],
3359 struct sk_buff *skb;
3363 stmmac_get_desc_addr(priv, p, &des);
3364 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3366 /* If frame length is greater than skb buffer size
3367 * (preallocated during init) then the packet is
3370 if (frame_len > priv->dma_buf_sz) {
3371 if (net_ratelimit())
3372 netdev_err(priv->dev,
3373 "len %d larger than size (%d)\n",
3374 frame_len, priv->dma_buf_sz);
3375 priv->dev->stats.rx_length_errors++;
3379 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3380 * Type frames (LLC/LLC-SNAP)
3382 * llc_snap is never checked in GMAC >= 4, so this ACS
3383 * feature is always disabled and packets need to be
3384 * stripped manually.
3386 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3387 unlikely(status != llc_snap))
3388 frame_len -= ETH_FCS_LEN;
3390 if (netif_msg_rx_status(priv)) {
3391 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3393 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3397 /* The zero-copy is always used for all the sizes
3398 * in case of GMAC4 because it needs
3399 * to refill the used descriptors, always.
3401 if (unlikely(!xmac &&
3402 ((frame_len < priv->rx_copybreak) ||
3403 stmmac_rx_threshold_count(rx_q)))) {
3404 skb = netdev_alloc_skb_ip_align(priv->dev,
3406 if (unlikely(!skb)) {
3407 if (net_ratelimit())
3408 dev_warn(priv->device,
3409 "packet dropped\n");
3410 priv->dev->stats.rx_dropped++;
3414 dma_sync_single_for_cpu(priv->device,
3418 skb_copy_to_linear_data(skb,
3420 rx_skbuff[entry]->data,
3423 skb_put(skb, frame_len);
3424 dma_sync_single_for_device(priv->device,
3429 skb = rx_q->rx_skbuff[entry];
3430 if (unlikely(!skb)) {
3431 if (net_ratelimit())
3432 netdev_err(priv->dev,
3433 "%s: Inconsistent Rx chain\n",
3435 priv->dev->stats.rx_dropped++;
3438 prefetch(skb->data - NET_IP_ALIGN);
3439 rx_q->rx_skbuff[entry] = NULL;
3440 rx_q->rx_zeroc_thresh++;
3442 skb_put(skb, frame_len);
3443 dma_unmap_single(priv->device,
3444 rx_q->rx_skbuff_dma[entry],
3449 if (netif_msg_pktdata(priv)) {
3450 netdev_dbg(priv->dev, "frame received (%dbytes)",
3452 print_pkt(skb->data, frame_len);
3455 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3457 stmmac_rx_vlan(priv->dev, skb);
3459 skb->protocol = eth_type_trans(skb, priv->dev);
3462 skb_checksum_none_assert(skb);
3464 skb->ip_summed = CHECKSUM_UNNECESSARY;
3466 napi_gro_receive(&ch->rx_napi, skb);
3468 priv->dev->stats.rx_packets++;
3469 priv->dev->stats.rx_bytes += frame_len;
3473 stmmac_rx_refill(priv, queue);
3475 priv->xstats.rx_pkt_n += count;
3480 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3482 struct stmmac_channel *ch =
3483 container_of(napi, struct stmmac_channel, rx_napi);
3484 struct stmmac_priv *priv = ch->priv_data;
3485 u32 chan = ch->index;
3488 priv->xstats.napi_poll++;
3490 work_done = stmmac_rx(priv, budget, chan);
3491 if (work_done < budget && napi_complete_done(napi, work_done))
3492 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3496 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3498 struct stmmac_channel *ch =
3499 container_of(napi, struct stmmac_channel, tx_napi);
3500 struct stmmac_priv *priv = ch->priv_data;
3501 struct stmmac_tx_queue *tx_q;
3502 u32 chan = ch->index;
3505 priv->xstats.napi_poll++;
3507 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3508 work_done = min(work_done, budget);
3510 if (work_done < budget && napi_complete_done(napi, work_done))
3511 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3513 /* Force transmission restart */
3514 tx_q = &priv->tx_queue[chan];
3515 if (tx_q->cur_tx != tx_q->dirty_tx) {
3516 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3517 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3526 * @dev : Pointer to net device structure
3527 * Description: this function is called when a packet transmission fails to
3528 * complete within a reasonable time. The driver will mark the error in the
3529 * netdev structure and arrange for the device to be reset to a sane state
3530 * in order to transmit a new packet.
3532 static void stmmac_tx_timeout(struct net_device *dev)
3534 struct stmmac_priv *priv = netdev_priv(dev);
3536 stmmac_global_err(priv);
3540 * stmmac_set_rx_mode - entry point for multicast addressing
3541 * @dev : pointer to the device structure
3543 * This function is a driver entry point which gets called by the kernel
3544 * whenever multicast addresses must be enabled/disabled.
3548 static void stmmac_set_rx_mode(struct net_device *dev)
3550 struct stmmac_priv *priv = netdev_priv(dev);
3552 stmmac_set_filter(priv, priv->hw, dev);
3556 * stmmac_change_mtu - entry point to change MTU size for the device.
3557 * @dev : device pointer.
3558 * @new_mtu : the new MTU size for the device.
3559 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3560 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3561 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3563 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3566 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3568 struct stmmac_priv *priv = netdev_priv(dev);
3570 if (netif_running(dev)) {
3571 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3577 netdev_update_features(dev);
3582 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3583 netdev_features_t features)
3585 struct stmmac_priv *priv = netdev_priv(dev);
3587 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3588 features &= ~NETIF_F_RXCSUM;
3590 if (!priv->plat->tx_coe)
3591 features &= ~NETIF_F_CSUM_MASK;
3593 /* Some GMAC devices have a bugged Jumbo frame support that
3594 * needs to have the Tx COE disabled for oversized frames
3595 * (due to limited buffer sizes). In this case we disable
3596 * the TX csum insertion in the TDES and not use SF.
3598 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3599 features &= ~NETIF_F_CSUM_MASK;
3601 /* Disable tso if asked by ethtool */
3602 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3603 if (features & NETIF_F_TSO)
3612 static int stmmac_set_features(struct net_device *netdev,
3613 netdev_features_t features)
3615 struct stmmac_priv *priv = netdev_priv(netdev);
3617 /* Keep the COE Type in case of csum is supporting */
3618 if (features & NETIF_F_RXCSUM)
3619 priv->hw->rx_csum = priv->plat->rx_coe;
3621 priv->hw->rx_csum = 0;
3622 /* No check needed because rx_coe has been set before and it will be
3623 * fixed in case of issue.
3625 stmmac_rx_ipc(priv, priv->hw);
3631 * stmmac_interrupt - main ISR
3632 * @irq: interrupt number.
3633 * @dev_id: to pass the net device pointer.
3634 * Description: this is the main driver interrupt service routine.
3636 * o DMA service routine (to manage incoming frame reception and transmission
3638 * o Core interrupts to manage: remote wake-up, management counter, LPI
3641 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3643 struct net_device *dev = (struct net_device *)dev_id;
3644 struct stmmac_priv *priv = netdev_priv(dev);
3645 u32 rx_cnt = priv->plat->rx_queues_to_use;
3646 u32 tx_cnt = priv->plat->tx_queues_to_use;
3651 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3652 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3655 pm_wakeup_event(priv->device, 0);
3657 if (unlikely(!dev)) {
3658 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3662 /* Check if adapter is up */
3663 if (test_bit(STMMAC_DOWN, &priv->state))
3665 /* Check if a fatal error happened */
3666 if (stmmac_safety_feat_interrupt(priv))
3669 /* To handle GMAC own interrupts */
3670 if ((priv->plat->has_gmac) || xmac) {
3671 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3674 if (unlikely(status)) {
3675 /* For LPI we need to save the tx status */
3676 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3677 priv->tx_path_in_lpi_mode = true;
3678 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3679 priv->tx_path_in_lpi_mode = false;
3682 for (queue = 0; queue < queues_count; queue++) {
3683 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3685 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3687 if (mtl_status != -EINVAL)
3688 status |= mtl_status;
3690 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3691 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3696 /* PCS link status */
3697 if (priv->hw->pcs) {
3698 if (priv->xstats.pcs_link)
3699 netif_carrier_on(dev);
3701 netif_carrier_off(dev);
3705 /* To handle DMA interrupts */
3706 stmmac_dma_interrupt(priv);
3711 #ifdef CONFIG_NET_POLL_CONTROLLER
3712 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3713 * to allow network I/O with interrupts disabled.
3715 static void stmmac_poll_controller(struct net_device *dev)
3717 disable_irq(dev->irq);
3718 stmmac_interrupt(dev->irq, dev);
3719 enable_irq(dev->irq);
3724 * stmmac_ioctl - Entry point for the Ioctl
3725 * @dev: Device pointer.
3726 * @rq: An IOCTL specefic structure, that can contain a pointer to
3727 * a proprietary structure used to pass information to the driver.
3728 * @cmd: IOCTL command
3730 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3732 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3734 struct stmmac_priv *priv = netdev_priv (dev);
3735 int ret = -EOPNOTSUPP;
3737 if (!netif_running(dev))
3744 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3747 ret = stmmac_hwtstamp_set(dev, rq);
3750 ret = stmmac_hwtstamp_get(dev, rq);
3759 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3762 struct stmmac_priv *priv = cb_priv;
3763 int ret = -EOPNOTSUPP;
3765 stmmac_disable_all_queues(priv);
3768 case TC_SETUP_CLSU32:
3769 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3770 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3776 stmmac_enable_all_queues(priv);
3780 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3781 struct tc_block_offload *f)
3783 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3786 switch (f->command) {
3788 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3789 priv, priv, f->extack);
3790 case TC_BLOCK_UNBIND:
3791 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3798 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3801 struct stmmac_priv *priv = netdev_priv(ndev);
3804 case TC_SETUP_BLOCK:
3805 return stmmac_setup_tc_block(priv, type_data);
3806 case TC_SETUP_QDISC_CBS:
3807 return stmmac_tc_setup_cbs(priv, priv, type_data);
3813 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3815 struct stmmac_priv *priv = netdev_priv(ndev);
3818 ret = eth_mac_addr(ndev, addr);
3822 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3827 #ifdef CONFIG_DEBUG_FS
3828 static struct dentry *stmmac_fs_dir;
3830 static void sysfs_display_ring(void *head, int size, int extend_desc,
3831 struct seq_file *seq)
3834 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3835 struct dma_desc *p = (struct dma_desc *)head;
3837 for (i = 0; i < size; i++) {
3839 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3840 i, (unsigned int)virt_to_phys(ep),
3841 le32_to_cpu(ep->basic.des0),
3842 le32_to_cpu(ep->basic.des1),
3843 le32_to_cpu(ep->basic.des2),
3844 le32_to_cpu(ep->basic.des3));
3847 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3848 i, (unsigned int)virt_to_phys(p),
3849 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3850 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3853 seq_printf(seq, "\n");
3857 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3859 struct net_device *dev = seq->private;
3860 struct stmmac_priv *priv = netdev_priv(dev);
3861 u32 rx_count = priv->plat->rx_queues_to_use;
3862 u32 tx_count = priv->plat->tx_queues_to_use;
3865 if ((dev->flags & IFF_UP) == 0)
3868 for (queue = 0; queue < rx_count; queue++) {
3869 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3871 seq_printf(seq, "RX Queue %d:\n", queue);
3873 if (priv->extend_desc) {
3874 seq_printf(seq, "Extended descriptor ring:\n");
3875 sysfs_display_ring((void *)rx_q->dma_erx,
3876 DMA_RX_SIZE, 1, seq);
3878 seq_printf(seq, "Descriptor ring:\n");
3879 sysfs_display_ring((void *)rx_q->dma_rx,
3880 DMA_RX_SIZE, 0, seq);
3884 for (queue = 0; queue < tx_count; queue++) {
3885 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3887 seq_printf(seq, "TX Queue %d:\n", queue);
3889 if (priv->extend_desc) {
3890 seq_printf(seq, "Extended descriptor ring:\n");
3891 sysfs_display_ring((void *)tx_q->dma_etx,
3892 DMA_TX_SIZE, 1, seq);
3894 seq_printf(seq, "Descriptor ring:\n");
3895 sysfs_display_ring((void *)tx_q->dma_tx,
3896 DMA_TX_SIZE, 0, seq);
3902 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3904 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3906 struct net_device *dev = seq->private;
3907 struct stmmac_priv *priv = netdev_priv(dev);
3909 if (!priv->hw_cap_support) {
3910 seq_printf(seq, "DMA HW features not supported\n");
3914 seq_printf(seq, "==============================\n");
3915 seq_printf(seq, "\tDMA HW features\n");
3916 seq_printf(seq, "==============================\n");
3918 seq_printf(seq, "\t10/100 Mbps: %s\n",
3919 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3920 seq_printf(seq, "\t1000 Mbps: %s\n",
3921 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3922 seq_printf(seq, "\tHalf duplex: %s\n",
3923 (priv->dma_cap.half_duplex) ? "Y" : "N");
3924 seq_printf(seq, "\tHash Filter: %s\n",
3925 (priv->dma_cap.hash_filter) ? "Y" : "N");
3926 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3927 (priv->dma_cap.multi_addr) ? "Y" : "N");
3928 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3929 (priv->dma_cap.pcs) ? "Y" : "N");
3930 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3931 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3932 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3933 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3934 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3935 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3936 seq_printf(seq, "\tRMON module: %s\n",
3937 (priv->dma_cap.rmon) ? "Y" : "N");
3938 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3939 (priv->dma_cap.time_stamp) ? "Y" : "N");
3940 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3941 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3942 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3943 (priv->dma_cap.eee) ? "Y" : "N");
3944 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3945 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3946 (priv->dma_cap.tx_coe) ? "Y" : "N");
3947 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3948 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3949 (priv->dma_cap.rx_coe) ? "Y" : "N");
3951 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3952 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3953 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3954 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3956 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3957 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3958 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3959 priv->dma_cap.number_rx_channel);
3960 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3961 priv->dma_cap.number_tx_channel);
3962 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3963 (priv->dma_cap.enh_desc) ? "Y" : "N");
3967 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
3969 static int stmmac_init_fs(struct net_device *dev)
3971 struct stmmac_priv *priv = netdev_priv(dev);
3973 /* Create per netdev entries */
3974 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3976 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3977 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3982 /* Entry to report DMA RX/TX rings */
3983 priv->dbgfs_rings_status =
3984 debugfs_create_file("descriptors_status", 0444,
3985 priv->dbgfs_dir, dev,
3986 &stmmac_rings_status_fops);
3988 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3989 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3990 debugfs_remove_recursive(priv->dbgfs_dir);
3995 /* Entry to report the DMA HW features */
3996 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
3998 dev, &stmmac_dma_cap_fops);
4000 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4001 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4002 debugfs_remove_recursive(priv->dbgfs_dir);
4010 static void stmmac_exit_fs(struct net_device *dev)
4012 struct stmmac_priv *priv = netdev_priv(dev);
4014 debugfs_remove_recursive(priv->dbgfs_dir);
4016 #endif /* CONFIG_DEBUG_FS */
4018 static const struct net_device_ops stmmac_netdev_ops = {
4019 .ndo_open = stmmac_open,
4020 .ndo_start_xmit = stmmac_xmit,
4021 .ndo_stop = stmmac_release,
4022 .ndo_change_mtu = stmmac_change_mtu,
4023 .ndo_fix_features = stmmac_fix_features,
4024 .ndo_set_features = stmmac_set_features,
4025 .ndo_set_rx_mode = stmmac_set_rx_mode,
4026 .ndo_tx_timeout = stmmac_tx_timeout,
4027 .ndo_do_ioctl = stmmac_ioctl,
4028 .ndo_setup_tc = stmmac_setup_tc,
4029 #ifdef CONFIG_NET_POLL_CONTROLLER
4030 .ndo_poll_controller = stmmac_poll_controller,
4032 .ndo_set_mac_address = stmmac_set_mac_address,
4035 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4037 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4039 if (test_bit(STMMAC_DOWN, &priv->state))
4042 netdev_err(priv->dev, "Reset adapter.\n");
4045 netif_trans_update(priv->dev);
4046 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4047 usleep_range(1000, 2000);
4049 set_bit(STMMAC_DOWN, &priv->state);
4050 dev_close(priv->dev);
4051 dev_open(priv->dev, NULL);
4052 clear_bit(STMMAC_DOWN, &priv->state);
4053 clear_bit(STMMAC_RESETING, &priv->state);
4057 static void stmmac_service_task(struct work_struct *work)
4059 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4062 stmmac_reset_subtask(priv);
4063 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4067 * stmmac_hw_init - Init the MAC device
4068 * @priv: driver private structure
4069 * Description: this function is to configure the MAC device according to
4070 * some platform parameters or the HW capability register. It prepares the
4071 * driver to use either ring or chain modes and to setup either enhanced or
4072 * normal descriptors.
4074 static int stmmac_hw_init(struct stmmac_priv *priv)
4078 /* dwmac-sun8i only work in chain mode */
4079 if (priv->plat->has_sun8i)
4081 priv->chain_mode = chain_mode;
4083 /* Initialize HW Interface */
4084 ret = stmmac_hwif_init(priv);
4088 /* Get the HW capability (new GMAC newer than 3.50a) */
4089 priv->hw_cap_support = stmmac_get_hw_features(priv);
4090 if (priv->hw_cap_support) {
4091 dev_info(priv->device, "DMA HW capability register supported\n");
4093 /* We can override some gmac/dma configuration fields: e.g.
4094 * enh_desc, tx_coe (e.g. that are passed through the
4095 * platform) with the values from the HW capability
4096 * register (if supported).
4098 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4099 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4100 priv->hw->pmt = priv->plat->pmt;
4102 /* TXCOE doesn't work in thresh DMA mode */
4103 if (priv->plat->force_thresh_dma_mode)
4104 priv->plat->tx_coe = 0;
4106 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4108 /* In case of GMAC4 rx_coe is from HW cap register. */
4109 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4111 if (priv->dma_cap.rx_coe_type2)
4112 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4113 else if (priv->dma_cap.rx_coe_type1)
4114 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4117 dev_info(priv->device, "No HW DMA feature register supported\n");
4120 if (priv->plat->rx_coe) {
4121 priv->hw->rx_csum = priv->plat->rx_coe;
4122 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4123 if (priv->synopsys_id < DWMAC_CORE_4_00)
4124 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4126 if (priv->plat->tx_coe)
4127 dev_info(priv->device, "TX Checksum insertion supported\n");
4129 if (priv->plat->pmt) {
4130 dev_info(priv->device, "Wake-Up On Lan supported\n");
4131 device_set_wakeup_capable(priv->device, 1);
4134 if (priv->dma_cap.tsoen)
4135 dev_info(priv->device, "TSO supported\n");
4137 /* Run HW quirks, if any */
4138 if (priv->hwif_quirks) {
4139 ret = priv->hwif_quirks(priv);
4144 /* Rx Watchdog is available in the COREs newer than the 3.40.
4145 * In some case, for example on bugged HW this feature
4146 * has to be disable and this can be done by passing the
4147 * riwt_off field from the platform.
4149 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4150 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4152 dev_info(priv->device,
4153 "Enable RX Mitigation via HW Watchdog Timer\n");
4161 * @device: device pointer
4162 * @plat_dat: platform data pointer
4163 * @res: stmmac resource pointer
4164 * Description: this is the main probe function used to
4165 * call the alloc_etherdev, allocate the priv structure.
4167 * returns 0 on success, otherwise errno.
4169 int stmmac_dvr_probe(struct device *device,
4170 struct plat_stmmacenet_data *plat_dat,
4171 struct stmmac_resources *res)
4173 struct net_device *ndev = NULL;
4174 struct stmmac_priv *priv;
4178 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4179 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4183 SET_NETDEV_DEV(ndev, device);
4185 priv = netdev_priv(ndev);
4186 priv->device = device;
4189 stmmac_set_ethtool_ops(ndev);
4190 priv->pause = pause;
4191 priv->plat = plat_dat;
4192 priv->ioaddr = res->addr;
4193 priv->dev->base_addr = (unsigned long)res->addr;
4195 priv->dev->irq = res->irq;
4196 priv->wol_irq = res->wol_irq;
4197 priv->lpi_irq = res->lpi_irq;
4199 if (!IS_ERR_OR_NULL(res->mac))
4200 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4202 dev_set_drvdata(device, priv->dev);
4204 /* Verify driver arguments */
4205 stmmac_verify_args();
4207 /* Allocate workqueue */
4208 priv->wq = create_singlethread_workqueue("stmmac_wq");
4210 dev_err(priv->device, "failed to create workqueue\n");
4214 INIT_WORK(&priv->service_task, stmmac_service_task);
4216 /* Override with kernel parameters if supplied XXX CRS XXX
4217 * this needs to have multiple instances
4219 if ((phyaddr >= 0) && (phyaddr <= 31))
4220 priv->plat->phy_addr = phyaddr;
4222 if (priv->plat->stmmac_rst) {
4223 ret = reset_control_assert(priv->plat->stmmac_rst);
4224 reset_control_deassert(priv->plat->stmmac_rst);
4225 /* Some reset controllers have only reset callback instead of
4226 * assert + deassert callbacks pair.
4228 if (ret == -ENOTSUPP)
4229 reset_control_reset(priv->plat->stmmac_rst);
4232 /* Init MAC and get the capabilities */
4233 ret = stmmac_hw_init(priv);
4237 stmmac_check_ether_addr(priv);
4239 /* Configure real RX and TX queues */
4240 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4241 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4243 ndev->netdev_ops = &stmmac_netdev_ops;
4245 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4248 ret = stmmac_tc_init(priv, priv);
4250 ndev->hw_features |= NETIF_F_HW_TC;
4253 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4254 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4256 dev_info(priv->device, "TSO feature enabled\n");
4258 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4259 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4260 #ifdef STMMAC_VLAN_TAG_USED
4261 /* Both mac100 and gmac support receive VLAN tag detection */
4262 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4264 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4266 /* MTU range: 46 - hw-specific max */
4267 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4268 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4269 ndev->max_mtu = JUMBO_LEN;
4270 else if (priv->plat->has_xgmac)
4271 ndev->max_mtu = XGMAC_JUMBO_LEN;
4273 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4274 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4275 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4277 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4278 (priv->plat->maxmtu >= ndev->min_mtu))
4279 ndev->max_mtu = priv->plat->maxmtu;
4280 else if (priv->plat->maxmtu < ndev->min_mtu)
4281 dev_warn(priv->device,
4282 "%s: warning: maxmtu having invalid value (%d)\n",
4283 __func__, priv->plat->maxmtu);
4286 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4288 /* Setup channels NAPI */
4289 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4291 for (queue = 0; queue < maxq; queue++) {
4292 struct stmmac_channel *ch = &priv->channel[queue];
4294 ch->priv_data = priv;
4297 if (queue < priv->plat->rx_queues_to_use) {
4298 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4301 if (queue < priv->plat->tx_queues_to_use) {
4302 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4307 mutex_init(&priv->lock);
4309 /* If a specific clk_csr value is passed from the platform
4310 * this means that the CSR Clock Range selection cannot be
4311 * changed at run-time and it is fixed. Viceversa the driver'll try to
4312 * set the MDC clock dynamically according to the csr actual
4315 if (priv->plat->clk_csr >= 0)
4316 priv->clk_csr = priv->plat->clk_csr;
4318 stmmac_clk_csr_set(priv);
4320 stmmac_check_pcs_mode(priv);
4322 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4323 priv->hw->pcs != STMMAC_PCS_TBI &&
4324 priv->hw->pcs != STMMAC_PCS_RTBI) {
4325 /* MDIO bus Registration */
4326 ret = stmmac_mdio_register(ndev);
4328 dev_err(priv->device,
4329 "%s: MDIO bus (id: %d) registration failed",
4330 __func__, priv->plat->bus_id);
4331 goto error_mdio_register;
4335 ret = stmmac_phy_setup(priv);
4337 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4338 goto error_phy_setup;
4341 ret = register_netdev(ndev);
4343 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4345 goto error_netdev_register;
4348 #ifdef CONFIG_DEBUG_FS
4349 ret = stmmac_init_fs(ndev);
4351 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4357 error_netdev_register:
4358 phylink_destroy(priv->phylink);
4360 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4361 priv->hw->pcs != STMMAC_PCS_TBI &&
4362 priv->hw->pcs != STMMAC_PCS_RTBI)
4363 stmmac_mdio_unregister(ndev);
4364 error_mdio_register:
4365 for (queue = 0; queue < maxq; queue++) {
4366 struct stmmac_channel *ch = &priv->channel[queue];
4368 if (queue < priv->plat->rx_queues_to_use)
4369 netif_napi_del(&ch->rx_napi);
4370 if (queue < priv->plat->tx_queues_to_use)
4371 netif_napi_del(&ch->tx_napi);
4374 destroy_workqueue(priv->wq);
4378 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4382 * @dev: device pointer
4383 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4384 * changes the link status, releases the DMA descriptor rings.
4386 int stmmac_dvr_remove(struct device *dev)
4388 struct net_device *ndev = dev_get_drvdata(dev);
4389 struct stmmac_priv *priv = netdev_priv(ndev);
4391 netdev_info(priv->dev, "%s: removing driver", __func__);
4393 #ifdef CONFIG_DEBUG_FS
4394 stmmac_exit_fs(ndev);
4396 stmmac_stop_all_dma(priv);
4398 stmmac_mac_set(priv, priv->ioaddr, false);
4399 netif_carrier_off(ndev);
4400 unregister_netdev(ndev);
4401 phylink_destroy(priv->phylink);
4402 if (priv->plat->stmmac_rst)
4403 reset_control_assert(priv->plat->stmmac_rst);
4404 clk_disable_unprepare(priv->plat->pclk);
4405 clk_disable_unprepare(priv->plat->stmmac_clk);
4406 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4407 priv->hw->pcs != STMMAC_PCS_TBI &&
4408 priv->hw->pcs != STMMAC_PCS_RTBI)
4409 stmmac_mdio_unregister(ndev);
4410 destroy_workqueue(priv->wq);
4411 mutex_destroy(&priv->lock);
4415 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4418 * stmmac_suspend - suspend callback
4419 * @dev: device pointer
4420 * Description: this is the function to suspend the device and it is called
4421 * by the platform driver to stop the network queue, release the resources,
4422 * program the PMT register (for WoL), clean and release driver resources.
4424 int stmmac_suspend(struct device *dev)
4426 struct net_device *ndev = dev_get_drvdata(dev);
4427 struct stmmac_priv *priv = netdev_priv(ndev);
4429 if (!ndev || !netif_running(ndev))
4432 phylink_stop(priv->phylink);
4434 mutex_lock(&priv->lock);
4436 netif_device_detach(ndev);
4437 stmmac_stop_all_queues(priv);
4439 stmmac_disable_all_queues(priv);
4441 /* Stop TX/RX DMA */
4442 stmmac_stop_all_dma(priv);
4444 /* Enable Power down mode by programming the PMT regs */
4445 if (device_may_wakeup(priv->device)) {
4446 stmmac_pmt(priv, priv->hw, priv->wolopts);
4449 stmmac_mac_set(priv, priv->ioaddr, false);
4450 pinctrl_pm_select_sleep_state(priv->device);
4451 /* Disable clock in case of PWM is off */
4452 clk_disable(priv->plat->pclk);
4453 clk_disable(priv->plat->stmmac_clk);
4455 mutex_unlock(&priv->lock);
4457 priv->speed = SPEED_UNKNOWN;
4460 EXPORT_SYMBOL_GPL(stmmac_suspend);
4463 * stmmac_reset_queues_param - reset queue parameters
4464 * @dev: device pointer
4466 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4468 u32 rx_cnt = priv->plat->rx_queues_to_use;
4469 u32 tx_cnt = priv->plat->tx_queues_to_use;
4472 for (queue = 0; queue < rx_cnt; queue++) {
4473 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4479 for (queue = 0; queue < tx_cnt; queue++) {
4480 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4489 * stmmac_resume - resume callback
4490 * @dev: device pointer
4491 * Description: when resume this function is invoked to setup the DMA and CORE
4492 * in a usable state.
4494 int stmmac_resume(struct device *dev)
4496 struct net_device *ndev = dev_get_drvdata(dev);
4497 struct stmmac_priv *priv = netdev_priv(ndev);
4499 if (!netif_running(ndev))
4502 /* Power Down bit, into the PM register, is cleared
4503 * automatically as soon as a magic packet or a Wake-up frame
4504 * is received. Anyway, it's better to manually clear
4505 * this bit because it can generate problems while resuming
4506 * from another devices (e.g. serial console).
4508 if (device_may_wakeup(priv->device)) {
4509 mutex_lock(&priv->lock);
4510 stmmac_pmt(priv, priv->hw, 0);
4511 mutex_unlock(&priv->lock);
4514 pinctrl_pm_select_default_state(priv->device);
4515 /* enable the clk previously disabled */
4516 clk_enable(priv->plat->stmmac_clk);
4517 clk_enable(priv->plat->pclk);
4518 /* reset the phy so that it's ready */
4520 stmmac_mdio_reset(priv->mii);
4523 netif_device_attach(ndev);
4525 mutex_lock(&priv->lock);
4527 stmmac_reset_queues_param(priv);
4529 stmmac_clear_descriptors(priv);
4531 stmmac_hw_setup(ndev, false);
4532 stmmac_init_tx_coalesce(priv);
4533 stmmac_set_rx_mode(ndev);
4535 stmmac_enable_all_queues(priv);
4537 stmmac_start_all_queues(priv);
4539 mutex_unlock(&priv->lock);
4541 phylink_start(priv->phylink);
4545 EXPORT_SYMBOL_GPL(stmmac_resume);
4548 static int __init stmmac_cmdline_opt(char *str)
4554 while ((opt = strsep(&str, ",")) != NULL) {
4555 if (!strncmp(opt, "debug:", 6)) {
4556 if (kstrtoint(opt + 6, 0, &debug))
4558 } else if (!strncmp(opt, "phyaddr:", 8)) {
4559 if (kstrtoint(opt + 8, 0, &phyaddr))
4561 } else if (!strncmp(opt, "buf_sz:", 7)) {
4562 if (kstrtoint(opt + 7, 0, &buf_sz))
4564 } else if (!strncmp(opt, "tc:", 3)) {
4565 if (kstrtoint(opt + 3, 0, &tc))
4567 } else if (!strncmp(opt, "watchdog:", 9)) {
4568 if (kstrtoint(opt + 9, 0, &watchdog))
4570 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4571 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4573 } else if (!strncmp(opt, "pause:", 6)) {
4574 if (kstrtoint(opt + 6, 0, &pause))
4576 } else if (!strncmp(opt, "eee_timer:", 10)) {
4577 if (kstrtoint(opt + 10, 0, &eee_timer))
4579 } else if (!strncmp(opt, "chain_mode:", 11)) {
4580 if (kstrtoint(opt + 11, 0, &chain_mode))
4587 pr_err("%s: ERROR broken module parameter conversion", __func__);
4591 __setup("stmmaceth=", stmmac_cmdline_opt);
4594 static int __init stmmac_init(void)
4596 #ifdef CONFIG_DEBUG_FS
4597 /* Create debugfs main directory if it doesn't exist yet */
4598 if (!stmmac_fs_dir) {
4599 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4601 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4602 pr_err("ERROR %s, debugfs create directory failed\n",
4603 STMMAC_RESOURCE_NAME);
4613 static void __exit stmmac_exit(void)
4615 #ifdef CONFIG_DEBUG_FS
4616 debugfs_remove_recursive(stmmac_fs_dir);
4620 module_init(stmmac_init)
4621 module_exit(stmmac_exit)
4623 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4624 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4625 MODULE_LICENSE("GPL");