1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/prefetch.h>
32 #include <linux/pinctrl/consumer.h>
33 #ifdef CONFIG_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/seq_file.h>
36 #endif /* CONFIG_DEBUG_FS */
37 #include <linux/net_tstamp.h>
38 #include <linux/phylink.h>
39 #include <net/pkt_cls.h>
40 #include "stmmac_ptp.h"
42 #include <linux/reset.h>
43 #include <linux/of_mdio.h>
44 #include "dwmac1000.h"
48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
51 /* Module parameters */
53 static int watchdog = TX_TIMEO;
54 module_param(watchdog, int, 0644);
55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
57 static int debug = -1;
58 module_param(debug, int, 0644);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static int phyaddr = -1;
62 module_param(phyaddr, int, 0444);
63 MODULE_PARM_DESC(phyaddr, "Physical device address");
65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
68 static int flow_ctrl = FLOW_AUTO;
69 module_param(flow_ctrl, int, 0644);
70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
72 static int pause = PAUSE_TIME;
73 module_param(pause, int, 0644);
74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
77 static int tc = TC_DEFAULT;
78 module_param(tc, int, 0644);
79 MODULE_PARM_DESC(tc, "DMA threshold control value");
81 #define DEFAULT_BUFSIZE 1536
82 static int buf_sz = DEFAULT_BUFSIZE;
83 module_param(buf_sz, int, 0644);
84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
86 #define STMMAC_RX_COPYBREAK 256
88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
89 NETIF_MSG_LINK | NETIF_MSG_IFUP |
90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
92 #define STMMAC_DEFAULT_LPI_TIMER 1000
93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
94 module_param(eee_timer, int, 0644);
95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
99 * but allow user to force to use the chain instead of the ring
101 static unsigned int chain_mode;
102 module_param(chain_mode, int, 0444);
103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
107 #ifdef CONFIG_DEBUG_FS
108 static int stmmac_init_fs(struct net_device *dev);
109 static void stmmac_exit_fs(struct net_device *dev);
112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
115 * stmmac_verify_args - verify the driver parameters.
116 * Description: it checks the driver parameters and set a default in case of
119 static void stmmac_verify_args(void)
121 if (unlikely(watchdog < 0))
123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
124 buf_sz = DEFAULT_BUFSIZE;
125 if (unlikely(flow_ctrl > 1))
126 flow_ctrl = FLOW_AUTO;
127 else if (likely(flow_ctrl < 0))
128 flow_ctrl = FLOW_OFF;
129 if (unlikely((pause < 0) || (pause > 0xffff)))
132 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
136 * stmmac_disable_all_queues - Disable all queues
137 * @priv: driver private structure
139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
146 for (queue = 0; queue < maxq; queue++) {
147 struct stmmac_channel *ch = &priv->channel[queue];
149 if (queue < rx_queues_cnt)
150 napi_disable(&ch->rx_napi);
151 if (queue < tx_queues_cnt)
152 napi_disable(&ch->tx_napi);
157 * stmmac_enable_all_queues - Enable all queues
158 * @priv: driver private structure
160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
167 for (queue = 0; queue < maxq; queue++) {
168 struct stmmac_channel *ch = &priv->channel[queue];
170 if (queue < rx_queues_cnt)
171 napi_enable(&ch->rx_napi);
172 if (queue < tx_queues_cnt)
173 napi_enable(&ch->tx_napi);
178 * stmmac_stop_all_queues - Stop all queues
179 * @priv: driver private structure
181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
186 for (queue = 0; queue < tx_queues_cnt; queue++)
187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
191 * stmmac_start_all_queues - Start all queues
192 * @priv: driver private structure
194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
199 for (queue = 0; queue < tx_queues_cnt; queue++)
200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
205 if (!test_bit(STMMAC_DOWN, &priv->state) &&
206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
207 queue_work(priv->wq, &priv->service_task);
210 static void stmmac_global_err(struct stmmac_priv *priv)
212 netif_carrier_off(priv->dev);
213 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
214 stmmac_service_event_schedule(priv);
218 * stmmac_clk_csr_set - dynamically set the MDC clock
219 * @priv: driver private structure
220 * Description: this is to dynamically set the MDC clock according to the csr
223 * If a specific clk_csr value is passed from the platform
224 * this means that the CSR Clock Range selection cannot be
225 * changed at run-time and it is fixed (as reported in the driver
226 * documentation). Viceversa the driver will try to set the MDC
227 * clock dynamically according to the actual clock input.
229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
233 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
235 /* Platform provided default clk_csr would be assumed valid
236 * for all other cases except for the below mentioned ones.
237 * For values higher than the IEEE 802.3 specified frequency
238 * we can not estimate the proper divider as it is not known
239 * the frequency of clk_csr_i. So we do not change the default
242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
243 if (clk_rate < CSR_F_35M)
244 priv->clk_csr = STMMAC_CSR_20_35M;
245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
246 priv->clk_csr = STMMAC_CSR_35_60M;
247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
248 priv->clk_csr = STMMAC_CSR_60_100M;
249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
250 priv->clk_csr = STMMAC_CSR_100_150M;
251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
252 priv->clk_csr = STMMAC_CSR_150_250M;
253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
254 priv->clk_csr = STMMAC_CSR_250_300M;
257 if (priv->plat->has_sun8i) {
258 if (clk_rate > 160000000)
259 priv->clk_csr = 0x03;
260 else if (clk_rate > 80000000)
261 priv->clk_csr = 0x02;
262 else if (clk_rate > 40000000)
263 priv->clk_csr = 0x01;
268 if (priv->plat->has_xgmac) {
269 if (clk_rate > 400000000)
271 else if (clk_rate > 350000000)
273 else if (clk_rate > 300000000)
275 else if (clk_rate > 250000000)
277 else if (clk_rate > 150000000)
284 static void print_pkt(unsigned char *buf, int len)
286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
295 if (tx_q->dirty_tx > tx_q->cur_tx)
296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
304 * stmmac_rx_dirty - Get RX queue dirty
305 * @priv: driver private structure
306 * @queue: RX queue index
308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
313 if (rx_q->dirty_rx <= rx_q->cur_rx)
314 dirty = rx_q->cur_rx - rx_q->dirty_rx;
316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
322 * stmmac_enable_eee_mode - check and enter in LPI mode
323 * @priv: driver private structure
324 * Description: this function is to verify and enter in LPI mode in case of
327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
329 u32 tx_cnt = priv->plat->tx_queues_to_use;
332 /* check if all TX queues have the work finished */
333 for (queue = 0; queue < tx_cnt; queue++) {
334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
336 if (tx_q->dirty_tx != tx_q->cur_tx)
337 return; /* still unfinished work */
340 /* Check and enter in LPI mode */
341 if (!priv->tx_path_in_lpi_mode)
342 stmmac_set_eee_mode(priv, priv->hw,
343 priv->plat->en_tx_lpi_clockgating);
347 * stmmac_disable_eee_mode - disable and exit from LPI mode
348 * @priv: driver private structure
349 * Description: this function is to exit and disable EEE in case of
350 * LPI state is true. This is called by the xmit.
352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
354 stmmac_reset_eee_mode(priv, priv->hw);
355 del_timer_sync(&priv->eee_ctrl_timer);
356 priv->tx_path_in_lpi_mode = false;
360 * stmmac_eee_ctrl_timer - EEE TX SW timer.
363 * if there is no data transfer and if we are not in LPI state,
364 * then MAC Transmitter can be moved to LPI state.
366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
370 stmmac_enable_eee_mode(priv);
371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
375 * stmmac_eee_init - init EEE
376 * @priv: driver private structure
378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
379 * can also manage EEE, this function enable the LPI state and start related
382 bool stmmac_eee_init(struct stmmac_priv *priv)
384 int tx_lpi_timer = priv->tx_lpi_timer;
386 /* Using PCS we cannot dial with the phy registers at this stage
387 * so we do not support extra feature like EEE.
389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
390 (priv->hw->pcs == STMMAC_PCS_TBI) ||
391 (priv->hw->pcs == STMMAC_PCS_RTBI))
394 /* Check if MAC core supports the EEE feature. */
395 if (!priv->dma_cap.eee)
398 mutex_lock(&priv->lock);
400 /* Check if it needs to be deactivated */
401 if (!priv->eee_active) {
402 if (priv->eee_enabled) {
403 netdev_dbg(priv->dev, "disable EEE\n");
404 del_timer_sync(&priv->eee_ctrl_timer);
405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
407 mutex_unlock(&priv->lock);
411 if (priv->eee_active && !priv->eee_enabled) {
412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
418 mutex_unlock(&priv->lock);
419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
424 * @priv: driver private structure
425 * @p : descriptor pointer
426 * @skb : the socket buffer
428 * This function will read timestamp from the descriptor & pass it to stack.
429 * and also perform some sanity checks.
431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
432 struct dma_desc *p, struct sk_buff *skb)
434 struct skb_shared_hwtstamps shhwtstamp;
437 if (!priv->hwts_tx_en)
440 /* exit if skb doesn't support hw tstamp */
441 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
444 /* check tx tstamp status */
445 if (stmmac_get_tx_timestamp_status(priv, p)) {
446 /* get the valid tstamp */
447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
449 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
450 shhwtstamp.hwtstamp = ns_to_ktime(ns);
452 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
453 /* pass tstamp to stack */
454 skb_tstamp_tx(skb, &shhwtstamp);
460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
461 * @priv: driver private structure
462 * @p : descriptor pointer
463 * @np : next descriptor pointer
464 * @skb : the socket buffer
466 * This function will read received packet's timestamp from the descriptor
467 * and pass it to stack. It also perform some sanity checks.
469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
470 struct dma_desc *np, struct sk_buff *skb)
472 struct skb_shared_hwtstamps *shhwtstamp = NULL;
473 struct dma_desc *desc = p;
476 if (!priv->hwts_rx_en)
478 /* For GMAC4, the valid timestamp is from CTX next desc. */
479 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
482 /* Check if timestamp is available */
483 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
484 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
485 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
486 shhwtstamp = skb_hwtstamps(skb);
487 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
488 shhwtstamp->hwtstamp = ns_to_ktime(ns);
490 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
495 * stmmac_hwtstamp_set - control hardware timestamping.
496 * @dev: device pointer.
497 * @ifr: An IOCTL specific structure, that can contain a pointer to
498 * a proprietary structure used to pass information to the driver.
500 * This function configures the MAC to enable/disable both outgoing(TX)
501 * and incoming(RX) packets time stamping based on user input.
503 * 0 on success and an appropriate -ve integer on failure.
505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
507 struct stmmac_priv *priv = netdev_priv(dev);
508 struct hwtstamp_config config;
509 struct timespec64 now;
513 u32 ptp_over_ipv4_udp = 0;
514 u32 ptp_over_ipv6_udp = 0;
515 u32 ptp_over_ethernet = 0;
516 u32 snap_type_sel = 0;
517 u32 ts_master_en = 0;
523 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
525 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
526 netdev_alert(priv->dev, "No support for HW time stamping\n");
527 priv->hwts_tx_en = 0;
528 priv->hwts_rx_en = 0;
533 if (copy_from_user(&config, ifr->ifr_data,
537 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
538 __func__, config.flags, config.tx_type, config.rx_filter);
540 /* reserved for future extensions */
544 if (config.tx_type != HWTSTAMP_TX_OFF &&
545 config.tx_type != HWTSTAMP_TX_ON)
549 switch (config.rx_filter) {
550 case HWTSTAMP_FILTER_NONE:
551 /* time stamp no incoming packet at all */
552 config.rx_filter = HWTSTAMP_FILTER_NONE;
555 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
556 /* PTP v1, UDP, any kind of event packet */
557 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
558 /* 'xmac' hardware can support Sync, Pdelay_Req and
559 * Pdelay_resp by setting bit14 and bits17/16 to 01
560 * This leaves Delay_Req timestamps out.
561 * Enable all events *and* general purpose message
564 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
565 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
566 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
569 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
570 /* PTP v1, UDP, Sync packet */
571 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
572 /* take time stamp for SYNC messages only */
573 ts_event_en = PTP_TCR_TSEVNTENA;
575 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
576 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
579 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
580 /* PTP v1, UDP, Delay_req packet */
581 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
582 /* take time stamp for Delay_Req messages only */
583 ts_master_en = PTP_TCR_TSMSTRENA;
584 ts_event_en = PTP_TCR_TSEVNTENA;
586 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
587 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
590 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
591 /* PTP v2, UDP, any kind of event packet */
592 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
593 ptp_v2 = PTP_TCR_TSVER2ENA;
594 /* take time stamp for all event messages */
595 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
597 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
598 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
601 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
602 /* PTP v2, UDP, Sync packet */
603 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
604 ptp_v2 = PTP_TCR_TSVER2ENA;
605 /* take time stamp for SYNC messages only */
606 ts_event_en = PTP_TCR_TSEVNTENA;
608 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
609 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
612 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
613 /* PTP v2, UDP, Delay_req packet */
614 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
615 ptp_v2 = PTP_TCR_TSVER2ENA;
616 /* take time stamp for Delay_Req messages only */
617 ts_master_en = PTP_TCR_TSMSTRENA;
618 ts_event_en = PTP_TCR_TSEVNTENA;
620 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
621 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
624 case HWTSTAMP_FILTER_PTP_V2_EVENT:
625 /* PTP v2/802.AS1 any layer, any kind of event packet */
626 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
627 ptp_v2 = PTP_TCR_TSVER2ENA;
628 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
629 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
630 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
631 ptp_over_ethernet = PTP_TCR_TSIPENA;
634 case HWTSTAMP_FILTER_PTP_V2_SYNC:
635 /* PTP v2/802.AS1, any layer, Sync packet */
636 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
637 ptp_v2 = PTP_TCR_TSVER2ENA;
638 /* take time stamp for SYNC messages only */
639 ts_event_en = PTP_TCR_TSEVNTENA;
641 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
642 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
643 ptp_over_ethernet = PTP_TCR_TSIPENA;
646 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
647 /* PTP v2/802.AS1, any layer, Delay_req packet */
648 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
649 ptp_v2 = PTP_TCR_TSVER2ENA;
650 /* take time stamp for Delay_Req messages only */
651 ts_master_en = PTP_TCR_TSMSTRENA;
652 ts_event_en = PTP_TCR_TSEVNTENA;
654 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
655 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
656 ptp_over_ethernet = PTP_TCR_TSIPENA;
659 case HWTSTAMP_FILTER_NTP_ALL:
660 case HWTSTAMP_FILTER_ALL:
661 /* time stamp any incoming packet */
662 config.rx_filter = HWTSTAMP_FILTER_ALL;
663 tstamp_all = PTP_TCR_TSENALL;
670 switch (config.rx_filter) {
671 case HWTSTAMP_FILTER_NONE:
672 config.rx_filter = HWTSTAMP_FILTER_NONE;
675 /* PTP v1, UDP, any kind of event packet */
676 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
680 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
681 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
683 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
684 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
686 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
687 tstamp_all | ptp_v2 | ptp_over_ethernet |
688 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
689 ts_master_en | snap_type_sel);
690 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
692 /* program Sub Second Increment reg */
693 stmmac_config_sub_second_increment(priv,
694 priv->ptpaddr, priv->plat->clk_ptp_rate,
696 temp = div_u64(1000000000ULL, sec_inc);
698 /* Store sub second increment and flags for later use */
699 priv->sub_second_inc = sec_inc;
700 priv->systime_flags = value;
702 /* calculate default added value:
704 * addend = (2^32)/freq_div_ratio;
705 * where, freq_div_ratio = 1e9ns/sec_inc
707 temp = (u64)(temp << 32);
708 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
709 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
711 /* initialize system time */
712 ktime_get_real_ts64(&now);
714 /* lower 32 bits of tv_sec are safe until y2106 */
715 stmmac_init_systime(priv, priv->ptpaddr,
716 (u32)now.tv_sec, now.tv_nsec);
719 memcpy(&priv->tstamp_config, &config, sizeof(config));
721 return copy_to_user(ifr->ifr_data, &config,
722 sizeof(config)) ? -EFAULT : 0;
726 * stmmac_hwtstamp_get - read hardware timestamping.
727 * @dev: device pointer.
728 * @ifr: An IOCTL specific structure, that can contain a pointer to
729 * a proprietary structure used to pass information to the driver.
731 * This function obtain the current hardware timestamping settings
734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
736 struct stmmac_priv *priv = netdev_priv(dev);
737 struct hwtstamp_config *config = &priv->tstamp_config;
739 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
742 return copy_to_user(ifr->ifr_data, config,
743 sizeof(*config)) ? -EFAULT : 0;
747 * stmmac_init_ptp - init PTP
748 * @priv: driver private structure
749 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
750 * This is done by looking at the HW cap. register.
751 * This function also registers the ptp driver.
753 static int stmmac_init_ptp(struct stmmac_priv *priv)
755 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
757 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
761 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
762 if (xmac && priv->dma_cap.atime_stamp)
764 /* Dwmac 3.x core with extend_desc can support adv_ts */
765 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
768 if (priv->dma_cap.time_stamp)
769 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
772 netdev_info(priv->dev,
773 "IEEE 1588-2008 Advanced Timestamp supported\n");
775 priv->hwts_tx_en = 0;
776 priv->hwts_rx_en = 0;
778 stmmac_ptp_register(priv);
783 static void stmmac_release_ptp(struct stmmac_priv *priv)
785 if (priv->plat->clk_ptp_ref)
786 clk_disable_unprepare(priv->plat->clk_ptp_ref);
787 stmmac_ptp_unregister(priv);
791 * stmmac_mac_flow_ctrl - Configure flow control in all queues
792 * @priv: driver private structure
793 * Description: It is used for configuring the flow control in all queues
795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
797 u32 tx_cnt = priv->plat->tx_queues_to_use;
799 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
800 priv->pause, tx_cnt);
803 static void stmmac_validate(struct phylink_config *config,
804 unsigned long *supported,
805 struct phylink_link_state *state)
807 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
808 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
809 int tx_cnt = priv->plat->tx_queues_to_use;
810 int max_speed = priv->plat->max_speed;
812 /* Cut down 1G if asked to */
813 if ((max_speed > 0) && (max_speed < 1000)) {
814 phylink_set(mask, 1000baseT_Full);
815 phylink_set(mask, 1000baseX_Full);
818 /* Half-Duplex can only work with single queue */
820 phylink_set(mask, 10baseT_Half);
821 phylink_set(mask, 100baseT_Half);
822 phylink_set(mask, 1000baseT_Half);
825 bitmap_andnot(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
826 bitmap_andnot(state->advertising, state->advertising, mask,
827 __ETHTOOL_LINK_MODE_MASK_NBITS);
830 static int stmmac_mac_link_state(struct phylink_config *config,
831 struct phylink_link_state *state)
836 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
837 const struct phylink_link_state *state)
839 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
842 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
843 ctrl &= ~priv->hw->link.speed_mask;
845 switch (state->speed) {
847 ctrl |= priv->hw->link.speed1000;
850 ctrl |= priv->hw->link.speed100;
853 ctrl |= priv->hw->link.speed10;
859 priv->speed = state->speed;
861 if (priv->plat->fix_mac_speed)
862 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
865 ctrl &= ~priv->hw->link.duplex;
867 ctrl |= priv->hw->link.duplex;
869 /* Flow Control operation */
871 stmmac_mac_flow_ctrl(priv, state->duplex);
873 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
876 static void stmmac_mac_an_restart(struct phylink_config *config)
881 static void stmmac_mac_link_down(struct phylink_config *config,
882 unsigned int mode, phy_interface_t interface)
884 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
886 stmmac_mac_set(priv, priv->ioaddr, false);
887 priv->eee_active = false;
888 stmmac_eee_init(priv);
889 stmmac_set_eee_pls(priv, priv->hw, false);
892 static void stmmac_mac_link_up(struct phylink_config *config,
893 unsigned int mode, phy_interface_t interface,
894 struct phy_device *phy)
896 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
898 stmmac_mac_set(priv, priv->ioaddr, true);
899 if (phy && priv->dma_cap.eee) {
900 priv->eee_active = phy_init_eee(phy, 1) >= 0;
901 priv->eee_enabled = stmmac_eee_init(priv);
902 stmmac_set_eee_pls(priv, priv->hw, true);
906 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
907 .validate = stmmac_validate,
908 .mac_link_state = stmmac_mac_link_state,
909 .mac_config = stmmac_mac_config,
910 .mac_an_restart = stmmac_mac_an_restart,
911 .mac_link_down = stmmac_mac_link_down,
912 .mac_link_up = stmmac_mac_link_up,
916 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
917 * @priv: driver private structure
918 * Description: this is to verify if the HW supports the PCS.
919 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
920 * configured for the TBI, RTBI, or SGMII PHY interface.
922 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
924 int interface = priv->plat->interface;
926 if (priv->dma_cap.pcs) {
927 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
928 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
929 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
930 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
931 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
932 priv->hw->pcs = STMMAC_PCS_RGMII;
933 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
934 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
935 priv->hw->pcs = STMMAC_PCS_SGMII;
941 * stmmac_init_phy - PHY initialization
942 * @dev: net device structure
943 * Description: it initializes the driver's PHY state, and attaches the PHY
948 static int stmmac_init_phy(struct net_device *dev)
950 struct stmmac_priv *priv = netdev_priv(dev);
951 struct device_node *node;
954 node = priv->plat->phylink_node;
957 ret = phylink_of_phy_connect(priv->phylink, node, 0);
959 /* Some DT bindings do not set-up the PHY handle. Let's try to
963 int addr = priv->plat->phy_addr;
964 struct phy_device *phydev;
966 phydev = mdiobus_get_phy(priv->mii, addr);
968 netdev_err(priv->dev, "no phy at addr %d\n", addr);
972 ret = phylink_connect_phy(priv->phylink, phydev);
978 static int stmmac_phy_setup(struct stmmac_priv *priv)
980 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
981 int mode = priv->plat->interface;
982 struct phylink *phylink;
984 priv->phylink_config.dev = &priv->dev->dev;
985 priv->phylink_config.type = PHYLINK_NETDEV;
987 phylink = phylink_create(&priv->phylink_config, fwnode,
988 mode, &stmmac_phylink_mac_ops);
990 return PTR_ERR(phylink);
992 priv->phylink = phylink;
996 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
998 u32 rx_cnt = priv->plat->rx_queues_to_use;
1002 /* Display RX rings */
1003 for (queue = 0; queue < rx_cnt; queue++) {
1004 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1006 pr_info("\tRX Queue %u rings\n", queue);
1008 if (priv->extend_desc)
1009 head_rx = (void *)rx_q->dma_erx;
1011 head_rx = (void *)rx_q->dma_rx;
1013 /* Display RX ring */
1014 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1018 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1020 u32 tx_cnt = priv->plat->tx_queues_to_use;
1024 /* Display TX rings */
1025 for (queue = 0; queue < tx_cnt; queue++) {
1026 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1028 pr_info("\tTX Queue %d rings\n", queue);
1030 if (priv->extend_desc)
1031 head_tx = (void *)tx_q->dma_etx;
1033 head_tx = (void *)tx_q->dma_tx;
1035 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1039 static void stmmac_display_rings(struct stmmac_priv *priv)
1041 /* Display RX ring */
1042 stmmac_display_rx_rings(priv);
1044 /* Display TX ring */
1045 stmmac_display_tx_rings(priv);
1048 static int stmmac_set_bfsize(int mtu, int bufsize)
1052 if (mtu >= BUF_SIZE_4KiB)
1053 ret = BUF_SIZE_8KiB;
1054 else if (mtu >= BUF_SIZE_2KiB)
1055 ret = BUF_SIZE_4KiB;
1056 else if (mtu > DEFAULT_BUFSIZE)
1057 ret = BUF_SIZE_2KiB;
1059 ret = DEFAULT_BUFSIZE;
1065 * stmmac_clear_rx_descriptors - clear RX descriptors
1066 * @priv: driver private structure
1067 * @queue: RX queue index
1068 * Description: this function is called to clear the RX descriptors
1069 * in case of both basic and extended descriptors are used.
1071 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1073 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1076 /* Clear the RX descriptors */
1077 for (i = 0; i < DMA_RX_SIZE; i++)
1078 if (priv->extend_desc)
1079 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1080 priv->use_riwt, priv->mode,
1081 (i == DMA_RX_SIZE - 1),
1084 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1085 priv->use_riwt, priv->mode,
1086 (i == DMA_RX_SIZE - 1),
1091 * stmmac_clear_tx_descriptors - clear tx descriptors
1092 * @priv: driver private structure
1093 * @queue: TX queue index.
1094 * Description: this function is called to clear the TX descriptors
1095 * in case of both basic and extended descriptors are used.
1097 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1099 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1102 /* Clear the TX descriptors */
1103 for (i = 0; i < DMA_TX_SIZE; i++)
1104 if (priv->extend_desc)
1105 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1106 priv->mode, (i == DMA_TX_SIZE - 1));
1108 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1109 priv->mode, (i == DMA_TX_SIZE - 1));
1113 * stmmac_clear_descriptors - clear descriptors
1114 * @priv: driver private structure
1115 * Description: this function is called to clear the TX and RX descriptors
1116 * in case of both basic and extended descriptors are used.
1118 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1120 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1121 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1124 /* Clear the RX descriptors */
1125 for (queue = 0; queue < rx_queue_cnt; queue++)
1126 stmmac_clear_rx_descriptors(priv, queue);
1128 /* Clear the TX descriptors */
1129 for (queue = 0; queue < tx_queue_cnt; queue++)
1130 stmmac_clear_tx_descriptors(priv, queue);
1134 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1135 * @priv: driver private structure
1136 * @p: descriptor pointer
1137 * @i: descriptor index
1139 * @queue: RX queue index
1140 * Description: this function is called to allocate a receive buffer, perform
1141 * the DMA mapping and init the descriptor.
1143 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1144 int i, gfp_t flags, u32 queue)
1146 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1147 struct sk_buff *skb;
1149 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1151 netdev_err(priv->dev,
1152 "%s: Rx init fails; skb is NULL\n", __func__);
1155 rx_q->rx_skbuff[i] = skb;
1156 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1159 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1160 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1161 dev_kfree_skb_any(skb);
1165 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1167 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1168 stmmac_init_desc3(priv, p);
1174 * stmmac_free_rx_buffer - free RX dma buffers
1175 * @priv: private structure
1176 * @queue: RX queue index
1179 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1181 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1183 if (rx_q->rx_skbuff[i]) {
1184 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1185 priv->dma_buf_sz, DMA_FROM_DEVICE);
1186 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1188 rx_q->rx_skbuff[i] = NULL;
1192 * stmmac_free_tx_buffer - free RX dma buffers
1193 * @priv: private structure
1194 * @queue: RX queue index
1197 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1199 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1201 if (tx_q->tx_skbuff_dma[i].buf) {
1202 if (tx_q->tx_skbuff_dma[i].map_as_page)
1203 dma_unmap_page(priv->device,
1204 tx_q->tx_skbuff_dma[i].buf,
1205 tx_q->tx_skbuff_dma[i].len,
1208 dma_unmap_single(priv->device,
1209 tx_q->tx_skbuff_dma[i].buf,
1210 tx_q->tx_skbuff_dma[i].len,
1214 if (tx_q->tx_skbuff[i]) {
1215 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1216 tx_q->tx_skbuff[i] = NULL;
1217 tx_q->tx_skbuff_dma[i].buf = 0;
1218 tx_q->tx_skbuff_dma[i].map_as_page = false;
1223 * init_dma_rx_desc_rings - init the RX descriptor rings
1224 * @dev: net device structure
1226 * Description: this function initializes the DMA RX descriptors
1227 * and allocates the socket buffers. It supports the chained and ring
1230 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1232 struct stmmac_priv *priv = netdev_priv(dev);
1233 u32 rx_count = priv->plat->rx_queues_to_use;
1239 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1243 if (bfsize < BUF_SIZE_16KiB)
1244 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1246 priv->dma_buf_sz = bfsize;
1248 /* RX INITIALIZATION */
1249 netif_dbg(priv, probe, priv->dev,
1250 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1252 for (queue = 0; queue < rx_count; queue++) {
1253 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1255 netif_dbg(priv, probe, priv->dev,
1256 "(%s) dma_rx_phy=0x%08x\n", __func__,
1257 (u32)rx_q->dma_rx_phy);
1259 for (i = 0; i < DMA_RX_SIZE; i++) {
1262 if (priv->extend_desc)
1263 p = &((rx_q->dma_erx + i)->basic);
1265 p = rx_q->dma_rx + i;
1267 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1270 goto err_init_rx_buffers;
1272 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1273 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1274 (unsigned int)rx_q->rx_skbuff_dma[i]);
1278 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1280 stmmac_clear_rx_descriptors(priv, queue);
1282 /* Setup the chained descriptor addresses */
1283 if (priv->mode == STMMAC_CHAIN_MODE) {
1284 if (priv->extend_desc)
1285 stmmac_mode_init(priv, rx_q->dma_erx,
1286 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1288 stmmac_mode_init(priv, rx_q->dma_rx,
1289 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1297 err_init_rx_buffers:
1298 while (queue >= 0) {
1300 stmmac_free_rx_buffer(priv, queue, i);
1313 * init_dma_tx_desc_rings - init the TX descriptor rings
1314 * @dev: net device structure.
1315 * Description: this function initializes the DMA TX descriptors
1316 * and allocates the socket buffers. It supports the chained and ring
1319 static int init_dma_tx_desc_rings(struct net_device *dev)
1321 struct stmmac_priv *priv = netdev_priv(dev);
1322 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1326 for (queue = 0; queue < tx_queue_cnt; queue++) {
1327 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1329 netif_dbg(priv, probe, priv->dev,
1330 "(%s) dma_tx_phy=0x%08x\n", __func__,
1331 (u32)tx_q->dma_tx_phy);
1333 /* Setup the chained descriptor addresses */
1334 if (priv->mode == STMMAC_CHAIN_MODE) {
1335 if (priv->extend_desc)
1336 stmmac_mode_init(priv, tx_q->dma_etx,
1337 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1339 stmmac_mode_init(priv, tx_q->dma_tx,
1340 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1343 for (i = 0; i < DMA_TX_SIZE; i++) {
1345 if (priv->extend_desc)
1346 p = &((tx_q->dma_etx + i)->basic);
1348 p = tx_q->dma_tx + i;
1350 stmmac_clear_desc(priv, p);
1352 tx_q->tx_skbuff_dma[i].buf = 0;
1353 tx_q->tx_skbuff_dma[i].map_as_page = false;
1354 tx_q->tx_skbuff_dma[i].len = 0;
1355 tx_q->tx_skbuff_dma[i].last_segment = false;
1356 tx_q->tx_skbuff[i] = NULL;
1363 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1370 * init_dma_desc_rings - init the RX/TX descriptor rings
1371 * @dev: net device structure
1373 * Description: this function initializes the DMA RX/TX descriptors
1374 * and allocates the socket buffers. It supports the chained and ring
1377 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1379 struct stmmac_priv *priv = netdev_priv(dev);
1382 ret = init_dma_rx_desc_rings(dev, flags);
1386 ret = init_dma_tx_desc_rings(dev);
1388 stmmac_clear_descriptors(priv);
1390 if (netif_msg_hw(priv))
1391 stmmac_display_rings(priv);
1397 * dma_free_rx_skbufs - free RX dma buffers
1398 * @priv: private structure
1399 * @queue: RX queue index
1401 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1405 for (i = 0; i < DMA_RX_SIZE; i++)
1406 stmmac_free_rx_buffer(priv, queue, i);
1410 * dma_free_tx_skbufs - free TX dma buffers
1411 * @priv: private structure
1412 * @queue: TX queue index
1414 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1418 for (i = 0; i < DMA_TX_SIZE; i++)
1419 stmmac_free_tx_buffer(priv, queue, i);
1423 * free_dma_rx_desc_resources - free RX dma desc resources
1424 * @priv: private structure
1426 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1428 u32 rx_count = priv->plat->rx_queues_to_use;
1431 /* Free RX queue resources */
1432 for (queue = 0; queue < rx_count; queue++) {
1433 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1435 /* Release the DMA RX socket buffers */
1436 dma_free_rx_skbufs(priv, queue);
1438 /* Free DMA regions of consistent memory previously allocated */
1439 if (!priv->extend_desc)
1440 dma_free_coherent(priv->device,
1441 DMA_RX_SIZE * sizeof(struct dma_desc),
1442 rx_q->dma_rx, rx_q->dma_rx_phy);
1444 dma_free_coherent(priv->device, DMA_RX_SIZE *
1445 sizeof(struct dma_extended_desc),
1446 rx_q->dma_erx, rx_q->dma_rx_phy);
1448 kfree(rx_q->rx_skbuff_dma);
1449 kfree(rx_q->rx_skbuff);
1454 * free_dma_tx_desc_resources - free TX dma desc resources
1455 * @priv: private structure
1457 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1459 u32 tx_count = priv->plat->tx_queues_to_use;
1462 /* Free TX queue resources */
1463 for (queue = 0; queue < tx_count; queue++) {
1464 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1466 /* Release the DMA TX socket buffers */
1467 dma_free_tx_skbufs(priv, queue);
1469 /* Free DMA regions of consistent memory previously allocated */
1470 if (!priv->extend_desc)
1471 dma_free_coherent(priv->device,
1472 DMA_TX_SIZE * sizeof(struct dma_desc),
1473 tx_q->dma_tx, tx_q->dma_tx_phy);
1475 dma_free_coherent(priv->device, DMA_TX_SIZE *
1476 sizeof(struct dma_extended_desc),
1477 tx_q->dma_etx, tx_q->dma_tx_phy);
1479 kfree(tx_q->tx_skbuff_dma);
1480 kfree(tx_q->tx_skbuff);
1485 * alloc_dma_rx_desc_resources - alloc RX resources.
1486 * @priv: private structure
1487 * Description: according to which descriptor can be used (extend or basic)
1488 * this function allocates the resources for TX and RX paths. In case of
1489 * reception, for example, it pre-allocated the RX socket buffer in order to
1490 * allow zero-copy mechanism.
1492 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1494 u32 rx_count = priv->plat->rx_queues_to_use;
1498 /* RX queues buffers and DMA */
1499 for (queue = 0; queue < rx_count; queue++) {
1500 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1502 rx_q->queue_index = queue;
1503 rx_q->priv_data = priv;
1505 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1508 if (!rx_q->rx_skbuff_dma)
1511 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1512 sizeof(struct sk_buff *),
1514 if (!rx_q->rx_skbuff)
1517 if (priv->extend_desc) {
1518 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1519 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1526 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1527 DMA_RX_SIZE * sizeof(struct dma_desc),
1538 free_dma_rx_desc_resources(priv);
1544 * alloc_dma_tx_desc_resources - alloc TX resources.
1545 * @priv: private structure
1546 * Description: according to which descriptor can be used (extend or basic)
1547 * this function allocates the resources for TX and RX paths. In case of
1548 * reception, for example, it pre-allocated the RX socket buffer in order to
1549 * allow zero-copy mechanism.
1551 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1553 u32 tx_count = priv->plat->tx_queues_to_use;
1557 /* TX queues buffers and DMA */
1558 for (queue = 0; queue < tx_count; queue++) {
1559 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1561 tx_q->queue_index = queue;
1562 tx_q->priv_data = priv;
1564 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1565 sizeof(*tx_q->tx_skbuff_dma),
1567 if (!tx_q->tx_skbuff_dma)
1570 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1571 sizeof(struct sk_buff *),
1573 if (!tx_q->tx_skbuff)
1576 if (priv->extend_desc) {
1577 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1578 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1584 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1585 DMA_TX_SIZE * sizeof(struct dma_desc),
1596 free_dma_tx_desc_resources(priv);
1602 * alloc_dma_desc_resources - alloc TX/RX resources.
1603 * @priv: private structure
1604 * Description: according to which descriptor can be used (extend or basic)
1605 * this function allocates the resources for TX and RX paths. In case of
1606 * reception, for example, it pre-allocated the RX socket buffer in order to
1607 * allow zero-copy mechanism.
1609 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1612 int ret = alloc_dma_rx_desc_resources(priv);
1617 ret = alloc_dma_tx_desc_resources(priv);
1623 * free_dma_desc_resources - free dma desc resources
1624 * @priv: private structure
1626 static void free_dma_desc_resources(struct stmmac_priv *priv)
1628 /* Release the DMA RX socket buffers */
1629 free_dma_rx_desc_resources(priv);
1631 /* Release the DMA TX socket buffers */
1632 free_dma_tx_desc_resources(priv);
1636 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1637 * @priv: driver private structure
1638 * Description: It is used for enabling the rx queues in the MAC
1640 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1642 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1646 for (queue = 0; queue < rx_queues_count; queue++) {
1647 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1648 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1653 * stmmac_start_rx_dma - start RX DMA channel
1654 * @priv: driver private structure
1655 * @chan: RX channel index
1657 * This starts a RX DMA channel
1659 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1661 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1662 stmmac_start_rx(priv, priv->ioaddr, chan);
1666 * stmmac_start_tx_dma - start TX DMA channel
1667 * @priv: driver private structure
1668 * @chan: TX channel index
1670 * This starts a TX DMA channel
1672 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1674 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1675 stmmac_start_tx(priv, priv->ioaddr, chan);
1679 * stmmac_stop_rx_dma - stop RX DMA channel
1680 * @priv: driver private structure
1681 * @chan: RX channel index
1683 * This stops a RX DMA channel
1685 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1687 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1688 stmmac_stop_rx(priv, priv->ioaddr, chan);
1692 * stmmac_stop_tx_dma - stop TX DMA channel
1693 * @priv: driver private structure
1694 * @chan: TX channel index
1696 * This stops a TX DMA channel
1698 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1700 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1701 stmmac_stop_tx(priv, priv->ioaddr, chan);
1705 * stmmac_start_all_dma - start all RX and TX DMA channels
1706 * @priv: driver private structure
1708 * This starts all the RX and TX DMA channels
1710 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1712 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1713 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1716 for (chan = 0; chan < rx_channels_count; chan++)
1717 stmmac_start_rx_dma(priv, chan);
1719 for (chan = 0; chan < tx_channels_count; chan++)
1720 stmmac_start_tx_dma(priv, chan);
1724 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1725 * @priv: driver private structure
1727 * This stops the RX and TX DMA channels
1729 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1731 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1732 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1735 for (chan = 0; chan < rx_channels_count; chan++)
1736 stmmac_stop_rx_dma(priv, chan);
1738 for (chan = 0; chan < tx_channels_count; chan++)
1739 stmmac_stop_tx_dma(priv, chan);
1743 * stmmac_dma_operation_mode - HW DMA operation mode
1744 * @priv: driver private structure
1745 * Description: it is used for configuring the DMA operation mode register in
1746 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1748 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1750 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1751 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1752 int rxfifosz = priv->plat->rx_fifo_size;
1753 int txfifosz = priv->plat->tx_fifo_size;
1760 rxfifosz = priv->dma_cap.rx_fifo_size;
1762 txfifosz = priv->dma_cap.tx_fifo_size;
1764 /* Adjust for real per queue fifo size */
1765 rxfifosz /= rx_channels_count;
1766 txfifosz /= tx_channels_count;
1768 if (priv->plat->force_thresh_dma_mode) {
1771 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1773 * In case of GMAC, SF mode can be enabled
1774 * to perform the TX COE in HW. This depends on:
1775 * 1) TX COE if actually supported
1776 * 2) There is no bugged Jumbo frame support
1777 * that needs to not insert csum in the TDES.
1779 txmode = SF_DMA_MODE;
1780 rxmode = SF_DMA_MODE;
1781 priv->xstats.threshold = SF_DMA_MODE;
1784 rxmode = SF_DMA_MODE;
1787 /* configure all channels */
1788 for (chan = 0; chan < rx_channels_count; chan++) {
1789 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1791 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1793 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1797 for (chan = 0; chan < tx_channels_count; chan++) {
1798 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1800 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1806 * stmmac_tx_clean - to manage the transmission completion
1807 * @priv: driver private structure
1808 * @queue: TX queue index
1809 * Description: it reclaims the transmit resources after transmission completes.
1811 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1813 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1814 unsigned int bytes_compl = 0, pkts_compl = 0;
1815 unsigned int entry, count = 0;
1817 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1819 priv->xstats.tx_clean++;
1821 entry = tx_q->dirty_tx;
1822 while ((entry != tx_q->cur_tx) && (count < budget)) {
1823 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1827 if (priv->extend_desc)
1828 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1830 p = tx_q->dma_tx + entry;
1832 status = stmmac_tx_status(priv, &priv->dev->stats,
1833 &priv->xstats, p, priv->ioaddr);
1834 /* Check if the descriptor is owned by the DMA */
1835 if (unlikely(status & tx_dma_own))
1840 /* Make sure descriptor fields are read after reading
1845 /* Just consider the last segment and ...*/
1846 if (likely(!(status & tx_not_ls))) {
1847 /* ... verify the status error condition */
1848 if (unlikely(status & tx_err)) {
1849 priv->dev->stats.tx_errors++;
1851 priv->dev->stats.tx_packets++;
1852 priv->xstats.tx_pkt_n++;
1854 stmmac_get_tx_hwtstamp(priv, p, skb);
1857 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1858 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1859 dma_unmap_page(priv->device,
1860 tx_q->tx_skbuff_dma[entry].buf,
1861 tx_q->tx_skbuff_dma[entry].len,
1864 dma_unmap_single(priv->device,
1865 tx_q->tx_skbuff_dma[entry].buf,
1866 tx_q->tx_skbuff_dma[entry].len,
1868 tx_q->tx_skbuff_dma[entry].buf = 0;
1869 tx_q->tx_skbuff_dma[entry].len = 0;
1870 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1873 stmmac_clean_desc3(priv, tx_q, p);
1875 tx_q->tx_skbuff_dma[entry].last_segment = false;
1876 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1878 if (likely(skb != NULL)) {
1880 bytes_compl += skb->len;
1881 dev_consume_skb_any(skb);
1882 tx_q->tx_skbuff[entry] = NULL;
1885 stmmac_release_tx_desc(priv, p, priv->mode);
1887 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1889 tx_q->dirty_tx = entry;
1891 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1892 pkts_compl, bytes_compl);
1894 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1896 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1898 netif_dbg(priv, tx_done, priv->dev,
1899 "%s: restart transmit\n", __func__);
1900 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1903 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1904 stmmac_enable_eee_mode(priv);
1905 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1908 /* We still have pending packets, let's call for a new scheduling */
1909 if (tx_q->dirty_tx != tx_q->cur_tx)
1910 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1912 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1918 * stmmac_tx_err - to manage the tx error
1919 * @priv: driver private structure
1920 * @chan: channel index
1921 * Description: it cleans the descriptors and restarts the transmission
1922 * in case of transmission errors.
1924 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1926 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1929 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1931 stmmac_stop_tx_dma(priv, chan);
1932 dma_free_tx_skbufs(priv, chan);
1933 for (i = 0; i < DMA_TX_SIZE; i++)
1934 if (priv->extend_desc)
1935 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1936 priv->mode, (i == DMA_TX_SIZE - 1));
1938 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1939 priv->mode, (i == DMA_TX_SIZE - 1));
1943 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1944 stmmac_start_tx_dma(priv, chan);
1946 priv->dev->stats.tx_errors++;
1947 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1951 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1952 * @priv: driver private structure
1953 * @txmode: TX operating mode
1954 * @rxmode: RX operating mode
1955 * @chan: channel index
1956 * Description: it is used for configuring of the DMA operation mode in
1957 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1960 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1961 u32 rxmode, u32 chan)
1963 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1964 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1965 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1966 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1967 int rxfifosz = priv->plat->rx_fifo_size;
1968 int txfifosz = priv->plat->tx_fifo_size;
1971 rxfifosz = priv->dma_cap.rx_fifo_size;
1973 txfifosz = priv->dma_cap.tx_fifo_size;
1975 /* Adjust for real per queue fifo size */
1976 rxfifosz /= rx_channels_count;
1977 txfifosz /= tx_channels_count;
1979 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
1980 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
1983 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
1987 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
1988 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
1989 if (ret && (ret != -EINVAL)) {
1990 stmmac_global_err(priv);
1997 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
1999 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2000 &priv->xstats, chan);
2001 struct stmmac_channel *ch = &priv->channel[chan];
2004 status |= handle_rx | handle_tx;
2006 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2007 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2008 napi_schedule_irqoff(&ch->rx_napi);
2011 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2012 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2013 napi_schedule_irqoff(&ch->tx_napi);
2020 * stmmac_dma_interrupt - DMA ISR
2021 * @priv: driver private structure
2022 * Description: this is the DMA ISR. It is called by the main ISR.
2023 * It calls the dwmac dma routine and schedule poll method in case of some
2026 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2028 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2029 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2030 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2031 tx_channel_count : rx_channel_count;
2033 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2035 /* Make sure we never check beyond our status buffer. */
2036 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2037 channels_to_check = ARRAY_SIZE(status);
2039 for (chan = 0; chan < channels_to_check; chan++)
2040 status[chan] = stmmac_napi_check(priv, chan);
2042 for (chan = 0; chan < tx_channel_count; chan++) {
2043 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2044 /* Try to bump up the dma threshold on this failure */
2045 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2048 if (priv->plat->force_thresh_dma_mode)
2049 stmmac_set_dma_operation_mode(priv,
2054 stmmac_set_dma_operation_mode(priv,
2058 priv->xstats.threshold = tc;
2060 } else if (unlikely(status[chan] == tx_hard_error)) {
2061 stmmac_tx_err(priv, chan);
2067 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2068 * @priv: driver private structure
2069 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2071 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2073 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2074 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2076 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2078 if (priv->dma_cap.rmon) {
2079 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2080 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2082 netdev_info(priv->dev, "No MAC Management Counters available\n");
2086 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2087 * @priv: driver private structure
2089 * new GMAC chip generations have a new register to indicate the
2090 * presence of the optional feature/functions.
2091 * This can be also used to override the value passed through the
2092 * platform and necessary for old MAC10/100 and GMAC chips.
2094 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2096 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2100 * stmmac_check_ether_addr - check if the MAC addr is valid
2101 * @priv: driver private structure
2103 * it is to verify if the MAC address is valid, in case of failures it
2104 * generates a random MAC address
2106 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2108 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2109 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2110 if (!is_valid_ether_addr(priv->dev->dev_addr))
2111 eth_hw_addr_random(priv->dev);
2112 dev_info(priv->device, "device MAC address %pM\n",
2113 priv->dev->dev_addr);
2118 * stmmac_init_dma_engine - DMA init.
2119 * @priv: driver private structure
2121 * It inits the DMA invoking the specific MAC/GMAC callback.
2122 * Some DMA parameters can be passed from the platform;
2123 * in case of these are not passed a default is kept for the MAC or GMAC.
2125 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2127 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2128 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2129 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2130 struct stmmac_rx_queue *rx_q;
2131 struct stmmac_tx_queue *tx_q;
2136 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2137 dev_err(priv->device, "Invalid DMA configuration\n");
2141 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2144 ret = stmmac_reset(priv, priv->ioaddr);
2146 dev_err(priv->device, "Failed to reset the dma\n");
2150 /* DMA Configuration */
2151 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2153 if (priv->plat->axi)
2154 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2156 /* DMA CSR Channel configuration */
2157 for (chan = 0; chan < dma_csr_ch; chan++)
2158 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2160 /* DMA RX Channel Configuration */
2161 for (chan = 0; chan < rx_channels_count; chan++) {
2162 rx_q = &priv->rx_queue[chan];
2164 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2165 rx_q->dma_rx_phy, chan);
2167 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2168 (DMA_RX_SIZE * sizeof(struct dma_desc));
2169 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2170 rx_q->rx_tail_addr, chan);
2173 /* DMA TX Channel Configuration */
2174 for (chan = 0; chan < tx_channels_count; chan++) {
2175 tx_q = &priv->tx_queue[chan];
2177 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2178 tx_q->dma_tx_phy, chan);
2180 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2181 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2182 tx_q->tx_tail_addr, chan);
2188 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2190 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2192 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2196 * stmmac_tx_timer - mitigation sw timer for tx.
2197 * @data: data pointer
2199 * This is the timer handler to directly invoke the stmmac_tx_clean.
2201 static void stmmac_tx_timer(struct timer_list *t)
2203 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2204 struct stmmac_priv *priv = tx_q->priv_data;
2205 struct stmmac_channel *ch;
2207 ch = &priv->channel[tx_q->queue_index];
2210 * If NAPI is already running we can miss some events. Let's rearm
2211 * the timer and try again.
2213 if (likely(napi_schedule_prep(&ch->tx_napi)))
2214 __napi_schedule(&ch->tx_napi);
2216 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2220 * stmmac_init_tx_coalesce - init tx mitigation options.
2221 * @priv: driver private structure
2223 * This inits the transmit coalesce parameters: i.e. timer rate,
2224 * timer handler and default threshold used for enabling the
2225 * interrupt on completion bit.
2227 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2229 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2232 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2233 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2235 for (chan = 0; chan < tx_channel_count; chan++) {
2236 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2238 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2242 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2244 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2245 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2248 /* set TX ring length */
2249 for (chan = 0; chan < tx_channels_count; chan++)
2250 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2251 (DMA_TX_SIZE - 1), chan);
2253 /* set RX ring length */
2254 for (chan = 0; chan < rx_channels_count; chan++)
2255 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2256 (DMA_RX_SIZE - 1), chan);
2260 * stmmac_set_tx_queue_weight - Set TX queue weight
2261 * @priv: driver private structure
2262 * Description: It is used for setting TX queues weight
2264 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2266 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2270 for (queue = 0; queue < tx_queues_count; queue++) {
2271 weight = priv->plat->tx_queues_cfg[queue].weight;
2272 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2277 * stmmac_configure_cbs - Configure CBS in TX queue
2278 * @priv: driver private structure
2279 * Description: It is used for configuring CBS in AVB TX queues
2281 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2283 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2287 /* queue 0 is reserved for legacy traffic */
2288 for (queue = 1; queue < tx_queues_count; queue++) {
2289 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2290 if (mode_to_use == MTL_QUEUE_DCB)
2293 stmmac_config_cbs(priv, priv->hw,
2294 priv->plat->tx_queues_cfg[queue].send_slope,
2295 priv->plat->tx_queues_cfg[queue].idle_slope,
2296 priv->plat->tx_queues_cfg[queue].high_credit,
2297 priv->plat->tx_queues_cfg[queue].low_credit,
2303 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2304 * @priv: driver private structure
2305 * Description: It is used for mapping RX queues to RX dma channels
2307 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2309 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2313 for (queue = 0; queue < rx_queues_count; queue++) {
2314 chan = priv->plat->rx_queues_cfg[queue].chan;
2315 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2320 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2321 * @priv: driver private structure
2322 * Description: It is used for configuring the RX Queue Priority
2324 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2326 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2330 for (queue = 0; queue < rx_queues_count; queue++) {
2331 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2334 prio = priv->plat->rx_queues_cfg[queue].prio;
2335 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2340 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2341 * @priv: driver private structure
2342 * Description: It is used for configuring the TX Queue Priority
2344 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2346 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2350 for (queue = 0; queue < tx_queues_count; queue++) {
2351 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2354 prio = priv->plat->tx_queues_cfg[queue].prio;
2355 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2360 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2361 * @priv: driver private structure
2362 * Description: It is used for configuring the RX queue routing
2364 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2366 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2370 for (queue = 0; queue < rx_queues_count; queue++) {
2371 /* no specific packet type routing specified for the queue */
2372 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2375 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2376 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2381 * stmmac_mtl_configuration - Configure MTL
2382 * @priv: driver private structure
2383 * Description: It is used for configurring MTL
2385 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2387 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2388 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2390 if (tx_queues_count > 1)
2391 stmmac_set_tx_queue_weight(priv);
2393 /* Configure MTL RX algorithms */
2394 if (rx_queues_count > 1)
2395 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2396 priv->plat->rx_sched_algorithm);
2398 /* Configure MTL TX algorithms */
2399 if (tx_queues_count > 1)
2400 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2401 priv->plat->tx_sched_algorithm);
2403 /* Configure CBS in AVB TX queues */
2404 if (tx_queues_count > 1)
2405 stmmac_configure_cbs(priv);
2407 /* Map RX MTL to DMA channels */
2408 stmmac_rx_queue_dma_chan_map(priv);
2410 /* Enable MAC RX Queues */
2411 stmmac_mac_enable_rx_queues(priv);
2413 /* Set RX priorities */
2414 if (rx_queues_count > 1)
2415 stmmac_mac_config_rx_queues_prio(priv);
2417 /* Set TX priorities */
2418 if (tx_queues_count > 1)
2419 stmmac_mac_config_tx_queues_prio(priv);
2421 /* Set RX routing */
2422 if (rx_queues_count > 1)
2423 stmmac_mac_config_rx_queues_routing(priv);
2426 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2428 if (priv->dma_cap.asp) {
2429 netdev_info(priv->dev, "Enabling Safety Features\n");
2430 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2432 netdev_info(priv->dev, "No Safety Features support found\n");
2437 * stmmac_hw_setup - setup mac in a usable state.
2438 * @dev : pointer to the device structure.
2440 * this is the main function to setup the HW in a usable state because the
2441 * dma engine is reset, the core registers are configured (e.g. AXI,
2442 * Checksum features, timers). The DMA is ready to start receiving and
2445 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2448 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2450 struct stmmac_priv *priv = netdev_priv(dev);
2451 u32 rx_cnt = priv->plat->rx_queues_to_use;
2452 u32 tx_cnt = priv->plat->tx_queues_to_use;
2456 /* DMA initialization and SW reset */
2457 ret = stmmac_init_dma_engine(priv);
2459 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2464 /* Copy the MAC addr into the HW */
2465 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2467 /* PS and related bits will be programmed according to the speed */
2468 if (priv->hw->pcs) {
2469 int speed = priv->plat->mac_port_sel_speed;
2471 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2472 (speed == SPEED_1000)) {
2473 priv->hw->ps = speed;
2475 dev_warn(priv->device, "invalid port speed\n");
2480 /* Initialize the MAC Core */
2481 stmmac_core_init(priv, priv->hw, dev);
2484 stmmac_mtl_configuration(priv);
2486 /* Initialize Safety Features */
2487 stmmac_safety_feat_configuration(priv);
2489 ret = stmmac_rx_ipc(priv, priv->hw);
2491 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2492 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2493 priv->hw->rx_csum = 0;
2496 /* Enable the MAC Rx/Tx */
2497 stmmac_mac_set(priv, priv->ioaddr, true);
2499 /* Set the HW DMA mode and the COE */
2500 stmmac_dma_operation_mode(priv);
2502 stmmac_mmc_setup(priv);
2505 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2507 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2509 ret = stmmac_init_ptp(priv);
2510 if (ret == -EOPNOTSUPP)
2511 netdev_warn(priv->dev, "PTP not supported by HW\n");
2513 netdev_warn(priv->dev, "PTP init failed\n");
2516 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2518 if (priv->use_riwt) {
2519 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2521 priv->rx_riwt = MAX_DMA_RIWT;
2525 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2527 /* set TX and RX rings length */
2528 stmmac_set_rings_length(priv);
2532 for (chan = 0; chan < tx_cnt; chan++)
2533 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2536 /* Start the ball rolling... */
2537 stmmac_start_all_dma(priv);
2542 static void stmmac_hw_teardown(struct net_device *dev)
2544 struct stmmac_priv *priv = netdev_priv(dev);
2546 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2550 * stmmac_open - open entry point of the driver
2551 * @dev : pointer to the device structure.
2553 * This function is the open entry point of the driver.
2555 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2558 static int stmmac_open(struct net_device *dev)
2560 struct stmmac_priv *priv = netdev_priv(dev);
2564 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2565 priv->hw->pcs != STMMAC_PCS_TBI &&
2566 priv->hw->pcs != STMMAC_PCS_RTBI) {
2567 ret = stmmac_init_phy(dev);
2569 netdev_err(priv->dev,
2570 "%s: Cannot attach to PHY (error: %d)\n",
2576 /* Extra statistics */
2577 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2578 priv->xstats.threshold = tc;
2580 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2581 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2583 ret = alloc_dma_desc_resources(priv);
2585 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2587 goto dma_desc_error;
2590 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2592 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2597 ret = stmmac_hw_setup(dev, true);
2599 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2603 stmmac_init_tx_coalesce(priv);
2605 phylink_start(priv->phylink);
2607 /* Request the IRQ lines */
2608 ret = request_irq(dev->irq, stmmac_interrupt,
2609 IRQF_SHARED, dev->name, dev);
2610 if (unlikely(ret < 0)) {
2611 netdev_err(priv->dev,
2612 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2613 __func__, dev->irq, ret);
2617 /* Request the Wake IRQ in case of another line is used for WoL */
2618 if (priv->wol_irq != dev->irq) {
2619 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2620 IRQF_SHARED, dev->name, dev);
2621 if (unlikely(ret < 0)) {
2622 netdev_err(priv->dev,
2623 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2624 __func__, priv->wol_irq, ret);
2629 /* Request the IRQ lines */
2630 if (priv->lpi_irq > 0) {
2631 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2633 if (unlikely(ret < 0)) {
2634 netdev_err(priv->dev,
2635 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2636 __func__, priv->lpi_irq, ret);
2641 stmmac_enable_all_queues(priv);
2642 stmmac_start_all_queues(priv);
2647 if (priv->wol_irq != dev->irq)
2648 free_irq(priv->wol_irq, dev);
2650 free_irq(dev->irq, dev);
2652 phylink_stop(priv->phylink);
2654 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2655 del_timer_sync(&priv->tx_queue[chan].txtimer);
2657 stmmac_hw_teardown(dev);
2659 free_dma_desc_resources(priv);
2661 phylink_disconnect_phy(priv->phylink);
2666 * stmmac_release - close entry point of the driver
2667 * @dev : device pointer.
2669 * This is the stop entry point of the driver.
2671 static int stmmac_release(struct net_device *dev)
2673 struct stmmac_priv *priv = netdev_priv(dev);
2676 if (priv->eee_enabled)
2677 del_timer_sync(&priv->eee_ctrl_timer);
2679 /* Stop and disconnect the PHY */
2680 phylink_stop(priv->phylink);
2681 phylink_disconnect_phy(priv->phylink);
2683 stmmac_stop_all_queues(priv);
2685 stmmac_disable_all_queues(priv);
2687 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2688 del_timer_sync(&priv->tx_queue[chan].txtimer);
2690 /* Free the IRQ lines */
2691 free_irq(dev->irq, dev);
2692 if (priv->wol_irq != dev->irq)
2693 free_irq(priv->wol_irq, dev);
2694 if (priv->lpi_irq > 0)
2695 free_irq(priv->lpi_irq, dev);
2697 /* Stop TX/RX DMA and clear the descriptors */
2698 stmmac_stop_all_dma(priv);
2700 /* Release and free the Rx/Tx resources */
2701 free_dma_desc_resources(priv);
2703 /* Disable the MAC Rx/Tx */
2704 stmmac_mac_set(priv, priv->ioaddr, false);
2706 netif_carrier_off(dev);
2708 stmmac_release_ptp(priv);
2714 * stmmac_tso_allocator - close entry point of the driver
2715 * @priv: driver private structure
2716 * @des: buffer start address
2717 * @total_len: total length to fill in descriptors
2718 * @last_segmant: condition for the last descriptor
2719 * @queue: TX queue index
2721 * This function fills descriptor and request new descriptors according to
2722 * buffer length to fill
2724 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2725 int total_len, bool last_segment, u32 queue)
2727 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2728 struct dma_desc *desc;
2732 tmp_len = total_len;
2734 while (tmp_len > 0) {
2735 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2736 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2737 desc = tx_q->dma_tx + tx_q->cur_tx;
2739 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2740 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2741 TSO_MAX_BUFF_SIZE : tmp_len;
2743 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2745 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2748 tmp_len -= TSO_MAX_BUFF_SIZE;
2753 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2754 * @skb : the socket buffer
2755 * @dev : device pointer
2756 * Description: this is the transmit function that is called on TSO frames
2757 * (support available on GMAC4 and newer chips).
2758 * Diagram below show the ring programming in case of TSO frames:
2762 * | DES0 |---> buffer1 = L2/L3/L4 header
2763 * | DES1 |---> TCP Payload (can continue on next descr...)
2764 * | DES2 |---> buffer 1 and 2 len
2765 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2771 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2773 * | DES2 | --> buffer 1 and 2 len
2777 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2779 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2781 struct dma_desc *desc, *first, *mss_desc = NULL;
2782 struct stmmac_priv *priv = netdev_priv(dev);
2783 int nfrags = skb_shinfo(skb)->nr_frags;
2784 u32 queue = skb_get_queue_mapping(skb);
2785 unsigned int first_entry, des;
2786 struct stmmac_tx_queue *tx_q;
2787 int tmp_pay_len = 0;
2792 tx_q = &priv->tx_queue[queue];
2794 /* Compute header lengths */
2795 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2797 /* Desc availability based on threshold should be enough safe */
2798 if (unlikely(stmmac_tx_avail(priv, queue) <
2799 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2800 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2801 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2803 /* This is a hard error, log it. */
2804 netdev_err(priv->dev,
2805 "%s: Tx Ring full when queue awake\n",
2808 return NETDEV_TX_BUSY;
2811 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2813 mss = skb_shinfo(skb)->gso_size;
2815 /* set new MSS value if needed */
2816 if (mss != tx_q->mss) {
2817 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2818 stmmac_set_mss(priv, mss_desc, mss);
2820 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2821 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2824 if (netif_msg_tx_queued(priv)) {
2825 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2826 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2827 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2831 first_entry = tx_q->cur_tx;
2832 WARN_ON(tx_q->tx_skbuff[first_entry]);
2834 desc = tx_q->dma_tx + first_entry;
2837 /* first descriptor: fill Headers on Buf1 */
2838 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2840 if (dma_mapping_error(priv->device, des))
2843 tx_q->tx_skbuff_dma[first_entry].buf = des;
2844 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2846 first->des0 = cpu_to_le32(des);
2848 /* Fill start of payload in buff2 of first descriptor */
2850 first->des1 = cpu_to_le32(des + proto_hdr_len);
2852 /* If needed take extra descriptors to fill the remaining payload */
2853 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2855 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2857 /* Prepare fragments */
2858 for (i = 0; i < nfrags; i++) {
2859 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2861 des = skb_frag_dma_map(priv->device, frag, 0,
2862 skb_frag_size(frag),
2864 if (dma_mapping_error(priv->device, des))
2867 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2868 (i == nfrags - 1), queue);
2870 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2871 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2872 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2875 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2877 /* Only the last descriptor gets to point to the skb. */
2878 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2880 /* We've used all descriptors we need for this skb, however,
2881 * advance cur_tx so that it references a fresh descriptor.
2882 * ndo_start_xmit will fill this descriptor the next time it's
2883 * called and stmmac_tx_clean may clean up to this descriptor.
2885 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2887 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2888 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2890 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2893 dev->stats.tx_bytes += skb->len;
2894 priv->xstats.tx_tso_frames++;
2895 priv->xstats.tx_tso_nfrags += nfrags;
2897 /* Manage tx mitigation */
2898 tx_q->tx_count_frames += nfrags + 1;
2899 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
2900 !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
2901 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2902 priv->hwts_tx_en)) {
2903 stmmac_tx_timer_arm(priv, queue);
2905 tx_q->tx_count_frames = 0;
2906 stmmac_set_tx_ic(priv, desc);
2907 priv->xstats.tx_set_ic_bit++;
2910 skb_tx_timestamp(skb);
2912 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2913 priv->hwts_tx_en)) {
2914 /* declare that device is doing timestamping */
2915 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2916 stmmac_enable_tx_timestamp(priv, first);
2919 /* Complete the first descriptor before granting the DMA */
2920 stmmac_prepare_tso_tx_desc(priv, first, 1,
2923 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2924 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2926 /* If context desc is used to change MSS */
2928 /* Make sure that first descriptor has been completely
2929 * written, including its own bit. This is because MSS is
2930 * actually before first descriptor, so we need to make
2931 * sure that MSS's own bit is the last thing written.
2934 stmmac_set_tx_owner(priv, mss_desc);
2937 /* The own bit must be the latest setting done when prepare the
2938 * descriptor and then barrier is needed to make sure that
2939 * all is coherent before granting the DMA engine.
2943 if (netif_msg_pktdata(priv)) {
2944 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2945 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2946 tx_q->cur_tx, first, nfrags);
2948 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
2950 pr_info(">>> frame to be transmitted: ");
2951 print_pkt(skb->data, skb_headlen(skb));
2954 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2956 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
2957 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
2959 return NETDEV_TX_OK;
2962 dev_err(priv->device, "Tx dma map failed\n");
2964 priv->dev->stats.tx_dropped++;
2965 return NETDEV_TX_OK;
2969 * stmmac_xmit - Tx entry point of the driver
2970 * @skb : the socket buffer
2971 * @dev : device pointer
2972 * Description : this is the tx entry point of the driver.
2973 * It programs the chain or the ring and supports oversized frames
2976 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2978 struct stmmac_priv *priv = netdev_priv(dev);
2979 unsigned int nopaged_len = skb_headlen(skb);
2980 int i, csum_insertion = 0, is_jumbo = 0;
2981 u32 queue = skb_get_queue_mapping(skb);
2982 int nfrags = skb_shinfo(skb)->nr_frags;
2984 unsigned int first_entry;
2985 struct dma_desc *desc, *first;
2986 struct stmmac_tx_queue *tx_q;
2987 unsigned int enh_desc;
2990 tx_q = &priv->tx_queue[queue];
2992 if (priv->tx_path_in_lpi_mode)
2993 stmmac_disable_eee_mode(priv);
2995 /* Manage oversized TCP frames for GMAC4 device */
2996 if (skb_is_gso(skb) && priv->tso) {
2997 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
2999 * There is no way to determine the number of TSO
3000 * capable Queues. Let's use always the Queue 0
3001 * because if TSO is supported then at least this
3002 * one will be capable.
3004 skb_set_queue_mapping(skb, 0);
3006 return stmmac_tso_xmit(skb, dev);
3010 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3011 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3012 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3014 /* This is a hard error, log it. */
3015 netdev_err(priv->dev,
3016 "%s: Tx Ring full when queue awake\n",
3019 return NETDEV_TX_BUSY;
3022 entry = tx_q->cur_tx;
3023 first_entry = entry;
3024 WARN_ON(tx_q->tx_skbuff[first_entry]);
3026 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3028 if (likely(priv->extend_desc))
3029 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3031 desc = tx_q->dma_tx + entry;
3035 enh_desc = priv->plat->enh_desc;
3036 /* To program the descriptors according to the size of the frame */
3038 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3040 if (unlikely(is_jumbo)) {
3041 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3042 if (unlikely(entry < 0) && (entry != -EINVAL))
3046 for (i = 0; i < nfrags; i++) {
3047 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3048 int len = skb_frag_size(frag);
3049 bool last_segment = (i == (nfrags - 1));
3051 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3052 WARN_ON(tx_q->tx_skbuff[entry]);
3054 if (likely(priv->extend_desc))
3055 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3057 desc = tx_q->dma_tx + entry;
3059 des = skb_frag_dma_map(priv->device, frag, 0, len,
3061 if (dma_mapping_error(priv->device, des))
3062 goto dma_map_err; /* should reuse desc w/o issues */
3064 tx_q->tx_skbuff_dma[entry].buf = des;
3066 stmmac_set_desc_addr(priv, desc, des);
3068 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3069 tx_q->tx_skbuff_dma[entry].len = len;
3070 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3072 /* Prepare the descriptor and set the own bit too */
3073 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3074 priv->mode, 1, last_segment, skb->len);
3077 /* Only the last descriptor gets to point to the skb. */
3078 tx_q->tx_skbuff[entry] = skb;
3080 /* We've used all descriptors we need for this skb, however,
3081 * advance cur_tx so that it references a fresh descriptor.
3082 * ndo_start_xmit will fill this descriptor the next time it's
3083 * called and stmmac_tx_clean may clean up to this descriptor.
3085 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3086 tx_q->cur_tx = entry;
3088 if (netif_msg_pktdata(priv)) {
3091 netdev_dbg(priv->dev,
3092 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3093 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3094 entry, first, nfrags);
3096 if (priv->extend_desc)
3097 tx_head = (void *)tx_q->dma_etx;
3099 tx_head = (void *)tx_q->dma_tx;
3101 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3103 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3104 print_pkt(skb->data, skb->len);
3107 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3108 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3110 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3113 dev->stats.tx_bytes += skb->len;
3115 /* According to the coalesce parameter the IC bit for the latest
3116 * segment is reset and the timer re-started to clean the tx status.
3117 * This approach takes care about the fragments: desc is the first
3118 * element in case of no SG.
3120 tx_q->tx_count_frames += nfrags + 1;
3121 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3122 !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3123 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3124 priv->hwts_tx_en)) {
3125 stmmac_tx_timer_arm(priv, queue);
3127 tx_q->tx_count_frames = 0;
3128 stmmac_set_tx_ic(priv, desc);
3129 priv->xstats.tx_set_ic_bit++;
3132 skb_tx_timestamp(skb);
3134 /* Ready to fill the first descriptor and set the OWN bit w/o any
3135 * problems because all the descriptors are actually ready to be
3136 * passed to the DMA engine.
3138 if (likely(!is_jumbo)) {
3139 bool last_segment = (nfrags == 0);
3141 des = dma_map_single(priv->device, skb->data,
3142 nopaged_len, DMA_TO_DEVICE);
3143 if (dma_mapping_error(priv->device, des))
3146 tx_q->tx_skbuff_dma[first_entry].buf = des;
3148 stmmac_set_desc_addr(priv, first, des);
3150 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3151 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3153 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3154 priv->hwts_tx_en)) {
3155 /* declare that device is doing timestamping */
3156 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3157 stmmac_enable_tx_timestamp(priv, first);
3160 /* Prepare the first descriptor setting the OWN bit too */
3161 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3162 csum_insertion, priv->mode, 1, last_segment,
3165 stmmac_set_tx_owner(priv, first);
3168 /* The own bit must be the latest setting done when prepare the
3169 * descriptor and then barrier is needed to make sure that
3170 * all is coherent before granting the DMA engine.
3174 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3176 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3178 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3179 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3181 return NETDEV_TX_OK;
3184 netdev_err(priv->dev, "Tx DMA map failed\n");
3186 priv->dev->stats.tx_dropped++;
3187 return NETDEV_TX_OK;
3190 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3192 struct vlan_ethhdr *veth;
3196 veth = (struct vlan_ethhdr *)skb->data;
3197 vlan_proto = veth->h_vlan_proto;
3199 if ((vlan_proto == htons(ETH_P_8021Q) &&
3200 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3201 (vlan_proto == htons(ETH_P_8021AD) &&
3202 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3203 /* pop the vlan tag */
3204 vlanid = ntohs(veth->h_vlan_TCI);
3205 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3206 skb_pull(skb, VLAN_HLEN);
3207 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3212 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3214 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3221 * stmmac_rx_refill - refill used skb preallocated buffers
3222 * @priv: driver private structure
3223 * @queue: RX queue index
3224 * Description : this is to reallocate the skb for the reception process
3225 * that is based on zero-copy.
3227 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3229 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3230 int dirty = stmmac_rx_dirty(priv, queue);
3231 unsigned int entry = rx_q->dirty_rx;
3233 int bfsize = priv->dma_buf_sz;
3235 while (dirty-- > 0) {
3238 if (priv->extend_desc)
3239 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3241 p = rx_q->dma_rx + entry;
3243 if (likely(!rx_q->rx_skbuff[entry])) {
3244 struct sk_buff *skb;
3246 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3247 if (unlikely(!skb)) {
3248 /* so for a while no zero-copy! */
3249 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3250 if (unlikely(net_ratelimit()))
3251 dev_err(priv->device,
3252 "fail to alloc skb entry %d\n",
3257 rx_q->rx_skbuff[entry] = skb;
3258 rx_q->rx_skbuff_dma[entry] =
3259 dma_map_single(priv->device, skb->data, bfsize,
3261 if (dma_mapping_error(priv->device,
3262 rx_q->rx_skbuff_dma[entry])) {
3263 netdev_err(priv->dev, "Rx DMA map failed\n");
3268 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3269 stmmac_refill_desc3(priv, rx_q, p);
3271 if (rx_q->rx_zeroc_thresh > 0)
3272 rx_q->rx_zeroc_thresh--;
3274 netif_dbg(priv, rx_status, priv->dev,
3275 "refill entry #%d\n", entry);
3279 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3283 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3285 rx_q->dirty_rx = entry;
3286 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3290 * stmmac_rx - manage the receive process
3291 * @priv: driver private structure
3292 * @limit: napi bugget
3293 * @queue: RX queue index.
3294 * Description : this the function called by the napi poll method.
3295 * It gets all the frames inside the ring.
3297 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3299 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3300 struct stmmac_channel *ch = &priv->channel[queue];
3301 unsigned int next_entry = rx_q->cur_rx;
3302 int coe = priv->hw->rx_csum;
3303 unsigned int count = 0;
3306 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3308 if (netif_msg_rx_status(priv)) {
3311 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3312 if (priv->extend_desc)
3313 rx_head = (void *)rx_q->dma_erx;
3315 rx_head = (void *)rx_q->dma_rx;
3317 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3319 while (count < limit) {
3322 struct dma_desc *np;
3326 if (priv->extend_desc)
3327 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3329 p = rx_q->dma_rx + entry;
3331 /* read the status of the incoming frame */
3332 status = stmmac_rx_status(priv, &priv->dev->stats,
3334 /* check if managed by the DMA otherwise go ahead */
3335 if (unlikely(status & dma_own))
3340 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3341 next_entry = rx_q->cur_rx;
3343 if (priv->extend_desc)
3344 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3346 np = rx_q->dma_rx + next_entry;
3350 if (priv->extend_desc)
3351 stmmac_rx_extended_status(priv, &priv->dev->stats,
3352 &priv->xstats, rx_q->dma_erx + entry);
3353 if (unlikely(status == discard_frame)) {
3354 priv->dev->stats.rx_errors++;
3355 if (priv->hwts_rx_en && !priv->extend_desc) {
3356 /* DESC2 & DESC3 will be overwritten by device
3357 * with timestamp value, hence reinitialize
3358 * them in stmmac_rx_refill() function so that
3359 * device can reuse it.
3361 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3362 rx_q->rx_skbuff[entry] = NULL;
3363 dma_unmap_single(priv->device,
3364 rx_q->rx_skbuff_dma[entry],
3369 struct sk_buff *skb;
3373 stmmac_get_desc_addr(priv, p, &des);
3374 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3376 /* If frame length is greater than skb buffer size
3377 * (preallocated during init) then the packet is
3380 if (frame_len > priv->dma_buf_sz) {
3381 if (net_ratelimit())
3382 netdev_err(priv->dev,
3383 "len %d larger than size (%d)\n",
3384 frame_len, priv->dma_buf_sz);
3385 priv->dev->stats.rx_length_errors++;
3389 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3390 * Type frames (LLC/LLC-SNAP)
3392 * llc_snap is never checked in GMAC >= 4, so this ACS
3393 * feature is always disabled and packets need to be
3394 * stripped manually.
3396 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3397 unlikely(status != llc_snap))
3398 frame_len -= ETH_FCS_LEN;
3400 if (netif_msg_rx_status(priv)) {
3401 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3403 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3407 /* The zero-copy is always used for all the sizes
3408 * in case of GMAC4 because it needs
3409 * to refill the used descriptors, always.
3411 if (unlikely(!xmac &&
3412 ((frame_len < priv->rx_copybreak) ||
3413 stmmac_rx_threshold_count(rx_q)))) {
3414 skb = netdev_alloc_skb_ip_align(priv->dev,
3416 if (unlikely(!skb)) {
3417 if (net_ratelimit())
3418 dev_warn(priv->device,
3419 "packet dropped\n");
3420 priv->dev->stats.rx_dropped++;
3424 dma_sync_single_for_cpu(priv->device,
3428 skb_copy_to_linear_data(skb,
3430 rx_skbuff[entry]->data,
3433 skb_put(skb, frame_len);
3434 dma_sync_single_for_device(priv->device,
3439 skb = rx_q->rx_skbuff[entry];
3440 if (unlikely(!skb)) {
3441 if (net_ratelimit())
3442 netdev_err(priv->dev,
3443 "%s: Inconsistent Rx chain\n",
3445 priv->dev->stats.rx_dropped++;
3448 prefetch(skb->data - NET_IP_ALIGN);
3449 rx_q->rx_skbuff[entry] = NULL;
3450 rx_q->rx_zeroc_thresh++;
3452 skb_put(skb, frame_len);
3453 dma_unmap_single(priv->device,
3454 rx_q->rx_skbuff_dma[entry],
3459 if (netif_msg_pktdata(priv)) {
3460 netdev_dbg(priv->dev, "frame received (%dbytes)",
3462 print_pkt(skb->data, frame_len);
3465 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3467 stmmac_rx_vlan(priv->dev, skb);
3469 skb->protocol = eth_type_trans(skb, priv->dev);
3472 skb_checksum_none_assert(skb);
3474 skb->ip_summed = CHECKSUM_UNNECESSARY;
3476 napi_gro_receive(&ch->rx_napi, skb);
3478 priv->dev->stats.rx_packets++;
3479 priv->dev->stats.rx_bytes += frame_len;
3483 stmmac_rx_refill(priv, queue);
3485 priv->xstats.rx_pkt_n += count;
3490 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3492 struct stmmac_channel *ch =
3493 container_of(napi, struct stmmac_channel, rx_napi);
3494 struct stmmac_priv *priv = ch->priv_data;
3495 u32 chan = ch->index;
3498 priv->xstats.napi_poll++;
3500 work_done = stmmac_rx(priv, budget, chan);
3501 if (work_done < budget && napi_complete_done(napi, work_done))
3502 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3506 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3508 struct stmmac_channel *ch =
3509 container_of(napi, struct stmmac_channel, tx_napi);
3510 struct stmmac_priv *priv = ch->priv_data;
3511 struct stmmac_tx_queue *tx_q;
3512 u32 chan = ch->index;
3515 priv->xstats.napi_poll++;
3517 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3518 work_done = min(work_done, budget);
3520 if (work_done < budget && napi_complete_done(napi, work_done))
3521 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3523 /* Force transmission restart */
3524 tx_q = &priv->tx_queue[chan];
3525 if (tx_q->cur_tx != tx_q->dirty_tx) {
3526 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3527 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3536 * @dev : Pointer to net device structure
3537 * Description: this function is called when a packet transmission fails to
3538 * complete within a reasonable time. The driver will mark the error in the
3539 * netdev structure and arrange for the device to be reset to a sane state
3540 * in order to transmit a new packet.
3542 static void stmmac_tx_timeout(struct net_device *dev)
3544 struct stmmac_priv *priv = netdev_priv(dev);
3546 stmmac_global_err(priv);
3550 * stmmac_set_rx_mode - entry point for multicast addressing
3551 * @dev : pointer to the device structure
3553 * This function is a driver entry point which gets called by the kernel
3554 * whenever multicast addresses must be enabled/disabled.
3558 static void stmmac_set_rx_mode(struct net_device *dev)
3560 struct stmmac_priv *priv = netdev_priv(dev);
3562 stmmac_set_filter(priv, priv->hw, dev);
3566 * stmmac_change_mtu - entry point to change MTU size for the device.
3567 * @dev : device pointer.
3568 * @new_mtu : the new MTU size for the device.
3569 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3570 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3571 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3573 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3576 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3578 struct stmmac_priv *priv = netdev_priv(dev);
3580 if (netif_running(dev)) {
3581 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3587 netdev_update_features(dev);
3592 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3593 netdev_features_t features)
3595 struct stmmac_priv *priv = netdev_priv(dev);
3597 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3598 features &= ~NETIF_F_RXCSUM;
3600 if (!priv->plat->tx_coe)
3601 features &= ~NETIF_F_CSUM_MASK;
3603 /* Some GMAC devices have a bugged Jumbo frame support that
3604 * needs to have the Tx COE disabled for oversized frames
3605 * (due to limited buffer sizes). In this case we disable
3606 * the TX csum insertion in the TDES and not use SF.
3608 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3609 features &= ~NETIF_F_CSUM_MASK;
3611 /* Disable tso if asked by ethtool */
3612 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3613 if (features & NETIF_F_TSO)
3622 static int stmmac_set_features(struct net_device *netdev,
3623 netdev_features_t features)
3625 struct stmmac_priv *priv = netdev_priv(netdev);
3627 /* Keep the COE Type in case of csum is supporting */
3628 if (features & NETIF_F_RXCSUM)
3629 priv->hw->rx_csum = priv->plat->rx_coe;
3631 priv->hw->rx_csum = 0;
3632 /* No check needed because rx_coe has been set before and it will be
3633 * fixed in case of issue.
3635 stmmac_rx_ipc(priv, priv->hw);
3641 * stmmac_interrupt - main ISR
3642 * @irq: interrupt number.
3643 * @dev_id: to pass the net device pointer.
3644 * Description: this is the main driver interrupt service routine.
3646 * o DMA service routine (to manage incoming frame reception and transmission
3648 * o Core interrupts to manage: remote wake-up, management counter, LPI
3651 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3653 struct net_device *dev = (struct net_device *)dev_id;
3654 struct stmmac_priv *priv = netdev_priv(dev);
3655 u32 rx_cnt = priv->plat->rx_queues_to_use;
3656 u32 tx_cnt = priv->plat->tx_queues_to_use;
3661 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3662 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3665 pm_wakeup_event(priv->device, 0);
3667 if (unlikely(!dev)) {
3668 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3672 /* Check if adapter is up */
3673 if (test_bit(STMMAC_DOWN, &priv->state))
3675 /* Check if a fatal error happened */
3676 if (stmmac_safety_feat_interrupt(priv))
3679 /* To handle GMAC own interrupts */
3680 if ((priv->plat->has_gmac) || xmac) {
3681 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3684 if (unlikely(status)) {
3685 /* For LPI we need to save the tx status */
3686 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3687 priv->tx_path_in_lpi_mode = true;
3688 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3689 priv->tx_path_in_lpi_mode = false;
3692 for (queue = 0; queue < queues_count; queue++) {
3693 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3695 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3697 if (mtl_status != -EINVAL)
3698 status |= mtl_status;
3700 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3701 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3706 /* PCS link status */
3707 if (priv->hw->pcs) {
3708 if (priv->xstats.pcs_link)
3709 netif_carrier_on(dev);
3711 netif_carrier_off(dev);
3715 /* To handle DMA interrupts */
3716 stmmac_dma_interrupt(priv);
3721 #ifdef CONFIG_NET_POLL_CONTROLLER
3722 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3723 * to allow network I/O with interrupts disabled.
3725 static void stmmac_poll_controller(struct net_device *dev)
3727 disable_irq(dev->irq);
3728 stmmac_interrupt(dev->irq, dev);
3729 enable_irq(dev->irq);
3734 * stmmac_ioctl - Entry point for the Ioctl
3735 * @dev: Device pointer.
3736 * @rq: An IOCTL specefic structure, that can contain a pointer to
3737 * a proprietary structure used to pass information to the driver.
3738 * @cmd: IOCTL command
3740 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3742 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3744 struct stmmac_priv *priv = netdev_priv (dev);
3745 int ret = -EOPNOTSUPP;
3747 if (!netif_running(dev))
3754 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3757 ret = stmmac_hwtstamp_set(dev, rq);
3760 ret = stmmac_hwtstamp_get(dev, rq);
3769 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3772 struct stmmac_priv *priv = cb_priv;
3773 int ret = -EOPNOTSUPP;
3775 stmmac_disable_all_queues(priv);
3778 case TC_SETUP_CLSU32:
3779 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3780 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3786 stmmac_enable_all_queues(priv);
3790 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3791 struct tc_block_offload *f)
3793 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3796 switch (f->command) {
3798 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3799 priv, priv, f->extack);
3800 case TC_BLOCK_UNBIND:
3801 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3808 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3811 struct stmmac_priv *priv = netdev_priv(ndev);
3814 case TC_SETUP_BLOCK:
3815 return stmmac_setup_tc_block(priv, type_data);
3816 case TC_SETUP_QDISC_CBS:
3817 return stmmac_tc_setup_cbs(priv, priv, type_data);
3823 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3825 struct stmmac_priv *priv = netdev_priv(ndev);
3828 ret = eth_mac_addr(ndev, addr);
3832 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3837 #ifdef CONFIG_DEBUG_FS
3838 static struct dentry *stmmac_fs_dir;
3840 static void sysfs_display_ring(void *head, int size, int extend_desc,
3841 struct seq_file *seq)
3844 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3845 struct dma_desc *p = (struct dma_desc *)head;
3847 for (i = 0; i < size; i++) {
3849 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3850 i, (unsigned int)virt_to_phys(ep),
3851 le32_to_cpu(ep->basic.des0),
3852 le32_to_cpu(ep->basic.des1),
3853 le32_to_cpu(ep->basic.des2),
3854 le32_to_cpu(ep->basic.des3));
3857 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3858 i, (unsigned int)virt_to_phys(p),
3859 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3860 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3863 seq_printf(seq, "\n");
3867 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3869 struct net_device *dev = seq->private;
3870 struct stmmac_priv *priv = netdev_priv(dev);
3871 u32 rx_count = priv->plat->rx_queues_to_use;
3872 u32 tx_count = priv->plat->tx_queues_to_use;
3875 if ((dev->flags & IFF_UP) == 0)
3878 for (queue = 0; queue < rx_count; queue++) {
3879 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3881 seq_printf(seq, "RX Queue %d:\n", queue);
3883 if (priv->extend_desc) {
3884 seq_printf(seq, "Extended descriptor ring:\n");
3885 sysfs_display_ring((void *)rx_q->dma_erx,
3886 DMA_RX_SIZE, 1, seq);
3888 seq_printf(seq, "Descriptor ring:\n");
3889 sysfs_display_ring((void *)rx_q->dma_rx,
3890 DMA_RX_SIZE, 0, seq);
3894 for (queue = 0; queue < tx_count; queue++) {
3895 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3897 seq_printf(seq, "TX Queue %d:\n", queue);
3899 if (priv->extend_desc) {
3900 seq_printf(seq, "Extended descriptor ring:\n");
3901 sysfs_display_ring((void *)tx_q->dma_etx,
3902 DMA_TX_SIZE, 1, seq);
3904 seq_printf(seq, "Descriptor ring:\n");
3905 sysfs_display_ring((void *)tx_q->dma_tx,
3906 DMA_TX_SIZE, 0, seq);
3912 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3914 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3916 struct net_device *dev = seq->private;
3917 struct stmmac_priv *priv = netdev_priv(dev);
3919 if (!priv->hw_cap_support) {
3920 seq_printf(seq, "DMA HW features not supported\n");
3924 seq_printf(seq, "==============================\n");
3925 seq_printf(seq, "\tDMA HW features\n");
3926 seq_printf(seq, "==============================\n");
3928 seq_printf(seq, "\t10/100 Mbps: %s\n",
3929 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3930 seq_printf(seq, "\t1000 Mbps: %s\n",
3931 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3932 seq_printf(seq, "\tHalf duplex: %s\n",
3933 (priv->dma_cap.half_duplex) ? "Y" : "N");
3934 seq_printf(seq, "\tHash Filter: %s\n",
3935 (priv->dma_cap.hash_filter) ? "Y" : "N");
3936 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3937 (priv->dma_cap.multi_addr) ? "Y" : "N");
3938 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3939 (priv->dma_cap.pcs) ? "Y" : "N");
3940 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3941 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3942 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3943 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3944 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3945 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3946 seq_printf(seq, "\tRMON module: %s\n",
3947 (priv->dma_cap.rmon) ? "Y" : "N");
3948 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3949 (priv->dma_cap.time_stamp) ? "Y" : "N");
3950 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3951 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3952 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3953 (priv->dma_cap.eee) ? "Y" : "N");
3954 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3955 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3956 (priv->dma_cap.tx_coe) ? "Y" : "N");
3957 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3958 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3959 (priv->dma_cap.rx_coe) ? "Y" : "N");
3961 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3962 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3963 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3964 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3966 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3967 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3968 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3969 priv->dma_cap.number_rx_channel);
3970 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3971 priv->dma_cap.number_tx_channel);
3972 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3973 (priv->dma_cap.enh_desc) ? "Y" : "N");
3977 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
3979 static int stmmac_init_fs(struct net_device *dev)
3981 struct stmmac_priv *priv = netdev_priv(dev);
3983 /* Create per netdev entries */
3984 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3986 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3987 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3992 /* Entry to report DMA RX/TX rings */
3993 priv->dbgfs_rings_status =
3994 debugfs_create_file("descriptors_status", 0444,
3995 priv->dbgfs_dir, dev,
3996 &stmmac_rings_status_fops);
3998 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3999 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4000 debugfs_remove_recursive(priv->dbgfs_dir);
4005 /* Entry to report the DMA HW features */
4006 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4008 dev, &stmmac_dma_cap_fops);
4010 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4011 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4012 debugfs_remove_recursive(priv->dbgfs_dir);
4020 static void stmmac_exit_fs(struct net_device *dev)
4022 struct stmmac_priv *priv = netdev_priv(dev);
4024 debugfs_remove_recursive(priv->dbgfs_dir);
4026 #endif /* CONFIG_DEBUG_FS */
4028 static const struct net_device_ops stmmac_netdev_ops = {
4029 .ndo_open = stmmac_open,
4030 .ndo_start_xmit = stmmac_xmit,
4031 .ndo_stop = stmmac_release,
4032 .ndo_change_mtu = stmmac_change_mtu,
4033 .ndo_fix_features = stmmac_fix_features,
4034 .ndo_set_features = stmmac_set_features,
4035 .ndo_set_rx_mode = stmmac_set_rx_mode,
4036 .ndo_tx_timeout = stmmac_tx_timeout,
4037 .ndo_do_ioctl = stmmac_ioctl,
4038 .ndo_setup_tc = stmmac_setup_tc,
4039 #ifdef CONFIG_NET_POLL_CONTROLLER
4040 .ndo_poll_controller = stmmac_poll_controller,
4042 .ndo_set_mac_address = stmmac_set_mac_address,
4045 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4047 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4049 if (test_bit(STMMAC_DOWN, &priv->state))
4052 netdev_err(priv->dev, "Reset adapter.\n");
4055 netif_trans_update(priv->dev);
4056 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4057 usleep_range(1000, 2000);
4059 set_bit(STMMAC_DOWN, &priv->state);
4060 dev_close(priv->dev);
4061 dev_open(priv->dev, NULL);
4062 clear_bit(STMMAC_DOWN, &priv->state);
4063 clear_bit(STMMAC_RESETING, &priv->state);
4067 static void stmmac_service_task(struct work_struct *work)
4069 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4072 stmmac_reset_subtask(priv);
4073 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4077 * stmmac_hw_init - Init the MAC device
4078 * @priv: driver private structure
4079 * Description: this function is to configure the MAC device according to
4080 * some platform parameters or the HW capability register. It prepares the
4081 * driver to use either ring or chain modes and to setup either enhanced or
4082 * normal descriptors.
4084 static int stmmac_hw_init(struct stmmac_priv *priv)
4088 /* dwmac-sun8i only work in chain mode */
4089 if (priv->plat->has_sun8i)
4091 priv->chain_mode = chain_mode;
4093 /* Initialize HW Interface */
4094 ret = stmmac_hwif_init(priv);
4098 /* Get the HW capability (new GMAC newer than 3.50a) */
4099 priv->hw_cap_support = stmmac_get_hw_features(priv);
4100 if (priv->hw_cap_support) {
4101 dev_info(priv->device, "DMA HW capability register supported\n");
4103 /* We can override some gmac/dma configuration fields: e.g.
4104 * enh_desc, tx_coe (e.g. that are passed through the
4105 * platform) with the values from the HW capability
4106 * register (if supported).
4108 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4109 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4110 priv->hw->pmt = priv->plat->pmt;
4112 /* TXCOE doesn't work in thresh DMA mode */
4113 if (priv->plat->force_thresh_dma_mode)
4114 priv->plat->tx_coe = 0;
4116 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4118 /* In case of GMAC4 rx_coe is from HW cap register. */
4119 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4121 if (priv->dma_cap.rx_coe_type2)
4122 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4123 else if (priv->dma_cap.rx_coe_type1)
4124 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4127 dev_info(priv->device, "No HW DMA feature register supported\n");
4130 if (priv->plat->rx_coe) {
4131 priv->hw->rx_csum = priv->plat->rx_coe;
4132 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4133 if (priv->synopsys_id < DWMAC_CORE_4_00)
4134 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4136 if (priv->plat->tx_coe)
4137 dev_info(priv->device, "TX Checksum insertion supported\n");
4139 if (priv->plat->pmt) {
4140 dev_info(priv->device, "Wake-Up On Lan supported\n");
4141 device_set_wakeup_capable(priv->device, 1);
4144 if (priv->dma_cap.tsoen)
4145 dev_info(priv->device, "TSO supported\n");
4147 /* Run HW quirks, if any */
4148 if (priv->hwif_quirks) {
4149 ret = priv->hwif_quirks(priv);
4154 /* Rx Watchdog is available in the COREs newer than the 3.40.
4155 * In some case, for example on bugged HW this feature
4156 * has to be disable and this can be done by passing the
4157 * riwt_off field from the platform.
4159 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4160 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4162 dev_info(priv->device,
4163 "Enable RX Mitigation via HW Watchdog Timer\n");
4171 * @device: device pointer
4172 * @plat_dat: platform data pointer
4173 * @res: stmmac resource pointer
4174 * Description: this is the main probe function used to
4175 * call the alloc_etherdev, allocate the priv structure.
4177 * returns 0 on success, otherwise errno.
4179 int stmmac_dvr_probe(struct device *device,
4180 struct plat_stmmacenet_data *plat_dat,
4181 struct stmmac_resources *res)
4183 struct net_device *ndev = NULL;
4184 struct stmmac_priv *priv;
4188 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4189 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4193 SET_NETDEV_DEV(ndev, device);
4195 priv = netdev_priv(ndev);
4196 priv->device = device;
4199 stmmac_set_ethtool_ops(ndev);
4200 priv->pause = pause;
4201 priv->plat = plat_dat;
4202 priv->ioaddr = res->addr;
4203 priv->dev->base_addr = (unsigned long)res->addr;
4205 priv->dev->irq = res->irq;
4206 priv->wol_irq = res->wol_irq;
4207 priv->lpi_irq = res->lpi_irq;
4209 if (!IS_ERR_OR_NULL(res->mac))
4210 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4212 dev_set_drvdata(device, priv->dev);
4214 /* Verify driver arguments */
4215 stmmac_verify_args();
4217 /* Allocate workqueue */
4218 priv->wq = create_singlethread_workqueue("stmmac_wq");
4220 dev_err(priv->device, "failed to create workqueue\n");
4224 INIT_WORK(&priv->service_task, stmmac_service_task);
4226 /* Override with kernel parameters if supplied XXX CRS XXX
4227 * this needs to have multiple instances
4229 if ((phyaddr >= 0) && (phyaddr <= 31))
4230 priv->plat->phy_addr = phyaddr;
4232 if (priv->plat->stmmac_rst) {
4233 ret = reset_control_assert(priv->plat->stmmac_rst);
4234 reset_control_deassert(priv->plat->stmmac_rst);
4235 /* Some reset controllers have only reset callback instead of
4236 * assert + deassert callbacks pair.
4238 if (ret == -ENOTSUPP)
4239 reset_control_reset(priv->plat->stmmac_rst);
4242 /* Init MAC and get the capabilities */
4243 ret = stmmac_hw_init(priv);
4247 stmmac_check_ether_addr(priv);
4249 /* Configure real RX and TX queues */
4250 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4251 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4253 ndev->netdev_ops = &stmmac_netdev_ops;
4255 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4258 ret = stmmac_tc_init(priv, priv);
4260 ndev->hw_features |= NETIF_F_HW_TC;
4263 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4264 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4266 dev_info(priv->device, "TSO feature enabled\n");
4268 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4269 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4270 #ifdef STMMAC_VLAN_TAG_USED
4271 /* Both mac100 and gmac support receive VLAN tag detection */
4272 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4274 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4276 /* MTU range: 46 - hw-specific max */
4277 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4278 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4279 ndev->max_mtu = JUMBO_LEN;
4280 else if (priv->plat->has_xgmac)
4281 ndev->max_mtu = XGMAC_JUMBO_LEN;
4283 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4284 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4285 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4287 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4288 (priv->plat->maxmtu >= ndev->min_mtu))
4289 ndev->max_mtu = priv->plat->maxmtu;
4290 else if (priv->plat->maxmtu < ndev->min_mtu)
4291 dev_warn(priv->device,
4292 "%s: warning: maxmtu having invalid value (%d)\n",
4293 __func__, priv->plat->maxmtu);
4296 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4298 /* Setup channels NAPI */
4299 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4301 for (queue = 0; queue < maxq; queue++) {
4302 struct stmmac_channel *ch = &priv->channel[queue];
4304 ch->priv_data = priv;
4307 if (queue < priv->plat->rx_queues_to_use) {
4308 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4311 if (queue < priv->plat->tx_queues_to_use) {
4312 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4317 mutex_init(&priv->lock);
4319 /* If a specific clk_csr value is passed from the platform
4320 * this means that the CSR Clock Range selection cannot be
4321 * changed at run-time and it is fixed. Viceversa the driver'll try to
4322 * set the MDC clock dynamically according to the csr actual
4325 if (priv->plat->clk_csr >= 0)
4326 priv->clk_csr = priv->plat->clk_csr;
4328 stmmac_clk_csr_set(priv);
4330 stmmac_check_pcs_mode(priv);
4332 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4333 priv->hw->pcs != STMMAC_PCS_TBI &&
4334 priv->hw->pcs != STMMAC_PCS_RTBI) {
4335 /* MDIO bus Registration */
4336 ret = stmmac_mdio_register(ndev);
4338 dev_err(priv->device,
4339 "%s: MDIO bus (id: %d) registration failed",
4340 __func__, priv->plat->bus_id);
4341 goto error_mdio_register;
4345 ret = stmmac_phy_setup(priv);
4347 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4348 goto error_phy_setup;
4351 ret = register_netdev(ndev);
4353 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4355 goto error_netdev_register;
4358 #ifdef CONFIG_DEBUG_FS
4359 ret = stmmac_init_fs(ndev);
4361 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4367 error_netdev_register:
4368 phylink_destroy(priv->phylink);
4370 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4371 priv->hw->pcs != STMMAC_PCS_TBI &&
4372 priv->hw->pcs != STMMAC_PCS_RTBI)
4373 stmmac_mdio_unregister(ndev);
4374 error_mdio_register:
4375 for (queue = 0; queue < maxq; queue++) {
4376 struct stmmac_channel *ch = &priv->channel[queue];
4378 if (queue < priv->plat->rx_queues_to_use)
4379 netif_napi_del(&ch->rx_napi);
4380 if (queue < priv->plat->tx_queues_to_use)
4381 netif_napi_del(&ch->tx_napi);
4384 destroy_workqueue(priv->wq);
4388 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4392 * @dev: device pointer
4393 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4394 * changes the link status, releases the DMA descriptor rings.
4396 int stmmac_dvr_remove(struct device *dev)
4398 struct net_device *ndev = dev_get_drvdata(dev);
4399 struct stmmac_priv *priv = netdev_priv(ndev);
4401 netdev_info(priv->dev, "%s: removing driver", __func__);
4403 #ifdef CONFIG_DEBUG_FS
4404 stmmac_exit_fs(ndev);
4406 stmmac_stop_all_dma(priv);
4408 stmmac_mac_set(priv, priv->ioaddr, false);
4409 netif_carrier_off(ndev);
4410 unregister_netdev(ndev);
4411 phylink_destroy(priv->phylink);
4412 if (priv->plat->stmmac_rst)
4413 reset_control_assert(priv->plat->stmmac_rst);
4414 clk_disable_unprepare(priv->plat->pclk);
4415 clk_disable_unprepare(priv->plat->stmmac_clk);
4416 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4417 priv->hw->pcs != STMMAC_PCS_TBI &&
4418 priv->hw->pcs != STMMAC_PCS_RTBI)
4419 stmmac_mdio_unregister(ndev);
4420 destroy_workqueue(priv->wq);
4421 mutex_destroy(&priv->lock);
4425 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4428 * stmmac_suspend - suspend callback
4429 * @dev: device pointer
4430 * Description: this is the function to suspend the device and it is called
4431 * by the platform driver to stop the network queue, release the resources,
4432 * program the PMT register (for WoL), clean and release driver resources.
4434 int stmmac_suspend(struct device *dev)
4436 struct net_device *ndev = dev_get_drvdata(dev);
4437 struct stmmac_priv *priv = netdev_priv(ndev);
4439 if (!ndev || !netif_running(ndev))
4442 phylink_stop(priv->phylink);
4444 mutex_lock(&priv->lock);
4446 netif_device_detach(ndev);
4447 stmmac_stop_all_queues(priv);
4449 stmmac_disable_all_queues(priv);
4451 /* Stop TX/RX DMA */
4452 stmmac_stop_all_dma(priv);
4454 /* Enable Power down mode by programming the PMT regs */
4455 if (device_may_wakeup(priv->device)) {
4456 stmmac_pmt(priv, priv->hw, priv->wolopts);
4459 stmmac_mac_set(priv, priv->ioaddr, false);
4460 pinctrl_pm_select_sleep_state(priv->device);
4461 /* Disable clock in case of PWM is off */
4462 clk_disable(priv->plat->pclk);
4463 clk_disable(priv->plat->stmmac_clk);
4465 mutex_unlock(&priv->lock);
4467 priv->speed = SPEED_UNKNOWN;
4470 EXPORT_SYMBOL_GPL(stmmac_suspend);
4473 * stmmac_reset_queues_param - reset queue parameters
4474 * @dev: device pointer
4476 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4478 u32 rx_cnt = priv->plat->rx_queues_to_use;
4479 u32 tx_cnt = priv->plat->tx_queues_to_use;
4482 for (queue = 0; queue < rx_cnt; queue++) {
4483 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4489 for (queue = 0; queue < tx_cnt; queue++) {
4490 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4499 * stmmac_resume - resume callback
4500 * @dev: device pointer
4501 * Description: when resume this function is invoked to setup the DMA and CORE
4502 * in a usable state.
4504 int stmmac_resume(struct device *dev)
4506 struct net_device *ndev = dev_get_drvdata(dev);
4507 struct stmmac_priv *priv = netdev_priv(ndev);
4509 if (!netif_running(ndev))
4512 /* Power Down bit, into the PM register, is cleared
4513 * automatically as soon as a magic packet or a Wake-up frame
4514 * is received. Anyway, it's better to manually clear
4515 * this bit because it can generate problems while resuming
4516 * from another devices (e.g. serial console).
4518 if (device_may_wakeup(priv->device)) {
4519 mutex_lock(&priv->lock);
4520 stmmac_pmt(priv, priv->hw, 0);
4521 mutex_unlock(&priv->lock);
4524 pinctrl_pm_select_default_state(priv->device);
4525 /* enable the clk previously disabled */
4526 clk_enable(priv->plat->stmmac_clk);
4527 clk_enable(priv->plat->pclk);
4528 /* reset the phy so that it's ready */
4530 stmmac_mdio_reset(priv->mii);
4533 netif_device_attach(ndev);
4535 mutex_lock(&priv->lock);
4537 stmmac_reset_queues_param(priv);
4539 stmmac_clear_descriptors(priv);
4541 stmmac_hw_setup(ndev, false);
4542 stmmac_init_tx_coalesce(priv);
4543 stmmac_set_rx_mode(ndev);
4545 stmmac_enable_all_queues(priv);
4547 stmmac_start_all_queues(priv);
4549 mutex_unlock(&priv->lock);
4551 phylink_start(priv->phylink);
4555 EXPORT_SYMBOL_GPL(stmmac_resume);
4558 static int __init stmmac_cmdline_opt(char *str)
4564 while ((opt = strsep(&str, ",")) != NULL) {
4565 if (!strncmp(opt, "debug:", 6)) {
4566 if (kstrtoint(opt + 6, 0, &debug))
4568 } else if (!strncmp(opt, "phyaddr:", 8)) {
4569 if (kstrtoint(opt + 8, 0, &phyaddr))
4571 } else if (!strncmp(opt, "buf_sz:", 7)) {
4572 if (kstrtoint(opt + 7, 0, &buf_sz))
4574 } else if (!strncmp(opt, "tc:", 3)) {
4575 if (kstrtoint(opt + 3, 0, &tc))
4577 } else if (!strncmp(opt, "watchdog:", 9)) {
4578 if (kstrtoint(opt + 9, 0, &watchdog))
4580 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4581 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4583 } else if (!strncmp(opt, "pause:", 6)) {
4584 if (kstrtoint(opt + 6, 0, &pause))
4586 } else if (!strncmp(opt, "eee_timer:", 10)) {
4587 if (kstrtoint(opt + 10, 0, &eee_timer))
4589 } else if (!strncmp(opt, "chain_mode:", 11)) {
4590 if (kstrtoint(opt + 11, 0, &chain_mode))
4597 pr_err("%s: ERROR broken module parameter conversion", __func__);
4601 __setup("stmmaceth=", stmmac_cmdline_opt);
4604 static int __init stmmac_init(void)
4606 #ifdef CONFIG_DEBUG_FS
4607 /* Create debugfs main directory if it doesn't exist yet */
4608 if (!stmmac_fs_dir) {
4609 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4611 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4612 pr_err("ERROR %s, debugfs create directory failed\n",
4613 STMMAC_RESOURCE_NAME);
4623 static void __exit stmmac_exit(void)
4625 #ifdef CONFIG_DEBUG_FS
4626 debugfs_remove_recursive(stmmac_fs_dir);
4630 module_init(stmmac_init)
4631 module_exit(stmmac_exit)
4633 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4634 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4635 MODULE_LICENSE("GPL");