1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include <net/pkt_cls.h>
49 #include "stmmac_ptp.h"
51 #include <linux/reset.h>
52 #include <linux/of_mdio.h>
53 #include "dwmac1000.h"
57 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
58 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
60 /* Module parameters */
62 static int watchdog = TX_TIMEO;
63 module_param(watchdog, int, 0644);
64 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
66 static int debug = -1;
67 module_param(debug, int, 0644);
68 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
70 static int phyaddr = -1;
71 module_param(phyaddr, int, 0444);
72 MODULE_PARM_DESC(phyaddr, "Physical device address");
74 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
75 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
77 static int flow_ctrl = FLOW_OFF;
78 module_param(flow_ctrl, int, 0644);
79 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
81 static int pause = PAUSE_TIME;
82 module_param(pause, int, 0644);
83 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
86 static int tc = TC_DEFAULT;
87 module_param(tc, int, 0644);
88 MODULE_PARM_DESC(tc, "DMA threshold control value");
90 #define DEFAULT_BUFSIZE 1536
91 static int buf_sz = DEFAULT_BUFSIZE;
92 module_param(buf_sz, int, 0644);
93 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
95 #define STMMAC_RX_COPYBREAK 256
97 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
98 NETIF_MSG_LINK | NETIF_MSG_IFUP |
99 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
101 #define STMMAC_DEFAULT_LPI_TIMER 1000
102 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
103 module_param(eee_timer, int, 0644);
104 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
105 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
107 /* By default the driver will use the ring mode to manage tx and rx descriptors,
108 * but allow user to force to use the chain instead of the ring
110 static unsigned int chain_mode;
111 module_param(chain_mode, int, 0444);
112 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
114 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
116 #ifdef CONFIG_DEBUG_FS
117 static int stmmac_init_fs(struct net_device *dev);
118 static void stmmac_exit_fs(struct net_device *dev);
121 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
124 * stmmac_verify_args - verify the driver parameters.
125 * Description: it checks the driver parameters and set a default in case of
128 static void stmmac_verify_args(void)
130 if (unlikely(watchdog < 0))
132 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
133 buf_sz = DEFAULT_BUFSIZE;
134 if (unlikely(flow_ctrl > 1))
135 flow_ctrl = FLOW_AUTO;
136 else if (likely(flow_ctrl < 0))
137 flow_ctrl = FLOW_OFF;
138 if (unlikely((pause < 0) || (pause > 0xffff)))
141 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
145 * stmmac_disable_all_queues - Disable all queues
146 * @priv: driver private structure
148 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
150 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
151 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
152 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
155 for (queue = 0; queue < maxq; queue++) {
156 struct stmmac_channel *ch = &priv->channel[queue];
158 if (queue < rx_queues_cnt)
159 napi_disable(&ch->rx_napi);
160 if (queue < tx_queues_cnt)
161 napi_disable(&ch->tx_napi);
166 * stmmac_enable_all_queues - Enable all queues
167 * @priv: driver private structure
169 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
171 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
172 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
173 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
176 for (queue = 0; queue < maxq; queue++) {
177 struct stmmac_channel *ch = &priv->channel[queue];
179 if (queue < rx_queues_cnt)
180 napi_enable(&ch->rx_napi);
181 if (queue < tx_queues_cnt)
182 napi_enable(&ch->tx_napi);
187 * stmmac_stop_all_queues - Stop all queues
188 * @priv: driver private structure
190 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
192 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
195 for (queue = 0; queue < tx_queues_cnt; queue++)
196 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
200 * stmmac_start_all_queues - Start all queues
201 * @priv: driver private structure
203 static void stmmac_start_all_queues(struct stmmac_priv *priv)
205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
208 for (queue = 0; queue < tx_queues_cnt; queue++)
209 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
212 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
214 if (!test_bit(STMMAC_DOWN, &priv->state) &&
215 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
216 queue_work(priv->wq, &priv->service_task);
219 static void stmmac_global_err(struct stmmac_priv *priv)
221 netif_carrier_off(priv->dev);
222 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
223 stmmac_service_event_schedule(priv);
227 * stmmac_clk_csr_set - dynamically set the MDC clock
228 * @priv: driver private structure
229 * Description: this is to dynamically set the MDC clock according to the csr
232 * If a specific clk_csr value is passed from the platform
233 * this means that the CSR Clock Range selection cannot be
234 * changed at run-time and it is fixed (as reported in the driver
235 * documentation). Viceversa the driver will try to set the MDC
236 * clock dynamically according to the actual clock input.
238 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
242 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
244 /* Platform provided default clk_csr would be assumed valid
245 * for all other cases except for the below mentioned ones.
246 * For values higher than the IEEE 802.3 specified frequency
247 * we can not estimate the proper divider as it is not known
248 * the frequency of clk_csr_i. So we do not change the default
251 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
252 if (clk_rate < CSR_F_35M)
253 priv->clk_csr = STMMAC_CSR_20_35M;
254 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
255 priv->clk_csr = STMMAC_CSR_35_60M;
256 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
257 priv->clk_csr = STMMAC_CSR_60_100M;
258 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
259 priv->clk_csr = STMMAC_CSR_100_150M;
260 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
261 priv->clk_csr = STMMAC_CSR_150_250M;
262 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
263 priv->clk_csr = STMMAC_CSR_250_300M;
266 if (priv->plat->has_sun8i) {
267 if (clk_rate > 160000000)
268 priv->clk_csr = 0x03;
269 else if (clk_rate > 80000000)
270 priv->clk_csr = 0x02;
271 else if (clk_rate > 40000000)
272 priv->clk_csr = 0x01;
277 if (priv->plat->has_xgmac) {
278 if (clk_rate > 400000000)
280 else if (clk_rate > 350000000)
282 else if (clk_rate > 300000000)
284 else if (clk_rate > 250000000)
286 else if (clk_rate > 150000000)
293 static void print_pkt(unsigned char *buf, int len)
295 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
296 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
299 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
301 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
304 if (tx_q->dirty_tx > tx_q->cur_tx)
305 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
307 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
313 * stmmac_rx_dirty - Get RX queue dirty
314 * @priv: driver private structure
315 * @queue: RX queue index
317 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
319 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
322 if (rx_q->dirty_rx <= rx_q->cur_rx)
323 dirty = rx_q->cur_rx - rx_q->dirty_rx;
325 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
331 * stmmac_hw_fix_mac_speed - callback for speed selection
332 * @priv: driver private structure
333 * Description: on some platforms (e.g. ST), some HW system configuration
334 * registers have to be set according to the link speed negotiated.
336 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
338 struct net_device *ndev = priv->dev;
339 struct phy_device *phydev = ndev->phydev;
341 if (likely(priv->plat->fix_mac_speed))
342 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
346 * stmmac_enable_eee_mode - check and enter in LPI mode
347 * @priv: driver private structure
348 * Description: this function is to verify and enter in LPI mode in case of
351 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
353 u32 tx_cnt = priv->plat->tx_queues_to_use;
356 /* check if all TX queues have the work finished */
357 for (queue = 0; queue < tx_cnt; queue++) {
358 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
360 if (tx_q->dirty_tx != tx_q->cur_tx)
361 return; /* still unfinished work */
364 /* Check and enter in LPI mode */
365 if (!priv->tx_path_in_lpi_mode)
366 stmmac_set_eee_mode(priv, priv->hw,
367 priv->plat->en_tx_lpi_clockgating);
371 * stmmac_disable_eee_mode - disable and exit from LPI mode
372 * @priv: driver private structure
373 * Description: this function is to exit and disable EEE in case of
374 * LPI state is true. This is called by the xmit.
376 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
378 stmmac_reset_eee_mode(priv, priv->hw);
379 del_timer_sync(&priv->eee_ctrl_timer);
380 priv->tx_path_in_lpi_mode = false;
384 * stmmac_eee_ctrl_timer - EEE TX SW timer.
387 * if there is no data transfer and if we are not in LPI state,
388 * then MAC Transmitter can be moved to LPI state.
390 static void stmmac_eee_ctrl_timer(struct timer_list *t)
392 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
394 stmmac_enable_eee_mode(priv);
395 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
399 * stmmac_eee_init - init EEE
400 * @priv: driver private structure
402 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
403 * can also manage EEE, this function enable the LPI state and start related
406 bool stmmac_eee_init(struct stmmac_priv *priv)
408 struct net_device *ndev = priv->dev;
409 int interface = priv->plat->interface;
412 if ((interface != PHY_INTERFACE_MODE_MII) &&
413 (interface != PHY_INTERFACE_MODE_GMII) &&
414 !phy_interface_mode_is_rgmii(interface))
417 /* Using PCS we cannot dial with the phy registers at this stage
418 * so we do not support extra feature like EEE.
420 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
421 (priv->hw->pcs == STMMAC_PCS_TBI) ||
422 (priv->hw->pcs == STMMAC_PCS_RTBI))
425 /* MAC core supports the EEE feature. */
426 if (priv->dma_cap.eee) {
427 int tx_lpi_timer = priv->tx_lpi_timer;
429 /* Check if the PHY supports EEE */
430 if (phy_init_eee(ndev->phydev, 1)) {
431 /* To manage at run-time if the EEE cannot be supported
432 * anymore (for example because the lp caps have been
434 * In that case the driver disable own timers.
436 mutex_lock(&priv->lock);
437 if (priv->eee_active) {
438 netdev_dbg(priv->dev, "disable EEE\n");
439 del_timer_sync(&priv->eee_ctrl_timer);
440 stmmac_set_eee_timer(priv, priv->hw, 0,
443 priv->eee_active = 0;
444 mutex_unlock(&priv->lock);
447 /* Activate the EEE and start timers */
448 mutex_lock(&priv->lock);
449 if (!priv->eee_active) {
450 priv->eee_active = 1;
451 timer_setup(&priv->eee_ctrl_timer,
452 stmmac_eee_ctrl_timer, 0);
453 mod_timer(&priv->eee_ctrl_timer,
454 STMMAC_LPI_T(eee_timer));
456 stmmac_set_eee_timer(priv, priv->hw,
457 STMMAC_DEFAULT_LIT_LS, tx_lpi_timer);
459 /* Set HW EEE according to the speed */
460 stmmac_set_eee_pls(priv, priv->hw, ndev->phydev->link);
463 mutex_unlock(&priv->lock);
465 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
471 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
472 * @priv: driver private structure
473 * @p : descriptor pointer
474 * @skb : the socket buffer
476 * This function will read timestamp from the descriptor & pass it to stack.
477 * and also perform some sanity checks.
479 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
480 struct dma_desc *p, struct sk_buff *skb)
482 struct skb_shared_hwtstamps shhwtstamp;
485 if (!priv->hwts_tx_en)
488 /* exit if skb doesn't support hw tstamp */
489 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
492 /* check tx tstamp status */
493 if (stmmac_get_tx_timestamp_status(priv, p)) {
494 /* get the valid tstamp */
495 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
497 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
498 shhwtstamp.hwtstamp = ns_to_ktime(ns);
500 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
501 /* pass tstamp to stack */
502 skb_tstamp_tx(skb, &shhwtstamp);
508 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
509 * @priv: driver private structure
510 * @p : descriptor pointer
511 * @np : next descriptor pointer
512 * @skb : the socket buffer
514 * This function will read received packet's timestamp from the descriptor
515 * and pass it to stack. It also perform some sanity checks.
517 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
518 struct dma_desc *np, struct sk_buff *skb)
520 struct skb_shared_hwtstamps *shhwtstamp = NULL;
521 struct dma_desc *desc = p;
524 if (!priv->hwts_rx_en)
526 /* For GMAC4, the valid timestamp is from CTX next desc. */
527 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
530 /* Check if timestamp is available */
531 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
532 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
533 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
534 shhwtstamp = skb_hwtstamps(skb);
535 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
536 shhwtstamp->hwtstamp = ns_to_ktime(ns);
538 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
543 * stmmac_hwtstamp_set - control hardware timestamping.
544 * @dev: device pointer.
545 * @ifr: An IOCTL specific structure, that can contain a pointer to
546 * a proprietary structure used to pass information to the driver.
548 * This function configures the MAC to enable/disable both outgoing(TX)
549 * and incoming(RX) packets time stamping based on user input.
551 * 0 on success and an appropriate -ve integer on failure.
553 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
555 struct stmmac_priv *priv = netdev_priv(dev);
556 struct hwtstamp_config config;
557 struct timespec64 now;
561 u32 ptp_over_ipv4_udp = 0;
562 u32 ptp_over_ipv6_udp = 0;
563 u32 ptp_over_ethernet = 0;
564 u32 snap_type_sel = 0;
565 u32 ts_master_en = 0;
571 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
573 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
574 netdev_alert(priv->dev, "No support for HW time stamping\n");
575 priv->hwts_tx_en = 0;
576 priv->hwts_rx_en = 0;
581 if (copy_from_user(&config, ifr->ifr_data,
585 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
586 __func__, config.flags, config.tx_type, config.rx_filter);
588 /* reserved for future extensions */
592 if (config.tx_type != HWTSTAMP_TX_OFF &&
593 config.tx_type != HWTSTAMP_TX_ON)
597 switch (config.rx_filter) {
598 case HWTSTAMP_FILTER_NONE:
599 /* time stamp no incoming packet at all */
600 config.rx_filter = HWTSTAMP_FILTER_NONE;
603 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
604 /* PTP v1, UDP, any kind of event packet */
605 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
606 /* 'xmac' hardware can support Sync, Pdelay_Req and
607 * Pdelay_resp by setting bit14 and bits17/16 to 01
608 * This leaves Delay_Req timestamps out.
609 * Enable all events *and* general purpose message
612 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
613 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
614 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
617 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
618 /* PTP v1, UDP, Sync packet */
619 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
620 /* take time stamp for SYNC messages only */
621 ts_event_en = PTP_TCR_TSEVNTENA;
623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
627 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
628 /* PTP v1, UDP, Delay_req packet */
629 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
630 /* take time stamp for Delay_Req messages only */
631 ts_master_en = PTP_TCR_TSMSTRENA;
632 ts_event_en = PTP_TCR_TSEVNTENA;
634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
638 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
639 /* PTP v2, UDP, any kind of event packet */
640 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
641 ptp_v2 = PTP_TCR_TSVER2ENA;
642 /* take time stamp for all event messages */
643 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
645 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
646 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
649 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
650 /* PTP v2, UDP, Sync packet */
651 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
652 ptp_v2 = PTP_TCR_TSVER2ENA;
653 /* take time stamp for SYNC messages only */
654 ts_event_en = PTP_TCR_TSEVNTENA;
656 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
657 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
660 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
661 /* PTP v2, UDP, Delay_req packet */
662 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
663 ptp_v2 = PTP_TCR_TSVER2ENA;
664 /* take time stamp for Delay_Req messages only */
665 ts_master_en = PTP_TCR_TSMSTRENA;
666 ts_event_en = PTP_TCR_TSEVNTENA;
668 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
669 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
672 case HWTSTAMP_FILTER_PTP_V2_EVENT:
673 /* PTP v2/802.AS1 any layer, any kind of event packet */
674 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
675 ptp_v2 = PTP_TCR_TSVER2ENA;
676 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
677 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
678 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
679 ptp_over_ethernet = PTP_TCR_TSIPENA;
682 case HWTSTAMP_FILTER_PTP_V2_SYNC:
683 /* PTP v2/802.AS1, any layer, Sync packet */
684 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
685 ptp_v2 = PTP_TCR_TSVER2ENA;
686 /* take time stamp for SYNC messages only */
687 ts_event_en = PTP_TCR_TSEVNTENA;
689 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
690 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
691 ptp_over_ethernet = PTP_TCR_TSIPENA;
694 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
695 /* PTP v2/802.AS1, any layer, Delay_req packet */
696 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
697 ptp_v2 = PTP_TCR_TSVER2ENA;
698 /* take time stamp for Delay_Req messages only */
699 ts_master_en = PTP_TCR_TSMSTRENA;
700 ts_event_en = PTP_TCR_TSEVNTENA;
702 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
703 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
704 ptp_over_ethernet = PTP_TCR_TSIPENA;
707 case HWTSTAMP_FILTER_NTP_ALL:
708 case HWTSTAMP_FILTER_ALL:
709 /* time stamp any incoming packet */
710 config.rx_filter = HWTSTAMP_FILTER_ALL;
711 tstamp_all = PTP_TCR_TSENALL;
718 switch (config.rx_filter) {
719 case HWTSTAMP_FILTER_NONE:
720 config.rx_filter = HWTSTAMP_FILTER_NONE;
723 /* PTP v1, UDP, any kind of event packet */
724 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
728 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
729 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
731 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
732 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
734 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
735 tstamp_all | ptp_v2 | ptp_over_ethernet |
736 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
737 ts_master_en | snap_type_sel);
738 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
740 /* program Sub Second Increment reg */
741 stmmac_config_sub_second_increment(priv,
742 priv->ptpaddr, priv->plat->clk_ptp_rate,
744 temp = div_u64(1000000000ULL, sec_inc);
746 /* Store sub second increment and flags for later use */
747 priv->sub_second_inc = sec_inc;
748 priv->systime_flags = value;
750 /* calculate default added value:
752 * addend = (2^32)/freq_div_ratio;
753 * where, freq_div_ratio = 1e9ns/sec_inc
755 temp = (u64)(temp << 32);
756 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
757 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
759 /* initialize system time */
760 ktime_get_real_ts64(&now);
762 /* lower 32 bits of tv_sec are safe until y2106 */
763 stmmac_init_systime(priv, priv->ptpaddr,
764 (u32)now.tv_sec, now.tv_nsec);
767 memcpy(&priv->tstamp_config, &config, sizeof(config));
769 return copy_to_user(ifr->ifr_data, &config,
770 sizeof(config)) ? -EFAULT : 0;
774 * stmmac_hwtstamp_get - read hardware timestamping.
775 * @dev: device pointer.
776 * @ifr: An IOCTL specific structure, that can contain a pointer to
777 * a proprietary structure used to pass information to the driver.
779 * This function obtain the current hardware timestamping settings
782 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
784 struct stmmac_priv *priv = netdev_priv(dev);
785 struct hwtstamp_config *config = &priv->tstamp_config;
787 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
790 return copy_to_user(ifr->ifr_data, config,
791 sizeof(*config)) ? -EFAULT : 0;
795 * stmmac_init_ptp - init PTP
796 * @priv: driver private structure
797 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
798 * This is done by looking at the HW cap. register.
799 * This function also registers the ptp driver.
801 static int stmmac_init_ptp(struct stmmac_priv *priv)
803 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
805 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
809 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
810 if (xmac && priv->dma_cap.atime_stamp)
812 /* Dwmac 3.x core with extend_desc can support adv_ts */
813 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
816 if (priv->dma_cap.time_stamp)
817 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
820 netdev_info(priv->dev,
821 "IEEE 1588-2008 Advanced Timestamp supported\n");
823 priv->hwts_tx_en = 0;
824 priv->hwts_rx_en = 0;
826 stmmac_ptp_register(priv);
831 static void stmmac_release_ptp(struct stmmac_priv *priv)
833 if (priv->plat->clk_ptp_ref)
834 clk_disable_unprepare(priv->plat->clk_ptp_ref);
835 stmmac_ptp_unregister(priv);
839 * stmmac_mac_flow_ctrl - Configure flow control in all queues
840 * @priv: driver private structure
841 * Description: It is used for configuring the flow control in all queues
843 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
845 u32 tx_cnt = priv->plat->tx_queues_to_use;
847 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
848 priv->pause, tx_cnt);
852 * stmmac_adjust_link - adjusts the link parameters
853 * @dev: net device structure
854 * Description: this is the helper called by the physical abstraction layer
855 * drivers to communicate the phy link status. According the speed and duplex
856 * this driver can invoke registered glue-logic as well.
857 * It also invoke the eee initialization because it could happen when switch
858 * on different networks (that are eee capable).
860 static void stmmac_adjust_link(struct net_device *dev)
862 struct stmmac_priv *priv = netdev_priv(dev);
863 struct phy_device *phydev = dev->phydev;
864 bool new_state = false;
869 mutex_lock(&priv->lock);
872 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
874 /* Now we make sure that we can be in full duplex mode.
875 * If not, we operate in half-duplex mode. */
876 if (phydev->duplex != priv->oldduplex) {
879 ctrl &= ~priv->hw->link.duplex;
881 ctrl |= priv->hw->link.duplex;
882 priv->oldduplex = phydev->duplex;
884 /* Flow Control operation */
886 stmmac_mac_flow_ctrl(priv, phydev->duplex);
888 if (phydev->speed != priv->speed) {
890 ctrl &= ~priv->hw->link.speed_mask;
891 switch (phydev->speed) {
893 ctrl |= priv->hw->link.speed1000;
896 ctrl |= priv->hw->link.speed100;
899 ctrl |= priv->hw->link.speed10;
902 netif_warn(priv, link, priv->dev,
903 "broken speed: %d\n", phydev->speed);
904 phydev->speed = SPEED_UNKNOWN;
907 if (phydev->speed != SPEED_UNKNOWN)
908 stmmac_hw_fix_mac_speed(priv);
909 priv->speed = phydev->speed;
912 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
914 if (!priv->oldlink) {
916 priv->oldlink = true;
918 } else if (priv->oldlink) {
920 priv->oldlink = false;
921 priv->speed = SPEED_UNKNOWN;
922 priv->oldduplex = DUPLEX_UNKNOWN;
925 if (new_state && netif_msg_link(priv))
926 phy_print_status(phydev);
928 mutex_unlock(&priv->lock);
930 if (phydev->is_pseudo_fixed_link)
931 /* Stop PHY layer to call the hook to adjust the link in case
932 * of a switch is attached to the stmmac driver.
934 phydev->irq = PHY_IGNORE_INTERRUPT;
936 /* At this stage, init the EEE if supported.
937 * Never called in case of fixed_link.
939 priv->eee_enabled = stmmac_eee_init(priv);
943 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
944 * @priv: driver private structure
945 * Description: this is to verify if the HW supports the PCS.
946 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
947 * configured for the TBI, RTBI, or SGMII PHY interface.
949 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
951 int interface = priv->plat->interface;
953 if (priv->dma_cap.pcs) {
954 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
955 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
956 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
957 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
958 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
959 priv->hw->pcs = STMMAC_PCS_RGMII;
960 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
961 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
962 priv->hw->pcs = STMMAC_PCS_SGMII;
968 * stmmac_init_phy - PHY initialization
969 * @dev: net device structure
970 * Description: it initializes the driver's PHY state, and attaches the PHY
975 static int stmmac_init_phy(struct net_device *dev)
977 struct stmmac_priv *priv = netdev_priv(dev);
978 u32 tx_cnt = priv->plat->tx_queues_to_use;
979 struct phy_device *phydev;
980 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
981 char bus_id[MII_BUS_ID_SIZE];
982 int interface = priv->plat->interface;
983 int max_speed = priv->plat->max_speed;
984 priv->oldlink = false;
985 priv->speed = SPEED_UNKNOWN;
986 priv->oldduplex = DUPLEX_UNKNOWN;
988 if (priv->plat->phy_node) {
989 phydev = of_phy_connect(dev, priv->plat->phy_node,
990 &stmmac_adjust_link, 0, interface);
992 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
995 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
996 priv->plat->phy_addr);
997 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
1000 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
1004 if (IS_ERR_OR_NULL(phydev)) {
1005 netdev_err(priv->dev, "Could not attach to PHY\n");
1009 return PTR_ERR(phydev);
1012 /* Stop Advertising 1000BASE Capability if interface is not GMII */
1013 if ((interface == PHY_INTERFACE_MODE_MII) ||
1014 (interface == PHY_INTERFACE_MODE_RMII) ||
1015 (max_speed < 1000 && max_speed > 0))
1016 phy_set_max_speed(phydev, SPEED_100);
1019 * Half-duplex mode not supported with multiqueue
1020 * half-duplex can only works with single queue
1023 phy_remove_link_mode(phydev,
1024 ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1025 phy_remove_link_mode(phydev,
1026 ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1027 phy_remove_link_mode(phydev,
1028 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1032 * Broken HW is sometimes missing the pull-up resistor on the
1033 * MDIO line, which results in reads to non-existent devices returning
1034 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
1036 * Note: phydev->phy_id is the result of reading the UID PHY registers.
1038 if (!priv->plat->phy_node && phydev->phy_id == 0) {
1039 phy_disconnect(phydev);
1043 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
1044 * subsequent PHY polling, make sure we force a link transition if
1045 * we have a UP/DOWN/UP transition
1047 if (phydev->is_pseudo_fixed_link)
1048 phydev->irq = PHY_POLL;
1050 phy_attached_info(phydev);
1054 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1056 u32 rx_cnt = priv->plat->rx_queues_to_use;
1060 /* Display RX rings */
1061 for (queue = 0; queue < rx_cnt; queue++) {
1062 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1064 pr_info("\tRX Queue %u rings\n", queue);
1066 if (priv->extend_desc)
1067 head_rx = (void *)rx_q->dma_erx;
1069 head_rx = (void *)rx_q->dma_rx;
1071 /* Display RX ring */
1072 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1076 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1078 u32 tx_cnt = priv->plat->tx_queues_to_use;
1082 /* Display TX rings */
1083 for (queue = 0; queue < tx_cnt; queue++) {
1084 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1086 pr_info("\tTX Queue %d rings\n", queue);
1088 if (priv->extend_desc)
1089 head_tx = (void *)tx_q->dma_etx;
1091 head_tx = (void *)tx_q->dma_tx;
1093 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1097 static void stmmac_display_rings(struct stmmac_priv *priv)
1099 /* Display RX ring */
1100 stmmac_display_rx_rings(priv);
1102 /* Display TX ring */
1103 stmmac_display_tx_rings(priv);
1106 static int stmmac_set_bfsize(int mtu, int bufsize)
1110 if (mtu >= BUF_SIZE_4KiB)
1111 ret = BUF_SIZE_8KiB;
1112 else if (mtu >= BUF_SIZE_2KiB)
1113 ret = BUF_SIZE_4KiB;
1114 else if (mtu > DEFAULT_BUFSIZE)
1115 ret = BUF_SIZE_2KiB;
1117 ret = DEFAULT_BUFSIZE;
1123 * stmmac_clear_rx_descriptors - clear RX descriptors
1124 * @priv: driver private structure
1125 * @queue: RX queue index
1126 * Description: this function is called to clear the RX descriptors
1127 * in case of both basic and extended descriptors are used.
1129 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1131 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1134 /* Clear the RX descriptors */
1135 for (i = 0; i < DMA_RX_SIZE; i++)
1136 if (priv->extend_desc)
1137 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1138 priv->use_riwt, priv->mode,
1139 (i == DMA_RX_SIZE - 1),
1142 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1143 priv->use_riwt, priv->mode,
1144 (i == DMA_RX_SIZE - 1),
1149 * stmmac_clear_tx_descriptors - clear tx descriptors
1150 * @priv: driver private structure
1151 * @queue: TX queue index.
1152 * Description: this function is called to clear the TX descriptors
1153 * in case of both basic and extended descriptors are used.
1155 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1157 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1160 /* Clear the TX descriptors */
1161 for (i = 0; i < DMA_TX_SIZE; i++)
1162 if (priv->extend_desc)
1163 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1164 priv->mode, (i == DMA_TX_SIZE - 1));
1166 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1167 priv->mode, (i == DMA_TX_SIZE - 1));
1171 * stmmac_clear_descriptors - clear descriptors
1172 * @priv: driver private structure
1173 * Description: this function is called to clear the TX and RX descriptors
1174 * in case of both basic and extended descriptors are used.
1176 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1178 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1179 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1182 /* Clear the RX descriptors */
1183 for (queue = 0; queue < rx_queue_cnt; queue++)
1184 stmmac_clear_rx_descriptors(priv, queue);
1186 /* Clear the TX descriptors */
1187 for (queue = 0; queue < tx_queue_cnt; queue++)
1188 stmmac_clear_tx_descriptors(priv, queue);
1192 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1193 * @priv: driver private structure
1194 * @p: descriptor pointer
1195 * @i: descriptor index
1197 * @queue: RX queue index
1198 * Description: this function is called to allocate a receive buffer, perform
1199 * the DMA mapping and init the descriptor.
1201 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1202 int i, gfp_t flags, u32 queue)
1204 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1205 struct sk_buff *skb;
1207 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1209 netdev_err(priv->dev,
1210 "%s: Rx init fails; skb is NULL\n", __func__);
1213 rx_q->rx_skbuff[i] = skb;
1214 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1217 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1218 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1219 dev_kfree_skb_any(skb);
1223 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1225 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1226 stmmac_init_desc3(priv, p);
1232 * stmmac_free_rx_buffer - free RX dma buffers
1233 * @priv: private structure
1234 * @queue: RX queue index
1237 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1239 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1241 if (rx_q->rx_skbuff[i]) {
1242 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1243 priv->dma_buf_sz, DMA_FROM_DEVICE);
1244 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1246 rx_q->rx_skbuff[i] = NULL;
1250 * stmmac_free_tx_buffer - free RX dma buffers
1251 * @priv: private structure
1252 * @queue: RX queue index
1255 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1257 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1259 if (tx_q->tx_skbuff_dma[i].buf) {
1260 if (tx_q->tx_skbuff_dma[i].map_as_page)
1261 dma_unmap_page(priv->device,
1262 tx_q->tx_skbuff_dma[i].buf,
1263 tx_q->tx_skbuff_dma[i].len,
1266 dma_unmap_single(priv->device,
1267 tx_q->tx_skbuff_dma[i].buf,
1268 tx_q->tx_skbuff_dma[i].len,
1272 if (tx_q->tx_skbuff[i]) {
1273 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1274 tx_q->tx_skbuff[i] = NULL;
1275 tx_q->tx_skbuff_dma[i].buf = 0;
1276 tx_q->tx_skbuff_dma[i].map_as_page = false;
1281 * init_dma_rx_desc_rings - init the RX descriptor rings
1282 * @dev: net device structure
1284 * Description: this function initializes the DMA RX descriptors
1285 * and allocates the socket buffers. It supports the chained and ring
1288 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1290 struct stmmac_priv *priv = netdev_priv(dev);
1291 u32 rx_count = priv->plat->rx_queues_to_use;
1297 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1301 if (bfsize < BUF_SIZE_16KiB)
1302 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1304 priv->dma_buf_sz = bfsize;
1306 /* RX INITIALIZATION */
1307 netif_dbg(priv, probe, priv->dev,
1308 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1310 for (queue = 0; queue < rx_count; queue++) {
1311 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1313 netif_dbg(priv, probe, priv->dev,
1314 "(%s) dma_rx_phy=0x%08x\n", __func__,
1315 (u32)rx_q->dma_rx_phy);
1317 for (i = 0; i < DMA_RX_SIZE; i++) {
1320 if (priv->extend_desc)
1321 p = &((rx_q->dma_erx + i)->basic);
1323 p = rx_q->dma_rx + i;
1325 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1328 goto err_init_rx_buffers;
1330 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1331 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1332 (unsigned int)rx_q->rx_skbuff_dma[i]);
1336 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1338 stmmac_clear_rx_descriptors(priv, queue);
1340 /* Setup the chained descriptor addresses */
1341 if (priv->mode == STMMAC_CHAIN_MODE) {
1342 if (priv->extend_desc)
1343 stmmac_mode_init(priv, rx_q->dma_erx,
1344 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1346 stmmac_mode_init(priv, rx_q->dma_rx,
1347 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1355 err_init_rx_buffers:
1356 while (queue >= 0) {
1358 stmmac_free_rx_buffer(priv, queue, i);
1371 * init_dma_tx_desc_rings - init the TX descriptor rings
1372 * @dev: net device structure.
1373 * Description: this function initializes the DMA TX descriptors
1374 * and allocates the socket buffers. It supports the chained and ring
1377 static int init_dma_tx_desc_rings(struct net_device *dev)
1379 struct stmmac_priv *priv = netdev_priv(dev);
1380 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1384 for (queue = 0; queue < tx_queue_cnt; queue++) {
1385 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1387 netif_dbg(priv, probe, priv->dev,
1388 "(%s) dma_tx_phy=0x%08x\n", __func__,
1389 (u32)tx_q->dma_tx_phy);
1391 /* Setup the chained descriptor addresses */
1392 if (priv->mode == STMMAC_CHAIN_MODE) {
1393 if (priv->extend_desc)
1394 stmmac_mode_init(priv, tx_q->dma_etx,
1395 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1397 stmmac_mode_init(priv, tx_q->dma_tx,
1398 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1401 for (i = 0; i < DMA_TX_SIZE; i++) {
1403 if (priv->extend_desc)
1404 p = &((tx_q->dma_etx + i)->basic);
1406 p = tx_q->dma_tx + i;
1408 stmmac_clear_desc(priv, p);
1410 tx_q->tx_skbuff_dma[i].buf = 0;
1411 tx_q->tx_skbuff_dma[i].map_as_page = false;
1412 tx_q->tx_skbuff_dma[i].len = 0;
1413 tx_q->tx_skbuff_dma[i].last_segment = false;
1414 tx_q->tx_skbuff[i] = NULL;
1421 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1428 * init_dma_desc_rings - init the RX/TX descriptor rings
1429 * @dev: net device structure
1431 * Description: this function initializes the DMA RX/TX descriptors
1432 * and allocates the socket buffers. It supports the chained and ring
1435 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1437 struct stmmac_priv *priv = netdev_priv(dev);
1440 ret = init_dma_rx_desc_rings(dev, flags);
1444 ret = init_dma_tx_desc_rings(dev);
1446 stmmac_clear_descriptors(priv);
1448 if (netif_msg_hw(priv))
1449 stmmac_display_rings(priv);
1455 * dma_free_rx_skbufs - free RX dma buffers
1456 * @priv: private structure
1457 * @queue: RX queue index
1459 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1463 for (i = 0; i < DMA_RX_SIZE; i++)
1464 stmmac_free_rx_buffer(priv, queue, i);
1468 * dma_free_tx_skbufs - free TX dma buffers
1469 * @priv: private structure
1470 * @queue: TX queue index
1472 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1476 for (i = 0; i < DMA_TX_SIZE; i++)
1477 stmmac_free_tx_buffer(priv, queue, i);
1481 * free_dma_rx_desc_resources - free RX dma desc resources
1482 * @priv: private structure
1484 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1486 u32 rx_count = priv->plat->rx_queues_to_use;
1489 /* Free RX queue resources */
1490 for (queue = 0; queue < rx_count; queue++) {
1491 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1493 /* Release the DMA RX socket buffers */
1494 dma_free_rx_skbufs(priv, queue);
1496 /* Free DMA regions of consistent memory previously allocated */
1497 if (!priv->extend_desc)
1498 dma_free_coherent(priv->device,
1499 DMA_RX_SIZE * sizeof(struct dma_desc),
1500 rx_q->dma_rx, rx_q->dma_rx_phy);
1502 dma_free_coherent(priv->device, DMA_RX_SIZE *
1503 sizeof(struct dma_extended_desc),
1504 rx_q->dma_erx, rx_q->dma_rx_phy);
1506 kfree(rx_q->rx_skbuff_dma);
1507 kfree(rx_q->rx_skbuff);
1512 * free_dma_tx_desc_resources - free TX dma desc resources
1513 * @priv: private structure
1515 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1517 u32 tx_count = priv->plat->tx_queues_to_use;
1520 /* Free TX queue resources */
1521 for (queue = 0; queue < tx_count; queue++) {
1522 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1524 /* Release the DMA TX socket buffers */
1525 dma_free_tx_skbufs(priv, queue);
1527 /* Free DMA regions of consistent memory previously allocated */
1528 if (!priv->extend_desc)
1529 dma_free_coherent(priv->device,
1530 DMA_TX_SIZE * sizeof(struct dma_desc),
1531 tx_q->dma_tx, tx_q->dma_tx_phy);
1533 dma_free_coherent(priv->device, DMA_TX_SIZE *
1534 sizeof(struct dma_extended_desc),
1535 tx_q->dma_etx, tx_q->dma_tx_phy);
1537 kfree(tx_q->tx_skbuff_dma);
1538 kfree(tx_q->tx_skbuff);
1543 * alloc_dma_rx_desc_resources - alloc RX resources.
1544 * @priv: private structure
1545 * Description: according to which descriptor can be used (extend or basic)
1546 * this function allocates the resources for TX and RX paths. In case of
1547 * reception, for example, it pre-allocated the RX socket buffer in order to
1548 * allow zero-copy mechanism.
1550 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1552 u32 rx_count = priv->plat->rx_queues_to_use;
1556 /* RX queues buffers and DMA */
1557 for (queue = 0; queue < rx_count; queue++) {
1558 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1560 rx_q->queue_index = queue;
1561 rx_q->priv_data = priv;
1563 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1566 if (!rx_q->rx_skbuff_dma)
1569 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1570 sizeof(struct sk_buff *),
1572 if (!rx_q->rx_skbuff)
1575 if (priv->extend_desc) {
1576 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1577 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1584 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1585 DMA_RX_SIZE * sizeof(struct dma_desc),
1596 free_dma_rx_desc_resources(priv);
1602 * alloc_dma_tx_desc_resources - alloc TX resources.
1603 * @priv: private structure
1604 * Description: according to which descriptor can be used (extend or basic)
1605 * this function allocates the resources for TX and RX paths. In case of
1606 * reception, for example, it pre-allocated the RX socket buffer in order to
1607 * allow zero-copy mechanism.
1609 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1611 u32 tx_count = priv->plat->tx_queues_to_use;
1615 /* TX queues buffers and DMA */
1616 for (queue = 0; queue < tx_count; queue++) {
1617 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1619 tx_q->queue_index = queue;
1620 tx_q->priv_data = priv;
1622 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1623 sizeof(*tx_q->tx_skbuff_dma),
1625 if (!tx_q->tx_skbuff_dma)
1628 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1629 sizeof(struct sk_buff *),
1631 if (!tx_q->tx_skbuff)
1634 if (priv->extend_desc) {
1635 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1636 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1642 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1643 DMA_TX_SIZE * sizeof(struct dma_desc),
1654 free_dma_tx_desc_resources(priv);
1660 * alloc_dma_desc_resources - alloc TX/RX resources.
1661 * @priv: private structure
1662 * Description: according to which descriptor can be used (extend or basic)
1663 * this function allocates the resources for TX and RX paths. In case of
1664 * reception, for example, it pre-allocated the RX socket buffer in order to
1665 * allow zero-copy mechanism.
1667 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1670 int ret = alloc_dma_rx_desc_resources(priv);
1675 ret = alloc_dma_tx_desc_resources(priv);
1681 * free_dma_desc_resources - free dma desc resources
1682 * @priv: private structure
1684 static void free_dma_desc_resources(struct stmmac_priv *priv)
1686 /* Release the DMA RX socket buffers */
1687 free_dma_rx_desc_resources(priv);
1689 /* Release the DMA TX socket buffers */
1690 free_dma_tx_desc_resources(priv);
1694 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1695 * @priv: driver private structure
1696 * Description: It is used for enabling the rx queues in the MAC
1698 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1700 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1704 for (queue = 0; queue < rx_queues_count; queue++) {
1705 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1706 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1711 * stmmac_start_rx_dma - start RX DMA channel
1712 * @priv: driver private structure
1713 * @chan: RX channel index
1715 * This starts a RX DMA channel
1717 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1719 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1720 stmmac_start_rx(priv, priv->ioaddr, chan);
1724 * stmmac_start_tx_dma - start TX DMA channel
1725 * @priv: driver private structure
1726 * @chan: TX channel index
1728 * This starts a TX DMA channel
1730 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1732 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1733 stmmac_start_tx(priv, priv->ioaddr, chan);
1737 * stmmac_stop_rx_dma - stop RX DMA channel
1738 * @priv: driver private structure
1739 * @chan: RX channel index
1741 * This stops a RX DMA channel
1743 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1745 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1746 stmmac_stop_rx(priv, priv->ioaddr, chan);
1750 * stmmac_stop_tx_dma - stop TX DMA channel
1751 * @priv: driver private structure
1752 * @chan: TX channel index
1754 * This stops a TX DMA channel
1756 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1758 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1759 stmmac_stop_tx(priv, priv->ioaddr, chan);
1763 * stmmac_start_all_dma - start all RX and TX DMA channels
1764 * @priv: driver private structure
1766 * This starts all the RX and TX DMA channels
1768 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1770 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1771 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1774 for (chan = 0; chan < rx_channels_count; chan++)
1775 stmmac_start_rx_dma(priv, chan);
1777 for (chan = 0; chan < tx_channels_count; chan++)
1778 stmmac_start_tx_dma(priv, chan);
1782 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1783 * @priv: driver private structure
1785 * This stops the RX and TX DMA channels
1787 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1789 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1790 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1793 for (chan = 0; chan < rx_channels_count; chan++)
1794 stmmac_stop_rx_dma(priv, chan);
1796 for (chan = 0; chan < tx_channels_count; chan++)
1797 stmmac_stop_tx_dma(priv, chan);
1801 * stmmac_dma_operation_mode - HW DMA operation mode
1802 * @priv: driver private structure
1803 * Description: it is used for configuring the DMA operation mode register in
1804 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1806 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1808 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1809 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1810 int rxfifosz = priv->plat->rx_fifo_size;
1811 int txfifosz = priv->plat->tx_fifo_size;
1818 rxfifosz = priv->dma_cap.rx_fifo_size;
1820 txfifosz = priv->dma_cap.tx_fifo_size;
1822 /* Adjust for real per queue fifo size */
1823 rxfifosz /= rx_channels_count;
1824 txfifosz /= tx_channels_count;
1826 if (priv->plat->force_thresh_dma_mode) {
1829 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1831 * In case of GMAC, SF mode can be enabled
1832 * to perform the TX COE in HW. This depends on:
1833 * 1) TX COE if actually supported
1834 * 2) There is no bugged Jumbo frame support
1835 * that needs to not insert csum in the TDES.
1837 txmode = SF_DMA_MODE;
1838 rxmode = SF_DMA_MODE;
1839 priv->xstats.threshold = SF_DMA_MODE;
1842 rxmode = SF_DMA_MODE;
1845 /* configure all channels */
1846 for (chan = 0; chan < rx_channels_count; chan++) {
1847 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1849 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1851 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1855 for (chan = 0; chan < tx_channels_count; chan++) {
1856 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1858 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1864 * stmmac_tx_clean - to manage the transmission completion
1865 * @priv: driver private structure
1866 * @queue: TX queue index
1867 * Description: it reclaims the transmit resources after transmission completes.
1869 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1871 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1872 unsigned int bytes_compl = 0, pkts_compl = 0;
1873 unsigned int entry, count = 0;
1875 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1877 priv->xstats.tx_clean++;
1879 entry = tx_q->dirty_tx;
1880 while ((entry != tx_q->cur_tx) && (count < budget)) {
1881 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1885 if (priv->extend_desc)
1886 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1888 p = tx_q->dma_tx + entry;
1890 status = stmmac_tx_status(priv, &priv->dev->stats,
1891 &priv->xstats, p, priv->ioaddr);
1892 /* Check if the descriptor is owned by the DMA */
1893 if (unlikely(status & tx_dma_own))
1898 /* Make sure descriptor fields are read after reading
1903 /* Just consider the last segment and ...*/
1904 if (likely(!(status & tx_not_ls))) {
1905 /* ... verify the status error condition */
1906 if (unlikely(status & tx_err)) {
1907 priv->dev->stats.tx_errors++;
1909 priv->dev->stats.tx_packets++;
1910 priv->xstats.tx_pkt_n++;
1912 stmmac_get_tx_hwtstamp(priv, p, skb);
1915 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1916 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1917 dma_unmap_page(priv->device,
1918 tx_q->tx_skbuff_dma[entry].buf,
1919 tx_q->tx_skbuff_dma[entry].len,
1922 dma_unmap_single(priv->device,
1923 tx_q->tx_skbuff_dma[entry].buf,
1924 tx_q->tx_skbuff_dma[entry].len,
1926 tx_q->tx_skbuff_dma[entry].buf = 0;
1927 tx_q->tx_skbuff_dma[entry].len = 0;
1928 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1931 stmmac_clean_desc3(priv, tx_q, p);
1933 tx_q->tx_skbuff_dma[entry].last_segment = false;
1934 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1936 if (likely(skb != NULL)) {
1938 bytes_compl += skb->len;
1939 dev_consume_skb_any(skb);
1940 tx_q->tx_skbuff[entry] = NULL;
1943 stmmac_release_tx_desc(priv, p, priv->mode);
1945 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1947 tx_q->dirty_tx = entry;
1949 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1950 pkts_compl, bytes_compl);
1952 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1954 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1956 netif_dbg(priv, tx_done, priv->dev,
1957 "%s: restart transmit\n", __func__);
1958 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1961 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1962 stmmac_enable_eee_mode(priv);
1963 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1966 /* We still have pending packets, let's call for a new scheduling */
1967 if (tx_q->dirty_tx != tx_q->cur_tx)
1968 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1970 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1976 * stmmac_tx_err - to manage the tx error
1977 * @priv: driver private structure
1978 * @chan: channel index
1979 * Description: it cleans the descriptors and restarts the transmission
1980 * in case of transmission errors.
1982 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1984 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1987 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1989 stmmac_stop_tx_dma(priv, chan);
1990 dma_free_tx_skbufs(priv, chan);
1991 for (i = 0; i < DMA_TX_SIZE; i++)
1992 if (priv->extend_desc)
1993 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1994 priv->mode, (i == DMA_TX_SIZE - 1));
1996 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1997 priv->mode, (i == DMA_TX_SIZE - 1));
2001 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2002 stmmac_start_tx_dma(priv, chan);
2004 priv->dev->stats.tx_errors++;
2005 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2009 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2010 * @priv: driver private structure
2011 * @txmode: TX operating mode
2012 * @rxmode: RX operating mode
2013 * @chan: channel index
2014 * Description: it is used for configuring of the DMA operation mode in
2015 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2018 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2019 u32 rxmode, u32 chan)
2021 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2022 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2023 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2024 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2025 int rxfifosz = priv->plat->rx_fifo_size;
2026 int txfifosz = priv->plat->tx_fifo_size;
2029 rxfifosz = priv->dma_cap.rx_fifo_size;
2031 txfifosz = priv->dma_cap.tx_fifo_size;
2033 /* Adjust for real per queue fifo size */
2034 rxfifosz /= rx_channels_count;
2035 txfifosz /= tx_channels_count;
2037 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2038 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2041 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2045 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2046 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2047 if (ret && (ret != -EINVAL)) {
2048 stmmac_global_err(priv);
2055 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2057 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2058 &priv->xstats, chan);
2059 struct stmmac_channel *ch = &priv->channel[chan];
2061 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2062 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2063 napi_schedule_irqoff(&ch->rx_napi);
2066 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2067 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2068 napi_schedule_irqoff(&ch->tx_napi);
2075 * stmmac_dma_interrupt - DMA ISR
2076 * @priv: driver private structure
2077 * Description: this is the DMA ISR. It is called by the main ISR.
2078 * It calls the dwmac dma routine and schedule poll method in case of some
2081 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2083 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2084 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2085 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2086 tx_channel_count : rx_channel_count;
2088 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2090 /* Make sure we never check beyond our status buffer. */
2091 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2092 channels_to_check = ARRAY_SIZE(status);
2094 for (chan = 0; chan < channels_to_check; chan++)
2095 status[chan] = stmmac_napi_check(priv, chan);
2097 for (chan = 0; chan < tx_channel_count; chan++) {
2098 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2099 /* Try to bump up the dma threshold on this failure */
2100 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2103 if (priv->plat->force_thresh_dma_mode)
2104 stmmac_set_dma_operation_mode(priv,
2109 stmmac_set_dma_operation_mode(priv,
2113 priv->xstats.threshold = tc;
2115 } else if (unlikely(status[chan] == tx_hard_error)) {
2116 stmmac_tx_err(priv, chan);
2122 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2123 * @priv: driver private structure
2124 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2126 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2128 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2129 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2131 dwmac_mmc_intr_all_mask(priv->mmcaddr);
2133 if (priv->dma_cap.rmon) {
2134 dwmac_mmc_ctrl(priv->mmcaddr, mode);
2135 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2137 netdev_info(priv->dev, "No MAC Management Counters available\n");
2141 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2142 * @priv: driver private structure
2144 * new GMAC chip generations have a new register to indicate the
2145 * presence of the optional feature/functions.
2146 * This can be also used to override the value passed through the
2147 * platform and necessary for old MAC10/100 and GMAC chips.
2149 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2151 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2155 * stmmac_check_ether_addr - check if the MAC addr is valid
2156 * @priv: driver private structure
2158 * it is to verify if the MAC address is valid, in case of failures it
2159 * generates a random MAC address
2161 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2163 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2164 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2165 if (!is_valid_ether_addr(priv->dev->dev_addr))
2166 eth_hw_addr_random(priv->dev);
2167 netdev_info(priv->dev, "device MAC address %pM\n",
2168 priv->dev->dev_addr);
2173 * stmmac_init_dma_engine - DMA init.
2174 * @priv: driver private structure
2176 * It inits the DMA invoking the specific MAC/GMAC callback.
2177 * Some DMA parameters can be passed from the platform;
2178 * in case of these are not passed a default is kept for the MAC or GMAC.
2180 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2182 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2183 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2184 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2185 struct stmmac_rx_queue *rx_q;
2186 struct stmmac_tx_queue *tx_q;
2191 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2192 dev_err(priv->device, "Invalid DMA configuration\n");
2196 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2199 ret = stmmac_reset(priv, priv->ioaddr);
2201 dev_err(priv->device, "Failed to reset the dma\n");
2205 /* DMA Configuration */
2206 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2208 if (priv->plat->axi)
2209 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2211 /* DMA RX Channel Configuration */
2212 for (chan = 0; chan < rx_channels_count; chan++) {
2213 rx_q = &priv->rx_queue[chan];
2215 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2216 rx_q->dma_rx_phy, chan);
2218 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2219 (DMA_RX_SIZE * sizeof(struct dma_desc));
2220 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2221 rx_q->rx_tail_addr, chan);
2224 /* DMA TX Channel Configuration */
2225 for (chan = 0; chan < tx_channels_count; chan++) {
2226 tx_q = &priv->tx_queue[chan];
2228 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2229 tx_q->dma_tx_phy, chan);
2231 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2232 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2233 tx_q->tx_tail_addr, chan);
2236 /* DMA CSR Channel configuration */
2237 for (chan = 0; chan < dma_csr_ch; chan++)
2238 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2243 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2245 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2247 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2251 * stmmac_tx_timer - mitigation sw timer for tx.
2252 * @data: data pointer
2254 * This is the timer handler to directly invoke the stmmac_tx_clean.
2256 static void stmmac_tx_timer(struct timer_list *t)
2258 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2259 struct stmmac_priv *priv = tx_q->priv_data;
2260 struct stmmac_channel *ch;
2262 ch = &priv->channel[tx_q->queue_index];
2265 * If NAPI is already running we can miss some events. Let's rearm
2266 * the timer and try again.
2268 if (likely(napi_schedule_prep(&ch->tx_napi)))
2269 __napi_schedule(&ch->tx_napi);
2271 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2275 * stmmac_init_tx_coalesce - init tx mitigation options.
2276 * @priv: driver private structure
2278 * This inits the transmit coalesce parameters: i.e. timer rate,
2279 * timer handler and default threshold used for enabling the
2280 * interrupt on completion bit.
2282 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2284 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2287 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2288 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2290 for (chan = 0; chan < tx_channel_count; chan++) {
2291 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2293 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2297 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2299 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2300 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2303 /* set TX ring length */
2304 for (chan = 0; chan < tx_channels_count; chan++)
2305 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2306 (DMA_TX_SIZE - 1), chan);
2308 /* set RX ring length */
2309 for (chan = 0; chan < rx_channels_count; chan++)
2310 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2311 (DMA_RX_SIZE - 1), chan);
2315 * stmmac_set_tx_queue_weight - Set TX queue weight
2316 * @priv: driver private structure
2317 * Description: It is used for setting TX queues weight
2319 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2321 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2325 for (queue = 0; queue < tx_queues_count; queue++) {
2326 weight = priv->plat->tx_queues_cfg[queue].weight;
2327 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2332 * stmmac_configure_cbs - Configure CBS in TX queue
2333 * @priv: driver private structure
2334 * Description: It is used for configuring CBS in AVB TX queues
2336 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2338 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2342 /* queue 0 is reserved for legacy traffic */
2343 for (queue = 1; queue < tx_queues_count; queue++) {
2344 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2345 if (mode_to_use == MTL_QUEUE_DCB)
2348 stmmac_config_cbs(priv, priv->hw,
2349 priv->plat->tx_queues_cfg[queue].send_slope,
2350 priv->plat->tx_queues_cfg[queue].idle_slope,
2351 priv->plat->tx_queues_cfg[queue].high_credit,
2352 priv->plat->tx_queues_cfg[queue].low_credit,
2358 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2359 * @priv: driver private structure
2360 * Description: It is used for mapping RX queues to RX dma channels
2362 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2364 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2368 for (queue = 0; queue < rx_queues_count; queue++) {
2369 chan = priv->plat->rx_queues_cfg[queue].chan;
2370 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2375 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2376 * @priv: driver private structure
2377 * Description: It is used for configuring the RX Queue Priority
2379 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2381 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2385 for (queue = 0; queue < rx_queues_count; queue++) {
2386 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2389 prio = priv->plat->rx_queues_cfg[queue].prio;
2390 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2395 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2396 * @priv: driver private structure
2397 * Description: It is used for configuring the TX Queue Priority
2399 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2401 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2405 for (queue = 0; queue < tx_queues_count; queue++) {
2406 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2409 prio = priv->plat->tx_queues_cfg[queue].prio;
2410 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2415 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2416 * @priv: driver private structure
2417 * Description: It is used for configuring the RX queue routing
2419 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2421 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2425 for (queue = 0; queue < rx_queues_count; queue++) {
2426 /* no specific packet type routing specified for the queue */
2427 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2430 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2431 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2436 * stmmac_mtl_configuration - Configure MTL
2437 * @priv: driver private structure
2438 * Description: It is used for configurring MTL
2440 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2442 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2443 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2445 if (tx_queues_count > 1)
2446 stmmac_set_tx_queue_weight(priv);
2448 /* Configure MTL RX algorithms */
2449 if (rx_queues_count > 1)
2450 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2451 priv->plat->rx_sched_algorithm);
2453 /* Configure MTL TX algorithms */
2454 if (tx_queues_count > 1)
2455 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2456 priv->plat->tx_sched_algorithm);
2458 /* Configure CBS in AVB TX queues */
2459 if (tx_queues_count > 1)
2460 stmmac_configure_cbs(priv);
2462 /* Map RX MTL to DMA channels */
2463 stmmac_rx_queue_dma_chan_map(priv);
2465 /* Enable MAC RX Queues */
2466 stmmac_mac_enable_rx_queues(priv);
2468 /* Set RX priorities */
2469 if (rx_queues_count > 1)
2470 stmmac_mac_config_rx_queues_prio(priv);
2472 /* Set TX priorities */
2473 if (tx_queues_count > 1)
2474 stmmac_mac_config_tx_queues_prio(priv);
2476 /* Set RX routing */
2477 if (rx_queues_count > 1)
2478 stmmac_mac_config_rx_queues_routing(priv);
2481 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2483 if (priv->dma_cap.asp) {
2484 netdev_info(priv->dev, "Enabling Safety Features\n");
2485 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2487 netdev_info(priv->dev, "No Safety Features support found\n");
2492 * stmmac_hw_setup - setup mac in a usable state.
2493 * @dev : pointer to the device structure.
2495 * this is the main function to setup the HW in a usable state because the
2496 * dma engine is reset, the core registers are configured (e.g. AXI,
2497 * Checksum features, timers). The DMA is ready to start receiving and
2500 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2503 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2505 struct stmmac_priv *priv = netdev_priv(dev);
2506 u32 rx_cnt = priv->plat->rx_queues_to_use;
2507 u32 tx_cnt = priv->plat->tx_queues_to_use;
2511 /* DMA initialization and SW reset */
2512 ret = stmmac_init_dma_engine(priv);
2514 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2519 /* Copy the MAC addr into the HW */
2520 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2522 /* PS and related bits will be programmed according to the speed */
2523 if (priv->hw->pcs) {
2524 int speed = priv->plat->mac_port_sel_speed;
2526 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2527 (speed == SPEED_1000)) {
2528 priv->hw->ps = speed;
2530 dev_warn(priv->device, "invalid port speed\n");
2535 /* Initialize the MAC Core */
2536 stmmac_core_init(priv, priv->hw, dev);
2539 stmmac_mtl_configuration(priv);
2541 /* Initialize Safety Features */
2542 stmmac_safety_feat_configuration(priv);
2544 ret = stmmac_rx_ipc(priv, priv->hw);
2546 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2547 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2548 priv->hw->rx_csum = 0;
2551 /* Enable the MAC Rx/Tx */
2552 stmmac_mac_set(priv, priv->ioaddr, true);
2554 /* Set the HW DMA mode and the COE */
2555 stmmac_dma_operation_mode(priv);
2557 stmmac_mmc_setup(priv);
2560 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2562 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2564 ret = stmmac_init_ptp(priv);
2565 if (ret == -EOPNOTSUPP)
2566 netdev_warn(priv->dev, "PTP not supported by HW\n");
2568 netdev_warn(priv->dev, "PTP init failed\n");
2571 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2573 if (priv->use_riwt) {
2574 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2576 priv->rx_riwt = MAX_DMA_RIWT;
2580 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2582 /* set TX and RX rings length */
2583 stmmac_set_rings_length(priv);
2587 for (chan = 0; chan < tx_cnt; chan++)
2588 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2591 /* Start the ball rolling... */
2592 stmmac_start_all_dma(priv);
2597 static void stmmac_hw_teardown(struct net_device *dev)
2599 struct stmmac_priv *priv = netdev_priv(dev);
2601 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2605 * stmmac_open - open entry point of the driver
2606 * @dev : pointer to the device structure.
2608 * This function is the open entry point of the driver.
2610 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2613 static int stmmac_open(struct net_device *dev)
2615 struct stmmac_priv *priv = netdev_priv(dev);
2619 stmmac_check_ether_addr(priv);
2621 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2622 priv->hw->pcs != STMMAC_PCS_TBI &&
2623 priv->hw->pcs != STMMAC_PCS_RTBI) {
2624 ret = stmmac_init_phy(dev);
2626 netdev_err(priv->dev,
2627 "%s: Cannot attach to PHY (error: %d)\n",
2633 /* Extra statistics */
2634 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2635 priv->xstats.threshold = tc;
2637 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2638 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2640 ret = alloc_dma_desc_resources(priv);
2642 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2644 goto dma_desc_error;
2647 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2649 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2654 ret = stmmac_hw_setup(dev, true);
2656 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2660 stmmac_init_tx_coalesce(priv);
2663 phy_start(dev->phydev);
2665 /* Request the IRQ lines */
2666 ret = request_irq(dev->irq, stmmac_interrupt,
2667 IRQF_SHARED, dev->name, dev);
2668 if (unlikely(ret < 0)) {
2669 netdev_err(priv->dev,
2670 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2671 __func__, dev->irq, ret);
2675 /* Request the Wake IRQ in case of another line is used for WoL */
2676 if (priv->wol_irq != dev->irq) {
2677 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2678 IRQF_SHARED, dev->name, dev);
2679 if (unlikely(ret < 0)) {
2680 netdev_err(priv->dev,
2681 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2682 __func__, priv->wol_irq, ret);
2687 /* Request the IRQ lines */
2688 if (priv->lpi_irq > 0) {
2689 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2691 if (unlikely(ret < 0)) {
2692 netdev_err(priv->dev,
2693 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2694 __func__, priv->lpi_irq, ret);
2699 stmmac_enable_all_queues(priv);
2700 stmmac_start_all_queues(priv);
2705 if (priv->wol_irq != dev->irq)
2706 free_irq(priv->wol_irq, dev);
2708 free_irq(dev->irq, dev);
2711 phy_stop(dev->phydev);
2713 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2714 del_timer_sync(&priv->tx_queue[chan].txtimer);
2716 stmmac_hw_teardown(dev);
2718 free_dma_desc_resources(priv);
2721 phy_disconnect(dev->phydev);
2727 * stmmac_release - close entry point of the driver
2728 * @dev : device pointer.
2730 * This is the stop entry point of the driver.
2732 static int stmmac_release(struct net_device *dev)
2734 struct stmmac_priv *priv = netdev_priv(dev);
2737 if (priv->eee_enabled)
2738 del_timer_sync(&priv->eee_ctrl_timer);
2740 /* Stop and disconnect the PHY */
2742 phy_stop(dev->phydev);
2743 phy_disconnect(dev->phydev);
2746 stmmac_stop_all_queues(priv);
2748 stmmac_disable_all_queues(priv);
2750 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2751 del_timer_sync(&priv->tx_queue[chan].txtimer);
2753 /* Free the IRQ lines */
2754 free_irq(dev->irq, dev);
2755 if (priv->wol_irq != dev->irq)
2756 free_irq(priv->wol_irq, dev);
2757 if (priv->lpi_irq > 0)
2758 free_irq(priv->lpi_irq, dev);
2760 /* Stop TX/RX DMA and clear the descriptors */
2761 stmmac_stop_all_dma(priv);
2763 /* Release and free the Rx/Tx resources */
2764 free_dma_desc_resources(priv);
2766 /* Disable the MAC Rx/Tx */
2767 stmmac_mac_set(priv, priv->ioaddr, false);
2769 netif_carrier_off(dev);
2771 stmmac_release_ptp(priv);
2777 * stmmac_tso_allocator - close entry point of the driver
2778 * @priv: driver private structure
2779 * @des: buffer start address
2780 * @total_len: total length to fill in descriptors
2781 * @last_segmant: condition for the last descriptor
2782 * @queue: TX queue index
2784 * This function fills descriptor and request new descriptors according to
2785 * buffer length to fill
2787 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2788 int total_len, bool last_segment, u32 queue)
2790 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2791 struct dma_desc *desc;
2795 tmp_len = total_len;
2797 while (tmp_len > 0) {
2798 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2799 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2800 desc = tx_q->dma_tx + tx_q->cur_tx;
2802 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2803 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2804 TSO_MAX_BUFF_SIZE : tmp_len;
2806 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2808 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2811 tmp_len -= TSO_MAX_BUFF_SIZE;
2816 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2817 * @skb : the socket buffer
2818 * @dev : device pointer
2819 * Description: this is the transmit function that is called on TSO frames
2820 * (support available on GMAC4 and newer chips).
2821 * Diagram below show the ring programming in case of TSO frames:
2825 * | DES0 |---> buffer1 = L2/L3/L4 header
2826 * | DES1 |---> TCP Payload (can continue on next descr...)
2827 * | DES2 |---> buffer 1 and 2 len
2828 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2834 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2836 * | DES2 | --> buffer 1 and 2 len
2840 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2842 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2844 struct dma_desc *desc, *first, *mss_desc = NULL;
2845 struct stmmac_priv *priv = netdev_priv(dev);
2846 int nfrags = skb_shinfo(skb)->nr_frags;
2847 u32 queue = skb_get_queue_mapping(skb);
2848 unsigned int first_entry, des;
2849 struct stmmac_tx_queue *tx_q;
2850 int tmp_pay_len = 0;
2855 tx_q = &priv->tx_queue[queue];
2857 /* Compute header lengths */
2858 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2860 /* Desc availability based on threshold should be enough safe */
2861 if (unlikely(stmmac_tx_avail(priv, queue) <
2862 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2863 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2864 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2866 /* This is a hard error, log it. */
2867 netdev_err(priv->dev,
2868 "%s: Tx Ring full when queue awake\n",
2871 return NETDEV_TX_BUSY;
2874 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2876 mss = skb_shinfo(skb)->gso_size;
2878 /* set new MSS value if needed */
2879 if (mss != tx_q->mss) {
2880 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2881 stmmac_set_mss(priv, mss_desc, mss);
2883 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2884 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2887 if (netif_msg_tx_queued(priv)) {
2888 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2889 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2890 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2894 first_entry = tx_q->cur_tx;
2895 WARN_ON(tx_q->tx_skbuff[first_entry]);
2897 desc = tx_q->dma_tx + first_entry;
2900 /* first descriptor: fill Headers on Buf1 */
2901 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2903 if (dma_mapping_error(priv->device, des))
2906 tx_q->tx_skbuff_dma[first_entry].buf = des;
2907 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2909 first->des0 = cpu_to_le32(des);
2911 /* Fill start of payload in buff2 of first descriptor */
2913 first->des1 = cpu_to_le32(des + proto_hdr_len);
2915 /* If needed take extra descriptors to fill the remaining payload */
2916 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2918 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2920 /* Prepare fragments */
2921 for (i = 0; i < nfrags; i++) {
2922 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2924 des = skb_frag_dma_map(priv->device, frag, 0,
2925 skb_frag_size(frag),
2927 if (dma_mapping_error(priv->device, des))
2930 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2931 (i == nfrags - 1), queue);
2933 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2934 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2935 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2938 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2940 /* Only the last descriptor gets to point to the skb. */
2941 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2943 /* We've used all descriptors we need for this skb, however,
2944 * advance cur_tx so that it references a fresh descriptor.
2945 * ndo_start_xmit will fill this descriptor the next time it's
2946 * called and stmmac_tx_clean may clean up to this descriptor.
2948 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2950 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2951 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2953 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2956 dev->stats.tx_bytes += skb->len;
2957 priv->xstats.tx_tso_frames++;
2958 priv->xstats.tx_tso_nfrags += nfrags;
2960 /* Manage tx mitigation */
2961 tx_q->tx_count_frames += nfrags + 1;
2962 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
2963 stmmac_set_tx_ic(priv, desc);
2964 priv->xstats.tx_set_ic_bit++;
2965 tx_q->tx_count_frames = 0;
2967 stmmac_tx_timer_arm(priv, queue);
2970 skb_tx_timestamp(skb);
2972 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2973 priv->hwts_tx_en)) {
2974 /* declare that device is doing timestamping */
2975 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2976 stmmac_enable_tx_timestamp(priv, first);
2979 /* Complete the first descriptor before granting the DMA */
2980 stmmac_prepare_tso_tx_desc(priv, first, 1,
2983 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2984 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2986 /* If context desc is used to change MSS */
2988 /* Make sure that first descriptor has been completely
2989 * written, including its own bit. This is because MSS is
2990 * actually before first descriptor, so we need to make
2991 * sure that MSS's own bit is the last thing written.
2994 stmmac_set_tx_owner(priv, mss_desc);
2997 /* The own bit must be the latest setting done when prepare the
2998 * descriptor and then barrier is needed to make sure that
2999 * all is coherent before granting the DMA engine.
3003 if (netif_msg_pktdata(priv)) {
3004 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3005 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3006 tx_q->cur_tx, first, nfrags);
3008 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3010 pr_info(">>> frame to be transmitted: ");
3011 print_pkt(skb->data, skb_headlen(skb));
3014 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3016 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3017 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3019 return NETDEV_TX_OK;
3022 dev_err(priv->device, "Tx dma map failed\n");
3024 priv->dev->stats.tx_dropped++;
3025 return NETDEV_TX_OK;
3029 * stmmac_xmit - Tx entry point of the driver
3030 * @skb : the socket buffer
3031 * @dev : device pointer
3032 * Description : this is the tx entry point of the driver.
3033 * It programs the chain or the ring and supports oversized frames
3036 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3038 struct stmmac_priv *priv = netdev_priv(dev);
3039 unsigned int nopaged_len = skb_headlen(skb);
3040 int i, csum_insertion = 0, is_jumbo = 0;
3041 u32 queue = skb_get_queue_mapping(skb);
3042 int nfrags = skb_shinfo(skb)->nr_frags;
3044 unsigned int first_entry;
3045 struct dma_desc *desc, *first;
3046 struct stmmac_tx_queue *tx_q;
3047 unsigned int enh_desc;
3050 tx_q = &priv->tx_queue[queue];
3052 if (priv->tx_path_in_lpi_mode)
3053 stmmac_disable_eee_mode(priv);
3055 /* Manage oversized TCP frames for GMAC4 device */
3056 if (skb_is_gso(skb) && priv->tso) {
3057 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3059 * There is no way to determine the number of TSO
3060 * capable Queues. Let's use always the Queue 0
3061 * because if TSO is supported then at least this
3062 * one will be capable.
3064 skb_set_queue_mapping(skb, 0);
3066 return stmmac_tso_xmit(skb, dev);
3070 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3071 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3072 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3074 /* This is a hard error, log it. */
3075 netdev_err(priv->dev,
3076 "%s: Tx Ring full when queue awake\n",
3079 return NETDEV_TX_BUSY;
3082 entry = tx_q->cur_tx;
3083 first_entry = entry;
3084 WARN_ON(tx_q->tx_skbuff[first_entry]);
3086 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3088 if (likely(priv->extend_desc))
3089 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3091 desc = tx_q->dma_tx + entry;
3095 enh_desc = priv->plat->enh_desc;
3096 /* To program the descriptors according to the size of the frame */
3098 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3100 if (unlikely(is_jumbo)) {
3101 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3102 if (unlikely(entry < 0) && (entry != -EINVAL))
3106 for (i = 0; i < nfrags; i++) {
3107 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3108 int len = skb_frag_size(frag);
3109 bool last_segment = (i == (nfrags - 1));
3111 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3112 WARN_ON(tx_q->tx_skbuff[entry]);
3114 if (likely(priv->extend_desc))
3115 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3117 desc = tx_q->dma_tx + entry;
3119 des = skb_frag_dma_map(priv->device, frag, 0, len,
3121 if (dma_mapping_error(priv->device, des))
3122 goto dma_map_err; /* should reuse desc w/o issues */
3124 tx_q->tx_skbuff_dma[entry].buf = des;
3126 stmmac_set_desc_addr(priv, desc, des);
3128 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3129 tx_q->tx_skbuff_dma[entry].len = len;
3130 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3132 /* Prepare the descriptor and set the own bit too */
3133 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3134 priv->mode, 1, last_segment, skb->len);
3137 /* Only the last descriptor gets to point to the skb. */
3138 tx_q->tx_skbuff[entry] = skb;
3140 /* We've used all descriptors we need for this skb, however,
3141 * advance cur_tx so that it references a fresh descriptor.
3142 * ndo_start_xmit will fill this descriptor the next time it's
3143 * called and stmmac_tx_clean may clean up to this descriptor.
3145 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3146 tx_q->cur_tx = entry;
3148 if (netif_msg_pktdata(priv)) {
3151 netdev_dbg(priv->dev,
3152 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3153 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3154 entry, first, nfrags);
3156 if (priv->extend_desc)
3157 tx_head = (void *)tx_q->dma_etx;
3159 tx_head = (void *)tx_q->dma_tx;
3161 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3163 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3164 print_pkt(skb->data, skb->len);
3167 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3168 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3170 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3173 dev->stats.tx_bytes += skb->len;
3175 /* According to the coalesce parameter the IC bit for the latest
3176 * segment is reset and the timer re-started to clean the tx status.
3177 * This approach takes care about the fragments: desc is the first
3178 * element in case of no SG.
3180 tx_q->tx_count_frames += nfrags + 1;
3181 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
3182 stmmac_set_tx_ic(priv, desc);
3183 priv->xstats.tx_set_ic_bit++;
3184 tx_q->tx_count_frames = 0;
3186 stmmac_tx_timer_arm(priv, queue);
3189 skb_tx_timestamp(skb);
3191 /* Ready to fill the first descriptor and set the OWN bit w/o any
3192 * problems because all the descriptors are actually ready to be
3193 * passed to the DMA engine.
3195 if (likely(!is_jumbo)) {
3196 bool last_segment = (nfrags == 0);
3198 des = dma_map_single(priv->device, skb->data,
3199 nopaged_len, DMA_TO_DEVICE);
3200 if (dma_mapping_error(priv->device, des))
3203 tx_q->tx_skbuff_dma[first_entry].buf = des;
3205 stmmac_set_desc_addr(priv, first, des);
3207 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3208 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3210 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3211 priv->hwts_tx_en)) {
3212 /* declare that device is doing timestamping */
3213 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3214 stmmac_enable_tx_timestamp(priv, first);
3217 /* Prepare the first descriptor setting the OWN bit too */
3218 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3219 csum_insertion, priv->mode, 1, last_segment,
3222 stmmac_set_tx_owner(priv, first);
3225 /* The own bit must be the latest setting done when prepare the
3226 * descriptor and then barrier is needed to make sure that
3227 * all is coherent before granting the DMA engine.
3231 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3233 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3235 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3236 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3238 return NETDEV_TX_OK;
3241 netdev_err(priv->dev, "Tx DMA map failed\n");
3243 priv->dev->stats.tx_dropped++;
3244 return NETDEV_TX_OK;
3247 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3249 struct vlan_ethhdr *veth;
3253 veth = (struct vlan_ethhdr *)skb->data;
3254 vlan_proto = veth->h_vlan_proto;
3256 if ((vlan_proto == htons(ETH_P_8021Q) &&
3257 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3258 (vlan_proto == htons(ETH_P_8021AD) &&
3259 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3260 /* pop the vlan tag */
3261 vlanid = ntohs(veth->h_vlan_TCI);
3262 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3263 skb_pull(skb, VLAN_HLEN);
3264 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3269 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3271 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3278 * stmmac_rx_refill - refill used skb preallocated buffers
3279 * @priv: driver private structure
3280 * @queue: RX queue index
3281 * Description : this is to reallocate the skb for the reception process
3282 * that is based on zero-copy.
3284 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3286 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3287 int dirty = stmmac_rx_dirty(priv, queue);
3288 unsigned int entry = rx_q->dirty_rx;
3290 int bfsize = priv->dma_buf_sz;
3292 while (dirty-- > 0) {
3295 if (priv->extend_desc)
3296 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3298 p = rx_q->dma_rx + entry;
3300 if (likely(!rx_q->rx_skbuff[entry])) {
3301 struct sk_buff *skb;
3303 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3304 if (unlikely(!skb)) {
3305 /* so for a while no zero-copy! */
3306 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3307 if (unlikely(net_ratelimit()))
3308 dev_err(priv->device,
3309 "fail to alloc skb entry %d\n",
3314 rx_q->rx_skbuff[entry] = skb;
3315 rx_q->rx_skbuff_dma[entry] =
3316 dma_map_single(priv->device, skb->data, bfsize,
3318 if (dma_mapping_error(priv->device,
3319 rx_q->rx_skbuff_dma[entry])) {
3320 netdev_err(priv->dev, "Rx DMA map failed\n");
3325 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3326 stmmac_refill_desc3(priv, rx_q, p);
3328 if (rx_q->rx_zeroc_thresh > 0)
3329 rx_q->rx_zeroc_thresh--;
3331 netif_dbg(priv, rx_status, priv->dev,
3332 "refill entry #%d\n", entry);
3336 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3340 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3342 rx_q->dirty_rx = entry;
3346 * stmmac_rx - manage the receive process
3347 * @priv: driver private structure
3348 * @limit: napi bugget
3349 * @queue: RX queue index.
3350 * Description : this the function called by the napi poll method.
3351 * It gets all the frames inside the ring.
3353 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3355 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3356 struct stmmac_channel *ch = &priv->channel[queue];
3357 unsigned int next_entry = rx_q->cur_rx;
3358 int coe = priv->hw->rx_csum;
3359 unsigned int count = 0;
3362 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3364 if (netif_msg_rx_status(priv)) {
3367 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3368 if (priv->extend_desc)
3369 rx_head = (void *)rx_q->dma_erx;
3371 rx_head = (void *)rx_q->dma_rx;
3373 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3375 while (count < limit) {
3378 struct dma_desc *np;
3382 if (priv->extend_desc)
3383 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3385 p = rx_q->dma_rx + entry;
3387 /* read the status of the incoming frame */
3388 status = stmmac_rx_status(priv, &priv->dev->stats,
3390 /* check if managed by the DMA otherwise go ahead */
3391 if (unlikely(status & dma_own))
3396 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3397 next_entry = rx_q->cur_rx;
3399 if (priv->extend_desc)
3400 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3402 np = rx_q->dma_rx + next_entry;
3406 if (priv->extend_desc)
3407 stmmac_rx_extended_status(priv, &priv->dev->stats,
3408 &priv->xstats, rx_q->dma_erx + entry);
3409 if (unlikely(status == discard_frame)) {
3410 priv->dev->stats.rx_errors++;
3411 if (priv->hwts_rx_en && !priv->extend_desc) {
3412 /* DESC2 & DESC3 will be overwritten by device
3413 * with timestamp value, hence reinitialize
3414 * them in stmmac_rx_refill() function so that
3415 * device can reuse it.
3417 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3418 rx_q->rx_skbuff[entry] = NULL;
3419 dma_unmap_single(priv->device,
3420 rx_q->rx_skbuff_dma[entry],
3425 struct sk_buff *skb;
3429 stmmac_get_desc_addr(priv, p, &des);
3430 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3432 /* If frame length is greater than skb buffer size
3433 * (preallocated during init) then the packet is
3436 if (frame_len > priv->dma_buf_sz) {
3437 if (net_ratelimit())
3438 netdev_err(priv->dev,
3439 "len %d larger than size (%d)\n",
3440 frame_len, priv->dma_buf_sz);
3441 priv->dev->stats.rx_length_errors++;
3445 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3446 * Type frames (LLC/LLC-SNAP)
3448 * llc_snap is never checked in GMAC >= 4, so this ACS
3449 * feature is always disabled and packets need to be
3450 * stripped manually.
3452 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3453 unlikely(status != llc_snap))
3454 frame_len -= ETH_FCS_LEN;
3456 if (netif_msg_rx_status(priv)) {
3457 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3459 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3463 /* The zero-copy is always used for all the sizes
3464 * in case of GMAC4 because it needs
3465 * to refill the used descriptors, always.
3467 if (unlikely(!xmac &&
3468 ((frame_len < priv->rx_copybreak) ||
3469 stmmac_rx_threshold_count(rx_q)))) {
3470 skb = netdev_alloc_skb_ip_align(priv->dev,
3472 if (unlikely(!skb)) {
3473 if (net_ratelimit())
3474 dev_warn(priv->device,
3475 "packet dropped\n");
3476 priv->dev->stats.rx_dropped++;
3480 dma_sync_single_for_cpu(priv->device,
3484 skb_copy_to_linear_data(skb,
3486 rx_skbuff[entry]->data,
3489 skb_put(skb, frame_len);
3490 dma_sync_single_for_device(priv->device,
3495 skb = rx_q->rx_skbuff[entry];
3496 if (unlikely(!skb)) {
3497 if (net_ratelimit())
3498 netdev_err(priv->dev,
3499 "%s: Inconsistent Rx chain\n",
3501 priv->dev->stats.rx_dropped++;
3504 prefetch(skb->data - NET_IP_ALIGN);
3505 rx_q->rx_skbuff[entry] = NULL;
3506 rx_q->rx_zeroc_thresh++;
3508 skb_put(skb, frame_len);
3509 dma_unmap_single(priv->device,
3510 rx_q->rx_skbuff_dma[entry],
3515 if (netif_msg_pktdata(priv)) {
3516 netdev_dbg(priv->dev, "frame received (%dbytes)",
3518 print_pkt(skb->data, frame_len);
3521 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3523 stmmac_rx_vlan(priv->dev, skb);
3525 skb->protocol = eth_type_trans(skb, priv->dev);
3528 skb_checksum_none_assert(skb);
3530 skb->ip_summed = CHECKSUM_UNNECESSARY;
3532 napi_gro_receive(&ch->rx_napi, skb);
3534 priv->dev->stats.rx_packets++;
3535 priv->dev->stats.rx_bytes += frame_len;
3539 stmmac_rx_refill(priv, queue);
3541 priv->xstats.rx_pkt_n += count;
3546 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3548 struct stmmac_channel *ch =
3549 container_of(napi, struct stmmac_channel, rx_napi);
3550 struct stmmac_priv *priv = ch->priv_data;
3551 u32 chan = ch->index;
3554 priv->xstats.napi_poll++;
3556 work_done = stmmac_rx(priv, budget, chan);
3557 if (work_done < budget && napi_complete_done(napi, work_done))
3558 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3562 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3564 struct stmmac_channel *ch =
3565 container_of(napi, struct stmmac_channel, tx_napi);
3566 struct stmmac_priv *priv = ch->priv_data;
3567 struct stmmac_tx_queue *tx_q;
3568 u32 chan = ch->index;
3571 priv->xstats.napi_poll++;
3573 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3574 work_done = min(work_done, budget);
3576 if (work_done < budget && napi_complete_done(napi, work_done))
3577 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3579 /* Force transmission restart */
3580 tx_q = &priv->tx_queue[chan];
3581 if (tx_q->cur_tx != tx_q->dirty_tx) {
3582 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3583 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3592 * @dev : Pointer to net device structure
3593 * Description: this function is called when a packet transmission fails to
3594 * complete within a reasonable time. The driver will mark the error in the
3595 * netdev structure and arrange for the device to be reset to a sane state
3596 * in order to transmit a new packet.
3598 static void stmmac_tx_timeout(struct net_device *dev)
3600 struct stmmac_priv *priv = netdev_priv(dev);
3602 stmmac_global_err(priv);
3606 * stmmac_set_rx_mode - entry point for multicast addressing
3607 * @dev : pointer to the device structure
3609 * This function is a driver entry point which gets called by the kernel
3610 * whenever multicast addresses must be enabled/disabled.
3614 static void stmmac_set_rx_mode(struct net_device *dev)
3616 struct stmmac_priv *priv = netdev_priv(dev);
3618 stmmac_set_filter(priv, priv->hw, dev);
3622 * stmmac_change_mtu - entry point to change MTU size for the device.
3623 * @dev : device pointer.
3624 * @new_mtu : the new MTU size for the device.
3625 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3626 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3627 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3629 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3632 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3634 struct stmmac_priv *priv = netdev_priv(dev);
3636 if (netif_running(dev)) {
3637 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3643 netdev_update_features(dev);
3648 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3649 netdev_features_t features)
3651 struct stmmac_priv *priv = netdev_priv(dev);
3653 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3654 features &= ~NETIF_F_RXCSUM;
3656 if (!priv->plat->tx_coe)
3657 features &= ~NETIF_F_CSUM_MASK;
3659 /* Some GMAC devices have a bugged Jumbo frame support that
3660 * needs to have the Tx COE disabled for oversized frames
3661 * (due to limited buffer sizes). In this case we disable
3662 * the TX csum insertion in the TDES and not use SF.
3664 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3665 features &= ~NETIF_F_CSUM_MASK;
3667 /* Disable tso if asked by ethtool */
3668 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3669 if (features & NETIF_F_TSO)
3678 static int stmmac_set_features(struct net_device *netdev,
3679 netdev_features_t features)
3681 struct stmmac_priv *priv = netdev_priv(netdev);
3683 /* Keep the COE Type in case of csum is supporting */
3684 if (features & NETIF_F_RXCSUM)
3685 priv->hw->rx_csum = priv->plat->rx_coe;
3687 priv->hw->rx_csum = 0;
3688 /* No check needed because rx_coe has been set before and it will be
3689 * fixed in case of issue.
3691 stmmac_rx_ipc(priv, priv->hw);
3697 * stmmac_interrupt - main ISR
3698 * @irq: interrupt number.
3699 * @dev_id: to pass the net device pointer.
3700 * Description: this is the main driver interrupt service routine.
3702 * o DMA service routine (to manage incoming frame reception and transmission
3704 * o Core interrupts to manage: remote wake-up, management counter, LPI
3707 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3709 struct net_device *dev = (struct net_device *)dev_id;
3710 struct stmmac_priv *priv = netdev_priv(dev);
3711 u32 rx_cnt = priv->plat->rx_queues_to_use;
3712 u32 tx_cnt = priv->plat->tx_queues_to_use;
3717 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3718 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3721 pm_wakeup_event(priv->device, 0);
3723 if (unlikely(!dev)) {
3724 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3728 /* Check if adapter is up */
3729 if (test_bit(STMMAC_DOWN, &priv->state))
3731 /* Check if a fatal error happened */
3732 if (stmmac_safety_feat_interrupt(priv))
3735 /* To handle GMAC own interrupts */
3736 if ((priv->plat->has_gmac) || xmac) {
3737 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3740 if (unlikely(status)) {
3741 /* For LPI we need to save the tx status */
3742 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3743 priv->tx_path_in_lpi_mode = true;
3744 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3745 priv->tx_path_in_lpi_mode = false;
3748 for (queue = 0; queue < queues_count; queue++) {
3749 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3751 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3753 if (mtl_status != -EINVAL)
3754 status |= mtl_status;
3756 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3757 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3762 /* PCS link status */
3763 if (priv->hw->pcs) {
3764 if (priv->xstats.pcs_link)
3765 netif_carrier_on(dev);
3767 netif_carrier_off(dev);
3771 /* To handle DMA interrupts */
3772 stmmac_dma_interrupt(priv);
3777 #ifdef CONFIG_NET_POLL_CONTROLLER
3778 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3779 * to allow network I/O with interrupts disabled.
3781 static void stmmac_poll_controller(struct net_device *dev)
3783 disable_irq(dev->irq);
3784 stmmac_interrupt(dev->irq, dev);
3785 enable_irq(dev->irq);
3790 * stmmac_ioctl - Entry point for the Ioctl
3791 * @dev: Device pointer.
3792 * @rq: An IOCTL specefic structure, that can contain a pointer to
3793 * a proprietary structure used to pass information to the driver.
3794 * @cmd: IOCTL command
3796 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3798 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3800 int ret = -EOPNOTSUPP;
3802 if (!netif_running(dev))
3811 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3814 ret = stmmac_hwtstamp_set(dev, rq);
3817 ret = stmmac_hwtstamp_get(dev, rq);
3826 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3829 struct stmmac_priv *priv = cb_priv;
3830 int ret = -EOPNOTSUPP;
3832 stmmac_disable_all_queues(priv);
3835 case TC_SETUP_CLSU32:
3836 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3837 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3843 stmmac_enable_all_queues(priv);
3847 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3848 struct tc_block_offload *f)
3850 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3853 switch (f->command) {
3855 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3856 priv, priv, f->extack);
3857 case TC_BLOCK_UNBIND:
3858 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3865 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3868 struct stmmac_priv *priv = netdev_priv(ndev);
3871 case TC_SETUP_BLOCK:
3872 return stmmac_setup_tc_block(priv, type_data);
3873 case TC_SETUP_QDISC_CBS:
3874 return stmmac_tc_setup_cbs(priv, priv, type_data);
3880 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3882 struct stmmac_priv *priv = netdev_priv(ndev);
3885 ret = eth_mac_addr(ndev, addr);
3889 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3894 #ifdef CONFIG_DEBUG_FS
3895 static struct dentry *stmmac_fs_dir;
3897 static void sysfs_display_ring(void *head, int size, int extend_desc,
3898 struct seq_file *seq)
3901 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3902 struct dma_desc *p = (struct dma_desc *)head;
3904 for (i = 0; i < size; i++) {
3906 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3907 i, (unsigned int)virt_to_phys(ep),
3908 le32_to_cpu(ep->basic.des0),
3909 le32_to_cpu(ep->basic.des1),
3910 le32_to_cpu(ep->basic.des2),
3911 le32_to_cpu(ep->basic.des3));
3914 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3915 i, (unsigned int)virt_to_phys(p),
3916 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3917 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3920 seq_printf(seq, "\n");
3924 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3926 struct net_device *dev = seq->private;
3927 struct stmmac_priv *priv = netdev_priv(dev);
3928 u32 rx_count = priv->plat->rx_queues_to_use;
3929 u32 tx_count = priv->plat->tx_queues_to_use;
3932 if ((dev->flags & IFF_UP) == 0)
3935 for (queue = 0; queue < rx_count; queue++) {
3936 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3938 seq_printf(seq, "RX Queue %d:\n", queue);
3940 if (priv->extend_desc) {
3941 seq_printf(seq, "Extended descriptor ring:\n");
3942 sysfs_display_ring((void *)rx_q->dma_erx,
3943 DMA_RX_SIZE, 1, seq);
3945 seq_printf(seq, "Descriptor ring:\n");
3946 sysfs_display_ring((void *)rx_q->dma_rx,
3947 DMA_RX_SIZE, 0, seq);
3951 for (queue = 0; queue < tx_count; queue++) {
3952 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3954 seq_printf(seq, "TX Queue %d:\n", queue);
3956 if (priv->extend_desc) {
3957 seq_printf(seq, "Extended descriptor ring:\n");
3958 sysfs_display_ring((void *)tx_q->dma_etx,
3959 DMA_TX_SIZE, 1, seq);
3961 seq_printf(seq, "Descriptor ring:\n");
3962 sysfs_display_ring((void *)tx_q->dma_tx,
3963 DMA_TX_SIZE, 0, seq);
3969 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3971 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3973 struct net_device *dev = seq->private;
3974 struct stmmac_priv *priv = netdev_priv(dev);
3976 if (!priv->hw_cap_support) {
3977 seq_printf(seq, "DMA HW features not supported\n");
3981 seq_printf(seq, "==============================\n");
3982 seq_printf(seq, "\tDMA HW features\n");
3983 seq_printf(seq, "==============================\n");
3985 seq_printf(seq, "\t10/100 Mbps: %s\n",
3986 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3987 seq_printf(seq, "\t1000 Mbps: %s\n",
3988 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3989 seq_printf(seq, "\tHalf duplex: %s\n",
3990 (priv->dma_cap.half_duplex) ? "Y" : "N");
3991 seq_printf(seq, "\tHash Filter: %s\n",
3992 (priv->dma_cap.hash_filter) ? "Y" : "N");
3993 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3994 (priv->dma_cap.multi_addr) ? "Y" : "N");
3995 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3996 (priv->dma_cap.pcs) ? "Y" : "N");
3997 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3998 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3999 seq_printf(seq, "\tPMT Remote wake up: %s\n",
4000 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4001 seq_printf(seq, "\tPMT Magic Frame: %s\n",
4002 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4003 seq_printf(seq, "\tRMON module: %s\n",
4004 (priv->dma_cap.rmon) ? "Y" : "N");
4005 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4006 (priv->dma_cap.time_stamp) ? "Y" : "N");
4007 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4008 (priv->dma_cap.atime_stamp) ? "Y" : "N");
4009 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4010 (priv->dma_cap.eee) ? "Y" : "N");
4011 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4012 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4013 (priv->dma_cap.tx_coe) ? "Y" : "N");
4014 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4015 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4016 (priv->dma_cap.rx_coe) ? "Y" : "N");
4018 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4019 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4020 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4021 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4023 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4024 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4025 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4026 priv->dma_cap.number_rx_channel);
4027 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4028 priv->dma_cap.number_tx_channel);
4029 seq_printf(seq, "\tEnhanced descriptors: %s\n",
4030 (priv->dma_cap.enh_desc) ? "Y" : "N");
4034 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4036 static int stmmac_init_fs(struct net_device *dev)
4038 struct stmmac_priv *priv = netdev_priv(dev);
4040 /* Create per netdev entries */
4041 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4043 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
4044 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
4049 /* Entry to report DMA RX/TX rings */
4050 priv->dbgfs_rings_status =
4051 debugfs_create_file("descriptors_status", 0444,
4052 priv->dbgfs_dir, dev,
4053 &stmmac_rings_status_fops);
4055 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
4056 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4057 debugfs_remove_recursive(priv->dbgfs_dir);
4062 /* Entry to report the DMA HW features */
4063 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4065 dev, &stmmac_dma_cap_fops);
4067 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4068 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4069 debugfs_remove_recursive(priv->dbgfs_dir);
4077 static void stmmac_exit_fs(struct net_device *dev)
4079 struct stmmac_priv *priv = netdev_priv(dev);
4081 debugfs_remove_recursive(priv->dbgfs_dir);
4083 #endif /* CONFIG_DEBUG_FS */
4085 static const struct net_device_ops stmmac_netdev_ops = {
4086 .ndo_open = stmmac_open,
4087 .ndo_start_xmit = stmmac_xmit,
4088 .ndo_stop = stmmac_release,
4089 .ndo_change_mtu = stmmac_change_mtu,
4090 .ndo_fix_features = stmmac_fix_features,
4091 .ndo_set_features = stmmac_set_features,
4092 .ndo_set_rx_mode = stmmac_set_rx_mode,
4093 .ndo_tx_timeout = stmmac_tx_timeout,
4094 .ndo_do_ioctl = stmmac_ioctl,
4095 .ndo_setup_tc = stmmac_setup_tc,
4096 #ifdef CONFIG_NET_POLL_CONTROLLER
4097 .ndo_poll_controller = stmmac_poll_controller,
4099 .ndo_set_mac_address = stmmac_set_mac_address,
4102 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4104 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4106 if (test_bit(STMMAC_DOWN, &priv->state))
4109 netdev_err(priv->dev, "Reset adapter.\n");
4112 netif_trans_update(priv->dev);
4113 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4114 usleep_range(1000, 2000);
4116 set_bit(STMMAC_DOWN, &priv->state);
4117 dev_close(priv->dev);
4118 dev_open(priv->dev, NULL);
4119 clear_bit(STMMAC_DOWN, &priv->state);
4120 clear_bit(STMMAC_RESETING, &priv->state);
4124 static void stmmac_service_task(struct work_struct *work)
4126 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4129 stmmac_reset_subtask(priv);
4130 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4134 * stmmac_hw_init - Init the MAC device
4135 * @priv: driver private structure
4136 * Description: this function is to configure the MAC device according to
4137 * some platform parameters or the HW capability register. It prepares the
4138 * driver to use either ring or chain modes and to setup either enhanced or
4139 * normal descriptors.
4141 static int stmmac_hw_init(struct stmmac_priv *priv)
4145 /* dwmac-sun8i only work in chain mode */
4146 if (priv->plat->has_sun8i)
4148 priv->chain_mode = chain_mode;
4150 /* Initialize HW Interface */
4151 ret = stmmac_hwif_init(priv);
4155 /* Get the HW capability (new GMAC newer than 3.50a) */
4156 priv->hw_cap_support = stmmac_get_hw_features(priv);
4157 if (priv->hw_cap_support) {
4158 dev_info(priv->device, "DMA HW capability register supported\n");
4160 /* We can override some gmac/dma configuration fields: e.g.
4161 * enh_desc, tx_coe (e.g. that are passed through the
4162 * platform) with the values from the HW capability
4163 * register (if supported).
4165 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4166 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4167 priv->hw->pmt = priv->plat->pmt;
4169 /* TXCOE doesn't work in thresh DMA mode */
4170 if (priv->plat->force_thresh_dma_mode)
4171 priv->plat->tx_coe = 0;
4173 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4175 /* In case of GMAC4 rx_coe is from HW cap register. */
4176 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4178 if (priv->dma_cap.rx_coe_type2)
4179 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4180 else if (priv->dma_cap.rx_coe_type1)
4181 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4184 dev_info(priv->device, "No HW DMA feature register supported\n");
4187 if (priv->plat->rx_coe) {
4188 priv->hw->rx_csum = priv->plat->rx_coe;
4189 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4190 if (priv->synopsys_id < DWMAC_CORE_4_00)
4191 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4193 if (priv->plat->tx_coe)
4194 dev_info(priv->device, "TX Checksum insertion supported\n");
4196 if (priv->plat->pmt) {
4197 dev_info(priv->device, "Wake-Up On Lan supported\n");
4198 device_set_wakeup_capable(priv->device, 1);
4201 if (priv->dma_cap.tsoen)
4202 dev_info(priv->device, "TSO supported\n");
4204 /* Run HW quirks, if any */
4205 if (priv->hwif_quirks) {
4206 ret = priv->hwif_quirks(priv);
4211 /* Rx Watchdog is available in the COREs newer than the 3.40.
4212 * In some case, for example on bugged HW this feature
4213 * has to be disable and this can be done by passing the
4214 * riwt_off field from the platform.
4216 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4217 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4219 dev_info(priv->device,
4220 "Enable RX Mitigation via HW Watchdog Timer\n");
4228 * @device: device pointer
4229 * @plat_dat: platform data pointer
4230 * @res: stmmac resource pointer
4231 * Description: this is the main probe function used to
4232 * call the alloc_etherdev, allocate the priv structure.
4234 * returns 0 on success, otherwise errno.
4236 int stmmac_dvr_probe(struct device *device,
4237 struct plat_stmmacenet_data *plat_dat,
4238 struct stmmac_resources *res)
4240 struct net_device *ndev = NULL;
4241 struct stmmac_priv *priv;
4245 ndev = alloc_etherdev_mqs(sizeof(struct stmmac_priv),
4251 SET_NETDEV_DEV(ndev, device);
4253 priv = netdev_priv(ndev);
4254 priv->device = device;
4257 stmmac_set_ethtool_ops(ndev);
4258 priv->pause = pause;
4259 priv->plat = plat_dat;
4260 priv->ioaddr = res->addr;
4261 priv->dev->base_addr = (unsigned long)res->addr;
4263 priv->dev->irq = res->irq;
4264 priv->wol_irq = res->wol_irq;
4265 priv->lpi_irq = res->lpi_irq;
4268 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4270 dev_set_drvdata(device, priv->dev);
4272 /* Verify driver arguments */
4273 stmmac_verify_args();
4275 /* Allocate workqueue */
4276 priv->wq = create_singlethread_workqueue("stmmac_wq");
4278 dev_err(priv->device, "failed to create workqueue\n");
4283 INIT_WORK(&priv->service_task, stmmac_service_task);
4285 /* Override with kernel parameters if supplied XXX CRS XXX
4286 * this needs to have multiple instances
4288 if ((phyaddr >= 0) && (phyaddr <= 31))
4289 priv->plat->phy_addr = phyaddr;
4291 if (priv->plat->stmmac_rst) {
4292 ret = reset_control_assert(priv->plat->stmmac_rst);
4293 reset_control_deassert(priv->plat->stmmac_rst);
4294 /* Some reset controllers have only reset callback instead of
4295 * assert + deassert callbacks pair.
4297 if (ret == -ENOTSUPP)
4298 reset_control_reset(priv->plat->stmmac_rst);
4301 /* Init MAC and get the capabilities */
4302 ret = stmmac_hw_init(priv);
4306 /* Configure real RX and TX queues */
4307 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4308 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4310 ndev->netdev_ops = &stmmac_netdev_ops;
4312 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4315 ret = stmmac_tc_init(priv, priv);
4317 ndev->hw_features |= NETIF_F_HW_TC;
4320 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4321 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4323 dev_info(priv->device, "TSO feature enabled\n");
4325 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4326 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4327 #ifdef STMMAC_VLAN_TAG_USED
4328 /* Both mac100 and gmac support receive VLAN tag detection */
4329 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4331 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4333 /* MTU range: 46 - hw-specific max */
4334 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4335 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4336 ndev->max_mtu = JUMBO_LEN;
4337 else if (priv->plat->has_xgmac)
4338 ndev->max_mtu = XGMAC_JUMBO_LEN;
4340 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4341 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4342 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4344 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4345 (priv->plat->maxmtu >= ndev->min_mtu))
4346 ndev->max_mtu = priv->plat->maxmtu;
4347 else if (priv->plat->maxmtu < ndev->min_mtu)
4348 dev_warn(priv->device,
4349 "%s: warning: maxmtu having invalid value (%d)\n",
4350 __func__, priv->plat->maxmtu);
4353 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4355 /* Setup channels NAPI */
4356 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4358 for (queue = 0; queue < maxq; queue++) {
4359 struct stmmac_channel *ch = &priv->channel[queue];
4361 ch->priv_data = priv;
4364 if (queue < priv->plat->rx_queues_to_use) {
4365 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4368 if (queue < priv->plat->tx_queues_to_use) {
4369 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4374 mutex_init(&priv->lock);
4376 /* If a specific clk_csr value is passed from the platform
4377 * this means that the CSR Clock Range selection cannot be
4378 * changed at run-time and it is fixed. Viceversa the driver'll try to
4379 * set the MDC clock dynamically according to the csr actual
4382 if (!priv->plat->clk_csr)
4383 stmmac_clk_csr_set(priv);
4385 priv->clk_csr = priv->plat->clk_csr;
4387 stmmac_check_pcs_mode(priv);
4389 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4390 priv->hw->pcs != STMMAC_PCS_TBI &&
4391 priv->hw->pcs != STMMAC_PCS_RTBI) {
4392 /* MDIO bus Registration */
4393 ret = stmmac_mdio_register(ndev);
4395 dev_err(priv->device,
4396 "%s: MDIO bus (id: %d) registration failed",
4397 __func__, priv->plat->bus_id);
4398 goto error_mdio_register;
4402 ret = register_netdev(ndev);
4404 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4406 goto error_netdev_register;
4409 #ifdef CONFIG_DEBUG_FS
4410 ret = stmmac_init_fs(ndev);
4412 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4418 error_netdev_register:
4419 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4420 priv->hw->pcs != STMMAC_PCS_TBI &&
4421 priv->hw->pcs != STMMAC_PCS_RTBI)
4422 stmmac_mdio_unregister(ndev);
4423 error_mdio_register:
4424 for (queue = 0; queue < maxq; queue++) {
4425 struct stmmac_channel *ch = &priv->channel[queue];
4427 if (queue < priv->plat->rx_queues_to_use)
4428 netif_napi_del(&ch->rx_napi);
4429 if (queue < priv->plat->tx_queues_to_use)
4430 netif_napi_del(&ch->tx_napi);
4433 destroy_workqueue(priv->wq);
4439 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4443 * @dev: device pointer
4444 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4445 * changes the link status, releases the DMA descriptor rings.
4447 int stmmac_dvr_remove(struct device *dev)
4449 struct net_device *ndev = dev_get_drvdata(dev);
4450 struct stmmac_priv *priv = netdev_priv(ndev);
4452 netdev_info(priv->dev, "%s: removing driver", __func__);
4454 #ifdef CONFIG_DEBUG_FS
4455 stmmac_exit_fs(ndev);
4457 stmmac_stop_all_dma(priv);
4459 stmmac_mac_set(priv, priv->ioaddr, false);
4460 netif_carrier_off(ndev);
4461 unregister_netdev(ndev);
4462 if (priv->plat->stmmac_rst)
4463 reset_control_assert(priv->plat->stmmac_rst);
4464 clk_disable_unprepare(priv->plat->pclk);
4465 clk_disable_unprepare(priv->plat->stmmac_clk);
4466 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4467 priv->hw->pcs != STMMAC_PCS_TBI &&
4468 priv->hw->pcs != STMMAC_PCS_RTBI)
4469 stmmac_mdio_unregister(ndev);
4470 destroy_workqueue(priv->wq);
4471 mutex_destroy(&priv->lock);
4476 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4479 * stmmac_suspend - suspend callback
4480 * @dev: device pointer
4481 * Description: this is the function to suspend the device and it is called
4482 * by the platform driver to stop the network queue, release the resources,
4483 * program the PMT register (for WoL), clean and release driver resources.
4485 int stmmac_suspend(struct device *dev)
4487 struct net_device *ndev = dev_get_drvdata(dev);
4488 struct stmmac_priv *priv = netdev_priv(ndev);
4490 if (!ndev || !netif_running(ndev))
4494 phy_stop(ndev->phydev);
4496 mutex_lock(&priv->lock);
4498 netif_device_detach(ndev);
4499 stmmac_stop_all_queues(priv);
4501 stmmac_disable_all_queues(priv);
4503 /* Stop TX/RX DMA */
4504 stmmac_stop_all_dma(priv);
4506 /* Enable Power down mode by programming the PMT regs */
4507 if (device_may_wakeup(priv->device)) {
4508 stmmac_pmt(priv, priv->hw, priv->wolopts);
4511 stmmac_mac_set(priv, priv->ioaddr, false);
4512 pinctrl_pm_select_sleep_state(priv->device);
4513 /* Disable clock in case of PWM is off */
4514 clk_disable(priv->plat->pclk);
4515 clk_disable(priv->plat->stmmac_clk);
4517 mutex_unlock(&priv->lock);
4519 priv->oldlink = false;
4520 priv->speed = SPEED_UNKNOWN;
4521 priv->oldduplex = DUPLEX_UNKNOWN;
4524 EXPORT_SYMBOL_GPL(stmmac_suspend);
4527 * stmmac_reset_queues_param - reset queue parameters
4528 * @dev: device pointer
4530 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4532 u32 rx_cnt = priv->plat->rx_queues_to_use;
4533 u32 tx_cnt = priv->plat->tx_queues_to_use;
4536 for (queue = 0; queue < rx_cnt; queue++) {
4537 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4543 for (queue = 0; queue < tx_cnt; queue++) {
4544 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4553 * stmmac_resume - resume callback
4554 * @dev: device pointer
4555 * Description: when resume this function is invoked to setup the DMA and CORE
4556 * in a usable state.
4558 int stmmac_resume(struct device *dev)
4560 struct net_device *ndev = dev_get_drvdata(dev);
4561 struct stmmac_priv *priv = netdev_priv(ndev);
4563 if (!netif_running(ndev))
4566 /* Power Down bit, into the PM register, is cleared
4567 * automatically as soon as a magic packet or a Wake-up frame
4568 * is received. Anyway, it's better to manually clear
4569 * this bit because it can generate problems while resuming
4570 * from another devices (e.g. serial console).
4572 if (device_may_wakeup(priv->device)) {
4573 mutex_lock(&priv->lock);
4574 stmmac_pmt(priv, priv->hw, 0);
4575 mutex_unlock(&priv->lock);
4578 pinctrl_pm_select_default_state(priv->device);
4579 /* enable the clk previously disabled */
4580 clk_enable(priv->plat->stmmac_clk);
4581 clk_enable(priv->plat->pclk);
4582 /* reset the phy so that it's ready */
4584 stmmac_mdio_reset(priv->mii);
4587 netif_device_attach(ndev);
4589 mutex_lock(&priv->lock);
4591 stmmac_reset_queues_param(priv);
4593 stmmac_clear_descriptors(priv);
4595 stmmac_hw_setup(ndev, false);
4596 stmmac_init_tx_coalesce(priv);
4597 stmmac_set_rx_mode(ndev);
4599 stmmac_enable_all_queues(priv);
4601 stmmac_start_all_queues(priv);
4603 mutex_unlock(&priv->lock);
4606 phy_start(ndev->phydev);
4610 EXPORT_SYMBOL_GPL(stmmac_resume);
4613 static int __init stmmac_cmdline_opt(char *str)
4619 while ((opt = strsep(&str, ",")) != NULL) {
4620 if (!strncmp(opt, "debug:", 6)) {
4621 if (kstrtoint(opt + 6, 0, &debug))
4623 } else if (!strncmp(opt, "phyaddr:", 8)) {
4624 if (kstrtoint(opt + 8, 0, &phyaddr))
4626 } else if (!strncmp(opt, "buf_sz:", 7)) {
4627 if (kstrtoint(opt + 7, 0, &buf_sz))
4629 } else if (!strncmp(opt, "tc:", 3)) {
4630 if (kstrtoint(opt + 3, 0, &tc))
4632 } else if (!strncmp(opt, "watchdog:", 9)) {
4633 if (kstrtoint(opt + 9, 0, &watchdog))
4635 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4636 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4638 } else if (!strncmp(opt, "pause:", 6)) {
4639 if (kstrtoint(opt + 6, 0, &pause))
4641 } else if (!strncmp(opt, "eee_timer:", 10)) {
4642 if (kstrtoint(opt + 10, 0, &eee_timer))
4644 } else if (!strncmp(opt, "chain_mode:", 11)) {
4645 if (kstrtoint(opt + 11, 0, &chain_mode))
4652 pr_err("%s: ERROR broken module parameter conversion", __func__);
4656 __setup("stmmaceth=", stmmac_cmdline_opt);
4659 static int __init stmmac_init(void)
4661 #ifdef CONFIG_DEBUG_FS
4662 /* Create debugfs main directory if it doesn't exist yet */
4663 if (!stmmac_fs_dir) {
4664 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4666 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4667 pr_err("ERROR %s, debugfs create directory failed\n",
4668 STMMAC_RESOURCE_NAME);
4678 static void __exit stmmac_exit(void)
4680 #ifdef CONFIG_DEBUG_FS
4681 debugfs_remove_recursive(stmmac_fs_dir);
4685 module_init(stmmac_init)
4686 module_exit(stmmac_exit)
4688 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4689 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4690 MODULE_LICENSE("GPL");