drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <net/pkt_cls.h>
  40 #include "stmmac_ptp.h"
  41 #include "stmmac.h"
  42 #include <linux/reset.h>
  43 #include <linux/of_mdio.h>
  44 #include "dwmac1000.h"
  45 #include "dwxgmac2.h"
  46 #include "hwif.h"
  47
  48 #define STMMAC_ALIGN(x)         __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
  49 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  50
  51 /* Module parameters */
  52 #define TX_TIMEO        5000
  53 static int watchdog = TX_TIMEO;
  54 module_param(watchdog, int, 0644);
  55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  56
  57 static int debug = -1;
  58 module_param(debug, int, 0644);
  59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  60
  61 static int phyaddr = -1;
  62 module_param(phyaddr, int, 0444);
  63 MODULE_PARM_DESC(phyaddr, "Physical device address");
  64
  65 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  66 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  67
  68 static int flow_ctrl = FLOW_AUTO;
  69 module_param(flow_ctrl, int, 0644);
  70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  71
  72 static int pause = PAUSE_TIME;
  73 module_param(pause, int, 0644);
  74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  75
  76 #define TC_DEFAULT 64
  77 static int tc = TC_DEFAULT;
  78 module_param(tc, int, 0644);
  79 MODULE_PARM_DESC(tc, "DMA threshold control value");
  80
  81 #define DEFAULT_BUFSIZE 1536
  82 static int buf_sz = DEFAULT_BUFSIZE;
  83 module_param(buf_sz, int, 0644);
  84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  85
  86 #define STMMAC_RX_COPYBREAK     256
  87
  88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  89                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  90                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  91
  92 #define STMMAC_DEFAULT_LPI_TIMER        1000
  93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  94 module_param(eee_timer, int, 0644);
  95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  97
  98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
  99  * but allow user to force to use the chain instead of the ring
 100  */
 101 static unsigned int chain_mode;
 102 module_param(chain_mode, int, 0444);
 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 104
 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 106
 107 #ifdef CONFIG_DEBUG_FS
 108 static int stmmac_init_fs(struct net_device *dev);
 109 static void stmmac_exit_fs(struct net_device *dev);
 110 #endif
 111
 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 113
 114 /**
 115  * stmmac_verify_args - verify the driver parameters.
 116  * Description: it checks the driver parameters and set a default in case of
 117  * errors.
 118  */
 119 static void stmmac_verify_args(void)
 120 {
 121         if (unlikely(watchdog < 0))
 122                 watchdog = TX_TIMEO;
 123         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 124                 buf_sz = DEFAULT_BUFSIZE;
 125         if (unlikely(flow_ctrl > 1))
 126                 flow_ctrl = FLOW_AUTO;
 127         else if (likely(flow_ctrl < 0))
 128                 flow_ctrl = FLOW_OFF;
 129         if (unlikely((pause < 0) || (pause > 0xffff)))
 130                 pause = PAUSE_TIME;
 131         if (eee_timer < 0)
 132                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 133 }
 134
 135 /**
 136  * stmmac_disable_all_queues - Disable all queues
 137  * @priv: driver private structure
 138  */
 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 140 {
 141         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 142         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 143         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 144         u32 queue;
 145
 146         for (queue = 0; queue < maxq; queue++) {
 147                 struct stmmac_channel *ch = &priv->channel[queue];
 148
 149                 if (queue < rx_queues_cnt)
 150                         napi_disable(&ch->rx_napi);
 151                 if (queue < tx_queues_cnt)
 152                         napi_disable(&ch->tx_napi);
 153         }
 154 }
 155
 156 /**
 157  * stmmac_enable_all_queues - Enable all queues
 158  * @priv: driver private structure
 159  */
 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 161 {
 162         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 163         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 164         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 165         u32 queue;
 166
 167         for (queue = 0; queue < maxq; queue++) {
 168                 struct stmmac_channel *ch = &priv->channel[queue];
 169
 170                 if (queue < rx_queues_cnt)
 171                         napi_enable(&ch->rx_napi);
 172                 if (queue < tx_queues_cnt)
 173                         napi_enable(&ch->tx_napi);
 174         }
 175 }
 176
 177 /**
 178  * stmmac_stop_all_queues - Stop all queues
 179  * @priv: driver private structure
 180  */
 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 182 {
 183         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 184         u32 queue;
 185
 186         for (queue = 0; queue < tx_queues_cnt; queue++)
 187                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 188 }
 189
 190 /**
 191  * stmmac_start_all_queues - Start all queues
 192  * @priv: driver private structure
 193  */
 194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 195 {
 196         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 197         u32 queue;
 198
 199         for (queue = 0; queue < tx_queues_cnt; queue++)
 200                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 201 }
 202
 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 204 {
 205         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 206             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 207                 queue_work(priv->wq, &priv->service_task);
 208 }
 209
 210 static void stmmac_global_err(struct stmmac_priv *priv)
 211 {
 212         netif_carrier_off(priv->dev);
 213         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 214         stmmac_service_event_schedule(priv);
 215 }
 216
 217 /**
 218  * stmmac_clk_csr_set - dynamically set the MDC clock
 219  * @priv: driver private structure
 220  * Description: this is to dynamically set the MDC clock according to the csr
 221  * clock input.
 222  * Note:
 223  *      If a specific clk_csr value is passed from the platform
 224  *      this means that the CSR Clock Range selection cannot be
 225  *      changed at run-time and it is fixed (as reported in the driver
 226  *      documentation). Viceversa the driver will try to set the MDC
 227  *      clock dynamically according to the actual clock input.
 228  */
 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 230 {
 231         u32 clk_rate;
 232
 233         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 234
 235         /* Platform provided default clk_csr would be assumed valid
 236          * for all other cases except for the below mentioned ones.
 237          * For values higher than the IEEE 802.3 specified frequency
 238          * we can not estimate the proper divider as it is not known
 239          * the frequency of clk_csr_i. So we do not change the default
 240          * divider.
 241          */
 242         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 243                 if (clk_rate < CSR_F_35M)
 244                         priv->clk_csr = STMMAC_CSR_20_35M;
 245                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 246                         priv->clk_csr = STMMAC_CSR_35_60M;
 247                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 248                         priv->clk_csr = STMMAC_CSR_60_100M;
 249                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 250                         priv->clk_csr = STMMAC_CSR_100_150M;
 251                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 252                         priv->clk_csr = STMMAC_CSR_150_250M;
 253                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 254                         priv->clk_csr = STMMAC_CSR_250_300M;
 255         }
 256
 257         if (priv->plat->has_sun8i) {
 258                 if (clk_rate > 160000000)
 259                         priv->clk_csr = 0x03;
 260                 else if (clk_rate > 80000000)
 261                         priv->clk_csr = 0x02;
 262                 else if (clk_rate > 40000000)
 263                         priv->clk_csr = 0x01;
 264                 else
 265                         priv->clk_csr = 0;
 266         }
 267
 268         if (priv->plat->has_xgmac) {
 269                 if (clk_rate > 400000000)
 270                         priv->clk_csr = 0x5;
 271                 else if (clk_rate > 350000000)
 272                         priv->clk_csr = 0x4;
 273                 else if (clk_rate > 300000000)
 274                         priv->clk_csr = 0x3;
 275                 else if (clk_rate > 250000000)
 276                         priv->clk_csr = 0x2;
 277                 else if (clk_rate > 150000000)
 278                         priv->clk_csr = 0x1;
 279                 else
 280                         priv->clk_csr = 0x0;
 281         }
 282 }
 283
 284 static void print_pkt(unsigned char *buf, int len)
 285 {
 286         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 287         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 288 }
 289
 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 291 {
 292         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 293         u32 avail;
 294
 295         if (tx_q->dirty_tx > tx_q->cur_tx)
 296                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 297         else
 298                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 299
 300         return avail;
 301 }
 302
 303 /**
 304  * stmmac_rx_dirty - Get RX queue dirty
 305  * @priv: driver private structure
 306  * @queue: RX queue index
 307  */
 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 309 {
 310         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 311         u32 dirty;
 312
 313         if (rx_q->dirty_rx <= rx_q->cur_rx)
 314                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 315         else
 316                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 317
 318         return dirty;
 319 }
 320
 321 /**
 322  * stmmac_enable_eee_mode - check and enter in LPI mode
 323  * @priv: driver private structure
 324  * Description: this function is to verify and enter in LPI mode in case of
 325  * EEE.
 326  */
 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 328 {
 329         u32 tx_cnt = priv->plat->tx_queues_to_use;
 330         u32 queue;
 331
 332         /* check if all TX queues have the work finished */
 333         for (queue = 0; queue < tx_cnt; queue++) {
 334                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 335
 336                 if (tx_q->dirty_tx != tx_q->cur_tx)
 337                         return; /* still unfinished work */
 338         }
 339
 340         /* Check and enter in LPI mode */
 341         if (!priv->tx_path_in_lpi_mode)
 342                 stmmac_set_eee_mode(priv, priv->hw,
 343                                 priv->plat->en_tx_lpi_clockgating);
 344 }
 345
 346 /**
 347  * stmmac_disable_eee_mode - disable and exit from LPI mode
 348  * @priv: driver private structure
 349  * Description: this function is to exit and disable EEE in case of
 350  * LPI state is true. This is called by the xmit.
 351  */
 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 353 {
 354         stmmac_reset_eee_mode(priv, priv->hw);
 355         del_timer_sync(&priv->eee_ctrl_timer);
 356         priv->tx_path_in_lpi_mode = false;
 357 }
 358
 359 /**
 360  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 361  * @arg : data hook
 362  * Description:
 363  *  if there is no data transfer and if we are not in LPI state,
 364  *  then MAC Transmitter can be moved to LPI state.
 365  */
 366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 367 {
 368         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 369
 370         stmmac_enable_eee_mode(priv);
 371         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 372 }
 373
 374 /**
 375  * stmmac_eee_init - init EEE
 376  * @priv: driver private structure
 377  * Description:
 378  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 379  *  can also manage EEE, this function enable the LPI state and start related
 380  *  timer.
 381  */
 382 bool stmmac_eee_init(struct stmmac_priv *priv)
 383 {
 384         int tx_lpi_timer = priv->tx_lpi_timer;
 385
 386         /* Using PCS we cannot dial with the phy registers at this stage
 387          * so we do not support extra feature like EEE.
 388          */
 389         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 390             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 391             (priv->hw->pcs == STMMAC_PCS_RTBI))
 392                 return false;
 393
 394         /* Check if MAC core supports the EEE feature. */
 395         if (!priv->dma_cap.eee)
 396                 return false;
 397
 398         mutex_lock(&priv->lock);
 399
 400         /* Check if it needs to be deactivated */
 401         if (!priv->eee_active && priv->eee_enabled) {
 402                 netdev_dbg(priv->dev, "disable EEE\n");
 403                 del_timer_sync(&priv->eee_ctrl_timer);
 404                 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 405                 mutex_unlock(&priv->lock);
 406                 return false;
 407         }
 408
 409         if (priv->eee_active && !priv->eee_enabled) {
 410                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 411                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 412                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 413                                      tx_lpi_timer);
 414         }
 415
 416         mutex_unlock(&priv->lock);
 417         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 418         return true;
 419 }
 420
 421 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 422  * @priv: driver private structure
 423  * @p : descriptor pointer
 424  * @skb : the socket buffer
 425  * Description :
 426  * This function will read timestamp from the descriptor & pass it to stack.
 427  * and also perform some sanity checks.
 428  */
 429 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 430                                    struct dma_desc *p, struct sk_buff *skb)
 431 {
 432         struct skb_shared_hwtstamps shhwtstamp;
 433         u64 ns = 0;
 434
 435         if (!priv->hwts_tx_en)
 436                 return;
 437
 438         /* exit if skb doesn't support hw tstamp */
 439         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 440                 return;
 441
 442         /* check tx tstamp status */
 443         if (stmmac_get_tx_timestamp_status(priv, p)) {
 444                 /* get the valid tstamp */
 445                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 446
 447                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 448                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 449
 450                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 451                 /* pass tstamp to stack */
 452                 skb_tstamp_tx(skb, &shhwtstamp);
 453         }
 454
 455         return;
 456 }
 457
 458 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 459  * @priv: driver private structure
 460  * @p : descriptor pointer
 461  * @np : next descriptor pointer
 462  * @skb : the socket buffer
 463  * Description :
 464  * This function will read received packet's timestamp from the descriptor
 465  * and pass it to stack. It also perform some sanity checks.
 466  */
 467 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 468                                    struct dma_desc *np, struct sk_buff *skb)
 469 {
 470         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 471         struct dma_desc *desc = p;
 472         u64 ns = 0;
 473
 474         if (!priv->hwts_rx_en)
 475                 return;
 476         /* For GMAC4, the valid timestamp is from CTX next desc. */
 477         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 478                 desc = np;
 479
 480         /* Check if timestamp is available */
 481         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 482                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 483                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 484                 shhwtstamp = skb_hwtstamps(skb);
 485                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 486                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 487         } else  {
 488                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 489         }
 490 }
 491
 492 /**
 493  *  stmmac_hwtstamp_set - control hardware timestamping.
 494  *  @dev: device pointer.
 495  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 496  *  a proprietary structure used to pass information to the driver.
 497  *  Description:
 498  *  This function configures the MAC to enable/disable both outgoing(TX)
 499  *  and incoming(RX) packets time stamping based on user input.
 500  *  Return Value:
 501  *  0 on success and an appropriate -ve integer on failure.
 502  */
 503 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 504 {
 505         struct stmmac_priv *priv = netdev_priv(dev);
 506         struct hwtstamp_config config;
 507         struct timespec64 now;
 508         u64 temp = 0;
 509         u32 ptp_v2 = 0;
 510         u32 tstamp_all = 0;
 511         u32 ptp_over_ipv4_udp = 0;
 512         u32 ptp_over_ipv6_udp = 0;
 513         u32 ptp_over_ethernet = 0;
 514         u32 snap_type_sel = 0;
 515         u32 ts_master_en = 0;
 516         u32 ts_event_en = 0;
 517         u32 sec_inc = 0;
 518         u32 value = 0;
 519         bool xmac;
 520
 521         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 522
 523         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 524                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 525                 priv->hwts_tx_en = 0;
 526                 priv->hwts_rx_en = 0;
 527
 528                 return -EOPNOTSUPP;
 529         }
 530
 531         if (copy_from_user(&config, ifr->ifr_data,
 532                            sizeof(config)))
 533                 return -EFAULT;
 534
 535         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 536                    __func__, config.flags, config.tx_type, config.rx_filter);
 537
 538         /* reserved for future extensions */
 539         if (config.flags)
 540                 return -EINVAL;
 541
 542         if (config.tx_type != HWTSTAMP_TX_OFF &&
 543             config.tx_type != HWTSTAMP_TX_ON)
 544                 return -ERANGE;
 545
 546         if (priv->adv_ts) {
 547                 switch (config.rx_filter) {
 548                 case HWTSTAMP_FILTER_NONE:
 549                         /* time stamp no incoming packet at all */
 550                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 551                         break;
 552
 553                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 554                         /* PTP v1, UDP, any kind of event packet */
 555                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 556                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 557                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 558                          * This leaves Delay_Req timestamps out.
 559                          * Enable all events *and* general purpose message
 560                          * timestamping
 561                          */
 562                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 563                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 564                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 565                         break;
 566
 567                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 568                         /* PTP v1, UDP, Sync packet */
 569                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 570                         /* take time stamp for SYNC messages only */
 571                         ts_event_en = PTP_TCR_TSEVNTENA;
 572
 573                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 574                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 575                         break;
 576
 577                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 578                         /* PTP v1, UDP, Delay_req packet */
 579                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 580                         /* take time stamp for Delay_Req messages only */
 581                         ts_master_en = PTP_TCR_TSMSTRENA;
 582                         ts_event_en = PTP_TCR_TSEVNTENA;
 583
 584                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 585                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 586                         break;
 587
 588                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 589                         /* PTP v2, UDP, any kind of event packet */
 590                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 591                         ptp_v2 = PTP_TCR_TSVER2ENA;
 592                         /* take time stamp for all event messages */
 593                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 594
 595                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 596                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 597                         break;
 598
 599                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 600                         /* PTP v2, UDP, Sync packet */
 601                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 602                         ptp_v2 = PTP_TCR_TSVER2ENA;
 603                         /* take time stamp for SYNC messages only */
 604                         ts_event_en = PTP_TCR_TSEVNTENA;
 605
 606                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 607                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 608                         break;
 609
 610                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 611                         /* PTP v2, UDP, Delay_req packet */
 612                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 613                         ptp_v2 = PTP_TCR_TSVER2ENA;
 614                         /* take time stamp for Delay_Req messages only */
 615                         ts_master_en = PTP_TCR_TSMSTRENA;
 616                         ts_event_en = PTP_TCR_TSEVNTENA;
 617
 618                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 619                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 620                         break;
 621
 622                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 623                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 624                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 625                         ptp_v2 = PTP_TCR_TSVER2ENA;
 626                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 627                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 628                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 629                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 630                         break;
 631
 632                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 633                         /* PTP v2/802.AS1, any layer, Sync packet */
 634                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 635                         ptp_v2 = PTP_TCR_TSVER2ENA;
 636                         /* take time stamp for SYNC messages only */
 637                         ts_event_en = PTP_TCR_TSEVNTENA;
 638
 639                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 640                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 641                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 642                         break;
 643
 644                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 645                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 646                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 647                         ptp_v2 = PTP_TCR_TSVER2ENA;
 648                         /* take time stamp for Delay_Req messages only */
 649                         ts_master_en = PTP_TCR_TSMSTRENA;
 650                         ts_event_en = PTP_TCR_TSEVNTENA;
 651
 652                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 653                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 654                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 655                         break;
 656
 657                 case HWTSTAMP_FILTER_NTP_ALL:
 658                 case HWTSTAMP_FILTER_ALL:
 659                         /* time stamp any incoming packet */
 660                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 661                         tstamp_all = PTP_TCR_TSENALL;
 662                         break;
 663
 664                 default:
 665                         return -ERANGE;
 666                 }
 667         } else {
 668                 switch (config.rx_filter) {
 669                 case HWTSTAMP_FILTER_NONE:
 670                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 671                         break;
 672                 default:
 673                         /* PTP v1, UDP, any kind of event packet */
 674                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 675                         break;
 676                 }
 677         }
 678         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 679         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 680
 681         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 682                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 683         else {
 684                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 685                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 686                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 687                          ts_master_en | snap_type_sel);
 688                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 689
 690                 /* program Sub Second Increment reg */
 691                 stmmac_config_sub_second_increment(priv,
 692                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 693                                 xmac, &sec_inc);
 694                 temp = div_u64(1000000000ULL, sec_inc);
 695
 696                 /* Store sub second increment and flags for later use */
 697                 priv->sub_second_inc = sec_inc;
 698                 priv->systime_flags = value;
 699
 700                 /* calculate default added value:
 701                  * formula is :
 702                  * addend = (2^32)/freq_div_ratio;
 703                  * where, freq_div_ratio = 1e9ns/sec_inc
 704                  */
 705                 temp = (u64)(temp << 32);
 706                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 707                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 708
 709                 /* initialize system time */
 710                 ktime_get_real_ts64(&now);
 711
 712                 /* lower 32 bits of tv_sec are safe until y2106 */
 713                 stmmac_init_systime(priv, priv->ptpaddr,
 714                                 (u32)now.tv_sec, now.tv_nsec);
 715         }
 716
 717         memcpy(&priv->tstamp_config, &config, sizeof(config));
 718
 719         return copy_to_user(ifr->ifr_data, &config,
 720                             sizeof(config)) ? -EFAULT : 0;
 721 }
 722
 723 /**
 724  *  stmmac_hwtstamp_get - read hardware timestamping.
 725  *  @dev: device pointer.
 726  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 727  *  a proprietary structure used to pass information to the driver.
 728  *  Description:
 729  *  This function obtain the current hardware timestamping settings
 730     as requested.
 731  */
 732 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 733 {
 734         struct stmmac_priv *priv = netdev_priv(dev);
 735         struct hwtstamp_config *config = &priv->tstamp_config;
 736
 737         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 738                 return -EOPNOTSUPP;
 739
 740         return copy_to_user(ifr->ifr_data, config,
 741                             sizeof(*config)) ? -EFAULT : 0;
 742 }
 743
 744 /**
 745  * stmmac_init_ptp - init PTP
 746  * @priv: driver private structure
 747  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 748  * This is done by looking at the HW cap. register.
 749  * This function also registers the ptp driver.
 750  */
 751 static int stmmac_init_ptp(struct stmmac_priv *priv)
 752 {
 753         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 754
 755         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 756                 return -EOPNOTSUPP;
 757
 758         priv->adv_ts = 0;
 759         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 760         if (xmac && priv->dma_cap.atime_stamp)
 761                 priv->adv_ts = 1;
 762         /* Dwmac 3.x core with extend_desc can support adv_ts */
 763         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 764                 priv->adv_ts = 1;
 765
 766         if (priv->dma_cap.time_stamp)
 767                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 768
 769         if (priv->adv_ts)
 770                 netdev_info(priv->dev,
 771                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 772
 773         priv->hwts_tx_en = 0;
 774         priv->hwts_rx_en = 0;
 775
 776         stmmac_ptp_register(priv);
 777
 778         return 0;
 779 }
 780
 781 static void stmmac_release_ptp(struct stmmac_priv *priv)
 782 {
 783         if (priv->plat->clk_ptp_ref)
 784                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 785         stmmac_ptp_unregister(priv);
 786 }
 787
 788 /**
 789  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 790  *  @priv: driver private structure
 791  *  Description: It is used for configuring the flow control in all queues
 792  */
 793 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 794 {
 795         u32 tx_cnt = priv->plat->tx_queues_to_use;
 796
 797         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 798                         priv->pause, tx_cnt);
 799 }
 800
 801 static void stmmac_validate(struct phylink_config *config,
 802                             unsigned long *supported,
 803                             struct phylink_link_state *state)
 804 {
 805         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 806         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 807         int tx_cnt = priv->plat->tx_queues_to_use;
 808         int max_speed = priv->plat->max_speed;
 809
 810         /* Cut down 1G if asked to */
 811         if ((max_speed > 0) && (max_speed < 1000)) {
 812                 phylink_set(mask, 1000baseT_Full);
 813                 phylink_set(mask, 1000baseX_Full);
 814         }
 815
 816         /* Half-Duplex can only work with single queue */
 817         if (tx_cnt > 1) {
 818                 phylink_set(mask, 10baseT_Half);
 819                 phylink_set(mask, 100baseT_Half);
 820                 phylink_set(mask, 1000baseT_Half);
 821         }
 822
 823         bitmap_andnot(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 824         bitmap_andnot(state->advertising, state->advertising, mask,
 825                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 826 }
 827
 828 static int stmmac_mac_link_state(struct phylink_config *config,
 829                                  struct phylink_link_state *state)
 830 {
 831         return -EOPNOTSUPP;
 832 }
 833
 834 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 835                               const struct phylink_link_state *state)
 836 {
 837         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 838         u32 ctrl;
 839
 840         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 841         ctrl &= ~priv->hw->link.speed_mask;
 842
 843         switch (state->speed) {
 844         case SPEED_1000:
 845                 ctrl |= priv->hw->link.speed1000;
 846                 break;
 847         case SPEED_100:
 848                 ctrl |= priv->hw->link.speed100;
 849                 break;
 850         case SPEED_10:
 851                 ctrl |= priv->hw->link.speed10;
 852                 break;
 853         default:
 854                 return;
 855         }
 856
 857         priv->speed = state->speed;
 858
 859         if (priv->plat->fix_mac_speed)
 860                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
 861
 862         if (!state->duplex)
 863                 ctrl &= ~priv->hw->link.duplex;
 864         else
 865                 ctrl |= priv->hw->link.duplex;
 866
 867         /* Flow Control operation */
 868         if (state->pause)
 869                 stmmac_mac_flow_ctrl(priv, state->duplex);
 870
 871         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 872 }
 873
 874 static void stmmac_mac_an_restart(struct phylink_config *config)
 875 {
 876         /* Not Supported */
 877 }
 878
 879 static void stmmac_mac_link_down(struct phylink_config *config,
 880                                  unsigned int mode, phy_interface_t interface)
 881 {
 882         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 883
 884         stmmac_mac_set(priv, priv->ioaddr, false);
 885         priv->eee_active = false;
 886         stmmac_eee_init(priv);
 887         stmmac_set_eee_pls(priv, priv->hw, false);
 888 }
 889
 890 static void stmmac_mac_link_up(struct phylink_config *config,
 891                                unsigned int mode, phy_interface_t interface,
 892                                struct phy_device *phy)
 893 {
 894         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 895
 896         stmmac_mac_set(priv, priv->ioaddr, true);
 897         if (phy) {
 898                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
 899                 priv->eee_enabled = stmmac_eee_init(priv);
 900                 stmmac_set_eee_pls(priv, priv->hw, true);
 901         }
 902 }
 903
 904 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
 905         .validate = stmmac_validate,
 906         .mac_link_state = stmmac_mac_link_state,
 907         .mac_config = stmmac_mac_config,
 908         .mac_an_restart = stmmac_mac_an_restart,
 909         .mac_link_down = stmmac_mac_link_down,
 910         .mac_link_up = stmmac_mac_link_up,
 911 };
 912
 913 /**
 914  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 915  * @priv: driver private structure
 916  * Description: this is to verify if the HW supports the PCS.
 917  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 918  * configured for the TBI, RTBI, or SGMII PHY interface.
 919  */
 920 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 921 {
 922         int interface = priv->plat->interface;
 923
 924         if (priv->dma_cap.pcs) {
 925                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 926                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 927                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 928                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 929                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 930                         priv->hw->pcs = STMMAC_PCS_RGMII;
 931                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 932                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 933                         priv->hw->pcs = STMMAC_PCS_SGMII;
 934                 }
 935         }
 936 }
 937
 938 /**
 939  * stmmac_init_phy - PHY initialization
 940  * @dev: net device structure
 941  * Description: it initializes the driver's PHY state, and attaches the PHY
 942  * to the mac driver.
 943  *  Return value:
 944  *  0 on success
 945  */
 946 static int stmmac_init_phy(struct net_device *dev)
 947 {
 948         struct stmmac_priv *priv = netdev_priv(dev);
 949         struct device_node *node;
 950         int ret;
 951
 952         node = priv->plat->phylink_node;
 953
 954         if (node) {
 955                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
 956         } else {
 957                 int addr = priv->plat->phy_addr;
 958                 struct phy_device *phydev;
 959
 960                 phydev = mdiobus_get_phy(priv->mii, addr);
 961                 if (!phydev) {
 962                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
 963                         return -ENODEV;
 964                 }
 965
 966                 ret = phylink_connect_phy(priv->phylink, phydev);
 967         }
 968
 969         return ret;
 970 }
 971
 972 static int stmmac_phy_setup(struct stmmac_priv *priv)
 973 {
 974         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
 975         int mode = priv->plat->interface;
 976         struct phylink *phylink;
 977
 978         priv->phylink_config.dev = &priv->dev->dev;
 979         priv->phylink_config.type = PHYLINK_NETDEV;
 980
 981         phylink = phylink_create(&priv->phylink_config, fwnode,
 982                                  mode, &stmmac_phylink_mac_ops);
 983         if (IS_ERR(phylink))
 984                 return PTR_ERR(phylink);
 985
 986         priv->phylink = phylink;
 987         return 0;
 988 }
 989
 990 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
 991 {
 992         u32 rx_cnt = priv->plat->rx_queues_to_use;
 993         void *head_rx;
 994         u32 queue;
 995
 996         /* Display RX rings */
 997         for (queue = 0; queue < rx_cnt; queue++) {
 998                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 999
1000                 pr_info("\tRX Queue %u rings\n", queue);
1001
1002                 if (priv->extend_desc)
1003                         head_rx = (void *)rx_q->dma_erx;
1004                 else
1005                         head_rx = (void *)rx_q->dma_rx;
1006
1007                 /* Display RX ring */
1008                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1009         }
1010 }
1011
1012 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1013 {
1014         u32 tx_cnt = priv->plat->tx_queues_to_use;
1015         void *head_tx;
1016         u32 queue;
1017
1018         /* Display TX rings */
1019         for (queue = 0; queue < tx_cnt; queue++) {
1020                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1021
1022                 pr_info("\tTX Queue %d rings\n", queue);
1023
1024                 if (priv->extend_desc)
1025                         head_tx = (void *)tx_q->dma_etx;
1026                 else
1027                         head_tx = (void *)tx_q->dma_tx;
1028
1029                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1030         }
1031 }
1032
1033 static void stmmac_display_rings(struct stmmac_priv *priv)
1034 {
1035         /* Display RX ring */
1036         stmmac_display_rx_rings(priv);
1037
1038         /* Display TX ring */
1039         stmmac_display_tx_rings(priv);
1040 }
1041
1042 static int stmmac_set_bfsize(int mtu, int bufsize)
1043 {
1044         int ret = bufsize;
1045
1046         if (mtu >= BUF_SIZE_4KiB)
1047                 ret = BUF_SIZE_8KiB;
1048         else if (mtu >= BUF_SIZE_2KiB)
1049                 ret = BUF_SIZE_4KiB;
1050         else if (mtu > DEFAULT_BUFSIZE)
1051                 ret = BUF_SIZE_2KiB;
1052         else
1053                 ret = DEFAULT_BUFSIZE;
1054
1055         return ret;
1056 }
1057
1058 /**
1059  * stmmac_clear_rx_descriptors - clear RX descriptors
1060  * @priv: driver private structure
1061  * @queue: RX queue index
1062  * Description: this function is called to clear the RX descriptors
1063  * in case of both basic and extended descriptors are used.
1064  */
1065 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1066 {
1067         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1068         int i;
1069
1070         /* Clear the RX descriptors */
1071         for (i = 0; i < DMA_RX_SIZE; i++)
1072                 if (priv->extend_desc)
1073                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1074                                         priv->use_riwt, priv->mode,
1075                                         (i == DMA_RX_SIZE - 1),
1076                                         priv->dma_buf_sz);
1077                 else
1078                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1079                                         priv->use_riwt, priv->mode,
1080                                         (i == DMA_RX_SIZE - 1),
1081                                         priv->dma_buf_sz);
1082 }
1083
1084 /**
1085  * stmmac_clear_tx_descriptors - clear tx descriptors
1086  * @priv: driver private structure
1087  * @queue: TX queue index.
1088  * Description: this function is called to clear the TX descriptors
1089  * in case of both basic and extended descriptors are used.
1090  */
1091 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1092 {
1093         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1094         int i;
1095
1096         /* Clear the TX descriptors */
1097         for (i = 0; i < DMA_TX_SIZE; i++)
1098                 if (priv->extend_desc)
1099                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1100                                         priv->mode, (i == DMA_TX_SIZE - 1));
1101                 else
1102                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1103                                         priv->mode, (i == DMA_TX_SIZE - 1));
1104 }
1105
1106 /**
1107  * stmmac_clear_descriptors - clear descriptors
1108  * @priv: driver private structure
1109  * Description: this function is called to clear the TX and RX descriptors
1110  * in case of both basic and extended descriptors are used.
1111  */
1112 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1113 {
1114         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1115         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1116         u32 queue;
1117
1118         /* Clear the RX descriptors */
1119         for (queue = 0; queue < rx_queue_cnt; queue++)
1120                 stmmac_clear_rx_descriptors(priv, queue);
1121
1122         /* Clear the TX descriptors */
1123         for (queue = 0; queue < tx_queue_cnt; queue++)
1124                 stmmac_clear_tx_descriptors(priv, queue);
1125 }
1126
1127 /**
1128  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1129  * @priv: driver private structure
1130  * @p: descriptor pointer
1131  * @i: descriptor index
1132  * @flags: gfp flag
1133  * @queue: RX queue index
1134  * Description: this function is called to allocate a receive buffer, perform
1135  * the DMA mapping and init the descriptor.
1136  */
1137 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1138                                   int i, gfp_t flags, u32 queue)
1139 {
1140         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1141         struct sk_buff *skb;
1142
1143         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1144         if (!skb) {
1145                 netdev_err(priv->dev,
1146                            "%s: Rx init fails; skb is NULL\n", __func__);
1147                 return -ENOMEM;
1148         }
1149         rx_q->rx_skbuff[i] = skb;
1150         rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1151                                                 priv->dma_buf_sz,
1152                                                 DMA_FROM_DEVICE);
1153         if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1154                 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1155                 dev_kfree_skb_any(skb);
1156                 return -EINVAL;
1157         }
1158
1159         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1160
1161         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1162                 stmmac_init_desc3(priv, p);
1163
1164         return 0;
1165 }
1166
1167 /**
1168  * stmmac_free_rx_buffer - free RX dma buffers
1169  * @priv: private structure
1170  * @queue: RX queue index
1171  * @i: buffer index.
1172  */
1173 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1174 {
1175         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1176
1177         if (rx_q->rx_skbuff[i]) {
1178                 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1179                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1180                 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1181         }
1182         rx_q->rx_skbuff[i] = NULL;
1183 }
1184
1185 /**
1186  * stmmac_free_tx_buffer - free RX dma buffers
1187  * @priv: private structure
1188  * @queue: RX queue index
1189  * @i: buffer index.
1190  */
1191 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1192 {
1193         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1194
1195         if (tx_q->tx_skbuff_dma[i].buf) {
1196                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1197                         dma_unmap_page(priv->device,
1198                                        tx_q->tx_skbuff_dma[i].buf,
1199                                        tx_q->tx_skbuff_dma[i].len,
1200                                        DMA_TO_DEVICE);
1201                 else
1202                         dma_unmap_single(priv->device,
1203                                          tx_q->tx_skbuff_dma[i].buf,
1204                                          tx_q->tx_skbuff_dma[i].len,
1205                                          DMA_TO_DEVICE);
1206         }
1207
1208         if (tx_q->tx_skbuff[i]) {
1209                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1210                 tx_q->tx_skbuff[i] = NULL;
1211                 tx_q->tx_skbuff_dma[i].buf = 0;
1212                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1213         }
1214 }
1215
1216 /**
1217  * init_dma_rx_desc_rings - init the RX descriptor rings
1218  * @dev: net device structure
1219  * @flags: gfp flag.
1220  * Description: this function initializes the DMA RX descriptors
1221  * and allocates the socket buffers. It supports the chained and ring
1222  * modes.
1223  */
1224 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1225 {
1226         struct stmmac_priv *priv = netdev_priv(dev);
1227         u32 rx_count = priv->plat->rx_queues_to_use;
1228         int ret = -ENOMEM;
1229         int bfsize = 0;
1230         int queue;
1231         int i;
1232
1233         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1234         if (bfsize < 0)
1235                 bfsize = 0;
1236
1237         if (bfsize < BUF_SIZE_16KiB)
1238                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1239
1240         priv->dma_buf_sz = bfsize;
1241
1242         /* RX INITIALIZATION */
1243         netif_dbg(priv, probe, priv->dev,
1244                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1245
1246         for (queue = 0; queue < rx_count; queue++) {
1247                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1248
1249                 netif_dbg(priv, probe, priv->dev,
1250                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1251                           (u32)rx_q->dma_rx_phy);
1252
1253                 for (i = 0; i < DMA_RX_SIZE; i++) {
1254                         struct dma_desc *p;
1255
1256                         if (priv->extend_desc)
1257                                 p = &((rx_q->dma_erx + i)->basic);
1258                         else
1259                                 p = rx_q->dma_rx + i;
1260
1261                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1262                                                      queue);
1263                         if (ret)
1264                                 goto err_init_rx_buffers;
1265
1266                         netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1267                                   rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1268                                   (unsigned int)rx_q->rx_skbuff_dma[i]);
1269                 }
1270
1271                 rx_q->cur_rx = 0;
1272                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1273
1274                 stmmac_clear_rx_descriptors(priv, queue);
1275
1276                 /* Setup the chained descriptor addresses */
1277                 if (priv->mode == STMMAC_CHAIN_MODE) {
1278                         if (priv->extend_desc)
1279                                 stmmac_mode_init(priv, rx_q->dma_erx,
1280                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1281                         else
1282                                 stmmac_mode_init(priv, rx_q->dma_rx,
1283                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1284                 }
1285         }
1286
1287         buf_sz = bfsize;
1288
1289         return 0;
1290
1291 err_init_rx_buffers:
1292         while (queue >= 0) {
1293                 while (--i >= 0)
1294                         stmmac_free_rx_buffer(priv, queue, i);
1295
1296                 if (queue == 0)
1297                         break;
1298
1299                 i = DMA_RX_SIZE;
1300                 queue--;
1301         }
1302
1303         return ret;
1304 }
1305
1306 /**
1307  * init_dma_tx_desc_rings - init the TX descriptor rings
1308  * @dev: net device structure.
1309  * Description: this function initializes the DMA TX descriptors
1310  * and allocates the socket buffers. It supports the chained and ring
1311  * modes.
1312  */
1313 static int init_dma_tx_desc_rings(struct net_device *dev)
1314 {
1315         struct stmmac_priv *priv = netdev_priv(dev);
1316         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1317         u32 queue;
1318         int i;
1319
1320         for (queue = 0; queue < tx_queue_cnt; queue++) {
1321                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1322
1323                 netif_dbg(priv, probe, priv->dev,
1324                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1325                          (u32)tx_q->dma_tx_phy);
1326
1327                 /* Setup the chained descriptor addresses */
1328                 if (priv->mode == STMMAC_CHAIN_MODE) {
1329                         if (priv->extend_desc)
1330                                 stmmac_mode_init(priv, tx_q->dma_etx,
1331                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1332                         else
1333                                 stmmac_mode_init(priv, tx_q->dma_tx,
1334                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1335                 }
1336
1337                 for (i = 0; i < DMA_TX_SIZE; i++) {
1338                         struct dma_desc *p;
1339                         if (priv->extend_desc)
1340                                 p = &((tx_q->dma_etx + i)->basic);
1341                         else
1342                                 p = tx_q->dma_tx + i;
1343
1344                         stmmac_clear_desc(priv, p);
1345
1346                         tx_q->tx_skbuff_dma[i].buf = 0;
1347                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1348                         tx_q->tx_skbuff_dma[i].len = 0;
1349                         tx_q->tx_skbuff_dma[i].last_segment = false;
1350                         tx_q->tx_skbuff[i] = NULL;
1351                 }
1352
1353                 tx_q->dirty_tx = 0;
1354                 tx_q->cur_tx = 0;
1355                 tx_q->mss = 0;
1356
1357                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1358         }
1359
1360         return 0;
1361 }
1362
1363 /**
1364  * init_dma_desc_rings - init the RX/TX descriptor rings
1365  * @dev: net device structure
1366  * @flags: gfp flag.
1367  * Description: this function initializes the DMA RX/TX descriptors
1368  * and allocates the socket buffers. It supports the chained and ring
1369  * modes.
1370  */
1371 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1372 {
1373         struct stmmac_priv *priv = netdev_priv(dev);
1374         int ret;
1375
1376         ret = init_dma_rx_desc_rings(dev, flags);
1377         if (ret)
1378                 return ret;
1379
1380         ret = init_dma_tx_desc_rings(dev);
1381
1382         stmmac_clear_descriptors(priv);
1383
1384         if (netif_msg_hw(priv))
1385                 stmmac_display_rings(priv);
1386
1387         return ret;
1388 }
1389
1390 /**
1391  * dma_free_rx_skbufs - free RX dma buffers
1392  * @priv: private structure
1393  * @queue: RX queue index
1394  */
1395 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1396 {
1397         int i;
1398
1399         for (i = 0; i < DMA_RX_SIZE; i++)
1400                 stmmac_free_rx_buffer(priv, queue, i);
1401 }
1402
1403 /**
1404  * dma_free_tx_skbufs - free TX dma buffers
1405  * @priv: private structure
1406  * @queue: TX queue index
1407  */
1408 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1409 {
1410         int i;
1411
1412         for (i = 0; i < DMA_TX_SIZE; i++)
1413                 stmmac_free_tx_buffer(priv, queue, i);
1414 }
1415
1416 /**
1417  * free_dma_rx_desc_resources - free RX dma desc resources
1418  * @priv: private structure
1419  */
1420 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1421 {
1422         u32 rx_count = priv->plat->rx_queues_to_use;
1423         u32 queue;
1424
1425         /* Free RX queue resources */
1426         for (queue = 0; queue < rx_count; queue++) {
1427                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1428
1429                 /* Release the DMA RX socket buffers */
1430                 dma_free_rx_skbufs(priv, queue);
1431
1432                 /* Free DMA regions of consistent memory previously allocated */
1433                 if (!priv->extend_desc)
1434                         dma_free_coherent(priv->device,
1435                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1436                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1437                 else
1438                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1439                                           sizeof(struct dma_extended_desc),
1440                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1441
1442                 kfree(rx_q->rx_skbuff_dma);
1443                 kfree(rx_q->rx_skbuff);
1444         }
1445 }
1446
1447 /**
1448  * free_dma_tx_desc_resources - free TX dma desc resources
1449  * @priv: private structure
1450  */
1451 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1452 {
1453         u32 tx_count = priv->plat->tx_queues_to_use;
1454         u32 queue;
1455
1456         /* Free TX queue resources */
1457         for (queue = 0; queue < tx_count; queue++) {
1458                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1459
1460                 /* Release the DMA TX socket buffers */
1461                 dma_free_tx_skbufs(priv, queue);
1462
1463                 /* Free DMA regions of consistent memory previously allocated */
1464                 if (!priv->extend_desc)
1465                         dma_free_coherent(priv->device,
1466                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1467                                           tx_q->dma_tx, tx_q->dma_tx_phy);
1468                 else
1469                         dma_free_coherent(priv->device, DMA_TX_SIZE *
1470                                           sizeof(struct dma_extended_desc),
1471                                           tx_q->dma_etx, tx_q->dma_tx_phy);
1472
1473                 kfree(tx_q->tx_skbuff_dma);
1474                 kfree(tx_q->tx_skbuff);
1475         }
1476 }
1477
1478 /**
1479  * alloc_dma_rx_desc_resources - alloc RX resources.
1480  * @priv: private structure
1481  * Description: according to which descriptor can be used (extend or basic)
1482  * this function allocates the resources for TX and RX paths. In case of
1483  * reception, for example, it pre-allocated the RX socket buffer in order to
1484  * allow zero-copy mechanism.
1485  */
1486 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1487 {
1488         u32 rx_count = priv->plat->rx_queues_to_use;
1489         int ret = -ENOMEM;
1490         u32 queue;
1491
1492         /* RX queues buffers and DMA */
1493         for (queue = 0; queue < rx_count; queue++) {
1494                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1495
1496                 rx_q->queue_index = queue;
1497                 rx_q->priv_data = priv;
1498
1499                 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1500                                                     sizeof(dma_addr_t),
1501                                                     GFP_KERNEL);
1502                 if (!rx_q->rx_skbuff_dma)
1503                         goto err_dma;
1504
1505                 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1506                                                 sizeof(struct sk_buff *),
1507                                                 GFP_KERNEL);
1508                 if (!rx_q->rx_skbuff)
1509                         goto err_dma;
1510
1511                 if (priv->extend_desc) {
1512                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1513                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1514                                                            &rx_q->dma_rx_phy,
1515                                                            GFP_KERNEL);
1516                         if (!rx_q->dma_erx)
1517                                 goto err_dma;
1518
1519                 } else {
1520                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1521                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1522                                                           &rx_q->dma_rx_phy,
1523                                                           GFP_KERNEL);
1524                         if (!rx_q->dma_rx)
1525                                 goto err_dma;
1526                 }
1527         }
1528
1529         return 0;
1530
1531 err_dma:
1532         free_dma_rx_desc_resources(priv);
1533
1534         return ret;
1535 }
1536
1537 /**
1538  * alloc_dma_tx_desc_resources - alloc TX resources.
1539  * @priv: private structure
1540  * Description: according to which descriptor can be used (extend or basic)
1541  * this function allocates the resources for TX and RX paths. In case of
1542  * reception, for example, it pre-allocated the RX socket buffer in order to
1543  * allow zero-copy mechanism.
1544  */
1545 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1546 {
1547         u32 tx_count = priv->plat->tx_queues_to_use;
1548         int ret = -ENOMEM;
1549         u32 queue;
1550
1551         /* TX queues buffers and DMA */
1552         for (queue = 0; queue < tx_count; queue++) {
1553                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1554
1555                 tx_q->queue_index = queue;
1556                 tx_q->priv_data = priv;
1557
1558                 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1559                                                     sizeof(*tx_q->tx_skbuff_dma),
1560                                                     GFP_KERNEL);
1561                 if (!tx_q->tx_skbuff_dma)
1562                         goto err_dma;
1563
1564                 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1565                                                 sizeof(struct sk_buff *),
1566                                                 GFP_KERNEL);
1567                 if (!tx_q->tx_skbuff)
1568                         goto err_dma;
1569
1570                 if (priv->extend_desc) {
1571                         tx_q->dma_etx = dma_alloc_coherent(priv->device,
1572                                                            DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1573                                                            &tx_q->dma_tx_phy,
1574                                                            GFP_KERNEL);
1575                         if (!tx_q->dma_etx)
1576                                 goto err_dma;
1577                 } else {
1578                         tx_q->dma_tx = dma_alloc_coherent(priv->device,
1579                                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1580                                                           &tx_q->dma_tx_phy,
1581                                                           GFP_KERNEL);
1582                         if (!tx_q->dma_tx)
1583                                 goto err_dma;
1584                 }
1585         }
1586
1587         return 0;
1588
1589 err_dma:
1590         free_dma_tx_desc_resources(priv);
1591
1592         return ret;
1593 }
1594
1595 /**
1596  * alloc_dma_desc_resources - alloc TX/RX resources.
1597  * @priv: private structure
1598  * Description: according to which descriptor can be used (extend or basic)
1599  * this function allocates the resources for TX and RX paths. In case of
1600  * reception, for example, it pre-allocated the RX socket buffer in order to
1601  * allow zero-copy mechanism.
1602  */
1603 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1604 {
1605         /* RX Allocation */
1606         int ret = alloc_dma_rx_desc_resources(priv);
1607
1608         if (ret)
1609                 return ret;
1610
1611         ret = alloc_dma_tx_desc_resources(priv);
1612
1613         return ret;
1614 }
1615
1616 /**
1617  * free_dma_desc_resources - free dma desc resources
1618  * @priv: private structure
1619  */
1620 static void free_dma_desc_resources(struct stmmac_priv *priv)
1621 {
1622         /* Release the DMA RX socket buffers */
1623         free_dma_rx_desc_resources(priv);
1624
1625         /* Release the DMA TX socket buffers */
1626         free_dma_tx_desc_resources(priv);
1627 }
1628
1629 /**
1630  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1631  *  @priv: driver private structure
1632  *  Description: It is used for enabling the rx queues in the MAC
1633  */
1634 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1635 {
1636         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1637         int queue;
1638         u8 mode;
1639
1640         for (queue = 0; queue < rx_queues_count; queue++) {
1641                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1642                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1643         }
1644 }
1645
1646 /**
1647  * stmmac_start_rx_dma - start RX DMA channel
1648  * @priv: driver private structure
1649  * @chan: RX channel index
1650  * Description:
1651  * This starts a RX DMA channel
1652  */
1653 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1654 {
1655         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1656         stmmac_start_rx(priv, priv->ioaddr, chan);
1657 }
1658
1659 /**
1660  * stmmac_start_tx_dma - start TX DMA channel
1661  * @priv: driver private structure
1662  * @chan: TX channel index
1663  * Description:
1664  * This starts a TX DMA channel
1665  */
1666 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1667 {
1668         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1669         stmmac_start_tx(priv, priv->ioaddr, chan);
1670 }
1671
1672 /**
1673  * stmmac_stop_rx_dma - stop RX DMA channel
1674  * @priv: driver private structure
1675  * @chan: RX channel index
1676  * Description:
1677  * This stops a RX DMA channel
1678  */
1679 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1680 {
1681         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1682         stmmac_stop_rx(priv, priv->ioaddr, chan);
1683 }
1684
1685 /**
1686  * stmmac_stop_tx_dma - stop TX DMA channel
1687  * @priv: driver private structure
1688  * @chan: TX channel index
1689  * Description:
1690  * This stops a TX DMA channel
1691  */
1692 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1693 {
1694         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1695         stmmac_stop_tx(priv, priv->ioaddr, chan);
1696 }
1697
1698 /**
1699  * stmmac_start_all_dma - start all RX and TX DMA channels
1700  * @priv: driver private structure
1701  * Description:
1702  * This starts all the RX and TX DMA channels
1703  */
1704 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1705 {
1706         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1707         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1708         u32 chan = 0;
1709
1710         for (chan = 0; chan < rx_channels_count; chan++)
1711                 stmmac_start_rx_dma(priv, chan);
1712
1713         for (chan = 0; chan < tx_channels_count; chan++)
1714                 stmmac_start_tx_dma(priv, chan);
1715 }
1716
1717 /**
1718  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1719  * @priv: driver private structure
1720  * Description:
1721  * This stops the RX and TX DMA channels
1722  */
1723 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1724 {
1725         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1726         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1727         u32 chan = 0;
1728
1729         for (chan = 0; chan < rx_channels_count; chan++)
1730                 stmmac_stop_rx_dma(priv, chan);
1731
1732         for (chan = 0; chan < tx_channels_count; chan++)
1733                 stmmac_stop_tx_dma(priv, chan);
1734 }
1735
1736 /**
1737  *  stmmac_dma_operation_mode - HW DMA operation mode
1738  *  @priv: driver private structure
1739  *  Description: it is used for configuring the DMA operation mode register in
1740  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1741  */
1742 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1743 {
1744         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1745         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1746         int rxfifosz = priv->plat->rx_fifo_size;
1747         int txfifosz = priv->plat->tx_fifo_size;
1748         u32 txmode = 0;
1749         u32 rxmode = 0;
1750         u32 chan = 0;
1751         u8 qmode = 0;
1752
1753         if (rxfifosz == 0)
1754                 rxfifosz = priv->dma_cap.rx_fifo_size;
1755         if (txfifosz == 0)
1756                 txfifosz = priv->dma_cap.tx_fifo_size;
1757
1758         /* Adjust for real per queue fifo size */
1759         rxfifosz /= rx_channels_count;
1760         txfifosz /= tx_channels_count;
1761
1762         if (priv->plat->force_thresh_dma_mode) {
1763                 txmode = tc;
1764                 rxmode = tc;
1765         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1766                 /*
1767                  * In case of GMAC, SF mode can be enabled
1768                  * to perform the TX COE in HW. This depends on:
1769                  * 1) TX COE if actually supported
1770                  * 2) There is no bugged Jumbo frame support
1771                  *    that needs to not insert csum in the TDES.
1772                  */
1773                 txmode = SF_DMA_MODE;
1774                 rxmode = SF_DMA_MODE;
1775                 priv->xstats.threshold = SF_DMA_MODE;
1776         } else {
1777                 txmode = tc;
1778                 rxmode = SF_DMA_MODE;
1779         }
1780
1781         /* configure all channels */
1782         for (chan = 0; chan < rx_channels_count; chan++) {
1783                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1784
1785                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1786                                 rxfifosz, qmode);
1787                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1788                                 chan);
1789         }
1790
1791         for (chan = 0; chan < tx_channels_count; chan++) {
1792                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1793
1794                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1795                                 txfifosz, qmode);
1796         }
1797 }
1798
1799 /**
1800  * stmmac_tx_clean - to manage the transmission completion
1801  * @priv: driver private structure
1802  * @queue: TX queue index
1803  * Description: it reclaims the transmit resources after transmission completes.
1804  */
1805 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1806 {
1807         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1808         unsigned int bytes_compl = 0, pkts_compl = 0;
1809         unsigned int entry, count = 0;
1810
1811         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1812
1813         priv->xstats.tx_clean++;
1814
1815         entry = tx_q->dirty_tx;
1816         while ((entry != tx_q->cur_tx) && (count < budget)) {
1817                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1818                 struct dma_desc *p;
1819                 int status;
1820
1821                 if (priv->extend_desc)
1822                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1823                 else
1824                         p = tx_q->dma_tx + entry;
1825
1826                 status = stmmac_tx_status(priv, &priv->dev->stats,
1827                                 &priv->xstats, p, priv->ioaddr);
1828                 /* Check if the descriptor is owned by the DMA */
1829                 if (unlikely(status & tx_dma_own))
1830                         break;
1831
1832                 count++;
1833
1834                 /* Make sure descriptor fields are read after reading
1835                  * the own bit.
1836                  */
1837                 dma_rmb();
1838
1839                 /* Just consider the last segment and ...*/
1840                 if (likely(!(status & tx_not_ls))) {
1841                         /* ... verify the status error condition */
1842                         if (unlikely(status & tx_err)) {
1843                                 priv->dev->stats.tx_errors++;
1844                         } else {
1845                                 priv->dev->stats.tx_packets++;
1846                                 priv->xstats.tx_pkt_n++;
1847                         }
1848                         stmmac_get_tx_hwtstamp(priv, p, skb);
1849                 }
1850
1851                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1852                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
1853                                 dma_unmap_page(priv->device,
1854                                                tx_q->tx_skbuff_dma[entry].buf,
1855                                                tx_q->tx_skbuff_dma[entry].len,
1856                                                DMA_TO_DEVICE);
1857                         else
1858                                 dma_unmap_single(priv->device,
1859                                                  tx_q->tx_skbuff_dma[entry].buf,
1860                                                  tx_q->tx_skbuff_dma[entry].len,
1861                                                  DMA_TO_DEVICE);
1862                         tx_q->tx_skbuff_dma[entry].buf = 0;
1863                         tx_q->tx_skbuff_dma[entry].len = 0;
1864                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
1865                 }
1866
1867                 stmmac_clean_desc3(priv, tx_q, p);
1868
1869                 tx_q->tx_skbuff_dma[entry].last_segment = false;
1870                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1871
1872                 if (likely(skb != NULL)) {
1873                         pkts_compl++;
1874                         bytes_compl += skb->len;
1875                         dev_consume_skb_any(skb);
1876                         tx_q->tx_skbuff[entry] = NULL;
1877                 }
1878
1879                 stmmac_release_tx_desc(priv, p, priv->mode);
1880
1881                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1882         }
1883         tx_q->dirty_tx = entry;
1884
1885         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1886                                   pkts_compl, bytes_compl);
1887
1888         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1889                                                                 queue))) &&
1890             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1891
1892                 netif_dbg(priv, tx_done, priv->dev,
1893                           "%s: restart transmit\n", __func__);
1894                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1895         }
1896
1897         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1898                 stmmac_enable_eee_mode(priv);
1899                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1900         }
1901
1902         /* We still have pending packets, let's call for a new scheduling */
1903         if (tx_q->dirty_tx != tx_q->cur_tx)
1904                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1905
1906         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1907
1908         return count;
1909 }
1910
1911 /**
1912  * stmmac_tx_err - to manage the tx error
1913  * @priv: driver private structure
1914  * @chan: channel index
1915  * Description: it cleans the descriptors and restarts the transmission
1916  * in case of transmission errors.
1917  */
1918 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1919 {
1920         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1921         int i;
1922
1923         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1924
1925         stmmac_stop_tx_dma(priv, chan);
1926         dma_free_tx_skbufs(priv, chan);
1927         for (i = 0; i < DMA_TX_SIZE; i++)
1928                 if (priv->extend_desc)
1929                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1930                                         priv->mode, (i == DMA_TX_SIZE - 1));
1931                 else
1932                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1933                                         priv->mode, (i == DMA_TX_SIZE - 1));
1934         tx_q->dirty_tx = 0;
1935         tx_q->cur_tx = 0;
1936         tx_q->mss = 0;
1937         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1938         stmmac_start_tx_dma(priv, chan);
1939
1940         priv->dev->stats.tx_errors++;
1941         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1942 }
1943
1944 /**
1945  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1946  *  @priv: driver private structure
1947  *  @txmode: TX operating mode
1948  *  @rxmode: RX operating mode
1949  *  @chan: channel index
1950  *  Description: it is used for configuring of the DMA operation mode in
1951  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1952  *  mode.
1953  */
1954 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1955                                           u32 rxmode, u32 chan)
1956 {
1957         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1958         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1959         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1960         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1961         int rxfifosz = priv->plat->rx_fifo_size;
1962         int txfifosz = priv->plat->tx_fifo_size;
1963
1964         if (rxfifosz == 0)
1965                 rxfifosz = priv->dma_cap.rx_fifo_size;
1966         if (txfifosz == 0)
1967                 txfifosz = priv->dma_cap.tx_fifo_size;
1968
1969         /* Adjust for real per queue fifo size */
1970         rxfifosz /= rx_channels_count;
1971         txfifosz /= tx_channels_count;
1972
1973         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
1974         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
1975 }
1976
1977 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
1978 {
1979         int ret;
1980
1981         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
1982                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
1983         if (ret && (ret != -EINVAL)) {
1984                 stmmac_global_err(priv);
1985                 return true;
1986         }
1987
1988         return false;
1989 }
1990
1991 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
1992 {
1993         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
1994                                                  &priv->xstats, chan);
1995         struct stmmac_channel *ch = &priv->channel[chan];
1996
1997         if (status)
1998                 status |= handle_rx | handle_tx;
1999
2000         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2001                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2002                 napi_schedule_irqoff(&ch->rx_napi);
2003         }
2004
2005         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2006                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2007                 napi_schedule_irqoff(&ch->tx_napi);
2008         }
2009
2010         return status;
2011 }
2012
2013 /**
2014  * stmmac_dma_interrupt - DMA ISR
2015  * @priv: driver private structure
2016  * Description: this is the DMA ISR. It is called by the main ISR.
2017  * It calls the dwmac dma routine and schedule poll method in case of some
2018  * work can be done.
2019  */
2020 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2021 {
2022         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2023         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2024         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2025                                 tx_channel_count : rx_channel_count;
2026         u32 chan;
2027         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2028
2029         /* Make sure we never check beyond our status buffer. */
2030         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2031                 channels_to_check = ARRAY_SIZE(status);
2032
2033         for (chan = 0; chan < channels_to_check; chan++)
2034                 status[chan] = stmmac_napi_check(priv, chan);
2035
2036         for (chan = 0; chan < tx_channel_count; chan++) {
2037                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2038                         /* Try to bump up the dma threshold on this failure */
2039                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2040                             (tc <= 256)) {
2041                                 tc += 64;
2042                                 if (priv->plat->force_thresh_dma_mode)
2043                                         stmmac_set_dma_operation_mode(priv,
2044                                                                       tc,
2045                                                                       tc,
2046                                                                       chan);
2047                                 else
2048                                         stmmac_set_dma_operation_mode(priv,
2049                                                                     tc,
2050                                                                     SF_DMA_MODE,
2051                                                                     chan);
2052                                 priv->xstats.threshold = tc;
2053                         }
2054                 } else if (unlikely(status[chan] == tx_hard_error)) {
2055                         stmmac_tx_err(priv, chan);
2056                 }
2057         }
2058 }
2059
2060 /**
2061  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2062  * @priv: driver private structure
2063  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2064  */
2065 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2066 {
2067         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2068                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2069
2070         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2071
2072         if (priv->dma_cap.rmon) {
2073                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2074                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2075         } else
2076                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2077 }
2078
2079 /**
2080  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2081  * @priv: driver private structure
2082  * Description:
2083  *  new GMAC chip generations have a new register to indicate the
2084  *  presence of the optional feature/functions.
2085  *  This can be also used to override the value passed through the
2086  *  platform and necessary for old MAC10/100 and GMAC chips.
2087  */
2088 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2089 {
2090         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2091 }
2092
2093 /**
2094  * stmmac_check_ether_addr - check if the MAC addr is valid
2095  * @priv: driver private structure
2096  * Description:
2097  * it is to verify if the MAC address is valid, in case of failures it
2098  * generates a random MAC address
2099  */
2100 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2101 {
2102         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2103                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2104                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2105                         eth_hw_addr_random(priv->dev);
2106                 dev_info(priv->device, "device MAC address %pM\n",
2107                          priv->dev->dev_addr);
2108         }
2109 }
2110
2111 /**
2112  * stmmac_init_dma_engine - DMA init.
2113  * @priv: driver private structure
2114  * Description:
2115  * It inits the DMA invoking the specific MAC/GMAC callback.
2116  * Some DMA parameters can be passed from the platform;
2117  * in case of these are not passed a default is kept for the MAC or GMAC.
2118  */
2119 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2120 {
2121         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2122         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2123         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2124         struct stmmac_rx_queue *rx_q;
2125         struct stmmac_tx_queue *tx_q;
2126         u32 chan = 0;
2127         int atds = 0;
2128         int ret = 0;
2129
2130         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2131                 dev_err(priv->device, "Invalid DMA configuration\n");
2132                 return -EINVAL;
2133         }
2134
2135         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2136                 atds = 1;
2137
2138         ret = stmmac_reset(priv, priv->ioaddr);
2139         if (ret) {
2140                 dev_err(priv->device, "Failed to reset the dma\n");
2141                 return ret;
2142         }
2143
2144         /* DMA Configuration */
2145         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2146
2147         if (priv->plat->axi)
2148                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2149
2150         /* DMA CSR Channel configuration */
2151         for (chan = 0; chan < dma_csr_ch; chan++)
2152                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2153
2154         /* DMA RX Channel Configuration */
2155         for (chan = 0; chan < rx_channels_count; chan++) {
2156                 rx_q = &priv->rx_queue[chan];
2157
2158                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2159                                     rx_q->dma_rx_phy, chan);
2160
2161                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2162                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2163                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2164                                        rx_q->rx_tail_addr, chan);
2165         }
2166
2167         /* DMA TX Channel Configuration */
2168         for (chan = 0; chan < tx_channels_count; chan++) {
2169                 tx_q = &priv->tx_queue[chan];
2170
2171                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2172                                     tx_q->dma_tx_phy, chan);
2173
2174                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2175                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2176                                        tx_q->tx_tail_addr, chan);
2177         }
2178
2179         return ret;
2180 }
2181
2182 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2183 {
2184         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2185
2186         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2187 }
2188
2189 /**
2190  * stmmac_tx_timer - mitigation sw timer for tx.
2191  * @data: data pointer
2192  * Description:
2193  * This is the timer handler to directly invoke the stmmac_tx_clean.
2194  */
2195 static void stmmac_tx_timer(struct timer_list *t)
2196 {
2197         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2198         struct stmmac_priv *priv = tx_q->priv_data;
2199         struct stmmac_channel *ch;
2200
2201         ch = &priv->channel[tx_q->queue_index];
2202
2203         /*
2204          * If NAPI is already running we can miss some events. Let's rearm
2205          * the timer and try again.
2206          */
2207         if (likely(napi_schedule_prep(&ch->tx_napi)))
2208                 __napi_schedule(&ch->tx_napi);
2209         else
2210                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2211 }
2212
2213 /**
2214  * stmmac_init_tx_coalesce - init tx mitigation options.
2215  * @priv: driver private structure
2216  * Description:
2217  * This inits the transmit coalesce parameters: i.e. timer rate,
2218  * timer handler and default threshold used for enabling the
2219  * interrupt on completion bit.
2220  */
2221 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2222 {
2223         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2224         u32 chan;
2225
2226         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2227         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2228
2229         for (chan = 0; chan < tx_channel_count; chan++) {
2230                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2231
2232                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2233         }
2234 }
2235
2236 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2237 {
2238         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2239         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2240         u32 chan;
2241
2242         /* set TX ring length */
2243         for (chan = 0; chan < tx_channels_count; chan++)
2244                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2245                                 (DMA_TX_SIZE - 1), chan);
2246
2247         /* set RX ring length */
2248         for (chan = 0; chan < rx_channels_count; chan++)
2249                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2250                                 (DMA_RX_SIZE - 1), chan);
2251 }
2252
2253 /**
2254  *  stmmac_set_tx_queue_weight - Set TX queue weight
2255  *  @priv: driver private structure
2256  *  Description: It is used for setting TX queues weight
2257  */
2258 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2259 {
2260         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2261         u32 weight;
2262         u32 queue;
2263
2264         for (queue = 0; queue < tx_queues_count; queue++) {
2265                 weight = priv->plat->tx_queues_cfg[queue].weight;
2266                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2267         }
2268 }
2269
2270 /**
2271  *  stmmac_configure_cbs - Configure CBS in TX queue
2272  *  @priv: driver private structure
2273  *  Description: It is used for configuring CBS in AVB TX queues
2274  */
2275 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2276 {
2277         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2278         u32 mode_to_use;
2279         u32 queue;
2280
2281         /* queue 0 is reserved for legacy traffic */
2282         for (queue = 1; queue < tx_queues_count; queue++) {
2283                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2284                 if (mode_to_use == MTL_QUEUE_DCB)
2285                         continue;
2286
2287                 stmmac_config_cbs(priv, priv->hw,
2288                                 priv->plat->tx_queues_cfg[queue].send_slope,
2289                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2290                                 priv->plat->tx_queues_cfg[queue].high_credit,
2291                                 priv->plat->tx_queues_cfg[queue].low_credit,
2292                                 queue);
2293         }
2294 }
2295
2296 /**
2297  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2298  *  @priv: driver private structure
2299  *  Description: It is used for mapping RX queues to RX dma channels
2300  */
2301 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2302 {
2303         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2304         u32 queue;
2305         u32 chan;
2306
2307         for (queue = 0; queue < rx_queues_count; queue++) {
2308                 chan = priv->plat->rx_queues_cfg[queue].chan;
2309                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2310         }
2311 }
2312
2313 /**
2314  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2315  *  @priv: driver private structure
2316  *  Description: It is used for configuring the RX Queue Priority
2317  */
2318 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2319 {
2320         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2321         u32 queue;
2322         u32 prio;
2323
2324         for (queue = 0; queue < rx_queues_count; queue++) {
2325                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2326                         continue;
2327
2328                 prio = priv->plat->rx_queues_cfg[queue].prio;
2329                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2330         }
2331 }
2332
2333 /**
2334  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2335  *  @priv: driver private structure
2336  *  Description: It is used for configuring the TX Queue Priority
2337  */
2338 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2339 {
2340         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2341         u32 queue;
2342         u32 prio;
2343
2344         for (queue = 0; queue < tx_queues_count; queue++) {
2345                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2346                         continue;
2347
2348                 prio = priv->plat->tx_queues_cfg[queue].prio;
2349                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2350         }
2351 }
2352
2353 /**
2354  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2355  *  @priv: driver private structure
2356  *  Description: It is used for configuring the RX queue routing
2357  */
2358 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2359 {
2360         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2361         u32 queue;
2362         u8 packet;
2363
2364         for (queue = 0; queue < rx_queues_count; queue++) {
2365                 /* no specific packet type routing specified for the queue */
2366                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2367                         continue;
2368
2369                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2370                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2371         }
2372 }
2373
2374 /**
2375  *  stmmac_mtl_configuration - Configure MTL
2376  *  @priv: driver private structure
2377  *  Description: It is used for configurring MTL
2378  */
2379 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2380 {
2381         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2382         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2383
2384         if (tx_queues_count > 1)
2385                 stmmac_set_tx_queue_weight(priv);
2386
2387         /* Configure MTL RX algorithms */
2388         if (rx_queues_count > 1)
2389                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2390                                 priv->plat->rx_sched_algorithm);
2391
2392         /* Configure MTL TX algorithms */
2393         if (tx_queues_count > 1)
2394                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2395                                 priv->plat->tx_sched_algorithm);
2396
2397         /* Configure CBS in AVB TX queues */
2398         if (tx_queues_count > 1)
2399                 stmmac_configure_cbs(priv);
2400
2401         /* Map RX MTL to DMA channels */
2402         stmmac_rx_queue_dma_chan_map(priv);
2403
2404         /* Enable MAC RX Queues */
2405         stmmac_mac_enable_rx_queues(priv);
2406
2407         /* Set RX priorities */
2408         if (rx_queues_count > 1)
2409                 stmmac_mac_config_rx_queues_prio(priv);
2410
2411         /* Set TX priorities */
2412         if (tx_queues_count > 1)
2413                 stmmac_mac_config_tx_queues_prio(priv);
2414
2415         /* Set RX routing */
2416         if (rx_queues_count > 1)
2417                 stmmac_mac_config_rx_queues_routing(priv);
2418 }
2419
2420 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2421 {
2422         if (priv->dma_cap.asp) {
2423                 netdev_info(priv->dev, "Enabling Safety Features\n");
2424                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2425         } else {
2426                 netdev_info(priv->dev, "No Safety Features support found\n");
2427         }
2428 }
2429
2430 /**
2431  * stmmac_hw_setup - setup mac in a usable state.
2432  *  @dev : pointer to the device structure.
2433  *  Description:
2434  *  this is the main function to setup the HW in a usable state because the
2435  *  dma engine is reset, the core registers are configured (e.g. AXI,
2436  *  Checksum features, timers). The DMA is ready to start receiving and
2437  *  transmitting.
2438  *  Return value:
2439  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2440  *  file on failure.
2441  */
2442 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2443 {
2444         struct stmmac_priv *priv = netdev_priv(dev);
2445         u32 rx_cnt = priv->plat->rx_queues_to_use;
2446         u32 tx_cnt = priv->plat->tx_queues_to_use;
2447         u32 chan;
2448         int ret;
2449
2450         /* DMA initialization and SW reset */
2451         ret = stmmac_init_dma_engine(priv);
2452         if (ret < 0) {
2453                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2454                            __func__);
2455                 return ret;
2456         }
2457
2458         /* Copy the MAC addr into the HW  */
2459         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2460
2461         /* PS and related bits will be programmed according to the speed */
2462         if (priv->hw->pcs) {
2463                 int speed = priv->plat->mac_port_sel_speed;
2464
2465                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2466                     (speed == SPEED_1000)) {
2467                         priv->hw->ps = speed;
2468                 } else {
2469                         dev_warn(priv->device, "invalid port speed\n");
2470                         priv->hw->ps = 0;
2471                 }
2472         }
2473
2474         /* Initialize the MAC Core */
2475         stmmac_core_init(priv, priv->hw, dev);
2476
2477         /* Initialize MTL*/
2478         stmmac_mtl_configuration(priv);
2479
2480         /* Initialize Safety Features */
2481         stmmac_safety_feat_configuration(priv);
2482
2483         ret = stmmac_rx_ipc(priv, priv->hw);
2484         if (!ret) {
2485                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2486                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2487                 priv->hw->rx_csum = 0;
2488         }
2489
2490         /* Enable the MAC Rx/Tx */
2491         stmmac_mac_set(priv, priv->ioaddr, true);
2492
2493         /* Set the HW DMA mode and the COE */
2494         stmmac_dma_operation_mode(priv);
2495
2496         stmmac_mmc_setup(priv);
2497
2498         if (init_ptp) {
2499                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2500                 if (ret < 0)
2501                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2502
2503                 ret = stmmac_init_ptp(priv);
2504                 if (ret == -EOPNOTSUPP)
2505                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2506                 else if (ret)
2507                         netdev_warn(priv->dev, "PTP init failed\n");
2508         }
2509
2510         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2511
2512         if (priv->use_riwt) {
2513                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2514                 if (!ret)
2515                         priv->rx_riwt = MAX_DMA_RIWT;
2516         }
2517
2518         if (priv->hw->pcs)
2519                 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2520
2521         /* set TX and RX rings length */
2522         stmmac_set_rings_length(priv);
2523
2524         /* Enable TSO */
2525         if (priv->tso) {
2526                 for (chan = 0; chan < tx_cnt; chan++)
2527                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2528         }
2529
2530         /* Start the ball rolling... */
2531         stmmac_start_all_dma(priv);
2532
2533         return 0;
2534 }
2535
2536 static void stmmac_hw_teardown(struct net_device *dev)
2537 {
2538         struct stmmac_priv *priv = netdev_priv(dev);
2539
2540         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2541 }
2542
2543 /**
2544  *  stmmac_open - open entry point of the driver
2545  *  @dev : pointer to the device structure.
2546  *  Description:
2547  *  This function is the open entry point of the driver.
2548  *  Return value:
2549  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2550  *  file on failure.
2551  */
2552 static int stmmac_open(struct net_device *dev)
2553 {
2554         struct stmmac_priv *priv = netdev_priv(dev);
2555         u32 chan;
2556         int ret;
2557
2558         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2559             priv->hw->pcs != STMMAC_PCS_TBI &&
2560             priv->hw->pcs != STMMAC_PCS_RTBI) {
2561                 ret = stmmac_init_phy(dev);
2562                 if (ret) {
2563                         netdev_err(priv->dev,
2564                                    "%s: Cannot attach to PHY (error: %d)\n",
2565                                    __func__, ret);
2566                         return ret;
2567                 }
2568         }
2569
2570         /* Extra statistics */
2571         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2572         priv->xstats.threshold = tc;
2573
2574         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2575         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2576
2577         ret = alloc_dma_desc_resources(priv);
2578         if (ret < 0) {
2579                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2580                            __func__);
2581                 goto dma_desc_error;
2582         }
2583
2584         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2585         if (ret < 0) {
2586                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2587                            __func__);
2588                 goto init_error;
2589         }
2590
2591         ret = stmmac_hw_setup(dev, true);
2592         if (ret < 0) {
2593                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2594                 goto init_error;
2595         }
2596
2597         stmmac_init_tx_coalesce(priv);
2598
2599         phylink_start(priv->phylink);
2600
2601         /* Request the IRQ lines */
2602         ret = request_irq(dev->irq, stmmac_interrupt,
2603                           IRQF_SHARED, dev->name, dev);
2604         if (unlikely(ret < 0)) {
2605                 netdev_err(priv->dev,
2606                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2607                            __func__, dev->irq, ret);
2608                 goto irq_error;
2609         }
2610
2611         /* Request the Wake IRQ in case of another line is used for WoL */
2612         if (priv->wol_irq != dev->irq) {
2613                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2614                                   IRQF_SHARED, dev->name, dev);
2615                 if (unlikely(ret < 0)) {
2616                         netdev_err(priv->dev,
2617                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2618                                    __func__, priv->wol_irq, ret);
2619                         goto wolirq_error;
2620                 }
2621         }
2622
2623         /* Request the IRQ lines */
2624         if (priv->lpi_irq > 0) {
2625                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2626                                   dev->name, dev);
2627                 if (unlikely(ret < 0)) {
2628                         netdev_err(priv->dev,
2629                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2630                                    __func__, priv->lpi_irq, ret);
2631                         goto lpiirq_error;
2632                 }
2633         }
2634
2635         stmmac_enable_all_queues(priv);
2636         stmmac_start_all_queues(priv);
2637
2638         return 0;
2639
2640 lpiirq_error:
2641         if (priv->wol_irq != dev->irq)
2642                 free_irq(priv->wol_irq, dev);
2643 wolirq_error:
2644         free_irq(dev->irq, dev);
2645 irq_error:
2646         phylink_stop(priv->phylink);
2647
2648         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2649                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2650
2651         stmmac_hw_teardown(dev);
2652 init_error:
2653         free_dma_desc_resources(priv);
2654 dma_desc_error:
2655         phylink_disconnect_phy(priv->phylink);
2656         return ret;
2657 }
2658
2659 /**
2660  *  stmmac_release - close entry point of the driver
2661  *  @dev : device pointer.
2662  *  Description:
2663  *  This is the stop entry point of the driver.
2664  */
2665 static int stmmac_release(struct net_device *dev)
2666 {
2667         struct stmmac_priv *priv = netdev_priv(dev);
2668         u32 chan;
2669
2670         if (priv->eee_enabled)
2671                 del_timer_sync(&priv->eee_ctrl_timer);
2672
2673         /* Stop and disconnect the PHY */
2674         phylink_stop(priv->phylink);
2675         phylink_disconnect_phy(priv->phylink);
2676
2677         stmmac_stop_all_queues(priv);
2678
2679         stmmac_disable_all_queues(priv);
2680
2681         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2682                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2683
2684         /* Free the IRQ lines */
2685         free_irq(dev->irq, dev);
2686         if (priv->wol_irq != dev->irq)
2687                 free_irq(priv->wol_irq, dev);
2688         if (priv->lpi_irq > 0)
2689                 free_irq(priv->lpi_irq, dev);
2690
2691         /* Stop TX/RX DMA and clear the descriptors */
2692         stmmac_stop_all_dma(priv);
2693
2694         /* Release and free the Rx/Tx resources */
2695         free_dma_desc_resources(priv);
2696
2697         /* Disable the MAC Rx/Tx */
2698         stmmac_mac_set(priv, priv->ioaddr, false);
2699
2700         netif_carrier_off(dev);
2701
2702         stmmac_release_ptp(priv);
2703
2704         return 0;
2705 }
2706
2707 /**
2708  *  stmmac_tso_allocator - close entry point of the driver
2709  *  @priv: driver private structure
2710  *  @des: buffer start address
2711  *  @total_len: total length to fill in descriptors
2712  *  @last_segmant: condition for the last descriptor
2713  *  @queue: TX queue index
2714  *  Description:
2715  *  This function fills descriptor and request new descriptors according to
2716  *  buffer length to fill
2717  */
2718 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2719                                  int total_len, bool last_segment, u32 queue)
2720 {
2721         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2722         struct dma_desc *desc;
2723         u32 buff_size;
2724         int tmp_len;
2725
2726         tmp_len = total_len;
2727
2728         while (tmp_len > 0) {
2729                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2730                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2731                 desc = tx_q->dma_tx + tx_q->cur_tx;
2732
2733                 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2734                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2735                             TSO_MAX_BUFF_SIZE : tmp_len;
2736
2737                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2738                                 0, 1,
2739                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2740                                 0, 0);
2741
2742                 tmp_len -= TSO_MAX_BUFF_SIZE;
2743         }
2744 }
2745
2746 /**
2747  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2748  *  @skb : the socket buffer
2749  *  @dev : device pointer
2750  *  Description: this is the transmit function that is called on TSO frames
2751  *  (support available on GMAC4 and newer chips).
2752  *  Diagram below show the ring programming in case of TSO frames:
2753  *
2754  *  First Descriptor
2755  *   --------
2756  *   | DES0 |---> buffer1 = L2/L3/L4 header
2757  *   | DES1 |---> TCP Payload (can continue on next descr...)
2758  *   | DES2 |---> buffer 1 and 2 len
2759  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2760  *   --------
2761  *      |
2762  *     ...
2763  *      |
2764  *   --------
2765  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2766  *   | DES1 | --|
2767  *   | DES2 | --> buffer 1 and 2 len
2768  *   | DES3 |
2769  *   --------
2770  *
2771  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2772  */
2773 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2774 {
2775         struct dma_desc *desc, *first, *mss_desc = NULL;
2776         struct stmmac_priv *priv = netdev_priv(dev);
2777         int nfrags = skb_shinfo(skb)->nr_frags;
2778         u32 queue = skb_get_queue_mapping(skb);
2779         unsigned int first_entry, des;
2780         struct stmmac_tx_queue *tx_q;
2781         int tmp_pay_len = 0;
2782         u32 pay_len, mss;
2783         u8 proto_hdr_len;
2784         int i;
2785
2786         tx_q = &priv->tx_queue[queue];
2787
2788         /* Compute header lengths */
2789         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2790
2791         /* Desc availability based on threshold should be enough safe */
2792         if (unlikely(stmmac_tx_avail(priv, queue) <
2793                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2794                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2795                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2796                                                                 queue));
2797                         /* This is a hard error, log it. */
2798                         netdev_err(priv->dev,
2799                                    "%s: Tx Ring full when queue awake\n",
2800                                    __func__);
2801                 }
2802                 return NETDEV_TX_BUSY;
2803         }
2804
2805         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2806
2807         mss = skb_shinfo(skb)->gso_size;
2808
2809         /* set new MSS value if needed */
2810         if (mss != tx_q->mss) {
2811                 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2812                 stmmac_set_mss(priv, mss_desc, mss);
2813                 tx_q->mss = mss;
2814                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2815                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2816         }
2817
2818         if (netif_msg_tx_queued(priv)) {
2819                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2820                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2821                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2822                         skb->data_len);
2823         }
2824
2825         first_entry = tx_q->cur_tx;
2826         WARN_ON(tx_q->tx_skbuff[first_entry]);
2827
2828         desc = tx_q->dma_tx + first_entry;
2829         first = desc;
2830
2831         /* first descriptor: fill Headers on Buf1 */
2832         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2833                              DMA_TO_DEVICE);
2834         if (dma_mapping_error(priv->device, des))
2835                 goto dma_map_err;
2836
2837         tx_q->tx_skbuff_dma[first_entry].buf = des;
2838         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2839
2840         first->des0 = cpu_to_le32(des);
2841
2842         /* Fill start of payload in buff2 of first descriptor */
2843         if (pay_len)
2844                 first->des1 = cpu_to_le32(des + proto_hdr_len);
2845
2846         /* If needed take extra descriptors to fill the remaining payload */
2847         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2848
2849         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2850
2851         /* Prepare fragments */
2852         for (i = 0; i < nfrags; i++) {
2853                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2854
2855                 des = skb_frag_dma_map(priv->device, frag, 0,
2856                                        skb_frag_size(frag),
2857                                        DMA_TO_DEVICE);
2858                 if (dma_mapping_error(priv->device, des))
2859                         goto dma_map_err;
2860
2861                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2862                                      (i == nfrags - 1), queue);
2863
2864                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2865                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2866                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2867         }
2868
2869         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2870
2871         /* Only the last descriptor gets to point to the skb. */
2872         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2873
2874         /* We've used all descriptors we need for this skb, however,
2875          * advance cur_tx so that it references a fresh descriptor.
2876          * ndo_start_xmit will fill this descriptor the next time it's
2877          * called and stmmac_tx_clean may clean up to this descriptor.
2878          */
2879         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2880
2881         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2882                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2883                           __func__);
2884                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2885         }
2886
2887         dev->stats.tx_bytes += skb->len;
2888         priv->xstats.tx_tso_frames++;
2889         priv->xstats.tx_tso_nfrags += nfrags;
2890
2891         /* Manage tx mitigation */
2892         tx_q->tx_count_frames += nfrags + 1;
2893         if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
2894                 stmmac_set_tx_ic(priv, desc);
2895                 priv->xstats.tx_set_ic_bit++;
2896                 tx_q->tx_count_frames = 0;
2897         } else {
2898                 stmmac_tx_timer_arm(priv, queue);
2899         }
2900
2901         skb_tx_timestamp(skb);
2902
2903         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2904                      priv->hwts_tx_en)) {
2905                 /* declare that device is doing timestamping */
2906                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2907                 stmmac_enable_tx_timestamp(priv, first);
2908         }
2909
2910         /* Complete the first descriptor before granting the DMA */
2911         stmmac_prepare_tso_tx_desc(priv, first, 1,
2912                         proto_hdr_len,
2913                         pay_len,
2914                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2915                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2916
2917         /* If context desc is used to change MSS */
2918         if (mss_desc) {
2919                 /* Make sure that first descriptor has been completely
2920                  * written, including its own bit. This is because MSS is
2921                  * actually before first descriptor, so we need to make
2922                  * sure that MSS's own bit is the last thing written.
2923                  */
2924                 dma_wmb();
2925                 stmmac_set_tx_owner(priv, mss_desc);
2926         }
2927
2928         /* The own bit must be the latest setting done when prepare the
2929          * descriptor and then barrier is needed to make sure that
2930          * all is coherent before granting the DMA engine.
2931          */
2932         wmb();
2933
2934         if (netif_msg_pktdata(priv)) {
2935                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2936                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2937                         tx_q->cur_tx, first, nfrags);
2938
2939                 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
2940
2941                 pr_info(">>> frame to be transmitted: ");
2942                 print_pkt(skb->data, skb_headlen(skb));
2943         }
2944
2945         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2946
2947         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
2948         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
2949
2950         return NETDEV_TX_OK;
2951
2952 dma_map_err:
2953         dev_err(priv->device, "Tx dma map failed\n");
2954         dev_kfree_skb(skb);
2955         priv->dev->stats.tx_dropped++;
2956         return NETDEV_TX_OK;
2957 }
2958
2959 /**
2960  *  stmmac_xmit - Tx entry point of the driver
2961  *  @skb : the socket buffer
2962  *  @dev : device pointer
2963  *  Description : this is the tx entry point of the driver.
2964  *  It programs the chain or the ring and supports oversized frames
2965  *  and SG feature.
2966  */
2967 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2968 {
2969         struct stmmac_priv *priv = netdev_priv(dev);
2970         unsigned int nopaged_len = skb_headlen(skb);
2971         int i, csum_insertion = 0, is_jumbo = 0;
2972         u32 queue = skb_get_queue_mapping(skb);
2973         int nfrags = skb_shinfo(skb)->nr_frags;
2974         int entry;
2975         unsigned int first_entry;
2976         struct dma_desc *desc, *first;
2977         struct stmmac_tx_queue *tx_q;
2978         unsigned int enh_desc;
2979         unsigned int des;
2980
2981         tx_q = &priv->tx_queue[queue];
2982
2983         if (priv->tx_path_in_lpi_mode)
2984                 stmmac_disable_eee_mode(priv);
2985
2986         /* Manage oversized TCP frames for GMAC4 device */
2987         if (skb_is_gso(skb) && priv->tso) {
2988                 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
2989                         /*
2990                          * There is no way to determine the number of TSO
2991                          * capable Queues. Let's use always the Queue 0
2992                          * because if TSO is supported then at least this
2993                          * one will be capable.
2994                          */
2995                         skb_set_queue_mapping(skb, 0);
2996
2997                         return stmmac_tso_xmit(skb, dev);
2998                 }
2999         }
3000
3001         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3002                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3003                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3004                                                                 queue));
3005                         /* This is a hard error, log it. */
3006                         netdev_err(priv->dev,
3007                                    "%s: Tx Ring full when queue awake\n",
3008                                    __func__);
3009                 }
3010                 return NETDEV_TX_BUSY;
3011         }
3012
3013         entry = tx_q->cur_tx;
3014         first_entry = entry;
3015         WARN_ON(tx_q->tx_skbuff[first_entry]);
3016
3017         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3018
3019         if (likely(priv->extend_desc))
3020                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3021         else
3022                 desc = tx_q->dma_tx + entry;
3023
3024         first = desc;
3025
3026         enh_desc = priv->plat->enh_desc;
3027         /* To program the descriptors according to the size of the frame */
3028         if (enh_desc)
3029                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3030
3031         if (unlikely(is_jumbo)) {
3032                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3033                 if (unlikely(entry < 0) && (entry != -EINVAL))
3034                         goto dma_map_err;
3035         }
3036
3037         for (i = 0; i < nfrags; i++) {
3038                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3039                 int len = skb_frag_size(frag);
3040                 bool last_segment = (i == (nfrags - 1));
3041
3042                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3043                 WARN_ON(tx_q->tx_skbuff[entry]);
3044
3045                 if (likely(priv->extend_desc))
3046                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3047                 else
3048                         desc = tx_q->dma_tx + entry;
3049
3050                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3051                                        DMA_TO_DEVICE);
3052                 if (dma_mapping_error(priv->device, des))
3053                         goto dma_map_err; /* should reuse desc w/o issues */
3054
3055                 tx_q->tx_skbuff_dma[entry].buf = des;
3056
3057                 stmmac_set_desc_addr(priv, desc, des);
3058
3059                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3060                 tx_q->tx_skbuff_dma[entry].len = len;
3061                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3062
3063                 /* Prepare the descriptor and set the own bit too */
3064                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3065                                 priv->mode, 1, last_segment, skb->len);
3066         }
3067
3068         /* Only the last descriptor gets to point to the skb. */
3069         tx_q->tx_skbuff[entry] = skb;
3070
3071         /* We've used all descriptors we need for this skb, however,
3072          * advance cur_tx so that it references a fresh descriptor.
3073          * ndo_start_xmit will fill this descriptor the next time it's
3074          * called and stmmac_tx_clean may clean up to this descriptor.
3075          */
3076         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3077         tx_q->cur_tx = entry;
3078
3079         if (netif_msg_pktdata(priv)) {
3080                 void *tx_head;
3081
3082                 netdev_dbg(priv->dev,
3083                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3084                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3085                            entry, first, nfrags);
3086
3087                 if (priv->extend_desc)
3088                         tx_head = (void *)tx_q->dma_etx;
3089                 else
3090                         tx_head = (void *)tx_q->dma_tx;
3091
3092                 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3093
3094                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3095                 print_pkt(skb->data, skb->len);
3096         }
3097
3098         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3099                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3100                           __func__);
3101                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3102         }
3103
3104         dev->stats.tx_bytes += skb->len;
3105
3106         /* According to the coalesce parameter the IC bit for the latest
3107          * segment is reset and the timer re-started to clean the tx status.
3108          * This approach takes care about the fragments: desc is the first
3109          * element in case of no SG.
3110          */
3111         tx_q->tx_count_frames += nfrags + 1;
3112         if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
3113                 stmmac_set_tx_ic(priv, desc);
3114                 priv->xstats.tx_set_ic_bit++;
3115                 tx_q->tx_count_frames = 0;
3116         } else {
3117                 stmmac_tx_timer_arm(priv, queue);
3118         }
3119
3120         skb_tx_timestamp(skb);
3121
3122         /* Ready to fill the first descriptor and set the OWN bit w/o any
3123          * problems because all the descriptors are actually ready to be
3124          * passed to the DMA engine.
3125          */
3126         if (likely(!is_jumbo)) {
3127                 bool last_segment = (nfrags == 0);
3128
3129                 des = dma_map_single(priv->device, skb->data,
3130                                      nopaged_len, DMA_TO_DEVICE);
3131                 if (dma_mapping_error(priv->device, des))
3132                         goto dma_map_err;
3133
3134                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3135
3136                 stmmac_set_desc_addr(priv, first, des);
3137
3138                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3139                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3140
3141                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3142                              priv->hwts_tx_en)) {
3143                         /* declare that device is doing timestamping */
3144                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3145                         stmmac_enable_tx_timestamp(priv, first);
3146                 }
3147
3148                 /* Prepare the first descriptor setting the OWN bit too */
3149                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3150                                 csum_insertion, priv->mode, 1, last_segment,
3151                                 skb->len);
3152         } else {
3153                 stmmac_set_tx_owner(priv, first);
3154         }
3155
3156         /* The own bit must be the latest setting done when prepare the
3157          * descriptor and then barrier is needed to make sure that
3158          * all is coherent before granting the DMA engine.
3159          */
3160         wmb();
3161
3162         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3163
3164         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3165
3166         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3167         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3168
3169         return NETDEV_TX_OK;
3170
3171 dma_map_err:
3172         netdev_err(priv->dev, "Tx DMA map failed\n");
3173         dev_kfree_skb(skb);
3174         priv->dev->stats.tx_dropped++;
3175         return NETDEV_TX_OK;
3176 }
3177
3178 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3179 {
3180         struct vlan_ethhdr *veth;
3181         __be16 vlan_proto;
3182         u16 vlanid;
3183
3184         veth = (struct vlan_ethhdr *)skb->data;
3185         vlan_proto = veth->h_vlan_proto;
3186
3187         if ((vlan_proto == htons(ETH_P_8021Q) &&
3188              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3189             (vlan_proto == htons(ETH_P_8021AD) &&
3190              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3191                 /* pop the vlan tag */
3192                 vlanid = ntohs(veth->h_vlan_TCI);
3193                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3194                 skb_pull(skb, VLAN_HLEN);
3195                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3196         }
3197 }
3198
3199
3200 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3201 {
3202         if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3203                 return 0;
3204
3205         return 1;
3206 }
3207
3208 /**
3209  * stmmac_rx_refill - refill used skb preallocated buffers
3210  * @priv: driver private structure
3211  * @queue: RX queue index
3212  * Description : this is to reallocate the skb for the reception process
3213  * that is based on zero-copy.
3214  */
3215 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3216 {
3217         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3218         int dirty = stmmac_rx_dirty(priv, queue);
3219         unsigned int entry = rx_q->dirty_rx;
3220
3221         int bfsize = priv->dma_buf_sz;
3222
3223         while (dirty-- > 0) {
3224                 struct dma_desc *p;
3225
3226                 if (priv->extend_desc)
3227                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3228                 else
3229                         p = rx_q->dma_rx + entry;
3230
3231                 if (likely(!rx_q->rx_skbuff[entry])) {
3232                         struct sk_buff *skb;
3233
3234                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3235                         if (unlikely(!skb)) {
3236                                 /* so for a while no zero-copy! */
3237                                 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3238                                 if (unlikely(net_ratelimit()))
3239                                         dev_err(priv->device,
3240                                                 "fail to alloc skb entry %d\n",
3241                                                 entry);
3242                                 break;
3243                         }
3244
3245                         rx_q->rx_skbuff[entry] = skb;
3246                         rx_q->rx_skbuff_dma[entry] =
3247                             dma_map_single(priv->device, skb->data, bfsize,
3248                                            DMA_FROM_DEVICE);
3249                         if (dma_mapping_error(priv->device,
3250                                               rx_q->rx_skbuff_dma[entry])) {
3251                                 netdev_err(priv->dev, "Rx DMA map failed\n");
3252                                 dev_kfree_skb(skb);
3253                                 break;
3254                         }
3255
3256                         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3257                         stmmac_refill_desc3(priv, rx_q, p);
3258
3259                         if (rx_q->rx_zeroc_thresh > 0)
3260                                 rx_q->rx_zeroc_thresh--;
3261
3262                         netif_dbg(priv, rx_status, priv->dev,
3263                                   "refill entry #%d\n", entry);
3264                 }
3265                 dma_wmb();
3266
3267                 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3268
3269                 dma_wmb();
3270
3271                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3272         }
3273         rx_q->dirty_rx = entry;
3274         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3275 }
3276
3277 /**
3278  * stmmac_rx - manage the receive process
3279  * @priv: driver private structure
3280  * @limit: napi bugget
3281  * @queue: RX queue index.
3282  * Description :  this the function called by the napi poll method.
3283  * It gets all the frames inside the ring.
3284  */
3285 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3286 {
3287         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3288         struct stmmac_channel *ch = &priv->channel[queue];
3289         unsigned int next_entry = rx_q->cur_rx;
3290         int coe = priv->hw->rx_csum;
3291         unsigned int count = 0;
3292         bool xmac;
3293
3294         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3295
3296         if (netif_msg_rx_status(priv)) {
3297                 void *rx_head;
3298
3299                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3300                 if (priv->extend_desc)
3301                         rx_head = (void *)rx_q->dma_erx;
3302                 else
3303                         rx_head = (void *)rx_q->dma_rx;
3304
3305                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3306         }
3307         while (count < limit) {
3308                 int entry, status;
3309                 struct dma_desc *p;
3310                 struct dma_desc *np;
3311
3312                 entry = next_entry;
3313
3314                 if (priv->extend_desc)
3315                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3316                 else
3317                         p = rx_q->dma_rx + entry;
3318
3319                 /* read the status of the incoming frame */
3320                 status = stmmac_rx_status(priv, &priv->dev->stats,
3321                                 &priv->xstats, p);
3322                 /* check if managed by the DMA otherwise go ahead */
3323                 if (unlikely(status & dma_own))
3324                         break;
3325
3326                 count++;
3327
3328                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3329                 next_entry = rx_q->cur_rx;
3330
3331                 if (priv->extend_desc)
3332                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3333                 else
3334                         np = rx_q->dma_rx + next_entry;
3335
3336                 prefetch(np);
3337
3338                 if (priv->extend_desc)
3339                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3340                                         &priv->xstats, rx_q->dma_erx + entry);
3341                 if (unlikely(status == discard_frame)) {
3342                         priv->dev->stats.rx_errors++;
3343                         if (priv->hwts_rx_en && !priv->extend_desc) {
3344                                 /* DESC2 & DESC3 will be overwritten by device
3345                                  * with timestamp value, hence reinitialize
3346                                  * them in stmmac_rx_refill() function so that
3347                                  * device can reuse it.
3348                                  */
3349                                 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3350                                 rx_q->rx_skbuff[entry] = NULL;
3351                                 dma_unmap_single(priv->device,
3352                                                  rx_q->rx_skbuff_dma[entry],
3353                                                  priv->dma_buf_sz,
3354                                                  DMA_FROM_DEVICE);
3355                         }
3356                 } else {
3357                         struct sk_buff *skb;
3358                         int frame_len;
3359                         unsigned int des;
3360
3361                         stmmac_get_desc_addr(priv, p, &des);
3362                         frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3363
3364                         /*  If frame length is greater than skb buffer size
3365                          *  (preallocated during init) then the packet is
3366                          *  ignored
3367                          */
3368                         if (frame_len > priv->dma_buf_sz) {
3369                                 if (net_ratelimit())
3370                                         netdev_err(priv->dev,
3371                                                    "len %d larger than size (%d)\n",
3372                                                    frame_len, priv->dma_buf_sz);
3373                                 priv->dev->stats.rx_length_errors++;
3374                                 continue;
3375                         }
3376
3377                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3378                          * Type frames (LLC/LLC-SNAP)
3379                          *
3380                          * llc_snap is never checked in GMAC >= 4, so this ACS
3381                          * feature is always disabled and packets need to be
3382                          * stripped manually.
3383                          */
3384                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3385                             unlikely(status != llc_snap))
3386                                 frame_len -= ETH_FCS_LEN;
3387
3388                         if (netif_msg_rx_status(priv)) {
3389                                 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3390                                            p, entry, des);
3391                                 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3392                                            frame_len, status);
3393                         }
3394
3395                         /* The zero-copy is always used for all the sizes
3396                          * in case of GMAC4 because it needs
3397                          * to refill the used descriptors, always.
3398                          */
3399                         if (unlikely(!xmac &&
3400                                      ((frame_len < priv->rx_copybreak) ||
3401                                      stmmac_rx_threshold_count(rx_q)))) {
3402                                 skb = netdev_alloc_skb_ip_align(priv->dev,
3403                                                                 frame_len);
3404                                 if (unlikely(!skb)) {
3405                                         if (net_ratelimit())
3406                                                 dev_warn(priv->device,
3407                                                          "packet dropped\n");
3408                                         priv->dev->stats.rx_dropped++;
3409                                         continue;
3410                                 }
3411
3412                                 dma_sync_single_for_cpu(priv->device,
3413                                                         rx_q->rx_skbuff_dma
3414                                                         [entry], frame_len,
3415                                                         DMA_FROM_DEVICE);
3416                                 skb_copy_to_linear_data(skb,
3417                                                         rx_q->
3418                                                         rx_skbuff[entry]->data,
3419                                                         frame_len);
3420
3421                                 skb_put(skb, frame_len);
3422                                 dma_sync_single_for_device(priv->device,
3423                                                            rx_q->rx_skbuff_dma
3424                                                            [entry], frame_len,
3425                                                            DMA_FROM_DEVICE);
3426                         } else {
3427                                 skb = rx_q->rx_skbuff[entry];
3428                                 if (unlikely(!skb)) {
3429                                         if (net_ratelimit())
3430                                                 netdev_err(priv->dev,
3431                                                            "%s: Inconsistent Rx chain\n",
3432                                                            priv->dev->name);
3433                                         priv->dev->stats.rx_dropped++;
3434                                         continue;
3435                                 }
3436                                 prefetch(skb->data - NET_IP_ALIGN);
3437                                 rx_q->rx_skbuff[entry] = NULL;
3438                                 rx_q->rx_zeroc_thresh++;
3439
3440                                 skb_put(skb, frame_len);
3441                                 dma_unmap_single(priv->device,
3442                                                  rx_q->rx_skbuff_dma[entry],
3443                                                  priv->dma_buf_sz,
3444                                                  DMA_FROM_DEVICE);
3445                         }
3446
3447                         if (netif_msg_pktdata(priv)) {
3448                                 netdev_dbg(priv->dev, "frame received (%dbytes)",
3449                                            frame_len);
3450                                 print_pkt(skb->data, frame_len);
3451                         }
3452
3453                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
3454
3455                         stmmac_rx_vlan(priv->dev, skb);
3456
3457                         skb->protocol = eth_type_trans(skb, priv->dev);
3458
3459                         if (unlikely(!coe))
3460                                 skb_checksum_none_assert(skb);
3461                         else
3462                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3463
3464                         napi_gro_receive(&ch->rx_napi, skb);
3465
3466                         priv->dev->stats.rx_packets++;
3467                         priv->dev->stats.rx_bytes += frame_len;
3468                 }
3469         }
3470
3471         stmmac_rx_refill(priv, queue);
3472
3473         priv->xstats.rx_pkt_n += count;
3474
3475         return count;
3476 }
3477
3478 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3479 {
3480         struct stmmac_channel *ch =
3481                 container_of(napi, struct stmmac_channel, rx_napi);
3482         struct stmmac_priv *priv = ch->priv_data;
3483         u32 chan = ch->index;
3484         int work_done;
3485
3486         priv->xstats.napi_poll++;
3487
3488         work_done = stmmac_rx(priv, budget, chan);
3489         if (work_done < budget && napi_complete_done(napi, work_done))
3490                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3491         return work_done;
3492 }
3493
3494 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3495 {
3496         struct stmmac_channel *ch =
3497                 container_of(napi, struct stmmac_channel, tx_napi);
3498         struct stmmac_priv *priv = ch->priv_data;
3499         struct stmmac_tx_queue *tx_q;
3500         u32 chan = ch->index;
3501         int work_done;
3502
3503         priv->xstats.napi_poll++;
3504
3505         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3506         work_done = min(work_done, budget);
3507
3508         if (work_done < budget && napi_complete_done(napi, work_done))
3509                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3510
3511         /* Force transmission restart */
3512         tx_q = &priv->tx_queue[chan];
3513         if (tx_q->cur_tx != tx_q->dirty_tx) {
3514                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3515                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3516                                        chan);
3517         }
3518
3519         return work_done;
3520 }
3521
3522 /**
3523  *  stmmac_tx_timeout
3524  *  @dev : Pointer to net device structure
3525  *  Description: this function is called when a packet transmission fails to
3526  *   complete within a reasonable time. The driver will mark the error in the
3527  *   netdev structure and arrange for the device to be reset to a sane state
3528  *   in order to transmit a new packet.
3529  */
3530 static void stmmac_tx_timeout(struct net_device *dev)
3531 {
3532         struct stmmac_priv *priv = netdev_priv(dev);
3533
3534         stmmac_global_err(priv);
3535 }
3536
3537 /**
3538  *  stmmac_set_rx_mode - entry point for multicast addressing
3539  *  @dev : pointer to the device structure
3540  *  Description:
3541  *  This function is a driver entry point which gets called by the kernel
3542  *  whenever multicast addresses must be enabled/disabled.
3543  *  Return value:
3544  *  void.
3545  */
3546 static void stmmac_set_rx_mode(struct net_device *dev)
3547 {
3548         struct stmmac_priv *priv = netdev_priv(dev);
3549
3550         stmmac_set_filter(priv, priv->hw, dev);
3551 }
3552
3553 /**
3554  *  stmmac_change_mtu - entry point to change MTU size for the device.
3555  *  @dev : device pointer.
3556  *  @new_mtu : the new MTU size for the device.
3557  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3558  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3559  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3560  *  Return value:
3561  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3562  *  file on failure.
3563  */
3564 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3565 {
3566         struct stmmac_priv *priv = netdev_priv(dev);
3567
3568         if (netif_running(dev)) {
3569                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3570                 return -EBUSY;
3571         }
3572
3573         dev->mtu = new_mtu;
3574
3575         netdev_update_features(dev);
3576
3577         return 0;
3578 }
3579
3580 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3581                                              netdev_features_t features)
3582 {
3583         struct stmmac_priv *priv = netdev_priv(dev);
3584
3585         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3586                 features &= ~NETIF_F_RXCSUM;
3587
3588         if (!priv->plat->tx_coe)
3589                 features &= ~NETIF_F_CSUM_MASK;
3590
3591         /* Some GMAC devices have a bugged Jumbo frame support that
3592          * needs to have the Tx COE disabled for oversized frames
3593          * (due to limited buffer sizes). In this case we disable
3594          * the TX csum insertion in the TDES and not use SF.
3595          */
3596         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3597                 features &= ~NETIF_F_CSUM_MASK;
3598
3599         /* Disable tso if asked by ethtool */
3600         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3601                 if (features & NETIF_F_TSO)
3602                         priv->tso = true;
3603                 else
3604                         priv->tso = false;
3605         }
3606
3607         return features;
3608 }
3609
3610 static int stmmac_set_features(struct net_device *netdev,
3611                                netdev_features_t features)
3612 {
3613         struct stmmac_priv *priv = netdev_priv(netdev);
3614
3615         /* Keep the COE Type in case of csum is supporting */
3616         if (features & NETIF_F_RXCSUM)
3617                 priv->hw->rx_csum = priv->plat->rx_coe;
3618         else
3619                 priv->hw->rx_csum = 0;
3620         /* No check needed because rx_coe has been set before and it will be
3621          * fixed in case of issue.
3622          */
3623         stmmac_rx_ipc(priv, priv->hw);
3624
3625         return 0;
3626 }
3627
3628 /**
3629  *  stmmac_interrupt - main ISR
3630  *  @irq: interrupt number.
3631  *  @dev_id: to pass the net device pointer.
3632  *  Description: this is the main driver interrupt service routine.
3633  *  It can call:
3634  *  o DMA service routine (to manage incoming frame reception and transmission
3635  *    status)
3636  *  o Core interrupts to manage: remote wake-up, management counter, LPI
3637  *    interrupts.
3638  */
3639 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3640 {
3641         struct net_device *dev = (struct net_device *)dev_id;
3642         struct stmmac_priv *priv = netdev_priv(dev);
3643         u32 rx_cnt = priv->plat->rx_queues_to_use;
3644         u32 tx_cnt = priv->plat->tx_queues_to_use;
3645         u32 queues_count;
3646         u32 queue;
3647         bool xmac;
3648
3649         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3650         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3651
3652         if (priv->irq_wake)
3653                 pm_wakeup_event(priv->device, 0);
3654
3655         if (unlikely(!dev)) {
3656                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3657                 return IRQ_NONE;
3658         }
3659
3660         /* Check if adapter is up */
3661         if (test_bit(STMMAC_DOWN, &priv->state))
3662                 return IRQ_HANDLED;
3663         /* Check if a fatal error happened */
3664         if (stmmac_safety_feat_interrupt(priv))
3665                 return IRQ_HANDLED;
3666
3667         /* To handle GMAC own interrupts */
3668         if ((priv->plat->has_gmac) || xmac) {
3669                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3670                 int mtl_status;
3671
3672                 if (unlikely(status)) {
3673                         /* For LPI we need to save the tx status */
3674                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3675                                 priv->tx_path_in_lpi_mode = true;
3676                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3677                                 priv->tx_path_in_lpi_mode = false;
3678                 }
3679
3680                 for (queue = 0; queue < queues_count; queue++) {
3681                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3682
3683                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3684                                                                 queue);
3685                         if (mtl_status != -EINVAL)
3686                                 status |= mtl_status;
3687
3688                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3689                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3690                                                        rx_q->rx_tail_addr,
3691                                                        queue);
3692                 }
3693
3694                 /* PCS link status */
3695                 if (priv->hw->pcs) {
3696                         if (priv->xstats.pcs_link)
3697                                 netif_carrier_on(dev);
3698                         else
3699                                 netif_carrier_off(dev);
3700                 }
3701         }
3702
3703         /* To handle DMA interrupts */
3704         stmmac_dma_interrupt(priv);
3705
3706         return IRQ_HANDLED;
3707 }
3708
3709 #ifdef CONFIG_NET_POLL_CONTROLLER
3710 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3711  * to allow network I/O with interrupts disabled.
3712  */
3713 static void stmmac_poll_controller(struct net_device *dev)
3714 {
3715         disable_irq(dev->irq);
3716         stmmac_interrupt(dev->irq, dev);
3717         enable_irq(dev->irq);
3718 }
3719 #endif
3720
3721 /**
3722  *  stmmac_ioctl - Entry point for the Ioctl
3723  *  @dev: Device pointer.
3724  *  @rq: An IOCTL specefic structure, that can contain a pointer to
3725  *  a proprietary structure used to pass information to the driver.
3726  *  @cmd: IOCTL command
3727  *  Description:
3728  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3729  */
3730 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3731 {
3732         struct stmmac_priv *priv = netdev_priv (dev);
3733         int ret = -EOPNOTSUPP;
3734
3735         if (!netif_running(dev))
3736                 return -EINVAL;
3737
3738         switch (cmd) {
3739         case SIOCGMIIPHY:
3740         case SIOCGMIIREG:
3741         case SIOCSMIIREG:
3742                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3743                 break;
3744         case SIOCSHWTSTAMP:
3745                 ret = stmmac_hwtstamp_set(dev, rq);
3746                 break;
3747         case SIOCGHWTSTAMP:
3748                 ret = stmmac_hwtstamp_get(dev, rq);
3749                 break;
3750         default:
3751                 break;
3752         }
3753
3754         return ret;
3755 }
3756
3757 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3758                                     void *cb_priv)
3759 {
3760         struct stmmac_priv *priv = cb_priv;
3761         int ret = -EOPNOTSUPP;
3762
3763         stmmac_disable_all_queues(priv);
3764
3765         switch (type) {
3766         case TC_SETUP_CLSU32:
3767                 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3768                         ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3769                 break;
3770         default:
3771                 break;
3772         }
3773
3774         stmmac_enable_all_queues(priv);
3775         return ret;
3776 }
3777
3778 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3779                                  struct tc_block_offload *f)
3780 {
3781         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3782                 return -EOPNOTSUPP;
3783
3784         switch (f->command) {
3785         case TC_BLOCK_BIND:
3786                 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3787                                 priv, priv, f->extack);
3788         case TC_BLOCK_UNBIND:
3789                 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3790                 return 0;
3791         default:
3792                 return -EOPNOTSUPP;
3793         }
3794 }
3795
3796 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3797                            void *type_data)
3798 {
3799         struct stmmac_priv *priv = netdev_priv(ndev);
3800
3801         switch (type) {
3802         case TC_SETUP_BLOCK:
3803                 return stmmac_setup_tc_block(priv, type_data);
3804         case TC_SETUP_QDISC_CBS:
3805                 return stmmac_tc_setup_cbs(priv, priv, type_data);
3806         default:
3807                 return -EOPNOTSUPP;
3808         }
3809 }
3810
3811 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3812 {
3813         struct stmmac_priv *priv = netdev_priv(ndev);
3814         int ret = 0;
3815
3816         ret = eth_mac_addr(ndev, addr);
3817         if (ret)
3818                 return ret;
3819
3820         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3821
3822         return ret;
3823 }
3824
3825 #ifdef CONFIG_DEBUG_FS
3826 static struct dentry *stmmac_fs_dir;
3827
3828 static void sysfs_display_ring(void *head, int size, int extend_desc,
3829                                struct seq_file *seq)
3830 {
3831         int i;
3832         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3833         struct dma_desc *p = (struct dma_desc *)head;
3834
3835         for (i = 0; i < size; i++) {
3836                 if (extend_desc) {
3837                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3838                                    i, (unsigned int)virt_to_phys(ep),
3839                                    le32_to_cpu(ep->basic.des0),
3840                                    le32_to_cpu(ep->basic.des1),
3841                                    le32_to_cpu(ep->basic.des2),
3842                                    le32_to_cpu(ep->basic.des3));
3843                         ep++;
3844                 } else {
3845                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3846                                    i, (unsigned int)virt_to_phys(p),
3847                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3848                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3849                         p++;
3850                 }
3851                 seq_printf(seq, "\n");
3852         }
3853 }
3854
3855 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3856 {
3857         struct net_device *dev = seq->private;
3858         struct stmmac_priv *priv = netdev_priv(dev);
3859         u32 rx_count = priv->plat->rx_queues_to_use;
3860         u32 tx_count = priv->plat->tx_queues_to_use;
3861         u32 queue;
3862
3863         if ((dev->flags & IFF_UP) == 0)
3864                 return 0;
3865
3866         for (queue = 0; queue < rx_count; queue++) {
3867                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3868
3869                 seq_printf(seq, "RX Queue %d:\n", queue);
3870
3871                 if (priv->extend_desc) {
3872                         seq_printf(seq, "Extended descriptor ring:\n");
3873                         sysfs_display_ring((void *)rx_q->dma_erx,
3874                                            DMA_RX_SIZE, 1, seq);
3875                 } else {
3876                         seq_printf(seq, "Descriptor ring:\n");
3877                         sysfs_display_ring((void *)rx_q->dma_rx,
3878                                            DMA_RX_SIZE, 0, seq);
3879                 }
3880         }
3881
3882         for (queue = 0; queue < tx_count; queue++) {
3883                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3884
3885                 seq_printf(seq, "TX Queue %d:\n", queue);
3886
3887                 if (priv->extend_desc) {
3888                         seq_printf(seq, "Extended descriptor ring:\n");
3889                         sysfs_display_ring((void *)tx_q->dma_etx,
3890                                            DMA_TX_SIZE, 1, seq);
3891                 } else {
3892                         seq_printf(seq, "Descriptor ring:\n");
3893                         sysfs_display_ring((void *)tx_q->dma_tx,
3894                                            DMA_TX_SIZE, 0, seq);
3895                 }
3896         }
3897
3898         return 0;
3899 }
3900 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3901
3902 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3903 {
3904         struct net_device *dev = seq->private;
3905         struct stmmac_priv *priv = netdev_priv(dev);
3906
3907         if (!priv->hw_cap_support) {
3908                 seq_printf(seq, "DMA HW features not supported\n");
3909                 return 0;
3910         }
3911
3912         seq_printf(seq, "==============================\n");
3913         seq_printf(seq, "\tDMA HW features\n");
3914         seq_printf(seq, "==============================\n");
3915
3916         seq_printf(seq, "\t10/100 Mbps: %s\n",
3917                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3918         seq_printf(seq, "\t1000 Mbps: %s\n",
3919                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
3920         seq_printf(seq, "\tHalf duplex: %s\n",
3921                    (priv->dma_cap.half_duplex) ? "Y" : "N");
3922         seq_printf(seq, "\tHash Filter: %s\n",
3923                    (priv->dma_cap.hash_filter) ? "Y" : "N");
3924         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3925                    (priv->dma_cap.multi_addr) ? "Y" : "N");
3926         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3927                    (priv->dma_cap.pcs) ? "Y" : "N");
3928         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3929                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
3930         seq_printf(seq, "\tPMT Remote wake up: %s\n",
3931                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3932         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3933                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3934         seq_printf(seq, "\tRMON module: %s\n",
3935                    (priv->dma_cap.rmon) ? "Y" : "N");
3936         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3937                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3938         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3939                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3940         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3941                    (priv->dma_cap.eee) ? "Y" : "N");
3942         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3943         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3944                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3945         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3946                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3947                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3948         } else {
3949                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3950                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3951                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3952                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3953         }
3954         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3955                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3956         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3957                    priv->dma_cap.number_rx_channel);
3958         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3959                    priv->dma_cap.number_tx_channel);
3960         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3961                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3962
3963         return 0;
3964 }
3965 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
3966
3967 static int stmmac_init_fs(struct net_device *dev)
3968 {
3969         struct stmmac_priv *priv = netdev_priv(dev);
3970
3971         /* Create per netdev entries */
3972         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3973
3974         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3975                 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3976
3977                 return -ENOMEM;
3978         }
3979
3980         /* Entry to report DMA RX/TX rings */
3981         priv->dbgfs_rings_status =
3982                 debugfs_create_file("descriptors_status", 0444,
3983                                     priv->dbgfs_dir, dev,
3984                                     &stmmac_rings_status_fops);
3985
3986         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3987                 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3988                 debugfs_remove_recursive(priv->dbgfs_dir);
3989
3990                 return -ENOMEM;
3991         }
3992
3993         /* Entry to report the DMA HW features */
3994         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
3995                                                   priv->dbgfs_dir,
3996                                                   dev, &stmmac_dma_cap_fops);
3997
3998         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3999                 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4000                 debugfs_remove_recursive(priv->dbgfs_dir);
4001
4002                 return -ENOMEM;
4003         }
4004
4005         return 0;
4006 }
4007
4008 static void stmmac_exit_fs(struct net_device *dev)
4009 {
4010         struct stmmac_priv *priv = netdev_priv(dev);
4011
4012         debugfs_remove_recursive(priv->dbgfs_dir);
4013 }
4014 #endif /* CONFIG_DEBUG_FS */
4015
4016 static const struct net_device_ops stmmac_netdev_ops = {
4017         .ndo_open = stmmac_open,
4018         .ndo_start_xmit = stmmac_xmit,
4019         .ndo_stop = stmmac_release,
4020         .ndo_change_mtu = stmmac_change_mtu,
4021         .ndo_fix_features = stmmac_fix_features,
4022         .ndo_set_features = stmmac_set_features,
4023         .ndo_set_rx_mode = stmmac_set_rx_mode,
4024         .ndo_tx_timeout = stmmac_tx_timeout,
4025         .ndo_do_ioctl = stmmac_ioctl,
4026         .ndo_setup_tc = stmmac_setup_tc,
4027 #ifdef CONFIG_NET_POLL_CONTROLLER
4028         .ndo_poll_controller = stmmac_poll_controller,
4029 #endif
4030         .ndo_set_mac_address = stmmac_set_mac_address,
4031 };
4032
4033 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4034 {
4035         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4036                 return;
4037         if (test_bit(STMMAC_DOWN, &priv->state))
4038                 return;
4039
4040         netdev_err(priv->dev, "Reset adapter.\n");
4041
4042         rtnl_lock();
4043         netif_trans_update(priv->dev);
4044         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4045                 usleep_range(1000, 2000);
4046
4047         set_bit(STMMAC_DOWN, &priv->state);
4048         dev_close(priv->dev);
4049         dev_open(priv->dev, NULL);
4050         clear_bit(STMMAC_DOWN, &priv->state);
4051         clear_bit(STMMAC_RESETING, &priv->state);
4052         rtnl_unlock();
4053 }
4054
4055 static void stmmac_service_task(struct work_struct *work)
4056 {
4057         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4058                         service_task);
4059
4060         stmmac_reset_subtask(priv);
4061         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4062 }
4063
4064 /**
4065  *  stmmac_hw_init - Init the MAC device
4066  *  @priv: driver private structure
4067  *  Description: this function is to configure the MAC device according to
4068  *  some platform parameters or the HW capability register. It prepares the
4069  *  driver to use either ring or chain modes and to setup either enhanced or
4070  *  normal descriptors.
4071  */
4072 static int stmmac_hw_init(struct stmmac_priv *priv)
4073 {
4074         int ret;
4075
4076         /* dwmac-sun8i only work in chain mode */
4077         if (priv->plat->has_sun8i)
4078                 chain_mode = 1;
4079         priv->chain_mode = chain_mode;
4080
4081         /* Initialize HW Interface */
4082         ret = stmmac_hwif_init(priv);
4083         if (ret)
4084                 return ret;
4085
4086         /* Get the HW capability (new GMAC newer than 3.50a) */
4087         priv->hw_cap_support = stmmac_get_hw_features(priv);
4088         if (priv->hw_cap_support) {
4089                 dev_info(priv->device, "DMA HW capability register supported\n");
4090
4091                 /* We can override some gmac/dma configuration fields: e.g.
4092                  * enh_desc, tx_coe (e.g. that are passed through the
4093                  * platform) with the values from the HW capability
4094                  * register (if supported).
4095                  */
4096                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4097                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4098                 priv->hw->pmt = priv->plat->pmt;
4099
4100                 /* TXCOE doesn't work in thresh DMA mode */
4101                 if (priv->plat->force_thresh_dma_mode)
4102                         priv->plat->tx_coe = 0;
4103                 else
4104                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4105
4106                 /* In case of GMAC4 rx_coe is from HW cap register. */
4107                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4108
4109                 if (priv->dma_cap.rx_coe_type2)
4110                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4111                 else if (priv->dma_cap.rx_coe_type1)
4112                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4113
4114         } else {
4115                 dev_info(priv->device, "No HW DMA feature register supported\n");
4116         }
4117
4118         if (priv->plat->rx_coe) {
4119                 priv->hw->rx_csum = priv->plat->rx_coe;
4120                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4121                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4122                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4123         }
4124         if (priv->plat->tx_coe)
4125                 dev_info(priv->device, "TX Checksum insertion supported\n");
4126
4127         if (priv->plat->pmt) {
4128                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4129                 device_set_wakeup_capable(priv->device, 1);
4130         }
4131
4132         if (priv->dma_cap.tsoen)
4133                 dev_info(priv->device, "TSO supported\n");
4134
4135         /* Run HW quirks, if any */
4136         if (priv->hwif_quirks) {
4137                 ret = priv->hwif_quirks(priv);
4138                 if (ret)
4139                         return ret;
4140         }
4141
4142         /* Rx Watchdog is available in the COREs newer than the 3.40.
4143          * In some case, for example on bugged HW this feature
4144          * has to be disable and this can be done by passing the
4145          * riwt_off field from the platform.
4146          */
4147         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4148             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4149                 priv->use_riwt = 1;
4150                 dev_info(priv->device,
4151                          "Enable RX Mitigation via HW Watchdog Timer\n");
4152         }
4153
4154         return 0;
4155 }
4156
4157 /**
4158  * stmmac_dvr_probe
4159  * @device: device pointer
4160  * @plat_dat: platform data pointer
4161  * @res: stmmac resource pointer
4162  * Description: this is the main probe function used to
4163  * call the alloc_etherdev, allocate the priv structure.
4164  * Return:
4165  * returns 0 on success, otherwise errno.
4166  */
4167 int stmmac_dvr_probe(struct device *device,
4168                      struct plat_stmmacenet_data *plat_dat,
4169                      struct stmmac_resources *res)
4170 {
4171         struct net_device *ndev = NULL;
4172         struct stmmac_priv *priv;
4173         u32 queue, maxq;
4174         int ret = 0;
4175
4176         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4177                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4178         if (!ndev)
4179                 return -ENOMEM;
4180
4181         SET_NETDEV_DEV(ndev, device);
4182
4183         priv = netdev_priv(ndev);
4184         priv->device = device;
4185         priv->dev = ndev;
4186
4187         stmmac_set_ethtool_ops(ndev);
4188         priv->pause = pause;
4189         priv->plat = plat_dat;
4190         priv->ioaddr = res->addr;
4191         priv->dev->base_addr = (unsigned long)res->addr;
4192
4193         priv->dev->irq = res->irq;
4194         priv->wol_irq = res->wol_irq;
4195         priv->lpi_irq = res->lpi_irq;
4196
4197         if (!IS_ERR_OR_NULL(res->mac))
4198                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4199
4200         dev_set_drvdata(device, priv->dev);
4201
4202         /* Verify driver arguments */
4203         stmmac_verify_args();
4204
4205         /* Allocate workqueue */
4206         priv->wq = create_singlethread_workqueue("stmmac_wq");
4207         if (!priv->wq) {
4208                 dev_err(priv->device, "failed to create workqueue\n");
4209                 return -ENOMEM;
4210         }
4211
4212         INIT_WORK(&priv->service_task, stmmac_service_task);
4213
4214         /* Override with kernel parameters if supplied XXX CRS XXX
4215          * this needs to have multiple instances
4216          */
4217         if ((phyaddr >= 0) && (phyaddr <= 31))
4218                 priv->plat->phy_addr = phyaddr;
4219
4220         if (priv->plat->stmmac_rst) {
4221                 ret = reset_control_assert(priv->plat->stmmac_rst);
4222                 reset_control_deassert(priv->plat->stmmac_rst);
4223                 /* Some reset controllers have only reset callback instead of
4224                  * assert + deassert callbacks pair.
4225                  */
4226                 if (ret == -ENOTSUPP)
4227                         reset_control_reset(priv->plat->stmmac_rst);
4228         }
4229
4230         /* Init MAC and get the capabilities */
4231         ret = stmmac_hw_init(priv);
4232         if (ret)
4233                 goto error_hw_init;
4234
4235         stmmac_check_ether_addr(priv);
4236
4237         /* Configure real RX and TX queues */
4238         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4239         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4240
4241         ndev->netdev_ops = &stmmac_netdev_ops;
4242
4243         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4244                             NETIF_F_RXCSUM;
4245
4246         ret = stmmac_tc_init(priv, priv);
4247         if (!ret) {
4248                 ndev->hw_features |= NETIF_F_HW_TC;
4249         }
4250
4251         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4252                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4253                 priv->tso = true;
4254                 dev_info(priv->device, "TSO feature enabled\n");
4255         }
4256         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4257         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4258 #ifdef STMMAC_VLAN_TAG_USED
4259         /* Both mac100 and gmac support receive VLAN tag detection */
4260         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4261 #endif
4262         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4263
4264         /* MTU range: 46 - hw-specific max */
4265         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4266         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4267                 ndev->max_mtu = JUMBO_LEN;
4268         else if (priv->plat->has_xgmac)
4269                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4270         else
4271                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4272         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4273          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4274          */
4275         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4276             (priv->plat->maxmtu >= ndev->min_mtu))
4277                 ndev->max_mtu = priv->plat->maxmtu;
4278         else if (priv->plat->maxmtu < ndev->min_mtu)
4279                 dev_warn(priv->device,
4280                          "%s: warning: maxmtu having invalid value (%d)\n",
4281                          __func__, priv->plat->maxmtu);
4282
4283         if (flow_ctrl)
4284                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4285
4286         /* Setup channels NAPI */
4287         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4288
4289         for (queue = 0; queue < maxq; queue++) {
4290                 struct stmmac_channel *ch = &priv->channel[queue];
4291
4292                 ch->priv_data = priv;
4293                 ch->index = queue;
4294
4295                 if (queue < priv->plat->rx_queues_to_use) {
4296                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4297                                        NAPI_POLL_WEIGHT);
4298                 }
4299                 if (queue < priv->plat->tx_queues_to_use) {
4300                         netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4301                                        NAPI_POLL_WEIGHT);
4302                 }
4303         }
4304
4305         mutex_init(&priv->lock);
4306
4307         /* If a specific clk_csr value is passed from the platform
4308          * this means that the CSR Clock Range selection cannot be
4309          * changed at run-time and it is fixed. Viceversa the driver'll try to
4310          * set the MDC clock dynamically according to the csr actual
4311          * clock input.
4312          */
4313         if (priv->plat->clk_csr >= 0)
4314                 priv->clk_csr = priv->plat->clk_csr;
4315         else
4316                 stmmac_clk_csr_set(priv);
4317
4318         stmmac_check_pcs_mode(priv);
4319
4320         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
4321             priv->hw->pcs != STMMAC_PCS_TBI &&
4322             priv->hw->pcs != STMMAC_PCS_RTBI) {
4323                 /* MDIO bus Registration */
4324                 ret = stmmac_mdio_register(ndev);
4325                 if (ret < 0) {
4326                         dev_err(priv->device,
4327                                 "%s: MDIO bus (id: %d) registration failed",
4328                                 __func__, priv->plat->bus_id);
4329                         goto error_mdio_register;
4330                 }
4331         }
4332
4333         ret = stmmac_phy_setup(priv);
4334         if (ret) {
4335                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4336                 goto error_phy_setup;
4337         }
4338
4339         ret = register_netdev(ndev);
4340         if (ret) {
4341                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4342                         __func__, ret);
4343                 goto error_netdev_register;
4344         }
4345
4346 #ifdef CONFIG_DEBUG_FS
4347         ret = stmmac_init_fs(ndev);
4348         if (ret < 0)
4349                 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4350                             __func__);
4351 #endif
4352
4353         return ret;
4354
4355 error_netdev_register:
4356         phylink_destroy(priv->phylink);
4357 error_phy_setup:
4358         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4359             priv->hw->pcs != STMMAC_PCS_TBI &&
4360             priv->hw->pcs != STMMAC_PCS_RTBI)
4361                 stmmac_mdio_unregister(ndev);
4362 error_mdio_register:
4363         for (queue = 0; queue < maxq; queue++) {
4364                 struct stmmac_channel *ch = &priv->channel[queue];
4365
4366                 if (queue < priv->plat->rx_queues_to_use)
4367                         netif_napi_del(&ch->rx_napi);
4368                 if (queue < priv->plat->tx_queues_to_use)
4369                         netif_napi_del(&ch->tx_napi);
4370         }
4371 error_hw_init:
4372         destroy_workqueue(priv->wq);
4373
4374         return ret;
4375 }
4376 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4377
4378 /**
4379  * stmmac_dvr_remove
4380  * @dev: device pointer
4381  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4382  * changes the link status, releases the DMA descriptor rings.
4383  */
4384 int stmmac_dvr_remove(struct device *dev)
4385 {
4386         struct net_device *ndev = dev_get_drvdata(dev);
4387         struct stmmac_priv *priv = netdev_priv(ndev);
4388
4389         netdev_info(priv->dev, "%s: removing driver", __func__);
4390
4391 #ifdef CONFIG_DEBUG_FS
4392         stmmac_exit_fs(ndev);
4393 #endif
4394         stmmac_stop_all_dma(priv);
4395
4396         stmmac_mac_set(priv, priv->ioaddr, false);
4397         netif_carrier_off(ndev);
4398         unregister_netdev(ndev);
4399         phylink_destroy(priv->phylink);
4400         if (priv->plat->stmmac_rst)
4401                 reset_control_assert(priv->plat->stmmac_rst);
4402         clk_disable_unprepare(priv->plat->pclk);
4403         clk_disable_unprepare(priv->plat->stmmac_clk);
4404         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4405             priv->hw->pcs != STMMAC_PCS_TBI &&
4406             priv->hw->pcs != STMMAC_PCS_RTBI)
4407                 stmmac_mdio_unregister(ndev);
4408         destroy_workqueue(priv->wq);
4409         mutex_destroy(&priv->lock);
4410
4411         return 0;
4412 }
4413 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4414
4415 /**
4416  * stmmac_suspend - suspend callback
4417  * @dev: device pointer
4418  * Description: this is the function to suspend the device and it is called
4419  * by the platform driver to stop the network queue, release the resources,
4420  * program the PMT register (for WoL), clean and release driver resources.
4421  */
4422 int stmmac_suspend(struct device *dev)
4423 {
4424         struct net_device *ndev = dev_get_drvdata(dev);
4425         struct stmmac_priv *priv = netdev_priv(ndev);
4426
4427         if (!ndev || !netif_running(ndev))
4428                 return 0;
4429
4430         phylink_stop(priv->phylink);
4431
4432         mutex_lock(&priv->lock);
4433
4434         netif_device_detach(ndev);
4435         stmmac_stop_all_queues(priv);
4436
4437         stmmac_disable_all_queues(priv);
4438
4439         /* Stop TX/RX DMA */
4440         stmmac_stop_all_dma(priv);
4441
4442         /* Enable Power down mode by programming the PMT regs */
4443         if (device_may_wakeup(priv->device)) {
4444                 stmmac_pmt(priv, priv->hw, priv->wolopts);
4445                 priv->irq_wake = 1;
4446         } else {
4447                 stmmac_mac_set(priv, priv->ioaddr, false);
4448                 pinctrl_pm_select_sleep_state(priv->device);
4449                 /* Disable clock in case of PWM is off */
4450                 clk_disable(priv->plat->pclk);
4451                 clk_disable(priv->plat->stmmac_clk);
4452         }
4453         mutex_unlock(&priv->lock);
4454
4455         priv->speed = SPEED_UNKNOWN;
4456         return 0;
4457 }
4458 EXPORT_SYMBOL_GPL(stmmac_suspend);
4459
4460 /**
4461  * stmmac_reset_queues_param - reset queue parameters
4462  * @dev: device pointer
4463  */
4464 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4465 {
4466         u32 rx_cnt = priv->plat->rx_queues_to_use;
4467         u32 tx_cnt = priv->plat->tx_queues_to_use;
4468         u32 queue;
4469
4470         for (queue = 0; queue < rx_cnt; queue++) {
4471                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4472
4473                 rx_q->cur_rx = 0;
4474                 rx_q->dirty_rx = 0;
4475         }
4476
4477         for (queue = 0; queue < tx_cnt; queue++) {
4478                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4479
4480                 tx_q->cur_tx = 0;
4481                 tx_q->dirty_tx = 0;
4482                 tx_q->mss = 0;
4483         }
4484 }
4485
4486 /**
4487  * stmmac_resume - resume callback
4488  * @dev: device pointer
4489  * Description: when resume this function is invoked to setup the DMA and CORE
4490  * in a usable state.
4491  */
4492 int stmmac_resume(struct device *dev)
4493 {
4494         struct net_device *ndev = dev_get_drvdata(dev);
4495         struct stmmac_priv *priv = netdev_priv(ndev);
4496
4497         if (!netif_running(ndev))
4498                 return 0;
4499
4500         /* Power Down bit, into the PM register, is cleared
4501          * automatically as soon as a magic packet or a Wake-up frame
4502          * is received. Anyway, it's better to manually clear
4503          * this bit because it can generate problems while resuming
4504          * from another devices (e.g. serial console).
4505          */
4506         if (device_may_wakeup(priv->device)) {
4507                 mutex_lock(&priv->lock);
4508                 stmmac_pmt(priv, priv->hw, 0);
4509                 mutex_unlock(&priv->lock);
4510                 priv->irq_wake = 0;
4511         } else {
4512                 pinctrl_pm_select_default_state(priv->device);
4513                 /* enable the clk previously disabled */
4514                 clk_enable(priv->plat->stmmac_clk);
4515                 clk_enable(priv->plat->pclk);
4516                 /* reset the phy so that it's ready */
4517                 if (priv->mii)
4518                         stmmac_mdio_reset(priv->mii);
4519         }
4520
4521         netif_device_attach(ndev);
4522
4523         mutex_lock(&priv->lock);
4524
4525         stmmac_reset_queues_param(priv);
4526
4527         stmmac_clear_descriptors(priv);
4528
4529         stmmac_hw_setup(ndev, false);
4530         stmmac_init_tx_coalesce(priv);
4531         stmmac_set_rx_mode(ndev);
4532
4533         stmmac_enable_all_queues(priv);
4534
4535         stmmac_start_all_queues(priv);
4536
4537         mutex_unlock(&priv->lock);
4538
4539         phylink_start(priv->phylink);
4540
4541         return 0;
4542 }
4543 EXPORT_SYMBOL_GPL(stmmac_resume);
4544
4545 #ifndef MODULE
4546 static int __init stmmac_cmdline_opt(char *str)
4547 {
4548         char *opt;
4549
4550         if (!str || !*str)
4551                 return -EINVAL;
4552         while ((opt = strsep(&str, ",")) != NULL) {
4553                 if (!strncmp(opt, "debug:", 6)) {
4554                         if (kstrtoint(opt + 6, 0, &debug))
4555                                 goto err;
4556                 } else if (!strncmp(opt, "phyaddr:", 8)) {
4557                         if (kstrtoint(opt + 8, 0, &phyaddr))
4558                                 goto err;
4559                 } else if (!strncmp(opt, "buf_sz:", 7)) {
4560                         if (kstrtoint(opt + 7, 0, &buf_sz))
4561                                 goto err;
4562                 } else if (!strncmp(opt, "tc:", 3)) {
4563                         if (kstrtoint(opt + 3, 0, &tc))
4564                                 goto err;
4565                 } else if (!strncmp(opt, "watchdog:", 9)) {
4566                         if (kstrtoint(opt + 9, 0, &watchdog))
4567                                 goto err;
4568                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4569                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
4570                                 goto err;
4571                 } else if (!strncmp(opt, "pause:", 6)) {
4572                         if (kstrtoint(opt + 6, 0, &pause))
4573                                 goto err;
4574                 } else if (!strncmp(opt, "eee_timer:", 10)) {
4575                         if (kstrtoint(opt + 10, 0, &eee_timer))
4576                                 goto err;
4577                 } else if (!strncmp(opt, "chain_mode:", 11)) {
4578                         if (kstrtoint(opt + 11, 0, &chain_mode))
4579                                 goto err;
4580                 }
4581         }
4582         return 0;
4583
4584 err:
4585         pr_err("%s: ERROR broken module parameter conversion", __func__);
4586         return -EINVAL;
4587 }
4588
4589 __setup("stmmaceth=", stmmac_cmdline_opt);
4590 #endif /* MODULE */
4591
4592 static int __init stmmac_init(void)
4593 {
4594 #ifdef CONFIG_DEBUG_FS
4595         /* Create debugfs main directory if it doesn't exist yet */
4596         if (!stmmac_fs_dir) {
4597                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4598
4599                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4600                         pr_err("ERROR %s, debugfs create directory failed\n",
4601                                STMMAC_RESOURCE_NAME);
4602
4603                         return -ENOMEM;
4604                 }
4605         }
4606 #endif
4607
4608         return 0;
4609 }
4610
4611 static void __exit stmmac_exit(void)
4612 {
4613 #ifdef CONFIG_DEBUG_FS
4614         debugfs_remove_recursive(stmmac_fs_dir);
4615 #endif
4616 }
4617
4618 module_init(stmmac_init)
4619 module_exit(stmmac_exit)
4620
4621 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4622 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4623 MODULE_LICENSE("GPL");