drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/prefetch.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #ifdef CONFIG_DEBUG_FS
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #endif /* CONFIG_DEBUG_FS */
  38 #include <linux/net_tstamp.h>
  39 #include <linux/phylink.h>
  40 #include <linux/udp.h>
  41 #include <linux/bpf_trace.h>
  42 #include <net/pkt_cls.h>
  43 #include <net/xdp_sock_drv.h>
  44 #include "stmmac_ptp.h"
  45 #include "stmmac.h"
  46 #include "stmmac_xdp.h"
  47 #include <linux/reset.h>
  48 #include <linux/of_mdio.h>
  49 #include "dwmac1000.h"
  50 #include "dwxgmac2.h"
  51 #include "hwif.h"
  52
  53 /* As long as the interface is active, we keep the timestamping counter enabled
  54  * with fine resolution and binary rollover. This avoid non-monotonic behavior
  55  * (clock jumps) when changing timestamping settings at runtime.
  56  */
  57 #define STMMAC_HWTS_ACTIVE      (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
  58                                  PTP_TCR_TSCTRLSSR)
  59
  60 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  61 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  62
  63 /* Module parameters */
  64 #define TX_TIMEO        5000
  65 static int watchdog = TX_TIMEO;
  66 module_param(watchdog, int, 0644);
  67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  68
  69 static int debug = -1;
  70 module_param(debug, int, 0644);
  71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  72
  73 static int phyaddr = -1;
  74 module_param(phyaddr, int, 0444);
  75 MODULE_PARM_DESC(phyaddr, "Physical device address");
  76
  77 #define STMMAC_TX_THRESH(x)     ((x)->dma_tx_size / 4)
  78 #define STMMAC_RX_THRESH(x)     ((x)->dma_rx_size / 4)
  79
  80 /* Limit to make sure XDP TX and slow path can coexist */
  81 #define STMMAC_XSK_TX_BUDGET_MAX        256
  82 #define STMMAC_TX_XSK_AVAIL             16
  83 #define STMMAC_RX_FILL_BATCH            16
  84
  85 #define STMMAC_XDP_PASS         0
  86 #define STMMAC_XDP_CONSUMED     BIT(0)
  87 #define STMMAC_XDP_TX           BIT(1)
  88 #define STMMAC_XDP_REDIRECT     BIT(2)
  89
  90 static int flow_ctrl = FLOW_AUTO;
  91 module_param(flow_ctrl, int, 0644);
  92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  93
  94 static int pause = PAUSE_TIME;
  95 module_param(pause, int, 0644);
  96 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  97
  98 #define TC_DEFAULT 64
  99 static int tc = TC_DEFAULT;
 100 module_param(tc, int, 0644);
 101 MODULE_PARM_DESC(tc, "DMA threshold control value");
 102
 103 #define DEFAULT_BUFSIZE 1536
 104 static int buf_sz = DEFAULT_BUFSIZE;
 105 module_param(buf_sz, int, 0644);
 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 107
 108 #define STMMAC_RX_COPYBREAK     256
 109
 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 111                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 112                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 113
 114 #define STMMAC_DEFAULT_LPI_TIMER        1000
 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 116 module_param(eee_timer, int, 0644);
 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
 119
 120 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 121  * but allow user to force to use the chain instead of the ring
 122  */
 123 static unsigned int chain_mode;
 124 module_param(chain_mode, int, 0444);
 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 126
 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 128 /* For MSI interrupts handling */
 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
 133 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
 134 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
 135 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
 136                                           u32 rxmode, u32 chan);
 137
 138 #ifdef CONFIG_DEBUG_FS
 139 static const struct net_device_ops stmmac_netdev_ops;
 140 static void stmmac_init_fs(struct net_device *dev);
 141 static void stmmac_exit_fs(struct net_device *dev);
 142 #endif
 143
 144 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
 145
 146 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
 147 {
 148         int ret = 0;
 149
 150         if (enabled) {
 151                 ret = clk_prepare_enable(priv->plat->stmmac_clk);
 152                 if (ret)
 153                         return ret;
 154                 ret = clk_prepare_enable(priv->plat->pclk);
 155                 if (ret) {
 156                         clk_disable_unprepare(priv->plat->stmmac_clk);
 157                         return ret;
 158                 }
 159                 if (priv->plat->clks_config) {
 160                         ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 161                         if (ret) {
 162                                 clk_disable_unprepare(priv->plat->stmmac_clk);
 163                                 clk_disable_unprepare(priv->plat->pclk);
 164                                 return ret;
 165                         }
 166                 }
 167         } else {
 168                 clk_disable_unprepare(priv->plat->stmmac_clk);
 169                 clk_disable_unprepare(priv->plat->pclk);
 170                 if (priv->plat->clks_config)
 171                         priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 172         }
 173
 174         return ret;
 175 }
 176 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
 177
 178 /**
 179  * stmmac_verify_args - verify the driver parameters.
 180  * Description: it checks the driver parameters and set a default in case of
 181  * errors.
 182  */
 183 static void stmmac_verify_args(void)
 184 {
 185         if (unlikely(watchdog < 0))
 186                 watchdog = TX_TIMEO;
 187         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 188                 buf_sz = DEFAULT_BUFSIZE;
 189         if (unlikely(flow_ctrl > 1))
 190                 flow_ctrl = FLOW_AUTO;
 191         else if (likely(flow_ctrl < 0))
 192                 flow_ctrl = FLOW_OFF;
 193         if (unlikely((pause < 0) || (pause > 0xffff)))
 194                 pause = PAUSE_TIME;
 195         if (eee_timer < 0)
 196                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 197 }
 198
 199 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
 200 {
 201         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 202         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 203         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 204         u32 queue;
 205
 206         for (queue = 0; queue < maxq; queue++) {
 207                 struct stmmac_channel *ch = &priv->channel[queue];
 208
 209                 if (stmmac_xdp_is_enabled(priv) &&
 210                     test_bit(queue, priv->af_xdp_zc_qps)) {
 211                         napi_disable(&ch->rxtx_napi);
 212                         continue;
 213                 }
 214
 215                 if (queue < rx_queues_cnt)
 216                         napi_disable(&ch->rx_napi);
 217                 if (queue < tx_queues_cnt)
 218                         napi_disable(&ch->tx_napi);
 219         }
 220 }
 221
 222 /**
 223  * stmmac_disable_all_queues - Disable all queues
 224  * @priv: driver private structure
 225  */
 226 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 227 {
 228         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 229         struct stmmac_rx_queue *rx_q;
 230         u32 queue;
 231
 232         /* synchronize_rcu() needed for pending XDP buffers to drain */
 233         for (queue = 0; queue < rx_queues_cnt; queue++) {
 234                 rx_q = &priv->rx_queue[queue];
 235                 if (rx_q->xsk_pool) {
 236                         synchronize_rcu();
 237                         break;
 238                 }
 239         }
 240
 241         __stmmac_disable_all_queues(priv);
 242 }
 243
 244 /**
 245  * stmmac_enable_all_queues - Enable all queues
 246  * @priv: driver private structure
 247  */
 248 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 249 {
 250         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 251         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 252         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 253         u32 queue;
 254
 255         for (queue = 0; queue < maxq; queue++) {
 256                 struct stmmac_channel *ch = &priv->channel[queue];
 257
 258                 if (stmmac_xdp_is_enabled(priv) &&
 259                     test_bit(queue, priv->af_xdp_zc_qps)) {
 260                         napi_enable(&ch->rxtx_napi);
 261                         continue;
 262                 }
 263
 264                 if (queue < rx_queues_cnt)
 265                         napi_enable(&ch->rx_napi);
 266                 if (queue < tx_queues_cnt)
 267                         napi_enable(&ch->tx_napi);
 268         }
 269 }
 270
 271 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 272 {
 273         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 274             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 275                 queue_work(priv->wq, &priv->service_task);
 276 }
 277
 278 static void stmmac_global_err(struct stmmac_priv *priv)
 279 {
 280         netif_carrier_off(priv->dev);
 281         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 282         stmmac_service_event_schedule(priv);
 283 }
 284
 285 /**
 286  * stmmac_clk_csr_set - dynamically set the MDC clock
 287  * @priv: driver private structure
 288  * Description: this is to dynamically set the MDC clock according to the csr
 289  * clock input.
 290  * Note:
 291  *      If a specific clk_csr value is passed from the platform
 292  *      this means that the CSR Clock Range selection cannot be
 293  *      changed at run-time and it is fixed (as reported in the driver
 294  *      documentation). Viceversa the driver will try to set the MDC
 295  *      clock dynamically according to the actual clock input.
 296  */
 297 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 298 {
 299         u32 clk_rate;
 300
 301         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 302
 303         /* Platform provided default clk_csr would be assumed valid
 304          * for all other cases except for the below mentioned ones.
 305          * For values higher than the IEEE 802.3 specified frequency
 306          * we can not estimate the proper divider as it is not known
 307          * the frequency of clk_csr_i. So we do not change the default
 308          * divider.
 309          */
 310         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 311                 if (clk_rate < CSR_F_35M)
 312                         priv->clk_csr = STMMAC_CSR_20_35M;
 313                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 314                         priv->clk_csr = STMMAC_CSR_35_60M;
 315                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 316                         priv->clk_csr = STMMAC_CSR_60_100M;
 317                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 318                         priv->clk_csr = STMMAC_CSR_100_150M;
 319                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 320                         priv->clk_csr = STMMAC_CSR_150_250M;
 321                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 322                         priv->clk_csr = STMMAC_CSR_250_300M;
 323         }
 324
 325         if (priv->plat->has_sun8i) {
 326                 if (clk_rate > 160000000)
 327                         priv->clk_csr = 0x03;
 328                 else if (clk_rate > 80000000)
 329                         priv->clk_csr = 0x02;
 330                 else if (clk_rate > 40000000)
 331                         priv->clk_csr = 0x01;
 332                 else
 333                         priv->clk_csr = 0;
 334         }
 335
 336         if (priv->plat->has_xgmac) {
 337                 if (clk_rate > 400000000)
 338                         priv->clk_csr = 0x5;
 339                 else if (clk_rate > 350000000)
 340                         priv->clk_csr = 0x4;
 341                 else if (clk_rate > 300000000)
 342                         priv->clk_csr = 0x3;
 343                 else if (clk_rate > 250000000)
 344                         priv->clk_csr = 0x2;
 345                 else if (clk_rate > 150000000)
 346                         priv->clk_csr = 0x1;
 347                 else
 348                         priv->clk_csr = 0x0;
 349         }
 350 }
 351
 352 static void print_pkt(unsigned char *buf, int len)
 353 {
 354         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 355         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 356 }
 357
 358 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 359 {
 360         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 361         u32 avail;
 362
 363         if (tx_q->dirty_tx > tx_q->cur_tx)
 364                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 365         else
 366                 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
 367
 368         return avail;
 369 }
 370
 371 /**
 372  * stmmac_rx_dirty - Get RX queue dirty
 373  * @priv: driver private structure
 374  * @queue: RX queue index
 375  */
 376 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 377 {
 378         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 379         u32 dirty;
 380
 381         if (rx_q->dirty_rx <= rx_q->cur_rx)
 382                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 383         else
 384                 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
 385
 386         return dirty;
 387 }
 388
 389 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
 390 {
 391         int tx_lpi_timer;
 392
 393         /* Clear/set the SW EEE timer flag based on LPI ET enablement */
 394         priv->eee_sw_timer_en = en ? 0 : 1;
 395         tx_lpi_timer  = en ? priv->tx_lpi_timer : 0;
 396         stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
 397 }
 398
 399 /**
 400  * stmmac_enable_eee_mode - check and enter in LPI mode
 401  * @priv: driver private structure
 402  * Description: this function is to verify and enter in LPI mode in case of
 403  * EEE.
 404  */
 405 static int stmmac_enable_eee_mode(struct stmmac_priv *priv)
 406 {
 407         u32 tx_cnt = priv->plat->tx_queues_to_use;
 408         u32 queue;
 409
 410         /* check if all TX queues have the work finished */
 411         for (queue = 0; queue < tx_cnt; queue++) {
 412                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 413
 414                 if (tx_q->dirty_tx != tx_q->cur_tx)
 415                         return -EBUSY; /* still unfinished work */
 416         }
 417
 418         /* Check and enter in LPI mode */
 419         if (!priv->tx_path_in_lpi_mode)
 420                 stmmac_set_eee_mode(priv, priv->hw,
 421                                 priv->plat->en_tx_lpi_clockgating);
 422         return 0;
 423 }
 424
 425 /**
 426  * stmmac_disable_eee_mode - disable and exit from LPI mode
 427  * @priv: driver private structure
 428  * Description: this function is to exit and disable EEE in case of
 429  * LPI state is true. This is called by the xmit.
 430  */
 431 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 432 {
 433         if (!priv->eee_sw_timer_en) {
 434                 stmmac_lpi_entry_timer_config(priv, 0);
 435                 return;
 436         }
 437
 438         stmmac_reset_eee_mode(priv, priv->hw);
 439         del_timer_sync(&priv->eee_ctrl_timer);
 440         priv->tx_path_in_lpi_mode = false;
 441 }
 442
 443 /**
 444  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 445  * @t:  timer_list struct containing private info
 446  * Description:
 447  *  if there is no data transfer and if we are not in LPI state,
 448  *  then MAC Transmitter can be moved to LPI state.
 449  */
 450 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 451 {
 452         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 453
 454         if (stmmac_enable_eee_mode(priv))
 455                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
 456 }
 457
 458 /**
 459  * stmmac_eee_init - init EEE
 460  * @priv: driver private structure
 461  * Description:
 462  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 463  *  can also manage EEE, this function enable the LPI state and start related
 464  *  timer.
 465  */
 466 bool stmmac_eee_init(struct stmmac_priv *priv)
 467 {
 468         int eee_tw_timer = priv->eee_tw_timer;
 469
 470         /* Using PCS we cannot dial with the phy registers at this stage
 471          * so we do not support extra feature like EEE.
 472          */
 473         if (priv->hw->pcs == STMMAC_PCS_TBI ||
 474             priv->hw->pcs == STMMAC_PCS_RTBI)
 475                 return false;
 476
 477         /* Check if MAC core supports the EEE feature. */
 478         if (!priv->dma_cap.eee)
 479                 return false;
 480
 481         mutex_lock(&priv->lock);
 482
 483         /* Check if it needs to be deactivated */
 484         if (!priv->eee_active) {
 485                 if (priv->eee_enabled) {
 486                         netdev_dbg(priv->dev, "disable EEE\n");
 487                         stmmac_lpi_entry_timer_config(priv, 0);
 488                         del_timer_sync(&priv->eee_ctrl_timer);
 489                         stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
 490                         if (priv->hw->xpcs)
 491                                 xpcs_config_eee(priv->hw->xpcs,
 492                                                 priv->plat->mult_fact_100ns,
 493                                                 false);
 494                 }
 495                 mutex_unlock(&priv->lock);
 496                 return false;
 497         }
 498
 499         if (priv->eee_active && !priv->eee_enabled) {
 500                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 501                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 502                                      eee_tw_timer);
 503                 if (priv->hw->xpcs)
 504                         xpcs_config_eee(priv->hw->xpcs,
 505                                         priv->plat->mult_fact_100ns,
 506                                         true);
 507         }
 508
 509         if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
 510                 del_timer_sync(&priv->eee_ctrl_timer);
 511                 priv->tx_path_in_lpi_mode = false;
 512                 stmmac_lpi_entry_timer_config(priv, 1);
 513         } else {
 514                 stmmac_lpi_entry_timer_config(priv, 0);
 515                 mod_timer(&priv->eee_ctrl_timer,
 516                           STMMAC_LPI_T(priv->tx_lpi_timer));
 517         }
 518
 519         mutex_unlock(&priv->lock);
 520         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 521         return true;
 522 }
 523
 524 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 525  * @priv: driver private structure
 526  * @p : descriptor pointer
 527  * @skb : the socket buffer
 528  * Description :
 529  * This function will read timestamp from the descriptor & pass it to stack.
 530  * and also perform some sanity checks.
 531  */
 532 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 533                                    struct dma_desc *p, struct sk_buff *skb)
 534 {
 535         struct skb_shared_hwtstamps shhwtstamp;
 536         bool found = false;
 537         u64 ns = 0;
 538
 539         if (!priv->hwts_tx_en)
 540                 return;
 541
 542         /* exit if skb doesn't support hw tstamp */
 543         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 544                 return;
 545
 546         /* check tx tstamp status */
 547         if (stmmac_get_tx_timestamp_status(priv, p)) {
 548                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 549                 found = true;
 550         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 551                 found = true;
 552         }
 553
 554         if (found) {
 555                 ns -= priv->plat->cdc_error_adj;
 556
 557                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 558                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 559
 560                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 561                 /* pass tstamp to stack */
 562                 skb_tstamp_tx(skb, &shhwtstamp);
 563         }
 564 }
 565
 566 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 567  * @priv: driver private structure
 568  * @p : descriptor pointer
 569  * @np : next descriptor pointer
 570  * @skb : the socket buffer
 571  * Description :
 572  * This function will read received packet's timestamp from the descriptor
 573  * and pass it to stack. It also perform some sanity checks.
 574  */
 575 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 576                                    struct dma_desc *np, struct sk_buff *skb)
 577 {
 578         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 579         struct dma_desc *desc = p;
 580         u64 ns = 0;
 581
 582         if (!priv->hwts_rx_en)
 583                 return;
 584         /* For GMAC4, the valid timestamp is from CTX next desc. */
 585         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 586                 desc = np;
 587
 588         /* Check if timestamp is available */
 589         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 590                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 591
 592                 ns -= priv->plat->cdc_error_adj;
 593
 594                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 595                 shhwtstamp = skb_hwtstamps(skb);
 596                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 597                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 598         } else  {
 599                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 600         }
 601 }
 602
 603 /**
 604  *  stmmac_hwtstamp_set - control hardware timestamping.
 605  *  @dev: device pointer.
 606  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 607  *  a proprietary structure used to pass information to the driver.
 608  *  Description:
 609  *  This function configures the MAC to enable/disable both outgoing(TX)
 610  *  and incoming(RX) packets time stamping based on user input.
 611  *  Return Value:
 612  *  0 on success and an appropriate -ve integer on failure.
 613  */
 614 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 615 {
 616         struct stmmac_priv *priv = netdev_priv(dev);
 617         struct hwtstamp_config config;
 618         u32 ptp_v2 = 0;
 619         u32 tstamp_all = 0;
 620         u32 ptp_over_ipv4_udp = 0;
 621         u32 ptp_over_ipv6_udp = 0;
 622         u32 ptp_over_ethernet = 0;
 623         u32 snap_type_sel = 0;
 624         u32 ts_master_en = 0;
 625         u32 ts_event_en = 0;
 626
 627         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 628                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 629                 priv->hwts_tx_en = 0;
 630                 priv->hwts_rx_en = 0;
 631
 632                 return -EOPNOTSUPP;
 633         }
 634
 635         if (copy_from_user(&config, ifr->ifr_data,
 636                            sizeof(config)))
 637                 return -EFAULT;
 638
 639         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 640                    __func__, config.flags, config.tx_type, config.rx_filter);
 641
 642         if (config.tx_type != HWTSTAMP_TX_OFF &&
 643             config.tx_type != HWTSTAMP_TX_ON)
 644                 return -ERANGE;
 645
 646         if (priv->adv_ts) {
 647                 switch (config.rx_filter) {
 648                 case HWTSTAMP_FILTER_NONE:
 649                         /* time stamp no incoming packet at all */
 650                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 651                         break;
 652
 653                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 654                         /* PTP v1, UDP, any kind of event packet */
 655                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 656                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 657                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 658                          * This leaves Delay_Req timestamps out.
 659                          * Enable all events *and* general purpose message
 660                          * timestamping
 661                          */
 662                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 663                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 664                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 665                         break;
 666
 667                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 668                         /* PTP v1, UDP, Sync packet */
 669                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 670                         /* take time stamp for SYNC messages only */
 671                         ts_event_en = PTP_TCR_TSEVNTENA;
 672
 673                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 674                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 675                         break;
 676
 677                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 678                         /* PTP v1, UDP, Delay_req packet */
 679                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 680                         /* take time stamp for Delay_Req messages only */
 681                         ts_master_en = PTP_TCR_TSMSTRENA;
 682                         ts_event_en = PTP_TCR_TSEVNTENA;
 683
 684                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 685                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 686                         break;
 687
 688                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 689                         /* PTP v2, UDP, any kind of event packet */
 690                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 691                         ptp_v2 = PTP_TCR_TSVER2ENA;
 692                         /* take time stamp for all event messages */
 693                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 694
 695                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 696                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 697                         break;
 698
 699                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 700                         /* PTP v2, UDP, Sync packet */
 701                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 702                         ptp_v2 = PTP_TCR_TSVER2ENA;
 703                         /* take time stamp for SYNC messages only */
 704                         ts_event_en = PTP_TCR_TSEVNTENA;
 705
 706                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 707                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 708                         break;
 709
 710                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 711                         /* PTP v2, UDP, Delay_req packet */
 712                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 713                         ptp_v2 = PTP_TCR_TSVER2ENA;
 714                         /* take time stamp for Delay_Req messages only */
 715                         ts_master_en = PTP_TCR_TSMSTRENA;
 716                         ts_event_en = PTP_TCR_TSEVNTENA;
 717
 718                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 719                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 720                         break;
 721
 722                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 723                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 724                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 725                         ptp_v2 = PTP_TCR_TSVER2ENA;
 726                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 727                         if (priv->synopsys_id < DWMAC_CORE_4_10)
 728                                 ts_event_en = PTP_TCR_TSEVNTENA;
 729                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 730                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 731                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 732                         break;
 733
 734                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 735                         /* PTP v2/802.AS1, any layer, Sync packet */
 736                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 737                         ptp_v2 = PTP_TCR_TSVER2ENA;
 738                         /* take time stamp for SYNC messages only */
 739                         ts_event_en = PTP_TCR_TSEVNTENA;
 740
 741                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 742                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 743                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 744                         break;
 745
 746                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 747                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 748                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 749                         ptp_v2 = PTP_TCR_TSVER2ENA;
 750                         /* take time stamp for Delay_Req messages only */
 751                         ts_master_en = PTP_TCR_TSMSTRENA;
 752                         ts_event_en = PTP_TCR_TSEVNTENA;
 753
 754                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 755                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 756                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 757                         break;
 758
 759                 case HWTSTAMP_FILTER_NTP_ALL:
 760                 case HWTSTAMP_FILTER_ALL:
 761                         /* time stamp any incoming packet */
 762                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 763                         tstamp_all = PTP_TCR_TSENALL;
 764                         break;
 765
 766                 default:
 767                         return -ERANGE;
 768                 }
 769         } else {
 770                 switch (config.rx_filter) {
 771                 case HWTSTAMP_FILTER_NONE:
 772                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 773                         break;
 774                 default:
 775                         /* PTP v1, UDP, any kind of event packet */
 776                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 777                         break;
 778                 }
 779         }
 780         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 781         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 782
 783         priv->systime_flags = STMMAC_HWTS_ACTIVE;
 784
 785         if (priv->hwts_tx_en || priv->hwts_rx_en) {
 786                 priv->systime_flags |= tstamp_all | ptp_v2 |
 787                                        ptp_over_ethernet | ptp_over_ipv6_udp |
 788                                        ptp_over_ipv4_udp | ts_event_en |
 789                                        ts_master_en | snap_type_sel;
 790         }
 791
 792         stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags);
 793
 794         memcpy(&priv->tstamp_config, &config, sizeof(config));
 795
 796         return copy_to_user(ifr->ifr_data, &config,
 797                             sizeof(config)) ? -EFAULT : 0;
 798 }
 799
 800 /**
 801  *  stmmac_hwtstamp_get - read hardware timestamping.
 802  *  @dev: device pointer.
 803  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 804  *  a proprietary structure used to pass information to the driver.
 805  *  Description:
 806  *  This function obtain the current hardware timestamping settings
 807  *  as requested.
 808  */
 809 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 810 {
 811         struct stmmac_priv *priv = netdev_priv(dev);
 812         struct hwtstamp_config *config = &priv->tstamp_config;
 813
 814         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 815                 return -EOPNOTSUPP;
 816
 817         return copy_to_user(ifr->ifr_data, config,
 818                             sizeof(*config)) ? -EFAULT : 0;
 819 }
 820
 821 /**
 822  * stmmac_init_tstamp_counter - init hardware timestamping counter
 823  * @priv: driver private structure
 824  * @systime_flags: timestamping flags
 825  * Description:
 826  * Initialize hardware counter for packet timestamping.
 827  * This is valid as long as the interface is open and not suspended.
 828  * Will be rerun after resuming from suspend, case in which the timestamping
 829  * flags updated by stmmac_hwtstamp_set() also need to be restored.
 830  */
 831 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)
 832 {
 833         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 834         struct timespec64 now;
 835         u32 sec_inc = 0;
 836         u64 temp = 0;
 837         int ret;
 838
 839         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 840                 return -EOPNOTSUPP;
 841
 842         ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
 843         if (ret < 0) {
 844                 netdev_warn(priv->dev,
 845                             "failed to enable PTP reference clock: %pe\n",
 846                             ERR_PTR(ret));
 847                 return ret;
 848         }
 849
 850         stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags);
 851         priv->systime_flags = systime_flags;
 852
 853         /* program Sub Second Increment reg */
 854         stmmac_config_sub_second_increment(priv, priv->ptpaddr,
 855                                            priv->plat->clk_ptp_rate,
 856                                            xmac, &sec_inc);
 857         temp = div_u64(1000000000ULL, sec_inc);
 858
 859         /* Store sub second increment for later use */
 860         priv->sub_second_inc = sec_inc;
 861
 862         /* calculate default added value:
 863          * formula is :
 864          * addend = (2^32)/freq_div_ratio;
 865          * where, freq_div_ratio = 1e9ns/sec_inc
 866          */
 867         temp = (u64)(temp << 32);
 868         priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 869         stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 870
 871         /* initialize system time */
 872         ktime_get_real_ts64(&now);
 873
 874         /* lower 32 bits of tv_sec are safe until y2106 */
 875         stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec);
 876
 877         return 0;
 878 }
 879 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter);
 880
 881 /**
 882  * stmmac_init_ptp - init PTP
 883  * @priv: driver private structure
 884  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 885  * This is done by looking at the HW cap. register.
 886  * This function also registers the ptp driver.
 887  */
 888 static int stmmac_init_ptp(struct stmmac_priv *priv)
 889 {
 890         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 891         int ret;
 892
 893         if (priv->plat->ptp_clk_freq_config)
 894                 priv->plat->ptp_clk_freq_config(priv);
 895
 896         ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
 897         if (ret)
 898                 return ret;
 899
 900         priv->adv_ts = 0;
 901         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 902         if (xmac && priv->dma_cap.atime_stamp)
 903                 priv->adv_ts = 1;
 904         /* Dwmac 3.x core with extend_desc can support adv_ts */
 905         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 906                 priv->adv_ts = 1;
 907
 908         if (priv->dma_cap.time_stamp)
 909                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 910
 911         if (priv->adv_ts)
 912                 netdev_info(priv->dev,
 913                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 914
 915         priv->hwts_tx_en = 0;
 916         priv->hwts_rx_en = 0;
 917
 918         return 0;
 919 }
 920
 921 static void stmmac_release_ptp(struct stmmac_priv *priv)
 922 {
 923         clk_disable_unprepare(priv->plat->clk_ptp_ref);
 924         stmmac_ptp_unregister(priv);
 925 }
 926
 927 /**
 928  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 929  *  @priv: driver private structure
 930  *  @duplex: duplex passed to the next function
 931  *  Description: It is used for configuring the flow control in all queues
 932  */
 933 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 934 {
 935         u32 tx_cnt = priv->plat->tx_queues_to_use;
 936
 937         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 938                         priv->pause, tx_cnt);
 939 }
 940
 941 static void stmmac_validate(struct phylink_config *config,
 942                             unsigned long *supported,
 943                             struct phylink_link_state *state)
 944 {
 945         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 946         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 947         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 948         int tx_cnt = priv->plat->tx_queues_to_use;
 949         int max_speed = priv->plat->max_speed;
 950
 951         phylink_set(mac_supported, 10baseT_Half);
 952         phylink_set(mac_supported, 10baseT_Full);
 953         phylink_set(mac_supported, 100baseT_Half);
 954         phylink_set(mac_supported, 100baseT_Full);
 955         phylink_set(mac_supported, 1000baseT_Half);
 956         phylink_set(mac_supported, 1000baseT_Full);
 957         phylink_set(mac_supported, 1000baseKX_Full);
 958
 959         phylink_set(mac_supported, Autoneg);
 960         phylink_set(mac_supported, Pause);
 961         phylink_set(mac_supported, Asym_Pause);
 962         phylink_set_port_modes(mac_supported);
 963
 964         /* Cut down 1G if asked to */
 965         if ((max_speed > 0) && (max_speed < 1000)) {
 966                 phylink_set(mask, 1000baseT_Full);
 967                 phylink_set(mask, 1000baseX_Full);
 968         } else if (priv->plat->has_gmac4) {
 969                 if (!max_speed || max_speed >= 2500) {
 970                         phylink_set(mac_supported, 2500baseT_Full);
 971                         phylink_set(mac_supported, 2500baseX_Full);
 972                 }
 973         } else if (priv->plat->has_xgmac) {
 974                 if (!max_speed || (max_speed >= 2500)) {
 975                         phylink_set(mac_supported, 2500baseT_Full);
 976                         phylink_set(mac_supported, 2500baseX_Full);
 977                 }
 978                 if (!max_speed || (max_speed >= 5000)) {
 979                         phylink_set(mac_supported, 5000baseT_Full);
 980                 }
 981                 if (!max_speed || (max_speed >= 10000)) {
 982                         phylink_set(mac_supported, 10000baseSR_Full);
 983                         phylink_set(mac_supported, 10000baseLR_Full);
 984                         phylink_set(mac_supported, 10000baseER_Full);
 985                         phylink_set(mac_supported, 10000baseLRM_Full);
 986                         phylink_set(mac_supported, 10000baseT_Full);
 987                         phylink_set(mac_supported, 10000baseKX4_Full);
 988                         phylink_set(mac_supported, 10000baseKR_Full);
 989                 }
 990                 if (!max_speed || (max_speed >= 25000)) {
 991                         phylink_set(mac_supported, 25000baseCR_Full);
 992                         phylink_set(mac_supported, 25000baseKR_Full);
 993                         phylink_set(mac_supported, 25000baseSR_Full);
 994                 }
 995                 if (!max_speed || (max_speed >= 40000)) {
 996                         phylink_set(mac_supported, 40000baseKR4_Full);
 997                         phylink_set(mac_supported, 40000baseCR4_Full);
 998                         phylink_set(mac_supported, 40000baseSR4_Full);
 999                         phylink_set(mac_supported, 40000baseLR4_Full);
1000                 }
1001                 if (!max_speed || (max_speed >= 50000)) {
1002                         phylink_set(mac_supported, 50000baseCR2_Full);
1003                         phylink_set(mac_supported, 50000baseKR2_Full);
1004                         phylink_set(mac_supported, 50000baseSR2_Full);
1005                         phylink_set(mac_supported, 50000baseKR_Full);
1006                         phylink_set(mac_supported, 50000baseSR_Full);
1007                         phylink_set(mac_supported, 50000baseCR_Full);
1008                         phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
1009                         phylink_set(mac_supported, 50000baseDR_Full);
1010                 }
1011                 if (!max_speed || (max_speed >= 100000)) {
1012                         phylink_set(mac_supported, 100000baseKR4_Full);
1013                         phylink_set(mac_supported, 100000baseSR4_Full);
1014                         phylink_set(mac_supported, 100000baseCR4_Full);
1015                         phylink_set(mac_supported, 100000baseLR4_ER4_Full);
1016                         phylink_set(mac_supported, 100000baseKR2_Full);
1017                         phylink_set(mac_supported, 100000baseSR2_Full);
1018                         phylink_set(mac_supported, 100000baseCR2_Full);
1019                         phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
1020                         phylink_set(mac_supported, 100000baseDR2_Full);
1021                 }
1022         }
1023
1024         /* Half-Duplex can only work with single queue */
1025         if (tx_cnt > 1) {
1026                 phylink_set(mask, 10baseT_Half);
1027                 phylink_set(mask, 100baseT_Half);
1028                 phylink_set(mask, 1000baseT_Half);
1029         }
1030
1031         linkmode_and(supported, supported, mac_supported);
1032         linkmode_andnot(supported, supported, mask);
1033
1034         linkmode_and(state->advertising, state->advertising, mac_supported);
1035         linkmode_andnot(state->advertising, state->advertising, mask);
1036
1037         /* If PCS is supported, check which modes it supports. */
1038         if (priv->hw->xpcs)
1039                 xpcs_validate(priv->hw->xpcs, supported, state);
1040 }
1041
1042 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
1043                               const struct phylink_link_state *state)
1044 {
1045         /* Nothing to do, xpcs_config() handles everything */
1046 }
1047
1048 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
1049 {
1050         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
1051         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
1052         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
1053         bool *hs_enable = &fpe_cfg->hs_enable;
1054
1055         if (is_up && *hs_enable) {
1056                 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
1057         } else {
1058                 *lo_state = FPE_STATE_OFF;
1059                 *lp_state = FPE_STATE_OFF;
1060         }
1061 }
1062
1063 static void stmmac_mac_link_down(struct phylink_config *config,
1064                                  unsigned int mode, phy_interface_t interface)
1065 {
1066         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1067
1068         stmmac_mac_set(priv, priv->ioaddr, false);
1069         priv->eee_active = false;
1070         priv->tx_lpi_enabled = false;
1071         priv->eee_enabled = stmmac_eee_init(priv);
1072         stmmac_set_eee_pls(priv, priv->hw, false);
1073
1074         if (priv->dma_cap.fpesel)
1075                 stmmac_fpe_link_state_handle(priv, false);
1076 }
1077
1078 static void stmmac_mac_link_up(struct phylink_config *config,
1079                                struct phy_device *phy,
1080                                unsigned int mode, phy_interface_t interface,
1081                                int speed, int duplex,
1082                                bool tx_pause, bool rx_pause)
1083 {
1084         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1085         u32 ctrl;
1086
1087         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
1088         ctrl &= ~priv->hw->link.speed_mask;
1089
1090         if (interface == PHY_INTERFACE_MODE_USXGMII) {
1091                 switch (speed) {
1092                 case SPEED_10000:
1093                         ctrl |= priv->hw->link.xgmii.speed10000;
1094                         break;
1095                 case SPEED_5000:
1096                         ctrl |= priv->hw->link.xgmii.speed5000;
1097                         break;
1098                 case SPEED_2500:
1099                         ctrl |= priv->hw->link.xgmii.speed2500;
1100                         break;
1101                 default:
1102                         return;
1103                 }
1104         } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1105                 switch (speed) {
1106                 case SPEED_100000:
1107                         ctrl |= priv->hw->link.xlgmii.speed100000;
1108                         break;
1109                 case SPEED_50000:
1110                         ctrl |= priv->hw->link.xlgmii.speed50000;
1111                         break;
1112                 case SPEED_40000:
1113                         ctrl |= priv->hw->link.xlgmii.speed40000;
1114                         break;
1115                 case SPEED_25000:
1116                         ctrl |= priv->hw->link.xlgmii.speed25000;
1117                         break;
1118                 case SPEED_10000:
1119                         ctrl |= priv->hw->link.xgmii.speed10000;
1120                         break;
1121                 case SPEED_2500:
1122                         ctrl |= priv->hw->link.speed2500;
1123                         break;
1124                 case SPEED_1000:
1125                         ctrl |= priv->hw->link.speed1000;
1126                         break;
1127                 default:
1128                         return;
1129                 }
1130         } else {
1131                 switch (speed) {
1132                 case SPEED_2500:
1133                         ctrl |= priv->hw->link.speed2500;
1134                         break;
1135                 case SPEED_1000:
1136                         ctrl |= priv->hw->link.speed1000;
1137                         break;
1138                 case SPEED_100:
1139                         ctrl |= priv->hw->link.speed100;
1140                         break;
1141                 case SPEED_10:
1142                         ctrl |= priv->hw->link.speed10;
1143                         break;
1144                 default:
1145                         return;
1146                 }
1147         }
1148
1149         priv->speed = speed;
1150
1151         if (priv->plat->fix_mac_speed)
1152                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1153
1154         if (!duplex)
1155                 ctrl &= ~priv->hw->link.duplex;
1156         else
1157                 ctrl |= priv->hw->link.duplex;
1158
1159         /* Flow Control operation */
1160         if (tx_pause && rx_pause)
1161                 stmmac_mac_flow_ctrl(priv, duplex);
1162
1163         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1164
1165         stmmac_mac_set(priv, priv->ioaddr, true);
1166         if (phy && priv->dma_cap.eee) {
1167                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1168                 priv->eee_enabled = stmmac_eee_init(priv);
1169                 priv->tx_lpi_enabled = priv->eee_enabled;
1170                 stmmac_set_eee_pls(priv, priv->hw, true);
1171         }
1172
1173         if (priv->dma_cap.fpesel)
1174                 stmmac_fpe_link_state_handle(priv, true);
1175 }
1176
1177 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1178         .validate = stmmac_validate,
1179         .mac_config = stmmac_mac_config,
1180         .mac_link_down = stmmac_mac_link_down,
1181         .mac_link_up = stmmac_mac_link_up,
1182 };
1183
1184 /**
1185  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1186  * @priv: driver private structure
1187  * Description: this is to verify if the HW supports the PCS.
1188  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1189  * configured for the TBI, RTBI, or SGMII PHY interface.
1190  */
1191 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1192 {
1193         int interface = priv->plat->interface;
1194
1195         if (priv->dma_cap.pcs) {
1196                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1197                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1198                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1199                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1200                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1201                         priv->hw->pcs = STMMAC_PCS_RGMII;
1202                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1203                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1204                         priv->hw->pcs = STMMAC_PCS_SGMII;
1205                 }
1206         }
1207 }
1208
1209 /**
1210  * stmmac_init_phy - PHY initialization
1211  * @dev: net device structure
1212  * Description: it initializes the driver's PHY state, and attaches the PHY
1213  * to the mac driver.
1214  *  Return value:
1215  *  0 on success
1216  */
1217 static int stmmac_init_phy(struct net_device *dev)
1218 {
1219         struct stmmac_priv *priv = netdev_priv(dev);
1220         struct device_node *node;
1221         int ret;
1222
1223         node = priv->plat->phylink_node;
1224
1225         if (node)
1226                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1227
1228         /* Some DT bindings do not set-up the PHY handle. Let's try to
1229          * manually parse it
1230          */
1231         if (!node || ret) {
1232                 int addr = priv->plat->phy_addr;
1233                 struct phy_device *phydev;
1234
1235                 phydev = mdiobus_get_phy(priv->mii, addr);
1236                 if (!phydev) {
1237                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1238                         return -ENODEV;
1239                 }
1240
1241                 ret = phylink_connect_phy(priv->phylink, phydev);
1242         }
1243
1244         if (!priv->plat->pmt) {
1245                 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1246
1247                 phylink_ethtool_get_wol(priv->phylink, &wol);
1248                 device_set_wakeup_capable(priv->device, !!wol.supported);
1249         }
1250
1251         return ret;
1252 }
1253
1254 static int stmmac_phy_setup(struct stmmac_priv *priv)
1255 {
1256         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1257         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1258         int mode = priv->plat->phy_interface;
1259         struct phylink *phylink;
1260
1261         priv->phylink_config.dev = &priv->dev->dev;
1262         priv->phylink_config.type = PHYLINK_NETDEV;
1263         priv->phylink_config.pcs_poll = true;
1264         if (priv->plat->mdio_bus_data)
1265                 priv->phylink_config.ovr_an_inband =
1266                         mdio_bus_data->xpcs_an_inband;
1267
1268         if (!fwnode)
1269                 fwnode = dev_fwnode(priv->device);
1270
1271         phylink = phylink_create(&priv->phylink_config, fwnode,
1272                                  mode, &stmmac_phylink_mac_ops);
1273         if (IS_ERR(phylink))
1274                 return PTR_ERR(phylink);
1275
1276         if (priv->hw->xpcs)
1277                 phylink_set_pcs(phylink, &priv->hw->xpcs->pcs);
1278
1279         priv->phylink = phylink;
1280         return 0;
1281 }
1282
1283 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1284 {
1285         u32 rx_cnt = priv->plat->rx_queues_to_use;
1286         unsigned int desc_size;
1287         void *head_rx;
1288         u32 queue;
1289
1290         /* Display RX rings */
1291         for (queue = 0; queue < rx_cnt; queue++) {
1292                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1293
1294                 pr_info("\tRX Queue %u rings\n", queue);
1295
1296                 if (priv->extend_desc) {
1297                         head_rx = (void *)rx_q->dma_erx;
1298                         desc_size = sizeof(struct dma_extended_desc);
1299                 } else {
1300                         head_rx = (void *)rx_q->dma_rx;
1301                         desc_size = sizeof(struct dma_desc);
1302                 }
1303
1304                 /* Display RX ring */
1305                 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
1306                                     rx_q->dma_rx_phy, desc_size);
1307         }
1308 }
1309
1310 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1311 {
1312         u32 tx_cnt = priv->plat->tx_queues_to_use;
1313         unsigned int desc_size;
1314         void *head_tx;
1315         u32 queue;
1316
1317         /* Display TX rings */
1318         for (queue = 0; queue < tx_cnt; queue++) {
1319                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1320
1321                 pr_info("\tTX Queue %d rings\n", queue);
1322
1323                 if (priv->extend_desc) {
1324                         head_tx = (void *)tx_q->dma_etx;
1325                         desc_size = sizeof(struct dma_extended_desc);
1326                 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1327                         head_tx = (void *)tx_q->dma_entx;
1328                         desc_size = sizeof(struct dma_edesc);
1329                 } else {
1330                         head_tx = (void *)tx_q->dma_tx;
1331                         desc_size = sizeof(struct dma_desc);
1332                 }
1333
1334                 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
1335                                     tx_q->dma_tx_phy, desc_size);
1336         }
1337 }
1338
1339 static void stmmac_display_rings(struct stmmac_priv *priv)
1340 {
1341         /* Display RX ring */
1342         stmmac_display_rx_rings(priv);
1343
1344         /* Display TX ring */
1345         stmmac_display_tx_rings(priv);
1346 }
1347
1348 static int stmmac_set_bfsize(int mtu, int bufsize)
1349 {
1350         int ret = bufsize;
1351
1352         if (mtu >= BUF_SIZE_8KiB)
1353                 ret = BUF_SIZE_16KiB;
1354         else if (mtu >= BUF_SIZE_4KiB)
1355                 ret = BUF_SIZE_8KiB;
1356         else if (mtu >= BUF_SIZE_2KiB)
1357                 ret = BUF_SIZE_4KiB;
1358         else if (mtu > DEFAULT_BUFSIZE)
1359                 ret = BUF_SIZE_2KiB;
1360         else
1361                 ret = DEFAULT_BUFSIZE;
1362
1363         return ret;
1364 }
1365
1366 /**
1367  * stmmac_clear_rx_descriptors - clear RX descriptors
1368  * @priv: driver private structure
1369  * @queue: RX queue index
1370  * Description: this function is called to clear the RX descriptors
1371  * in case of both basic and extended descriptors are used.
1372  */
1373 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1374 {
1375         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1376         int i;
1377
1378         /* Clear the RX descriptors */
1379         for (i = 0; i < priv->dma_rx_size; i++)
1380                 if (priv->extend_desc)
1381                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1382                                         priv->use_riwt, priv->mode,
1383                                         (i == priv->dma_rx_size - 1),
1384                                         priv->dma_buf_sz);
1385                 else
1386                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1387                                         priv->use_riwt, priv->mode,
1388                                         (i == priv->dma_rx_size - 1),
1389                                         priv->dma_buf_sz);
1390 }
1391
1392 /**
1393  * stmmac_clear_tx_descriptors - clear tx descriptors
1394  * @priv: driver private structure
1395  * @queue: TX queue index.
1396  * Description: this function is called to clear the TX descriptors
1397  * in case of both basic and extended descriptors are used.
1398  */
1399 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1400 {
1401         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1402         int i;
1403
1404         /* Clear the TX descriptors */
1405         for (i = 0; i < priv->dma_tx_size; i++) {
1406                 int last = (i == (priv->dma_tx_size - 1));
1407                 struct dma_desc *p;
1408
1409                 if (priv->extend_desc)
1410                         p = &tx_q->dma_etx[i].basic;
1411                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1412                         p = &tx_q->dma_entx[i].basic;
1413                 else
1414                         p = &tx_q->dma_tx[i];
1415
1416                 stmmac_init_tx_desc(priv, p, priv->mode, last);
1417         }
1418 }
1419
1420 /**
1421  * stmmac_clear_descriptors - clear descriptors
1422  * @priv: driver private structure
1423  * Description: this function is called to clear the TX and RX descriptors
1424  * in case of both basic and extended descriptors are used.
1425  */
1426 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1427 {
1428         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1429         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1430         u32 queue;
1431
1432         /* Clear the RX descriptors */
1433         for (queue = 0; queue < rx_queue_cnt; queue++)
1434                 stmmac_clear_rx_descriptors(priv, queue);
1435
1436         /* Clear the TX descriptors */
1437         for (queue = 0; queue < tx_queue_cnt; queue++)
1438                 stmmac_clear_tx_descriptors(priv, queue);
1439 }
1440
1441 /**
1442  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1443  * @priv: driver private structure
1444  * @p: descriptor pointer
1445  * @i: descriptor index
1446  * @flags: gfp flag
1447  * @queue: RX queue index
1448  * Description: this function is called to allocate a receive buffer, perform
1449  * the DMA mapping and init the descriptor.
1450  */
1451 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1452                                   int i, gfp_t flags, u32 queue)
1453 {
1454         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1455         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1456         gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
1457
1458         if (priv->dma_cap.addr64 <= 32)
1459                 gfp |= GFP_DMA32;
1460
1461         if (!buf->page) {
1462                 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1463                 if (!buf->page)
1464                         return -ENOMEM;
1465                 buf->page_offset = stmmac_rx_offset(priv);
1466         }
1467
1468         if (priv->sph && !buf->sec_page) {
1469                 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1470                 if (!buf->sec_page)
1471                         return -ENOMEM;
1472
1473                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1474                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1475         } else {
1476                 buf->sec_page = NULL;
1477                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1478         }
1479
1480         buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1481
1482         stmmac_set_desc_addr(priv, p, buf->addr);
1483         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1484                 stmmac_init_desc3(priv, p);
1485
1486         return 0;
1487 }
1488
1489 /**
1490  * stmmac_free_rx_buffer - free RX dma buffers
1491  * @priv: private structure
1492  * @queue: RX queue index
1493  * @i: buffer index.
1494  */
1495 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1496 {
1497         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1498         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1499
1500         if (buf->page)
1501                 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1502         buf->page = NULL;
1503
1504         if (buf->sec_page)
1505                 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1506         buf->sec_page = NULL;
1507 }
1508
1509 /**
1510  * stmmac_free_tx_buffer - free RX dma buffers
1511  * @priv: private structure
1512  * @queue: RX queue index
1513  * @i: buffer index.
1514  */
1515 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1516 {
1517         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1518
1519         if (tx_q->tx_skbuff_dma[i].buf &&
1520             tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1521                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1522                         dma_unmap_page(priv->device,
1523                                        tx_q->tx_skbuff_dma[i].buf,
1524                                        tx_q->tx_skbuff_dma[i].len,
1525                                        DMA_TO_DEVICE);
1526                 else
1527                         dma_unmap_single(priv->device,
1528                                          tx_q->tx_skbuff_dma[i].buf,
1529                                          tx_q->tx_skbuff_dma[i].len,
1530                                          DMA_TO_DEVICE);
1531         }
1532
1533         if (tx_q->xdpf[i] &&
1534             (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1535              tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1536                 xdp_return_frame(tx_q->xdpf[i]);
1537                 tx_q->xdpf[i] = NULL;
1538         }
1539
1540         if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1541                 tx_q->xsk_frames_done++;
1542
1543         if (tx_q->tx_skbuff[i] &&
1544             tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1545                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1546                 tx_q->tx_skbuff[i] = NULL;
1547         }
1548
1549         tx_q->tx_skbuff_dma[i].buf = 0;
1550         tx_q->tx_skbuff_dma[i].map_as_page = false;
1551 }
1552
1553 /**
1554  * dma_free_rx_skbufs - free RX dma buffers
1555  * @priv: private structure
1556  * @queue: RX queue index
1557  */
1558 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1559 {
1560         int i;
1561
1562         for (i = 0; i < priv->dma_rx_size; i++)
1563                 stmmac_free_rx_buffer(priv, queue, i);
1564 }
1565
1566 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
1567                                    gfp_t flags)
1568 {
1569         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1570         int i;
1571
1572         for (i = 0; i < priv->dma_rx_size; i++) {
1573                 struct dma_desc *p;
1574                 int ret;
1575
1576                 if (priv->extend_desc)
1577                         p = &((rx_q->dma_erx + i)->basic);
1578                 else
1579                         p = rx_q->dma_rx + i;
1580
1581                 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1582                                              queue);
1583                 if (ret)
1584                         return ret;
1585
1586                 rx_q->buf_alloc_num++;
1587         }
1588
1589         return 0;
1590 }
1591
1592 /**
1593  * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1594  * @priv: private structure
1595  * @queue: RX queue index
1596  */
1597 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
1598 {
1599         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1600         int i;
1601
1602         for (i = 0; i < priv->dma_rx_size; i++) {
1603                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1604
1605                 if (!buf->xdp)
1606                         continue;
1607
1608                 xsk_buff_free(buf->xdp);
1609                 buf->xdp = NULL;
1610         }
1611 }
1612
1613 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
1614 {
1615         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1616         int i;
1617
1618         for (i = 0; i < priv->dma_rx_size; i++) {
1619                 struct stmmac_rx_buffer *buf;
1620                 dma_addr_t dma_addr;
1621                 struct dma_desc *p;
1622
1623                 if (priv->extend_desc)
1624                         p = (struct dma_desc *)(rx_q->dma_erx + i);
1625                 else
1626                         p = rx_q->dma_rx + i;
1627
1628                 buf = &rx_q->buf_pool[i];
1629
1630                 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1631                 if (!buf->xdp)
1632                         return -ENOMEM;
1633
1634                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1635                 stmmac_set_desc_addr(priv, p, dma_addr);
1636                 rx_q->buf_alloc_num++;
1637         }
1638
1639         return 0;
1640 }
1641
1642 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1643 {
1644         if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1645                 return NULL;
1646
1647         return xsk_get_pool_from_qid(priv->dev, queue);
1648 }
1649
1650 /**
1651  * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1652  * @priv: driver private structure
1653  * @queue: RX queue index
1654  * @flags: gfp flag.
1655  * Description: this function initializes the DMA RX descriptors
1656  * and allocates the socket buffers. It supports the chained and ring
1657  * modes.
1658  */
1659 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
1660 {
1661         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1662         int ret;
1663
1664         netif_dbg(priv, probe, priv->dev,
1665                   "(%s) dma_rx_phy=0x%08x\n", __func__,
1666                   (u32)rx_q->dma_rx_phy);
1667
1668         stmmac_clear_rx_descriptors(priv, queue);
1669
1670         xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1671
1672         rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1673
1674         if (rx_q->xsk_pool) {
1675                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1676                                                    MEM_TYPE_XSK_BUFF_POOL,
1677                                                    NULL));
1678                 netdev_info(priv->dev,
1679                             "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1680                             rx_q->queue_index);
1681                 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1682         } else {
1683                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1684                                                    MEM_TYPE_PAGE_POOL,
1685                                                    rx_q->page_pool));
1686                 netdev_info(priv->dev,
1687                             "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1688                             rx_q->queue_index);
1689         }
1690
1691         if (rx_q->xsk_pool) {
1692                 /* RX XDP ZC buffer pool may not be populated, e.g.
1693                  * xdpsock TX-only.
1694                  */
1695                 stmmac_alloc_rx_buffers_zc(priv, queue);
1696         } else {
1697                 ret = stmmac_alloc_rx_buffers(priv, queue, flags);
1698                 if (ret < 0)
1699                         return -ENOMEM;
1700         }
1701
1702         rx_q->cur_rx = 0;
1703         rx_q->dirty_rx = 0;
1704
1705         /* Setup the chained descriptor addresses */
1706         if (priv->mode == STMMAC_CHAIN_MODE) {
1707                 if (priv->extend_desc)
1708                         stmmac_mode_init(priv, rx_q->dma_erx,
1709                                          rx_q->dma_rx_phy,
1710                                          priv->dma_rx_size, 1);
1711                 else
1712                         stmmac_mode_init(priv, rx_q->dma_rx,
1713                                          rx_q->dma_rx_phy,
1714                                          priv->dma_rx_size, 0);
1715         }
1716
1717         return 0;
1718 }
1719
1720 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1721 {
1722         struct stmmac_priv *priv = netdev_priv(dev);
1723         u32 rx_count = priv->plat->rx_queues_to_use;
1724         u32 queue;
1725         int ret;
1726
1727         /* RX INITIALIZATION */
1728         netif_dbg(priv, probe, priv->dev,
1729                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1730
1731         for (queue = 0; queue < rx_count; queue++) {
1732                 ret = __init_dma_rx_desc_rings(priv, queue, flags);
1733                 if (ret)
1734                         goto err_init_rx_buffers;
1735         }
1736
1737         return 0;
1738
1739 err_init_rx_buffers:
1740         while (queue >= 0) {
1741                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1742
1743                 if (rx_q->xsk_pool)
1744                         dma_free_rx_xskbufs(priv, queue);
1745                 else
1746                         dma_free_rx_skbufs(priv, queue);
1747
1748                 rx_q->buf_alloc_num = 0;
1749                 rx_q->xsk_pool = NULL;
1750
1751                 if (queue == 0)
1752                         break;
1753
1754                 queue--;
1755         }
1756
1757         return ret;
1758 }
1759
1760 /**
1761  * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1762  * @priv: driver private structure
1763  * @queue : TX queue index
1764  * Description: this function initializes the DMA TX descriptors
1765  * and allocates the socket buffers. It supports the chained and ring
1766  * modes.
1767  */
1768 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
1769 {
1770         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1771         int i;
1772
1773         netif_dbg(priv, probe, priv->dev,
1774                   "(%s) dma_tx_phy=0x%08x\n", __func__,
1775                   (u32)tx_q->dma_tx_phy);
1776
1777         /* Setup the chained descriptor addresses */
1778         if (priv->mode == STMMAC_CHAIN_MODE) {
1779                 if (priv->extend_desc)
1780                         stmmac_mode_init(priv, tx_q->dma_etx,
1781                                          tx_q->dma_tx_phy,
1782                                          priv->dma_tx_size, 1);
1783                 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1784                         stmmac_mode_init(priv, tx_q->dma_tx,
1785                                          tx_q->dma_tx_phy,
1786                                          priv->dma_tx_size, 0);
1787         }
1788
1789         tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1790
1791         for (i = 0; i < priv->dma_tx_size; i++) {
1792                 struct dma_desc *p;
1793
1794                 if (priv->extend_desc)
1795                         p = &((tx_q->dma_etx + i)->basic);
1796                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1797                         p = &((tx_q->dma_entx + i)->basic);
1798                 else
1799                         p = tx_q->dma_tx + i;
1800
1801                 stmmac_clear_desc(priv, p);
1802
1803                 tx_q->tx_skbuff_dma[i].buf = 0;
1804                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1805                 tx_q->tx_skbuff_dma[i].len = 0;
1806                 tx_q->tx_skbuff_dma[i].last_segment = false;
1807                 tx_q->tx_skbuff[i] = NULL;
1808         }
1809
1810         tx_q->dirty_tx = 0;
1811         tx_q->cur_tx = 0;
1812         tx_q->mss = 0;
1813
1814         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1815
1816         return 0;
1817 }
1818
1819 static int init_dma_tx_desc_rings(struct net_device *dev)
1820 {
1821         struct stmmac_priv *priv = netdev_priv(dev);
1822         u32 tx_queue_cnt;
1823         u32 queue;
1824
1825         tx_queue_cnt = priv->plat->tx_queues_to_use;
1826
1827         for (queue = 0; queue < tx_queue_cnt; queue++)
1828                 __init_dma_tx_desc_rings(priv, queue);
1829
1830         return 0;
1831 }
1832
1833 /**
1834  * init_dma_desc_rings - init the RX/TX descriptor rings
1835  * @dev: net device structure
1836  * @flags: gfp flag.
1837  * Description: this function initializes the DMA RX/TX descriptors
1838  * and allocates the socket buffers. It supports the chained and ring
1839  * modes.
1840  */
1841 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1842 {
1843         struct stmmac_priv *priv = netdev_priv(dev);
1844         int ret;
1845
1846         ret = init_dma_rx_desc_rings(dev, flags);
1847         if (ret)
1848                 return ret;
1849
1850         ret = init_dma_tx_desc_rings(dev);
1851
1852         stmmac_clear_descriptors(priv);
1853
1854         if (netif_msg_hw(priv))
1855                 stmmac_display_rings(priv);
1856
1857         return ret;
1858 }
1859
1860 /**
1861  * dma_free_tx_skbufs - free TX dma buffers
1862  * @priv: private structure
1863  * @queue: TX queue index
1864  */
1865 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1866 {
1867         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1868         int i;
1869
1870         tx_q->xsk_frames_done = 0;
1871
1872         for (i = 0; i < priv->dma_tx_size; i++)
1873                 stmmac_free_tx_buffer(priv, queue, i);
1874
1875         if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1876                 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1877                 tx_q->xsk_frames_done = 0;
1878                 tx_q->xsk_pool = NULL;
1879         }
1880 }
1881
1882 /**
1883  * stmmac_free_tx_skbufs - free TX skb buffers
1884  * @priv: private structure
1885  */
1886 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1887 {
1888         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1889         u32 queue;
1890
1891         for (queue = 0; queue < tx_queue_cnt; queue++)
1892                 dma_free_tx_skbufs(priv, queue);
1893 }
1894
1895 /**
1896  * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1897  * @priv: private structure
1898  * @queue: RX queue index
1899  */
1900 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1901 {
1902         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1903
1904         /* Release the DMA RX socket buffers */
1905         if (rx_q->xsk_pool)
1906                 dma_free_rx_xskbufs(priv, queue);
1907         else
1908                 dma_free_rx_skbufs(priv, queue);
1909
1910         rx_q->buf_alloc_num = 0;
1911         rx_q->xsk_pool = NULL;
1912
1913         /* Free DMA regions of consistent memory previously allocated */
1914         if (!priv->extend_desc)
1915                 dma_free_coherent(priv->device, priv->dma_rx_size *
1916                                   sizeof(struct dma_desc),
1917                                   rx_q->dma_rx, rx_q->dma_rx_phy);
1918         else
1919                 dma_free_coherent(priv->device, priv->dma_rx_size *
1920                                   sizeof(struct dma_extended_desc),
1921                                   rx_q->dma_erx, rx_q->dma_rx_phy);
1922
1923         if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1924                 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1925
1926         kfree(rx_q->buf_pool);
1927         if (rx_q->page_pool)
1928                 page_pool_destroy(rx_q->page_pool);
1929 }
1930
1931 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1932 {
1933         u32 rx_count = priv->plat->rx_queues_to_use;
1934         u32 queue;
1935
1936         /* Free RX queue resources */
1937         for (queue = 0; queue < rx_count; queue++)
1938                 __free_dma_rx_desc_resources(priv, queue);
1939 }
1940
1941 /**
1942  * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1943  * @priv: private structure
1944  * @queue: TX queue index
1945  */
1946 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
1947 {
1948         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1949         size_t size;
1950         void *addr;
1951
1952         /* Release the DMA TX socket buffers */
1953         dma_free_tx_skbufs(priv, queue);
1954
1955         if (priv->extend_desc) {
1956                 size = sizeof(struct dma_extended_desc);
1957                 addr = tx_q->dma_etx;
1958         } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1959                 size = sizeof(struct dma_edesc);
1960                 addr = tx_q->dma_entx;
1961         } else {
1962                 size = sizeof(struct dma_desc);
1963                 addr = tx_q->dma_tx;
1964         }
1965
1966         size *= priv->dma_tx_size;
1967
1968         dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1969
1970         kfree(tx_q->tx_skbuff_dma);
1971         kfree(tx_q->tx_skbuff);
1972 }
1973
1974 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1975 {
1976         u32 tx_count = priv->plat->tx_queues_to_use;
1977         u32 queue;
1978
1979         /* Free TX queue resources */
1980         for (queue = 0; queue < tx_count; queue++)
1981                 __free_dma_tx_desc_resources(priv, queue);
1982 }
1983
1984 /**
1985  * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
1986  * @priv: private structure
1987  * @queue: RX queue index
1988  * Description: according to which descriptor can be used (extend or basic)
1989  * this function allocates the resources for TX and RX paths. In case of
1990  * reception, for example, it pre-allocated the RX socket buffer in order to
1991  * allow zero-copy mechanism.
1992  */
1993 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1994 {
1995         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1996         struct stmmac_channel *ch = &priv->channel[queue];
1997         bool xdp_prog = stmmac_xdp_is_enabled(priv);
1998         struct page_pool_params pp_params = { 0 };
1999         unsigned int num_pages;
2000         unsigned int napi_id;
2001         int ret;
2002
2003         rx_q->queue_index = queue;
2004         rx_q->priv_data = priv;
2005
2006         pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
2007         pp_params.pool_size = priv->dma_rx_size;
2008         num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
2009         pp_params.order = ilog2(num_pages);
2010         pp_params.nid = dev_to_node(priv->device);
2011         pp_params.dev = priv->device;
2012         pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
2013         pp_params.offset = stmmac_rx_offset(priv);
2014         pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
2015
2016         rx_q->page_pool = page_pool_create(&pp_params);
2017         if (IS_ERR(rx_q->page_pool)) {
2018                 ret = PTR_ERR(rx_q->page_pool);
2019                 rx_q->page_pool = NULL;
2020                 return ret;
2021         }
2022
2023         rx_q->buf_pool = kcalloc(priv->dma_rx_size,
2024                                  sizeof(*rx_q->buf_pool),
2025                                  GFP_KERNEL);
2026         if (!rx_q->buf_pool)
2027                 return -ENOMEM;
2028
2029         if (priv->extend_desc) {
2030                 rx_q->dma_erx = dma_alloc_coherent(priv->device,
2031                                                    priv->dma_rx_size *
2032                                                    sizeof(struct dma_extended_desc),
2033                                                    &rx_q->dma_rx_phy,
2034                                                    GFP_KERNEL);
2035                 if (!rx_q->dma_erx)
2036                         return -ENOMEM;
2037
2038         } else {
2039                 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2040                                                   priv->dma_rx_size *
2041                                                   sizeof(struct dma_desc),
2042                                                   &rx_q->dma_rx_phy,
2043                                                   GFP_KERNEL);
2044                 if (!rx_q->dma_rx)
2045                         return -ENOMEM;
2046         }
2047
2048         if (stmmac_xdp_is_enabled(priv) &&
2049             test_bit(queue, priv->af_xdp_zc_qps))
2050                 napi_id = ch->rxtx_napi.napi_id;
2051         else
2052                 napi_id = ch->rx_napi.napi_id;
2053
2054         ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2055                                rx_q->queue_index,
2056                                napi_id);
2057         if (ret) {
2058                 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2059                 return -EINVAL;
2060         }
2061
2062         return 0;
2063 }
2064
2065 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
2066 {
2067         u32 rx_count = priv->plat->rx_queues_to_use;
2068         u32 queue;
2069         int ret;
2070
2071         /* RX queues buffers and DMA */
2072         for (queue = 0; queue < rx_count; queue++) {
2073                 ret = __alloc_dma_rx_desc_resources(priv, queue);
2074                 if (ret)
2075                         goto err_dma;
2076         }
2077
2078         return 0;
2079
2080 err_dma:
2081         free_dma_rx_desc_resources(priv);
2082
2083         return ret;
2084 }
2085
2086 /**
2087  * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2088  * @priv: private structure
2089  * @queue: TX queue index
2090  * Description: according to which descriptor can be used (extend or basic)
2091  * this function allocates the resources for TX and RX paths. In case of
2092  * reception, for example, it pre-allocated the RX socket buffer in order to
2093  * allow zero-copy mechanism.
2094  */
2095 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
2096 {
2097         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2098         size_t size;
2099         void *addr;
2100
2101         tx_q->queue_index = queue;
2102         tx_q->priv_data = priv;
2103
2104         tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
2105                                       sizeof(*tx_q->tx_skbuff_dma),
2106                                       GFP_KERNEL);
2107         if (!tx_q->tx_skbuff_dma)
2108                 return -ENOMEM;
2109
2110         tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
2111                                   sizeof(struct sk_buff *),
2112                                   GFP_KERNEL);
2113         if (!tx_q->tx_skbuff)
2114                 return -ENOMEM;
2115
2116         if (priv->extend_desc)
2117                 size = sizeof(struct dma_extended_desc);
2118         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2119                 size = sizeof(struct dma_edesc);
2120         else
2121                 size = sizeof(struct dma_desc);
2122
2123         size *= priv->dma_tx_size;
2124
2125         addr = dma_alloc_coherent(priv->device, size,
2126                                   &tx_q->dma_tx_phy, GFP_KERNEL);
2127         if (!addr)
2128                 return -ENOMEM;
2129
2130         if (priv->extend_desc)
2131                 tx_q->dma_etx = addr;
2132         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2133                 tx_q->dma_entx = addr;
2134         else
2135                 tx_q->dma_tx = addr;
2136
2137         return 0;
2138 }
2139
2140 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
2141 {
2142         u32 tx_count = priv->plat->tx_queues_to_use;
2143         u32 queue;
2144         int ret;
2145
2146         /* TX queues buffers and DMA */
2147         for (queue = 0; queue < tx_count; queue++) {
2148                 ret = __alloc_dma_tx_desc_resources(priv, queue);
2149                 if (ret)
2150                         goto err_dma;
2151         }
2152
2153         return 0;
2154
2155 err_dma:
2156         free_dma_tx_desc_resources(priv);
2157         return ret;
2158 }
2159
2160 /**
2161  * alloc_dma_desc_resources - alloc TX/RX resources.
2162  * @priv: private structure
2163  * Description: according to which descriptor can be used (extend or basic)
2164  * this function allocates the resources for TX and RX paths. In case of
2165  * reception, for example, it pre-allocated the RX socket buffer in order to
2166  * allow zero-copy mechanism.
2167  */
2168 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
2169 {
2170         /* RX Allocation */
2171         int ret = alloc_dma_rx_desc_resources(priv);
2172
2173         if (ret)
2174                 return ret;
2175
2176         ret = alloc_dma_tx_desc_resources(priv);
2177
2178         return ret;
2179 }
2180
2181 /**
2182  * free_dma_desc_resources - free dma desc resources
2183  * @priv: private structure
2184  */
2185 static void free_dma_desc_resources(struct stmmac_priv *priv)
2186 {
2187         /* Release the DMA TX socket buffers */
2188         free_dma_tx_desc_resources(priv);
2189
2190         /* Release the DMA RX socket buffers later
2191          * to ensure all pending XDP_TX buffers are returned.
2192          */
2193         free_dma_rx_desc_resources(priv);
2194 }
2195
2196 /**
2197  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
2198  *  @priv: driver private structure
2199  *  Description: It is used for enabling the rx queues in the MAC
2200  */
2201 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2202 {
2203         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2204         int queue;
2205         u8 mode;
2206
2207         for (queue = 0; queue < rx_queues_count; queue++) {
2208                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2209                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2210         }
2211 }
2212
2213 /**
2214  * stmmac_start_rx_dma - start RX DMA channel
2215  * @priv: driver private structure
2216  * @chan: RX channel index
2217  * Description:
2218  * This starts a RX DMA channel
2219  */
2220 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2221 {
2222         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2223         stmmac_start_rx(priv, priv->ioaddr, chan);
2224 }
2225
2226 /**
2227  * stmmac_start_tx_dma - start TX DMA channel
2228  * @priv: driver private structure
2229  * @chan: TX channel index
2230  * Description:
2231  * This starts a TX DMA channel
2232  */
2233 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2234 {
2235         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2236         stmmac_start_tx(priv, priv->ioaddr, chan);
2237 }
2238
2239 /**
2240  * stmmac_stop_rx_dma - stop RX DMA channel
2241  * @priv: driver private structure
2242  * @chan: RX channel index
2243  * Description:
2244  * This stops a RX DMA channel
2245  */
2246 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2247 {
2248         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2249         stmmac_stop_rx(priv, priv->ioaddr, chan);
2250 }
2251
2252 /**
2253  * stmmac_stop_tx_dma - stop TX DMA channel
2254  * @priv: driver private structure
2255  * @chan: TX channel index
2256  * Description:
2257  * This stops a TX DMA channel
2258  */
2259 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2260 {
2261         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2262         stmmac_stop_tx(priv, priv->ioaddr, chan);
2263 }
2264
2265 /**
2266  * stmmac_start_all_dma - start all RX and TX DMA channels
2267  * @priv: driver private structure
2268  * Description:
2269  * This starts all the RX and TX DMA channels
2270  */
2271 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2272 {
2273         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2274         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2275         u32 chan = 0;
2276
2277         for (chan = 0; chan < rx_channels_count; chan++)
2278                 stmmac_start_rx_dma(priv, chan);
2279
2280         for (chan = 0; chan < tx_channels_count; chan++)
2281                 stmmac_start_tx_dma(priv, chan);
2282 }
2283
2284 /**
2285  * stmmac_stop_all_dma - stop all RX and TX DMA channels
2286  * @priv: driver private structure
2287  * Description:
2288  * This stops the RX and TX DMA channels
2289  */
2290 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2291 {
2292         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2293         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2294         u32 chan = 0;
2295
2296         for (chan = 0; chan < rx_channels_count; chan++)
2297                 stmmac_stop_rx_dma(priv, chan);
2298
2299         for (chan = 0; chan < tx_channels_count; chan++)
2300                 stmmac_stop_tx_dma(priv, chan);
2301 }
2302
2303 /**
2304  *  stmmac_dma_operation_mode - HW DMA operation mode
2305  *  @priv: driver private structure
2306  *  Description: it is used for configuring the DMA operation mode register in
2307  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2308  */
2309 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2310 {
2311         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2312         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2313         int rxfifosz = priv->plat->rx_fifo_size;
2314         int txfifosz = priv->plat->tx_fifo_size;
2315         u32 txmode = 0;
2316         u32 rxmode = 0;
2317         u32 chan = 0;
2318         u8 qmode = 0;
2319
2320         if (rxfifosz == 0)
2321                 rxfifosz = priv->dma_cap.rx_fifo_size;
2322         if (txfifosz == 0)
2323                 txfifosz = priv->dma_cap.tx_fifo_size;
2324
2325         /* Adjust for real per queue fifo size */
2326         rxfifosz /= rx_channels_count;
2327         txfifosz /= tx_channels_count;
2328
2329         if (priv->plat->force_thresh_dma_mode) {
2330                 txmode = tc;
2331                 rxmode = tc;
2332         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2333                 /*
2334                  * In case of GMAC, SF mode can be enabled
2335                  * to perform the TX COE in HW. This depends on:
2336                  * 1) TX COE if actually supported
2337                  * 2) There is no bugged Jumbo frame support
2338                  *    that needs to not insert csum in the TDES.
2339                  */
2340                 txmode = SF_DMA_MODE;
2341                 rxmode = SF_DMA_MODE;
2342                 priv->xstats.threshold = SF_DMA_MODE;
2343         } else {
2344                 txmode = tc;
2345                 rxmode = SF_DMA_MODE;
2346         }
2347
2348         /* configure all channels */
2349         for (chan = 0; chan < rx_channels_count; chan++) {
2350                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2351                 u32 buf_size;
2352
2353                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2354
2355                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2356                                 rxfifosz, qmode);
2357
2358                 if (rx_q->xsk_pool) {
2359                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2360                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2361                                               buf_size,
2362                                               chan);
2363                 } else {
2364                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2365                                               priv->dma_buf_sz,
2366                                               chan);
2367                 }
2368         }
2369
2370         for (chan = 0; chan < tx_channels_count; chan++) {
2371                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2372
2373                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2374                                 txfifosz, qmode);
2375         }
2376 }
2377
2378 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2379 {
2380         struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2381         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2382         struct xsk_buff_pool *pool = tx_q->xsk_pool;
2383         unsigned int entry = tx_q->cur_tx;
2384         struct dma_desc *tx_desc = NULL;
2385         struct xdp_desc xdp_desc;
2386         bool work_done = true;
2387
2388         /* Avoids TX time-out as we are sharing with slow path */
2389         txq_trans_cond_update(nq);
2390
2391         budget = min(budget, stmmac_tx_avail(priv, queue));
2392
2393         while (budget-- > 0) {
2394                 dma_addr_t dma_addr;
2395                 bool set_ic;
2396
2397                 /* We are sharing with slow path and stop XSK TX desc submission when
2398                  * available TX ring is less than threshold.
2399                  */
2400                 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2401                     !netif_carrier_ok(priv->dev)) {
2402                         work_done = false;
2403                         break;
2404                 }
2405
2406                 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2407                         break;
2408
2409                 if (likely(priv->extend_desc))
2410                         tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2411                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2412                         tx_desc = &tx_q->dma_entx[entry].basic;
2413                 else
2414                         tx_desc = tx_q->dma_tx + entry;
2415
2416                 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2417                 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2418
2419                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2420
2421                 /* To return XDP buffer to XSK pool, we simple call
2422                  * xsk_tx_completed(), so we don't need to fill up
2423                  * 'buf' and 'xdpf'.
2424                  */
2425                 tx_q->tx_skbuff_dma[entry].buf = 0;
2426                 tx_q->xdpf[entry] = NULL;
2427
2428                 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2429                 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2430                 tx_q->tx_skbuff_dma[entry].last_segment = true;
2431                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2432
2433                 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2434
2435                 tx_q->tx_count_frames++;
2436
2437                 if (!priv->tx_coal_frames[queue])
2438                         set_ic = false;
2439                 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2440                         set_ic = true;
2441                 else
2442                         set_ic = false;
2443
2444                 if (set_ic) {
2445                         tx_q->tx_count_frames = 0;
2446                         stmmac_set_tx_ic(priv, tx_desc);
2447                         priv->xstats.tx_set_ic_bit++;
2448                 }
2449
2450                 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2451                                        true, priv->mode, true, true,
2452                                        xdp_desc.len);
2453
2454                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2455
2456                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
2457                 entry = tx_q->cur_tx;
2458         }
2459
2460         if (tx_desc) {
2461                 stmmac_flush_tx_descriptors(priv, queue);
2462                 xsk_tx_release(pool);
2463         }
2464
2465         /* Return true if all of the 3 conditions are met
2466          *  a) TX Budget is still available
2467          *  b) work_done = true when XSK TX desc peek is empty (no more
2468          *     pending XSK TX for transmission)
2469          */
2470         return !!budget && work_done;
2471 }
2472
2473 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan)
2474 {
2475         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) {
2476                 tc += 64;
2477
2478                 if (priv->plat->force_thresh_dma_mode)
2479                         stmmac_set_dma_operation_mode(priv, tc, tc, chan);
2480                 else
2481                         stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE,
2482                                                       chan);
2483
2484                 priv->xstats.threshold = tc;
2485         }
2486 }
2487
2488 /**
2489  * stmmac_tx_clean - to manage the transmission completion
2490  * @priv: driver private structure
2491  * @budget: napi budget limiting this functions packet handling
2492  * @queue: TX queue index
2493  * Description: it reclaims the transmit resources after transmission completes.
2494  */
2495 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2496 {
2497         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2498         unsigned int bytes_compl = 0, pkts_compl = 0;
2499         unsigned int entry, xmits = 0, count = 0;
2500
2501         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2502
2503         priv->xstats.tx_clean++;
2504
2505         tx_q->xsk_frames_done = 0;
2506
2507         entry = tx_q->dirty_tx;
2508
2509         /* Try to clean all TX complete frame in 1 shot */
2510         while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
2511                 struct xdp_frame *xdpf;
2512                 struct sk_buff *skb;
2513                 struct dma_desc *p;
2514                 int status;
2515
2516                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2517                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2518                         xdpf = tx_q->xdpf[entry];
2519                         skb = NULL;
2520                 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2521                         xdpf = NULL;
2522                         skb = tx_q->tx_skbuff[entry];
2523                 } else {
2524                         xdpf = NULL;
2525                         skb = NULL;
2526                 }
2527
2528                 if (priv->extend_desc)
2529                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
2530                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2531                         p = &tx_q->dma_entx[entry].basic;
2532                 else
2533                         p = tx_q->dma_tx + entry;
2534
2535                 status = stmmac_tx_status(priv, &priv->dev->stats,
2536                                 &priv->xstats, p, priv->ioaddr);
2537                 /* Check if the descriptor is owned by the DMA */
2538                 if (unlikely(status & tx_dma_own))
2539                         break;
2540
2541                 count++;
2542
2543                 /* Make sure descriptor fields are read after reading
2544                  * the own bit.
2545                  */
2546                 dma_rmb();
2547
2548                 /* Just consider the last segment and ...*/
2549                 if (likely(!(status & tx_not_ls))) {
2550                         /* ... verify the status error condition */
2551                         if (unlikely(status & tx_err)) {
2552                                 priv->dev->stats.tx_errors++;
2553                                 if (unlikely(status & tx_err_bump_tc))
2554                                         stmmac_bump_dma_threshold(priv, queue);
2555                         } else {
2556                                 priv->dev->stats.tx_packets++;
2557                                 priv->xstats.tx_pkt_n++;
2558                                 priv->xstats.txq_stats[queue].tx_pkt_n++;
2559                         }
2560                         if (skb)
2561                                 stmmac_get_tx_hwtstamp(priv, p, skb);
2562                 }
2563
2564                 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2565                            tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2566                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
2567                                 dma_unmap_page(priv->device,
2568                                                tx_q->tx_skbuff_dma[entry].buf,
2569                                                tx_q->tx_skbuff_dma[entry].len,
2570                                                DMA_TO_DEVICE);
2571                         else
2572                                 dma_unmap_single(priv->device,
2573                                                  tx_q->tx_skbuff_dma[entry].buf,
2574                                                  tx_q->tx_skbuff_dma[entry].len,
2575                                                  DMA_TO_DEVICE);
2576                         tx_q->tx_skbuff_dma[entry].buf = 0;
2577                         tx_q->tx_skbuff_dma[entry].len = 0;
2578                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
2579                 }
2580
2581                 stmmac_clean_desc3(priv, tx_q, p);
2582
2583                 tx_q->tx_skbuff_dma[entry].last_segment = false;
2584                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2585
2586                 if (xdpf &&
2587                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2588                         xdp_return_frame_rx_napi(xdpf);
2589                         tx_q->xdpf[entry] = NULL;
2590                 }
2591
2592                 if (xdpf &&
2593                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2594                         xdp_return_frame(xdpf);
2595                         tx_q->xdpf[entry] = NULL;
2596                 }
2597
2598                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2599                         tx_q->xsk_frames_done++;
2600
2601                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2602                         if (likely(skb)) {
2603                                 pkts_compl++;
2604                                 bytes_compl += skb->len;
2605                                 dev_consume_skb_any(skb);
2606                                 tx_q->tx_skbuff[entry] = NULL;
2607                         }
2608                 }
2609
2610                 stmmac_release_tx_desc(priv, p, priv->mode);
2611
2612                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
2613         }
2614         tx_q->dirty_tx = entry;
2615
2616         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2617                                   pkts_compl, bytes_compl);
2618
2619         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2620                                                                 queue))) &&
2621             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2622
2623                 netif_dbg(priv, tx_done, priv->dev,
2624                           "%s: restart transmit\n", __func__);
2625                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2626         }
2627
2628         if (tx_q->xsk_pool) {
2629                 bool work_done;
2630
2631                 if (tx_q->xsk_frames_done)
2632                         xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2633
2634                 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2635                         xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2636
2637                 /* For XSK TX, we try to send as many as possible.
2638                  * If XSK work done (XSK TX desc empty and budget still
2639                  * available), return "budget - 1" to reenable TX IRQ.
2640                  * Else, return "budget" to make NAPI continue polling.
2641                  */
2642                 work_done = stmmac_xdp_xmit_zc(priv, queue,
2643                                                STMMAC_XSK_TX_BUDGET_MAX);
2644                 if (work_done)
2645                         xmits = budget - 1;
2646                 else
2647                         xmits = budget;
2648         }
2649
2650         if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2651             priv->eee_sw_timer_en) {
2652                 if (stmmac_enable_eee_mode(priv))
2653                         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2654         }
2655
2656         /* We still have pending packets, let's call for a new scheduling */
2657         if (tx_q->dirty_tx != tx_q->cur_tx)
2658                 hrtimer_start(&tx_q->txtimer,
2659                               STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2660                               HRTIMER_MODE_REL);
2661
2662         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2663
2664         /* Combine decisions from TX clean and XSK TX */
2665         return max(count, xmits);
2666 }
2667
2668 /**
2669  * stmmac_tx_err - to manage the tx error
2670  * @priv: driver private structure
2671  * @chan: channel index
2672  * Description: it cleans the descriptors and restarts the transmission
2673  * in case of transmission errors.
2674  */
2675 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2676 {
2677         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2678
2679         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2680
2681         stmmac_stop_tx_dma(priv, chan);
2682         dma_free_tx_skbufs(priv, chan);
2683         stmmac_clear_tx_descriptors(priv, chan);
2684         tx_q->dirty_tx = 0;
2685         tx_q->cur_tx = 0;
2686         tx_q->mss = 0;
2687         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2688         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2689                             tx_q->dma_tx_phy, chan);
2690         stmmac_start_tx_dma(priv, chan);
2691
2692         priv->dev->stats.tx_errors++;
2693         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2694 }
2695
2696 /**
2697  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2698  *  @priv: driver private structure
2699  *  @txmode: TX operating mode
2700  *  @rxmode: RX operating mode
2701  *  @chan: channel index
2702  *  Description: it is used for configuring of the DMA operation mode in
2703  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2704  *  mode.
2705  */
2706 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2707                                           u32 rxmode, u32 chan)
2708 {
2709         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2710         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2711         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2712         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2713         int rxfifosz = priv->plat->rx_fifo_size;
2714         int txfifosz = priv->plat->tx_fifo_size;
2715
2716         if (rxfifosz == 0)
2717                 rxfifosz = priv->dma_cap.rx_fifo_size;
2718         if (txfifosz == 0)
2719                 txfifosz = priv->dma_cap.tx_fifo_size;
2720
2721         /* Adjust for real per queue fifo size */
2722         rxfifosz /= rx_channels_count;
2723         txfifosz /= tx_channels_count;
2724
2725         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2726         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2727 }
2728
2729 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2730 {
2731         int ret;
2732
2733         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2734                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2735         if (ret && (ret != -EINVAL)) {
2736                 stmmac_global_err(priv);
2737                 return true;
2738         }
2739
2740         return false;
2741 }
2742
2743 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2744 {
2745         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2746                                                  &priv->xstats, chan, dir);
2747         struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2748         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2749         struct stmmac_channel *ch = &priv->channel[chan];
2750         struct napi_struct *rx_napi;
2751         struct napi_struct *tx_napi;
2752         unsigned long flags;
2753
2754         rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2755         tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2756
2757         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2758                 if (napi_schedule_prep(rx_napi)) {
2759                         spin_lock_irqsave(&ch->lock, flags);
2760                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2761                         spin_unlock_irqrestore(&ch->lock, flags);
2762                         __napi_schedule(rx_napi);
2763                 }
2764         }
2765
2766         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2767                 if (napi_schedule_prep(tx_napi)) {
2768                         spin_lock_irqsave(&ch->lock, flags);
2769                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2770                         spin_unlock_irqrestore(&ch->lock, flags);
2771                         __napi_schedule(tx_napi);
2772                 }
2773         }
2774
2775         return status;
2776 }
2777
2778 /**
2779  * stmmac_dma_interrupt - DMA ISR
2780  * @priv: driver private structure
2781  * Description: this is the DMA ISR. It is called by the main ISR.
2782  * It calls the dwmac dma routine and schedule poll method in case of some
2783  * work can be done.
2784  */
2785 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2786 {
2787         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2788         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2789         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2790                                 tx_channel_count : rx_channel_count;
2791         u32 chan;
2792         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2793
2794         /* Make sure we never check beyond our status buffer. */
2795         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2796                 channels_to_check = ARRAY_SIZE(status);
2797
2798         for (chan = 0; chan < channels_to_check; chan++)
2799                 status[chan] = stmmac_napi_check(priv, chan,
2800                                                  DMA_DIR_RXTX);
2801
2802         for (chan = 0; chan < tx_channel_count; chan++) {
2803                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2804                         /* Try to bump up the dma threshold on this failure */
2805                         stmmac_bump_dma_threshold(priv, chan);
2806                 } else if (unlikely(status[chan] == tx_hard_error)) {
2807                         stmmac_tx_err(priv, chan);
2808                 }
2809         }
2810 }
2811
2812 /**
2813  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2814  * @priv: driver private structure
2815  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2816  */
2817 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2818 {
2819         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2820                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2821
2822         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2823
2824         if (priv->dma_cap.rmon) {
2825                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2826                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2827         } else
2828                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2829 }
2830
2831 /**
2832  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2833  * @priv: driver private structure
2834  * Description:
2835  *  new GMAC chip generations have a new register to indicate the
2836  *  presence of the optional feature/functions.
2837  *  This can be also used to override the value passed through the
2838  *  platform and necessary for old MAC10/100 and GMAC chips.
2839  */
2840 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2841 {
2842         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2843 }
2844
2845 /**
2846  * stmmac_check_ether_addr - check if the MAC addr is valid
2847  * @priv: driver private structure
2848  * Description:
2849  * it is to verify if the MAC address is valid, in case of failures it
2850  * generates a random MAC address
2851  */
2852 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2853 {
2854         u8 addr[ETH_ALEN];
2855
2856         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2857                 stmmac_get_umac_addr(priv, priv->hw, addr, 0);
2858                 if (is_valid_ether_addr(addr))
2859                         eth_hw_addr_set(priv->dev, addr);
2860                 else
2861                         eth_hw_addr_random(priv->dev);
2862                 dev_info(priv->device, "device MAC address %pM\n",
2863                          priv->dev->dev_addr);
2864         }
2865 }
2866
2867 /**
2868  * stmmac_init_dma_engine - DMA init.
2869  * @priv: driver private structure
2870  * Description:
2871  * It inits the DMA invoking the specific MAC/GMAC callback.
2872  * Some DMA parameters can be passed from the platform;
2873  * in case of these are not passed a default is kept for the MAC or GMAC.
2874  */
2875 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2876 {
2877         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2878         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2879         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2880         struct stmmac_rx_queue *rx_q;
2881         struct stmmac_tx_queue *tx_q;
2882         u32 chan = 0;
2883         int atds = 0;
2884         int ret = 0;
2885
2886         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2887                 dev_err(priv->device, "Invalid DMA configuration\n");
2888                 return -EINVAL;
2889         }
2890
2891         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2892                 atds = 1;
2893
2894         ret = stmmac_reset(priv, priv->ioaddr);
2895         if (ret) {
2896                 dev_err(priv->device, "Failed to reset the dma\n");
2897                 return ret;
2898         }
2899
2900         /* DMA Configuration */
2901         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2902
2903         if (priv->plat->axi)
2904                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2905
2906         /* DMA CSR Channel configuration */
2907         for (chan = 0; chan < dma_csr_ch; chan++)
2908                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2909
2910         /* DMA RX Channel Configuration */
2911         for (chan = 0; chan < rx_channels_count; chan++) {
2912                 rx_q = &priv->rx_queue[chan];
2913
2914                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2915                                     rx_q->dma_rx_phy, chan);
2916
2917                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2918                                      (rx_q->buf_alloc_num *
2919                                       sizeof(struct dma_desc));
2920                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2921                                        rx_q->rx_tail_addr, chan);
2922         }
2923
2924         /* DMA TX Channel Configuration */
2925         for (chan = 0; chan < tx_channels_count; chan++) {
2926                 tx_q = &priv->tx_queue[chan];
2927
2928                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2929                                     tx_q->dma_tx_phy, chan);
2930
2931                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2932                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2933                                        tx_q->tx_tail_addr, chan);
2934         }
2935
2936         return ret;
2937 }
2938
2939 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2940 {
2941         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2942
2943         hrtimer_start(&tx_q->txtimer,
2944                       STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2945                       HRTIMER_MODE_REL);
2946 }
2947
2948 /**
2949  * stmmac_tx_timer - mitigation sw timer for tx.
2950  * @t: data pointer
2951  * Description:
2952  * This is the timer handler to directly invoke the stmmac_tx_clean.
2953  */
2954 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
2955 {
2956         struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
2957         struct stmmac_priv *priv = tx_q->priv_data;
2958         struct stmmac_channel *ch;
2959         struct napi_struct *napi;
2960
2961         ch = &priv->channel[tx_q->queue_index];
2962         napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2963
2964         if (likely(napi_schedule_prep(napi))) {
2965                 unsigned long flags;
2966
2967                 spin_lock_irqsave(&ch->lock, flags);
2968                 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2969                 spin_unlock_irqrestore(&ch->lock, flags);
2970                 __napi_schedule(napi);
2971         }
2972
2973         return HRTIMER_NORESTART;
2974 }
2975
2976 /**
2977  * stmmac_init_coalesce - init mitigation options.
2978  * @priv: driver private structure
2979  * Description:
2980  * This inits the coalesce parameters: i.e. timer rate,
2981  * timer handler and default threshold used for enabling the
2982  * interrupt on completion bit.
2983  */
2984 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2985 {
2986         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2987         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2988         u32 chan;
2989
2990         for (chan = 0; chan < tx_channel_count; chan++) {
2991                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2992
2993                 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
2994                 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
2995
2996                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2997                 tx_q->txtimer.function = stmmac_tx_timer;
2998         }
2999
3000         for (chan = 0; chan < rx_channel_count; chan++)
3001                 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
3002 }
3003
3004 static void stmmac_set_rings_length(struct stmmac_priv *priv)
3005 {
3006         u32 rx_channels_count = priv->plat->rx_queues_to_use;
3007         u32 tx_channels_count = priv->plat->tx_queues_to_use;
3008         u32 chan;
3009
3010         /* set TX ring length */
3011         for (chan = 0; chan < tx_channels_count; chan++)
3012                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
3013                                        (priv->dma_tx_size - 1), chan);
3014
3015         /* set RX ring length */
3016         for (chan = 0; chan < rx_channels_count; chan++)
3017                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
3018                                        (priv->dma_rx_size - 1), chan);
3019 }
3020
3021 /**
3022  *  stmmac_set_tx_queue_weight - Set TX queue weight
3023  *  @priv: driver private structure
3024  *  Description: It is used for setting TX queues weight
3025  */
3026 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
3027 {
3028         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3029         u32 weight;
3030         u32 queue;
3031
3032         for (queue = 0; queue < tx_queues_count; queue++) {
3033                 weight = priv->plat->tx_queues_cfg[queue].weight;
3034                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
3035         }
3036 }
3037
3038 /**
3039  *  stmmac_configure_cbs - Configure CBS in TX queue
3040  *  @priv: driver private structure
3041  *  Description: It is used for configuring CBS in AVB TX queues
3042  */
3043 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3044 {
3045         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3046         u32 mode_to_use;
3047         u32 queue;
3048
3049         /* queue 0 is reserved for legacy traffic */
3050         for (queue = 1; queue < tx_queues_count; queue++) {
3051                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3052                 if (mode_to_use == MTL_QUEUE_DCB)
3053                         continue;
3054
3055                 stmmac_config_cbs(priv, priv->hw,
3056                                 priv->plat->tx_queues_cfg[queue].send_slope,
3057                                 priv->plat->tx_queues_cfg[queue].idle_slope,
3058                                 priv->plat->tx_queues_cfg[queue].high_credit,
3059                                 priv->plat->tx_queues_cfg[queue].low_credit,
3060                                 queue);
3061         }
3062 }
3063
3064 /**
3065  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3066  *  @priv: driver private structure
3067  *  Description: It is used for mapping RX queues to RX dma channels
3068  */
3069 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3070 {
3071         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3072         u32 queue;
3073         u32 chan;
3074
3075         for (queue = 0; queue < rx_queues_count; queue++) {
3076                 chan = priv->plat->rx_queues_cfg[queue].chan;
3077                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3078         }
3079 }
3080
3081 /**
3082  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3083  *  @priv: driver private structure
3084  *  Description: It is used for configuring the RX Queue Priority
3085  */
3086 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3087 {
3088         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3089         u32 queue;
3090         u32 prio;
3091
3092         for (queue = 0; queue < rx_queues_count; queue++) {
3093                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3094                         continue;
3095
3096                 prio = priv->plat->rx_queues_cfg[queue].prio;
3097                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3098         }
3099 }
3100
3101 /**
3102  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3103  *  @priv: driver private structure
3104  *  Description: It is used for configuring the TX Queue Priority
3105  */
3106 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3107 {
3108         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3109         u32 queue;
3110         u32 prio;
3111
3112         for (queue = 0; queue < tx_queues_count; queue++) {
3113                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3114                         continue;
3115
3116                 prio = priv->plat->tx_queues_cfg[queue].prio;
3117                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3118         }
3119 }
3120
3121 /**
3122  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3123  *  @priv: driver private structure
3124  *  Description: It is used for configuring the RX queue routing
3125  */
3126 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3127 {
3128         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3129         u32 queue;
3130         u8 packet;
3131
3132         for (queue = 0; queue < rx_queues_count; queue++) {
3133                 /* no specific packet type routing specified for the queue */
3134                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3135                         continue;
3136
3137                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3138                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3139         }
3140 }
3141
3142 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3143 {
3144         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3145                 priv->rss.enable = false;
3146                 return;
3147         }
3148
3149         if (priv->dev->features & NETIF_F_RXHASH)
3150                 priv->rss.enable = true;
3151         else
3152                 priv->rss.enable = false;
3153
3154         stmmac_rss_configure(priv, priv->hw, &priv->rss,
3155                              priv->plat->rx_queues_to_use);
3156 }
3157
3158 /**
3159  *  stmmac_mtl_configuration - Configure MTL
3160  *  @priv: driver private structure
3161  *  Description: It is used for configurring MTL
3162  */
3163 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3164 {
3165         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3166         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3167
3168         if (tx_queues_count > 1)
3169                 stmmac_set_tx_queue_weight(priv);
3170
3171         /* Configure MTL RX algorithms */
3172         if (rx_queues_count > 1)
3173                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3174                                 priv->plat->rx_sched_algorithm);
3175
3176         /* Configure MTL TX algorithms */
3177         if (tx_queues_count > 1)
3178                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3179                                 priv->plat->tx_sched_algorithm);
3180
3181         /* Configure CBS in AVB TX queues */
3182         if (tx_queues_count > 1)
3183                 stmmac_configure_cbs(priv);
3184
3185         /* Map RX MTL to DMA channels */
3186         stmmac_rx_queue_dma_chan_map(priv);
3187
3188         /* Enable MAC RX Queues */
3189         stmmac_mac_enable_rx_queues(priv);
3190
3191         /* Set RX priorities */
3192         if (rx_queues_count > 1)
3193                 stmmac_mac_config_rx_queues_prio(priv);
3194
3195         /* Set TX priorities */
3196         if (tx_queues_count > 1)
3197                 stmmac_mac_config_tx_queues_prio(priv);
3198
3199         /* Set RX routing */
3200         if (rx_queues_count > 1)
3201                 stmmac_mac_config_rx_queues_routing(priv);
3202
3203         /* Receive Side Scaling */
3204         if (rx_queues_count > 1)
3205                 stmmac_mac_config_rss(priv);
3206 }
3207
3208 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3209 {
3210         if (priv->dma_cap.asp) {
3211                 netdev_info(priv->dev, "Enabling Safety Features\n");
3212                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3213                                           priv->plat->safety_feat_cfg);
3214         } else {
3215                 netdev_info(priv->dev, "No Safety Features support found\n");
3216         }
3217 }
3218
3219 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3220 {
3221         char *name;
3222
3223         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3224         clear_bit(__FPE_REMOVING,  &priv->fpe_task_state);
3225
3226         name = priv->wq_name;
3227         sprintf(name, "%s-fpe", priv->dev->name);
3228
3229         priv->fpe_wq = create_singlethread_workqueue(name);
3230         if (!priv->fpe_wq) {
3231                 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3232
3233                 return -ENOMEM;
3234         }
3235         netdev_info(priv->dev, "FPE workqueue start");
3236
3237         return 0;
3238 }
3239
3240 /**
3241  * stmmac_hw_setup - setup mac in a usable state.
3242  *  @dev : pointer to the device structure.
3243  *  @ptp_register: register PTP if set
3244  *  Description:
3245  *  this is the main function to setup the HW in a usable state because the
3246  *  dma engine is reset, the core registers are configured (e.g. AXI,
3247  *  Checksum features, timers). The DMA is ready to start receiving and
3248  *  transmitting.
3249  *  Return value:
3250  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3251  *  file on failure.
3252  */
3253 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register)
3254 {
3255         struct stmmac_priv *priv = netdev_priv(dev);
3256         u32 rx_cnt = priv->plat->rx_queues_to_use;
3257         u32 tx_cnt = priv->plat->tx_queues_to_use;
3258         bool sph_en;
3259         u32 chan;
3260         int ret;
3261
3262         /* DMA initialization and SW reset */
3263         ret = stmmac_init_dma_engine(priv);
3264         if (ret < 0) {
3265                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3266                            __func__);
3267                 return ret;
3268         }
3269
3270         /* Copy the MAC addr into the HW  */
3271         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3272
3273         /* PS and related bits will be programmed according to the speed */
3274         if (priv->hw->pcs) {
3275                 int speed = priv->plat->mac_port_sel_speed;
3276
3277                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3278                     (speed == SPEED_1000)) {
3279                         priv->hw->ps = speed;
3280                 } else {
3281                         dev_warn(priv->device, "invalid port speed\n");
3282                         priv->hw->ps = 0;
3283                 }
3284         }
3285
3286         /* Initialize the MAC Core */
3287         stmmac_core_init(priv, priv->hw, dev);
3288
3289         /* Initialize MTL*/
3290         stmmac_mtl_configuration(priv);
3291
3292         /* Initialize Safety Features */
3293         stmmac_safety_feat_configuration(priv);
3294
3295         ret = stmmac_rx_ipc(priv, priv->hw);
3296         if (!ret) {
3297                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3298                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3299                 priv->hw->rx_csum = 0;
3300         }
3301
3302         /* Enable the MAC Rx/Tx */
3303         stmmac_mac_set(priv, priv->ioaddr, true);
3304
3305         /* Set the HW DMA mode and the COE */
3306         stmmac_dma_operation_mode(priv);
3307
3308         stmmac_mmc_setup(priv);
3309
3310         ret = stmmac_init_ptp(priv);
3311         if (ret == -EOPNOTSUPP)
3312                 netdev_warn(priv->dev, "PTP not supported by HW\n");
3313         else if (ret)
3314                 netdev_warn(priv->dev, "PTP init failed\n");
3315         else if (ptp_register)
3316                 stmmac_ptp_register(priv);
3317
3318         priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3319
3320         /* Convert the timer from msec to usec */
3321         if (!priv->tx_lpi_timer)
3322                 priv->tx_lpi_timer = eee_timer * 1000;
3323
3324         if (priv->use_riwt) {
3325                 u32 queue;
3326
3327                 for (queue = 0; queue < rx_cnt; queue++) {
3328                         if (!priv->rx_riwt[queue])
3329                                 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3330
3331                         stmmac_rx_watchdog(priv, priv->ioaddr,
3332                                            priv->rx_riwt[queue], queue);
3333                 }
3334         }
3335
3336         if (priv->hw->pcs)
3337                 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3338
3339         /* set TX and RX rings length */
3340         stmmac_set_rings_length(priv);
3341
3342         /* Enable TSO */
3343         if (priv->tso) {
3344                 for (chan = 0; chan < tx_cnt; chan++) {
3345                         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3346
3347                         /* TSO and TBS cannot co-exist */
3348                         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3349                                 continue;
3350
3351                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3352                 }
3353         }
3354
3355         /* Enable Split Header */
3356         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3357         for (chan = 0; chan < rx_cnt; chan++)
3358                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3359
3360
3361         /* VLAN Tag Insertion */
3362         if (priv->dma_cap.vlins)
3363                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3364
3365         /* TBS */
3366         for (chan = 0; chan < tx_cnt; chan++) {
3367                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3368                 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3369
3370                 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3371         }
3372
3373         /* Configure real RX and TX queues */
3374         netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3375         netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3376
3377         /* Start the ball rolling... */
3378         stmmac_start_all_dma(priv);
3379
3380         if (priv->dma_cap.fpesel) {
3381                 stmmac_fpe_start_wq(priv);
3382
3383                 if (priv->plat->fpe_cfg->enable)
3384                         stmmac_fpe_handshake(priv, true);
3385         }
3386
3387         return 0;
3388 }
3389
3390 static void stmmac_hw_teardown(struct net_device *dev)
3391 {
3392         struct stmmac_priv *priv = netdev_priv(dev);
3393
3394         clk_disable_unprepare(priv->plat->clk_ptp_ref);
3395 }
3396
3397 static void stmmac_free_irq(struct net_device *dev,
3398                             enum request_irq_err irq_err, int irq_idx)
3399 {
3400         struct stmmac_priv *priv = netdev_priv(dev);
3401         int j;
3402
3403         switch (irq_err) {
3404         case REQ_IRQ_ERR_ALL:
3405                 irq_idx = priv->plat->tx_queues_to_use;
3406                 fallthrough;
3407         case REQ_IRQ_ERR_TX:
3408                 for (j = irq_idx - 1; j >= 0; j--) {
3409                         if (priv->tx_irq[j] > 0) {
3410                                 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3411                                 free_irq(priv->tx_irq[j], &priv->tx_queue[j]);
3412                         }
3413                 }
3414                 irq_idx = priv->plat->rx_queues_to_use;
3415                 fallthrough;
3416         case REQ_IRQ_ERR_RX:
3417                 for (j = irq_idx - 1; j >= 0; j--) {
3418                         if (priv->rx_irq[j] > 0) {
3419                                 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3420                                 free_irq(priv->rx_irq[j], &priv->rx_queue[j]);
3421                         }
3422                 }
3423
3424                 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3425                         free_irq(priv->sfty_ue_irq, dev);
3426                 fallthrough;
3427         case REQ_IRQ_ERR_SFTY_UE:
3428                 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3429                         free_irq(priv->sfty_ce_irq, dev);
3430                 fallthrough;
3431         case REQ_IRQ_ERR_SFTY_CE:
3432                 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3433                         free_irq(priv->lpi_irq, dev);
3434                 fallthrough;
3435         case REQ_IRQ_ERR_LPI:
3436                 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3437                         free_irq(priv->wol_irq, dev);
3438                 fallthrough;
3439         case REQ_IRQ_ERR_WOL:
3440                 free_irq(dev->irq, dev);
3441                 fallthrough;
3442         case REQ_IRQ_ERR_MAC:
3443         case REQ_IRQ_ERR_NO:
3444                 /* If MAC IRQ request error, no more IRQ to free */
3445                 break;
3446         }
3447 }
3448
3449 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3450 {
3451         struct stmmac_priv *priv = netdev_priv(dev);
3452         enum request_irq_err irq_err;
3453         cpumask_t cpu_mask;
3454         int irq_idx = 0;
3455         char *int_name;
3456         int ret;
3457         int i;
3458
3459         /* For common interrupt */
3460         int_name = priv->int_name_mac;
3461         sprintf(int_name, "%s:%s", dev->name, "mac");
3462         ret = request_irq(dev->irq, stmmac_mac_interrupt,
3463                           0, int_name, dev);
3464         if (unlikely(ret < 0)) {
3465                 netdev_err(priv->dev,
3466                            "%s: alloc mac MSI %d (error: %d)\n",
3467                            __func__, dev->irq, ret);
3468                 irq_err = REQ_IRQ_ERR_MAC;
3469                 goto irq_error;
3470         }
3471
3472         /* Request the Wake IRQ in case of another line
3473          * is used for WoL
3474          */
3475         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3476                 int_name = priv->int_name_wol;
3477                 sprintf(int_name, "%s:%s", dev->name, "wol");
3478                 ret = request_irq(priv->wol_irq,
3479                                   stmmac_mac_interrupt,
3480                                   0, int_name, dev);
3481                 if (unlikely(ret < 0)) {
3482                         netdev_err(priv->dev,
3483                                    "%s: alloc wol MSI %d (error: %d)\n",
3484                                    __func__, priv->wol_irq, ret);
3485                         irq_err = REQ_IRQ_ERR_WOL;
3486                         goto irq_error;
3487                 }
3488         }
3489
3490         /* Request the LPI IRQ in case of another line
3491          * is used for LPI
3492          */
3493         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3494                 int_name = priv->int_name_lpi;
3495                 sprintf(int_name, "%s:%s", dev->name, "lpi");
3496                 ret = request_irq(priv->lpi_irq,
3497                                   stmmac_mac_interrupt,
3498                                   0, int_name, dev);
3499                 if (unlikely(ret < 0)) {
3500                         netdev_err(priv->dev,
3501                                    "%s: alloc lpi MSI %d (error: %d)\n",
3502                                    __func__, priv->lpi_irq, ret);
3503                         irq_err = REQ_IRQ_ERR_LPI;
3504                         goto irq_error;
3505                 }
3506         }
3507
3508         /* Request the Safety Feature Correctible Error line in
3509          * case of another line is used
3510          */
3511         if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3512                 int_name = priv->int_name_sfty_ce;
3513                 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3514                 ret = request_irq(priv->sfty_ce_irq,
3515                                   stmmac_safety_interrupt,
3516                                   0, int_name, dev);
3517                 if (unlikely(ret < 0)) {
3518                         netdev_err(priv->dev,
3519                                    "%s: alloc sfty ce MSI %d (error: %d)\n",
3520                                    __func__, priv->sfty_ce_irq, ret);
3521                         irq_err = REQ_IRQ_ERR_SFTY_CE;
3522                         goto irq_error;
3523                 }
3524         }
3525
3526         /* Request the Safety Feature Uncorrectible Error line in
3527          * case of another line is used
3528          */
3529         if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3530                 int_name = priv->int_name_sfty_ue;
3531                 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3532                 ret = request_irq(priv->sfty_ue_irq,
3533                                   stmmac_safety_interrupt,
3534                                   0, int_name, dev);
3535                 if (unlikely(ret < 0)) {
3536                         netdev_err(priv->dev,
3537                                    "%s: alloc sfty ue MSI %d (error: %d)\n",
3538                                    __func__, priv->sfty_ue_irq, ret);
3539                         irq_err = REQ_IRQ_ERR_SFTY_UE;
3540                         goto irq_error;
3541                 }
3542         }
3543
3544         /* Request Rx MSI irq */
3545         for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3546                 if (i >= MTL_MAX_RX_QUEUES)
3547                         break;
3548                 if (priv->rx_irq[i] == 0)
3549                         continue;
3550
3551                 int_name = priv->int_name_rx_irq[i];
3552                 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3553                 ret = request_irq(priv->rx_irq[i],
3554                                   stmmac_msi_intr_rx,
3555                                   0, int_name, &priv->rx_queue[i]);
3556                 if (unlikely(ret < 0)) {
3557                         netdev_err(priv->dev,
3558                                    "%s: alloc rx-%d  MSI %d (error: %d)\n",
3559                                    __func__, i, priv->rx_irq[i], ret);
3560                         irq_err = REQ_IRQ_ERR_RX;
3561                         irq_idx = i;
3562                         goto irq_error;
3563                 }
3564                 cpumask_clear(&cpu_mask);
3565                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3566                 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3567         }
3568
3569         /* Request Tx MSI irq */
3570         for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3571                 if (i >= MTL_MAX_TX_QUEUES)
3572                         break;
3573                 if (priv->tx_irq[i] == 0)
3574                         continue;
3575
3576                 int_name = priv->int_name_tx_irq[i];
3577                 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3578                 ret = request_irq(priv->tx_irq[i],
3579                                   stmmac_msi_intr_tx,
3580                                   0, int_name, &priv->tx_queue[i]);
3581                 if (unlikely(ret < 0)) {
3582                         netdev_err(priv->dev,
3583                                    "%s: alloc tx-%d  MSI %d (error: %d)\n",
3584                                    __func__, i, priv->tx_irq[i], ret);
3585                         irq_err = REQ_IRQ_ERR_TX;
3586                         irq_idx = i;
3587                         goto irq_error;
3588                 }
3589                 cpumask_clear(&cpu_mask);
3590                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3591                 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3592         }
3593
3594         return 0;
3595
3596 irq_error:
3597         stmmac_free_irq(dev, irq_err, irq_idx);
3598         return ret;
3599 }
3600
3601 static int stmmac_request_irq_single(struct net_device *dev)
3602 {
3603         struct stmmac_priv *priv = netdev_priv(dev);
3604         enum request_irq_err irq_err;
3605         int ret;
3606
3607         ret = request_irq(dev->irq, stmmac_interrupt,
3608                           IRQF_SHARED, dev->name, dev);
3609         if (unlikely(ret < 0)) {
3610                 netdev_err(priv->dev,
3611                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3612                            __func__, dev->irq, ret);
3613                 irq_err = REQ_IRQ_ERR_MAC;
3614                 goto irq_error;
3615         }
3616
3617         /* Request the Wake IRQ in case of another line
3618          * is used for WoL
3619          */
3620         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3621                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3622                                   IRQF_SHARED, dev->name, dev);
3623                 if (unlikely(ret < 0)) {
3624                         netdev_err(priv->dev,
3625                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3626                                    __func__, priv->wol_irq, ret);
3627                         irq_err = REQ_IRQ_ERR_WOL;
3628                         goto irq_error;
3629                 }
3630         }
3631
3632         /* Request the IRQ lines */
3633         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3634                 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3635                                   IRQF_SHARED, dev->name, dev);
3636                 if (unlikely(ret < 0)) {
3637                         netdev_err(priv->dev,
3638                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3639                                    __func__, priv->lpi_irq, ret);
3640                         irq_err = REQ_IRQ_ERR_LPI;
3641                         goto irq_error;
3642                 }
3643         }
3644
3645         return 0;
3646
3647 irq_error:
3648         stmmac_free_irq(dev, irq_err, 0);
3649         return ret;
3650 }
3651
3652 static int stmmac_request_irq(struct net_device *dev)
3653 {
3654         struct stmmac_priv *priv = netdev_priv(dev);
3655         int ret;
3656
3657         /* Request the IRQ lines */
3658         if (priv->plat->multi_msi_en)
3659                 ret = stmmac_request_irq_multi_msi(dev);
3660         else
3661                 ret = stmmac_request_irq_single(dev);
3662
3663         return ret;
3664 }
3665
3666 /**
3667  *  stmmac_open - open entry point of the driver
3668  *  @dev : pointer to the device structure.
3669  *  Description:
3670  *  This function is the open entry point of the driver.
3671  *  Return value:
3672  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3673  *  file on failure.
3674  */
3675 static int stmmac_open(struct net_device *dev)
3676 {
3677         struct stmmac_priv *priv = netdev_priv(dev);
3678         int mode = priv->plat->phy_interface;
3679         int bfsize = 0;
3680         u32 chan;
3681         int ret;
3682
3683         ret = pm_runtime_get_sync(priv->device);
3684         if (ret < 0) {
3685                 pm_runtime_put_noidle(priv->device);
3686                 return ret;
3687         }
3688
3689         if (priv->hw->pcs != STMMAC_PCS_TBI &&
3690             priv->hw->pcs != STMMAC_PCS_RTBI &&
3691             (!priv->hw->xpcs ||
3692              xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3693                 ret = stmmac_init_phy(dev);
3694                 if (ret) {
3695                         netdev_err(priv->dev,
3696                                    "%s: Cannot attach to PHY (error: %d)\n",
3697                                    __func__, ret);
3698                         goto init_phy_error;
3699                 }
3700         }
3701
3702         /* Extra statistics */
3703         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3704         priv->xstats.threshold = tc;
3705
3706         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
3707         if (bfsize < 0)
3708                 bfsize = 0;
3709
3710         if (bfsize < BUF_SIZE_16KiB)
3711                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
3712
3713         priv->dma_buf_sz = bfsize;
3714         buf_sz = bfsize;
3715
3716         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3717
3718         if (!priv->dma_tx_size)
3719                 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3720         if (!priv->dma_rx_size)
3721                 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3722
3723         /* Earlier check for TBS */
3724         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3725                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3726                 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3727
3728                 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3729                 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3730         }
3731
3732         ret = alloc_dma_desc_resources(priv);
3733         if (ret < 0) {
3734                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3735                            __func__);
3736                 goto dma_desc_error;
3737         }
3738
3739         ret = init_dma_desc_rings(dev, GFP_KERNEL);
3740         if (ret < 0) {
3741                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3742                            __func__);
3743                 goto init_error;
3744         }
3745
3746         ret = stmmac_hw_setup(dev, true);
3747         if (ret < 0) {
3748                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3749                 goto init_error;
3750         }
3751
3752         stmmac_init_coalesce(priv);
3753
3754         phylink_start(priv->phylink);
3755         /* We may have called phylink_speed_down before */
3756         phylink_speed_up(priv->phylink);
3757
3758         ret = stmmac_request_irq(dev);
3759         if (ret)
3760                 goto irq_error;
3761
3762         stmmac_enable_all_queues(priv);
3763         netif_tx_start_all_queues(priv->dev);
3764
3765         return 0;
3766
3767 irq_error:
3768         phylink_stop(priv->phylink);
3769
3770         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3771                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3772
3773         stmmac_hw_teardown(dev);
3774 init_error:
3775         free_dma_desc_resources(priv);
3776 dma_desc_error:
3777         phylink_disconnect_phy(priv->phylink);
3778 init_phy_error:
3779         pm_runtime_put(priv->device);
3780         return ret;
3781 }
3782
3783 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3784 {
3785         set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3786
3787         if (priv->fpe_wq)
3788                 destroy_workqueue(priv->fpe_wq);
3789
3790         netdev_info(priv->dev, "FPE workqueue stop");
3791 }
3792
3793 /**
3794  *  stmmac_release - close entry point of the driver
3795  *  @dev : device pointer.
3796  *  Description:
3797  *  This is the stop entry point of the driver.
3798  */
3799 static int stmmac_release(struct net_device *dev)
3800 {
3801         struct stmmac_priv *priv = netdev_priv(dev);
3802         u32 chan;
3803
3804         netif_tx_disable(dev);
3805
3806         if (device_may_wakeup(priv->device))
3807                 phylink_speed_down(priv->phylink, false);
3808         /* Stop and disconnect the PHY */
3809         phylink_stop(priv->phylink);
3810         phylink_disconnect_phy(priv->phylink);
3811
3812         stmmac_disable_all_queues(priv);
3813
3814         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3815                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3816
3817         /* Free the IRQ lines */
3818         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3819
3820         if (priv->eee_enabled) {
3821                 priv->tx_path_in_lpi_mode = false;
3822                 del_timer_sync(&priv->eee_ctrl_timer);
3823         }
3824
3825         /* Stop TX/RX DMA and clear the descriptors */
3826         stmmac_stop_all_dma(priv);
3827
3828         /* Release and free the Rx/Tx resources */
3829         free_dma_desc_resources(priv);
3830
3831         /* Disable the MAC Rx/Tx */
3832         stmmac_mac_set(priv, priv->ioaddr, false);
3833
3834         netif_carrier_off(dev);
3835
3836         stmmac_release_ptp(priv);
3837
3838         pm_runtime_put(priv->device);
3839
3840         if (priv->dma_cap.fpesel)
3841                 stmmac_fpe_stop_wq(priv);
3842
3843         return 0;
3844 }
3845
3846 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3847                                struct stmmac_tx_queue *tx_q)
3848 {
3849         u16 tag = 0x0, inner_tag = 0x0;
3850         u32 inner_type = 0x0;
3851         struct dma_desc *p;
3852
3853         if (!priv->dma_cap.vlins)
3854                 return false;
3855         if (!skb_vlan_tag_present(skb))
3856                 return false;
3857         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3858                 inner_tag = skb_vlan_tag_get(skb);
3859                 inner_type = STMMAC_VLAN_INSERT;
3860         }
3861
3862         tag = skb_vlan_tag_get(skb);
3863
3864         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3865                 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3866         else
3867                 p = &tx_q->dma_tx[tx_q->cur_tx];
3868
3869         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3870                 return false;
3871
3872         stmmac_set_tx_owner(priv, p);
3873         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
3874         return true;
3875 }
3876
3877 /**
3878  *  stmmac_tso_allocator - close entry point of the driver
3879  *  @priv: driver private structure
3880  *  @des: buffer start address
3881  *  @total_len: total length to fill in descriptors
3882  *  @last_segment: condition for the last descriptor
3883  *  @queue: TX queue index
3884  *  Description:
3885  *  This function fills descriptor and request new descriptors according to
3886  *  buffer length to fill
3887  */
3888 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
3889                                  int total_len, bool last_segment, u32 queue)
3890 {
3891         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3892         struct dma_desc *desc;
3893         u32 buff_size;
3894         int tmp_len;
3895
3896         tmp_len = total_len;
3897
3898         while (tmp_len > 0) {
3899                 dma_addr_t curr_addr;
3900
3901                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3902                                                 priv->dma_tx_size);
3903                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3904
3905                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3906                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3907                 else
3908                         desc = &tx_q->dma_tx[tx_q->cur_tx];
3909
3910                 curr_addr = des + (total_len - tmp_len);
3911                 if (priv->dma_cap.addr64 <= 32)
3912                         desc->des0 = cpu_to_le32(curr_addr);
3913                 else
3914                         stmmac_set_desc_addr(priv, desc, curr_addr);
3915
3916                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
3917                             TSO_MAX_BUFF_SIZE : tmp_len;
3918
3919                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3920                                 0, 1,
3921                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3922                                 0, 0);
3923
3924                 tmp_len -= TSO_MAX_BUFF_SIZE;
3925         }
3926 }
3927
3928 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
3929 {
3930         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3931         int desc_size;
3932
3933         if (likely(priv->extend_desc))
3934                 desc_size = sizeof(struct dma_extended_desc);
3935         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3936                 desc_size = sizeof(struct dma_edesc);
3937         else
3938                 desc_size = sizeof(struct dma_desc);
3939
3940         /* The own bit must be the latest setting done when prepare the
3941          * descriptor and then barrier is needed to make sure that
3942          * all is coherent before granting the DMA engine.
3943          */
3944         wmb();
3945
3946         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3947         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3948 }
3949
3950 /**
3951  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3952  *  @skb : the socket buffer
3953  *  @dev : device pointer
3954  *  Description: this is the transmit function that is called on TSO frames
3955  *  (support available on GMAC4 and newer chips).
3956  *  Diagram below show the ring programming in case of TSO frames:
3957  *
3958  *  First Descriptor
3959  *   --------
3960  *   | DES0 |---> buffer1 = L2/L3/L4 header
3961  *   | DES1 |---> TCP Payload (can continue on next descr...)
3962  *   | DES2 |---> buffer 1 and 2 len
3963  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3964  *   --------
3965  *      |
3966  *     ...
3967  *      |
3968  *   --------
3969  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
3970  *   | DES1 | --|
3971  *   | DES2 | --> buffer 1 and 2 len
3972  *   | DES3 |
3973  *   --------
3974  *
3975  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3976  */
3977 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3978 {
3979         struct dma_desc *desc, *first, *mss_desc = NULL;
3980         struct stmmac_priv *priv = netdev_priv(dev);
3981         int nfrags = skb_shinfo(skb)->nr_frags;
3982         u32 queue = skb_get_queue_mapping(skb);
3983         unsigned int first_entry, tx_packets;
3984         int tmp_pay_len = 0, first_tx;
3985         struct stmmac_tx_queue *tx_q;
3986         bool has_vlan, set_ic;
3987         u8 proto_hdr_len, hdr;
3988         u32 pay_len, mss;
3989         dma_addr_t des;
3990         int i;
3991
3992         tx_q = &priv->tx_queue[queue];
3993         first_tx = tx_q->cur_tx;
3994
3995         /* Compute header lengths */
3996         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3997                 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3998                 hdr = sizeof(struct udphdr);
3999         } else {
4000                 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4001                 hdr = tcp_hdrlen(skb);
4002         }
4003
4004         /* Desc availability based on threshold should be enough safe */
4005         if (unlikely(stmmac_tx_avail(priv, queue) <
4006                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
4007                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4008                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4009                                                                 queue));
4010                         /* This is a hard error, log it. */
4011                         netdev_err(priv->dev,
4012                                    "%s: Tx Ring full when queue awake\n",
4013                                    __func__);
4014                 }
4015                 return NETDEV_TX_BUSY;
4016         }
4017
4018         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
4019
4020         mss = skb_shinfo(skb)->gso_size;
4021
4022         /* set new MSS value if needed */
4023         if (mss != tx_q->mss) {
4024                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4025                         mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4026                 else
4027                         mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
4028
4029                 stmmac_set_mss(priv, mss_desc, mss);
4030                 tx_q->mss = mss;
4031                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
4032                                                 priv->dma_tx_size);
4033                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4034         }
4035
4036         if (netif_msg_tx_queued(priv)) {
4037                 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
4038                         __func__, hdr, proto_hdr_len, pay_len, mss);
4039                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
4040                         skb->data_len);
4041         }
4042
4043         /* Check if VLAN can be inserted by HW */
4044         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4045
4046         first_entry = tx_q->cur_tx;
4047         WARN_ON(tx_q->tx_skbuff[first_entry]);
4048
4049         if (tx_q->tbs & STMMAC_TBS_AVAIL)
4050                 desc = &tx_q->dma_entx[first_entry].basic;
4051         else
4052                 desc = &tx_q->dma_tx[first_entry];
4053         first = desc;
4054
4055         if (has_vlan)
4056                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4057
4058         /* first descriptor: fill Headers on Buf1 */
4059         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4060                              DMA_TO_DEVICE);
4061         if (dma_mapping_error(priv->device, des))
4062                 goto dma_map_err;
4063
4064         tx_q->tx_skbuff_dma[first_entry].buf = des;
4065         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4066         tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4067         tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4068
4069         if (priv->dma_cap.addr64 <= 32) {
4070                 first->des0 = cpu_to_le32(des);
4071
4072                 /* Fill start of payload in buff2 of first descriptor */
4073                 if (pay_len)
4074                         first->des1 = cpu_to_le32(des + proto_hdr_len);
4075
4076                 /* If needed take extra descriptors to fill the remaining payload */
4077                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4078         } else {
4079                 stmmac_set_desc_addr(priv, first, des);
4080                 tmp_pay_len = pay_len;
4081                 des += proto_hdr_len;
4082                 pay_len = 0;
4083         }
4084
4085         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4086
4087         /* Prepare fragments */
4088         for (i = 0; i < nfrags; i++) {
4089                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4090
4091                 des = skb_frag_dma_map(priv->device, frag, 0,
4092                                        skb_frag_size(frag),
4093                                        DMA_TO_DEVICE);
4094                 if (dma_mapping_error(priv->device, des))
4095                         goto dma_map_err;
4096
4097                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4098                                      (i == nfrags - 1), queue);
4099
4100                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4101                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4102                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4103                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4104         }
4105
4106         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4107
4108         /* Only the last descriptor gets to point to the skb. */
4109         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4110         tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4111
4112         /* Manage tx mitigation */
4113         tx_packets = (tx_q->cur_tx + 1) - first_tx;
4114         tx_q->tx_count_frames += tx_packets;
4115
4116         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4117                 set_ic = true;
4118         else if (!priv->tx_coal_frames[queue])
4119                 set_ic = false;
4120         else if (tx_packets > priv->tx_coal_frames[queue])
4121                 set_ic = true;
4122         else if ((tx_q->tx_count_frames %
4123                   priv->tx_coal_frames[queue]) < tx_packets)
4124                 set_ic = true;
4125         else
4126                 set_ic = false;
4127
4128         if (set_ic) {
4129                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4130                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4131                 else
4132                         desc = &tx_q->dma_tx[tx_q->cur_tx];
4133
4134                 tx_q->tx_count_frames = 0;
4135                 stmmac_set_tx_ic(priv, desc);
4136                 priv->xstats.tx_set_ic_bit++;
4137         }
4138
4139         /* We've used all descriptors we need for this skb, however,
4140          * advance cur_tx so that it references a fresh descriptor.
4141          * ndo_start_xmit will fill this descriptor the next time it's
4142          * called and stmmac_tx_clean may clean up to this descriptor.
4143          */
4144         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
4145
4146         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4147                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4148                           __func__);
4149                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4150         }
4151
4152         dev->stats.tx_bytes += skb->len;
4153         priv->xstats.tx_tso_frames++;
4154         priv->xstats.tx_tso_nfrags += nfrags;
4155
4156         if (priv->sarc_type)
4157                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4158
4159         skb_tx_timestamp(skb);
4160
4161         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4162                      priv->hwts_tx_en)) {
4163                 /* declare that device is doing timestamping */
4164                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4165                 stmmac_enable_tx_timestamp(priv, first);
4166         }
4167
4168         /* Complete the first descriptor before granting the DMA */
4169         stmmac_prepare_tso_tx_desc(priv, first, 1,
4170                         proto_hdr_len,
4171                         pay_len,
4172                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4173                         hdr / 4, (skb->len - proto_hdr_len));
4174
4175         /* If context desc is used to change MSS */
4176         if (mss_desc) {
4177                 /* Make sure that first descriptor has been completely
4178                  * written, including its own bit. This is because MSS is
4179                  * actually before first descriptor, so we need to make
4180                  * sure that MSS's own bit is the last thing written.
4181                  */
4182                 dma_wmb();
4183                 stmmac_set_tx_owner(priv, mss_desc);
4184         }
4185
4186         if (netif_msg_pktdata(priv)) {
4187                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4188                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4189                         tx_q->cur_tx, first, nfrags);
4190                 pr_info(">>> frame to be transmitted: ");
4191                 print_pkt(skb->data, skb_headlen(skb));
4192         }
4193
4194         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4195
4196         stmmac_flush_tx_descriptors(priv, queue);
4197         stmmac_tx_timer_arm(priv, queue);
4198
4199         return NETDEV_TX_OK;
4200
4201 dma_map_err:
4202         dev_err(priv->device, "Tx dma map failed\n");
4203         dev_kfree_skb(skb);
4204         priv->dev->stats.tx_dropped++;
4205         return NETDEV_TX_OK;
4206 }
4207
4208 /**
4209  *  stmmac_xmit - Tx entry point of the driver
4210  *  @skb : the socket buffer
4211  *  @dev : device pointer
4212  *  Description : this is the tx entry point of the driver.
4213  *  It programs the chain or the ring and supports oversized frames
4214  *  and SG feature.
4215  */
4216 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4217 {
4218         unsigned int first_entry, tx_packets, enh_desc;
4219         struct stmmac_priv *priv = netdev_priv(dev);
4220         unsigned int nopaged_len = skb_headlen(skb);
4221         int i, csum_insertion = 0, is_jumbo = 0;
4222         u32 queue = skb_get_queue_mapping(skb);
4223         int nfrags = skb_shinfo(skb)->nr_frags;
4224         int gso = skb_shinfo(skb)->gso_type;
4225         struct dma_edesc *tbs_desc = NULL;
4226         struct dma_desc *desc, *first;
4227         struct stmmac_tx_queue *tx_q;
4228         bool has_vlan, set_ic;
4229         int entry, first_tx;
4230         dma_addr_t des;
4231
4232         tx_q = &priv->tx_queue[queue];
4233         first_tx = tx_q->cur_tx;
4234
4235         if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4236                 stmmac_disable_eee_mode(priv);
4237
4238         /* Manage oversized TCP frames for GMAC4 device */
4239         if (skb_is_gso(skb) && priv->tso) {
4240                 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4241                         return stmmac_tso_xmit(skb, dev);
4242                 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4243                         return stmmac_tso_xmit(skb, dev);
4244         }
4245
4246         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4247                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4248                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4249                                                                 queue));
4250                         /* This is a hard error, log it. */
4251                         netdev_err(priv->dev,
4252                                    "%s: Tx Ring full when queue awake\n",
4253                                    __func__);
4254                 }
4255                 return NETDEV_TX_BUSY;
4256         }
4257
4258         /* Check if VLAN can be inserted by HW */
4259         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4260
4261         entry = tx_q->cur_tx;
4262         first_entry = entry;
4263         WARN_ON(tx_q->tx_skbuff[first_entry]);
4264
4265         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4266
4267         if (likely(priv->extend_desc))
4268                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4269         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4270                 desc = &tx_q->dma_entx[entry].basic;
4271         else
4272                 desc = tx_q->dma_tx + entry;
4273
4274         first = desc;
4275
4276         if (has_vlan)
4277                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4278
4279         enh_desc = priv->plat->enh_desc;
4280         /* To program the descriptors according to the size of the frame */
4281         if (enh_desc)
4282                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4283
4284         if (unlikely(is_jumbo)) {
4285                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4286                 if (unlikely(entry < 0) && (entry != -EINVAL))
4287                         goto dma_map_err;
4288         }
4289
4290         for (i = 0; i < nfrags; i++) {
4291                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4292                 int len = skb_frag_size(frag);
4293                 bool last_segment = (i == (nfrags - 1));
4294
4295                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4296                 WARN_ON(tx_q->tx_skbuff[entry]);
4297
4298                 if (likely(priv->extend_desc))
4299                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4300                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4301                         desc = &tx_q->dma_entx[entry].basic;
4302                 else
4303                         desc = tx_q->dma_tx + entry;
4304
4305                 des = skb_frag_dma_map(priv->device, frag, 0, len,
4306                                        DMA_TO_DEVICE);
4307                 if (dma_mapping_error(priv->device, des))
4308                         goto dma_map_err; /* should reuse desc w/o issues */
4309
4310                 tx_q->tx_skbuff_dma[entry].buf = des;
4311
4312                 stmmac_set_desc_addr(priv, desc, des);
4313
4314                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4315                 tx_q->tx_skbuff_dma[entry].len = len;
4316                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4317                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4318
4319                 /* Prepare the descriptor and set the own bit too */
4320                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4321                                 priv->mode, 1, last_segment, skb->len);
4322         }
4323
4324         /* Only the last descriptor gets to point to the skb. */
4325         tx_q->tx_skbuff[entry] = skb;
4326         tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4327
4328         /* According to the coalesce parameter the IC bit for the latest
4329          * segment is reset and the timer re-started to clean the tx status.
4330          * This approach takes care about the fragments: desc is the first
4331          * element in case of no SG.
4332          */
4333         tx_packets = (entry + 1) - first_tx;
4334         tx_q->tx_count_frames += tx_packets;
4335
4336         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4337                 set_ic = true;
4338         else if (!priv->tx_coal_frames[queue])
4339                 set_ic = false;
4340         else if (tx_packets > priv->tx_coal_frames[queue])
4341                 set_ic = true;
4342         else if ((tx_q->tx_count_frames %
4343                   priv->tx_coal_frames[queue]) < tx_packets)
4344                 set_ic = true;
4345         else
4346                 set_ic = false;
4347
4348         if (set_ic) {
4349                 if (likely(priv->extend_desc))
4350                         desc = &tx_q->dma_etx[entry].basic;
4351                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4352                         desc = &tx_q->dma_entx[entry].basic;
4353                 else
4354                         desc = &tx_q->dma_tx[entry];
4355
4356                 tx_q->tx_count_frames = 0;
4357                 stmmac_set_tx_ic(priv, desc);
4358                 priv->xstats.tx_set_ic_bit++;
4359         }
4360
4361         /* We've used all descriptors we need for this skb, however,
4362          * advance cur_tx so that it references a fresh descriptor.
4363          * ndo_start_xmit will fill this descriptor the next time it's
4364          * called and stmmac_tx_clean may clean up to this descriptor.
4365          */
4366         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4367         tx_q->cur_tx = entry;
4368
4369         if (netif_msg_pktdata(priv)) {
4370                 netdev_dbg(priv->dev,
4371                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4372                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4373                            entry, first, nfrags);
4374
4375                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4376                 print_pkt(skb->data, skb->len);
4377         }
4378
4379         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4380                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4381                           __func__);
4382                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4383         }
4384
4385         dev->stats.tx_bytes += skb->len;
4386
4387         if (priv->sarc_type)
4388                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4389
4390         skb_tx_timestamp(skb);
4391
4392         /* Ready to fill the first descriptor and set the OWN bit w/o any
4393          * problems because all the descriptors are actually ready to be
4394          * passed to the DMA engine.
4395          */
4396         if (likely(!is_jumbo)) {
4397                 bool last_segment = (nfrags == 0);
4398
4399                 des = dma_map_single(priv->device, skb->data,
4400                                      nopaged_len, DMA_TO_DEVICE);
4401                 if (dma_mapping_error(priv->device, des))
4402                         goto dma_map_err;
4403
4404                 tx_q->tx_skbuff_dma[first_entry].buf = des;
4405                 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4406                 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4407
4408                 stmmac_set_desc_addr(priv, first, des);
4409
4410                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4411                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4412
4413                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4414                              priv->hwts_tx_en)) {
4415                         /* declare that device is doing timestamping */
4416                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4417                         stmmac_enable_tx_timestamp(priv, first);
4418                 }
4419
4420                 /* Prepare the first descriptor setting the OWN bit too */
4421                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4422                                 csum_insertion, priv->mode, 0, last_segment,
4423                                 skb->len);
4424         }
4425
4426         if (tx_q->tbs & STMMAC_TBS_EN) {
4427                 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4428
4429                 tbs_desc = &tx_q->dma_entx[first_entry];
4430                 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4431         }
4432
4433         stmmac_set_tx_owner(priv, first);
4434
4435         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4436
4437         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4438
4439         stmmac_flush_tx_descriptors(priv, queue);
4440         stmmac_tx_timer_arm(priv, queue);
4441
4442         return NETDEV_TX_OK;
4443
4444 dma_map_err:
4445         netdev_err(priv->dev, "Tx DMA map failed\n");
4446         dev_kfree_skb(skb);
4447         priv->dev->stats.tx_dropped++;
4448         return NETDEV_TX_OK;
4449 }
4450
4451 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4452 {
4453         struct vlan_ethhdr *veth;
4454         __be16 vlan_proto;
4455         u16 vlanid;
4456
4457         veth = (struct vlan_ethhdr *)skb->data;
4458         vlan_proto = veth->h_vlan_proto;
4459
4460         if ((vlan_proto == htons(ETH_P_8021Q) &&
4461              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4462             (vlan_proto == htons(ETH_P_8021AD) &&
4463              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4464                 /* pop the vlan tag */
4465                 vlanid = ntohs(veth->h_vlan_TCI);
4466                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4467                 skb_pull(skb, VLAN_HLEN);
4468                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4469         }
4470 }
4471
4472 /**
4473  * stmmac_rx_refill - refill used skb preallocated buffers
4474  * @priv: driver private structure
4475  * @queue: RX queue index
4476  * Description : this is to reallocate the skb for the reception process
4477  * that is based on zero-copy.
4478  */
4479 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4480 {
4481         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4482         int dirty = stmmac_rx_dirty(priv, queue);
4483         unsigned int entry = rx_q->dirty_rx;
4484         gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
4485
4486         if (priv->dma_cap.addr64 <= 32)
4487                 gfp |= GFP_DMA32;
4488
4489         while (dirty-- > 0) {
4490                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4491                 struct dma_desc *p;
4492                 bool use_rx_wd;
4493
4494                 if (priv->extend_desc)
4495                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4496                 else
4497                         p = rx_q->dma_rx + entry;
4498
4499                 if (!buf->page) {
4500                         buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4501                         if (!buf->page)
4502                                 break;
4503                 }
4504
4505                 if (priv->sph && !buf->sec_page) {
4506                         buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4507                         if (!buf->sec_page)
4508                                 break;
4509
4510                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4511                 }
4512
4513                 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4514
4515                 stmmac_set_desc_addr(priv, p, buf->addr);
4516                 if (priv->sph)
4517                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4518                 else
4519                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4520                 stmmac_refill_desc3(priv, rx_q, p);
4521
4522                 rx_q->rx_count_frames++;
4523                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4524                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4525                         rx_q->rx_count_frames = 0;
4526
4527                 use_rx_wd = !priv->rx_coal_frames[queue];
4528                 use_rx_wd |= rx_q->rx_count_frames > 0;
4529                 if (!priv->use_riwt)
4530                         use_rx_wd = false;
4531
4532                 dma_wmb();
4533                 stmmac_set_rx_owner(priv, p, use_rx_wd);
4534
4535                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4536         }
4537         rx_q->dirty_rx = entry;
4538         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4539                             (rx_q->dirty_rx * sizeof(struct dma_desc));
4540         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4541 }
4542
4543 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4544                                        struct dma_desc *p,
4545                                        int status, unsigned int len)
4546 {
4547         unsigned int plen = 0, hlen = 0;
4548         int coe = priv->hw->rx_csum;
4549
4550         /* Not first descriptor, buffer is always zero */
4551         if (priv->sph && len)
4552                 return 0;
4553
4554         /* First descriptor, get split header length */
4555         stmmac_get_rx_header_len(priv, p, &hlen);
4556         if (priv->sph && hlen) {
4557                 priv->xstats.rx_split_hdr_pkt_n++;
4558                 return hlen;
4559         }
4560
4561         /* First descriptor, not last descriptor and not split header */
4562         if (status & rx_not_ls)
4563                 return priv->dma_buf_sz;
4564
4565         plen = stmmac_get_rx_frame_len(priv, p, coe);
4566
4567         /* First descriptor and last descriptor and not split header */
4568         return min_t(unsigned int, priv->dma_buf_sz, plen);
4569 }
4570
4571 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4572                                        struct dma_desc *p,
4573                                        int status, unsigned int len)
4574 {
4575         int coe = priv->hw->rx_csum;
4576         unsigned int plen = 0;
4577
4578         /* Not split header, buffer is not available */
4579         if (!priv->sph)
4580                 return 0;
4581
4582         /* Not last descriptor */
4583         if (status & rx_not_ls)
4584                 return priv->dma_buf_sz;
4585
4586         plen = stmmac_get_rx_frame_len(priv, p, coe);
4587
4588         /* Last descriptor */
4589         return plen - len;
4590 }
4591
4592 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4593                                 struct xdp_frame *xdpf, bool dma_map)
4594 {
4595         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4596         unsigned int entry = tx_q->cur_tx;
4597         struct dma_desc *tx_desc;
4598         dma_addr_t dma_addr;
4599         bool set_ic;
4600
4601         if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4602                 return STMMAC_XDP_CONSUMED;
4603
4604         if (likely(priv->extend_desc))
4605                 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4606         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4607                 tx_desc = &tx_q->dma_entx[entry].basic;
4608         else
4609                 tx_desc = tx_q->dma_tx + entry;
4610
4611         if (dma_map) {
4612                 dma_addr = dma_map_single(priv->device, xdpf->data,
4613                                           xdpf->len, DMA_TO_DEVICE);
4614                 if (dma_mapping_error(priv->device, dma_addr))
4615                         return STMMAC_XDP_CONSUMED;
4616
4617                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4618         } else {
4619                 struct page *page = virt_to_page(xdpf->data);
4620
4621                 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4622                            xdpf->headroom;
4623                 dma_sync_single_for_device(priv->device, dma_addr,
4624                                            xdpf->len, DMA_BIDIRECTIONAL);
4625
4626                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4627         }
4628
4629         tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4630         tx_q->tx_skbuff_dma[entry].map_as_page = false;
4631         tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4632         tx_q->tx_skbuff_dma[entry].last_segment = true;
4633         tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4634
4635         tx_q->xdpf[entry] = xdpf;
4636
4637         stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4638
4639         stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4640                                true, priv->mode, true, true,
4641                                xdpf->len);
4642
4643         tx_q->tx_count_frames++;
4644
4645         if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4646                 set_ic = true;
4647         else
4648                 set_ic = false;
4649
4650         if (set_ic) {
4651                 tx_q->tx_count_frames = 0;
4652                 stmmac_set_tx_ic(priv, tx_desc);
4653                 priv->xstats.tx_set_ic_bit++;
4654         }
4655
4656         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4657
4658         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4659         tx_q->cur_tx = entry;
4660
4661         return STMMAC_XDP_TX;
4662 }
4663
4664 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4665                                    int cpu)
4666 {
4667         int index = cpu;
4668
4669         if (unlikely(index < 0))
4670                 index = 0;
4671
4672         while (index >= priv->plat->tx_queues_to_use)
4673                 index -= priv->plat->tx_queues_to_use;
4674
4675         return index;
4676 }
4677
4678 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4679                                 struct xdp_buff *xdp)
4680 {
4681         struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4682         int cpu = smp_processor_id();
4683         struct netdev_queue *nq;
4684         int queue;
4685         int res;
4686
4687         if (unlikely(!xdpf))
4688                 return STMMAC_XDP_CONSUMED;
4689
4690         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4691         nq = netdev_get_tx_queue(priv->dev, queue);
4692
4693         __netif_tx_lock(nq, cpu);
4694         /* Avoids TX time-out as we are sharing with slow path */
4695         txq_trans_cond_update(nq);
4696
4697         res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4698         if (res == STMMAC_XDP_TX)
4699                 stmmac_flush_tx_descriptors(priv, queue);
4700
4701         __netif_tx_unlock(nq);
4702
4703         return res;
4704 }
4705
4706 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4707                                  struct bpf_prog *prog,
4708                                  struct xdp_buff *xdp)
4709 {
4710         u32 act;
4711         int res;
4712
4713         act = bpf_prog_run_xdp(prog, xdp);
4714         switch (act) {
4715         case XDP_PASS:
4716                 res = STMMAC_XDP_PASS;
4717                 break;
4718         case XDP_TX:
4719                 res = stmmac_xdp_xmit_back(priv, xdp);
4720                 break;
4721         case XDP_REDIRECT:
4722                 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4723                         res = STMMAC_XDP_CONSUMED;
4724                 else
4725                         res = STMMAC_XDP_REDIRECT;
4726                 break;
4727         default:
4728                 bpf_warn_invalid_xdp_action(priv->dev, prog, act);
4729                 fallthrough;
4730         case XDP_ABORTED:
4731                 trace_xdp_exception(priv->dev, prog, act);
4732                 fallthrough;
4733         case XDP_DROP:
4734                 res = STMMAC_XDP_CONSUMED;
4735                 break;
4736         }
4737
4738         return res;
4739 }
4740
4741 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4742                                            struct xdp_buff *xdp)
4743 {
4744         struct bpf_prog *prog;
4745         int res;
4746
4747         prog = READ_ONCE(priv->xdp_prog);
4748         if (!prog) {
4749                 res = STMMAC_XDP_PASS;
4750                 goto out;
4751         }
4752
4753         res = __stmmac_xdp_run_prog(priv, prog, xdp);
4754 out:
4755         return ERR_PTR(-res);
4756 }
4757
4758 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4759                                    int xdp_status)
4760 {
4761         int cpu = smp_processor_id();
4762         int queue;
4763
4764         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4765
4766         if (xdp_status & STMMAC_XDP_TX)
4767                 stmmac_tx_timer_arm(priv, queue);
4768
4769         if (xdp_status & STMMAC_XDP_REDIRECT)
4770                 xdp_do_flush();
4771 }
4772
4773 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4774                                                struct xdp_buff *xdp)
4775 {
4776         unsigned int metasize = xdp->data - xdp->data_meta;
4777         unsigned int datasize = xdp->data_end - xdp->data;
4778         struct sk_buff *skb;
4779
4780         skb = __napi_alloc_skb(&ch->rxtx_napi,
4781                                xdp->data_end - xdp->data_hard_start,
4782                                GFP_ATOMIC | __GFP_NOWARN);
4783         if (unlikely(!skb))
4784                 return NULL;
4785
4786         skb_reserve(skb, xdp->data - xdp->data_hard_start);
4787         memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4788         if (metasize)
4789                 skb_metadata_set(skb, metasize);
4790
4791         return skb;
4792 }
4793
4794 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4795                                    struct dma_desc *p, struct dma_desc *np,
4796                                    struct xdp_buff *xdp)
4797 {
4798         struct stmmac_channel *ch = &priv->channel[queue];
4799         unsigned int len = xdp->data_end - xdp->data;
4800         enum pkt_hash_types hash_type;
4801         int coe = priv->hw->rx_csum;
4802         struct sk_buff *skb;
4803         u32 hash;
4804
4805         skb = stmmac_construct_skb_zc(ch, xdp);
4806         if (!skb) {
4807                 priv->dev->stats.rx_dropped++;
4808                 return;
4809         }
4810
4811         stmmac_get_rx_hwtstamp(priv, p, np, skb);
4812         stmmac_rx_vlan(priv->dev, skb);
4813         skb->protocol = eth_type_trans(skb, priv->dev);
4814
4815         if (unlikely(!coe))
4816                 skb_checksum_none_assert(skb);
4817         else
4818                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4819
4820         if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4821                 skb_set_hash(skb, hash, hash_type);
4822
4823         skb_record_rx_queue(skb, queue);
4824         napi_gro_receive(&ch->rxtx_napi, skb);
4825
4826         priv->dev->stats.rx_packets++;
4827         priv->dev->stats.rx_bytes += len;
4828 }
4829
4830 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4831 {
4832         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4833         unsigned int entry = rx_q->dirty_rx;
4834         struct dma_desc *rx_desc = NULL;
4835         bool ret = true;
4836
4837         budget = min(budget, stmmac_rx_dirty(priv, queue));
4838
4839         while (budget-- > 0 && entry != rx_q->cur_rx) {
4840                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4841                 dma_addr_t dma_addr;
4842                 bool use_rx_wd;
4843
4844                 if (!buf->xdp) {
4845                         buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4846                         if (!buf->xdp) {
4847                                 ret = false;
4848                                 break;
4849                         }
4850                 }
4851
4852                 if (priv->extend_desc)
4853                         rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4854                 else
4855                         rx_desc = rx_q->dma_rx + entry;
4856
4857                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4858                 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4859                 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4860                 stmmac_refill_desc3(priv, rx_q, rx_desc);
4861
4862                 rx_q->rx_count_frames++;
4863                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4864                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4865                         rx_q->rx_count_frames = 0;
4866
4867                 use_rx_wd = !priv->rx_coal_frames[queue];
4868                 use_rx_wd |= rx_q->rx_count_frames > 0;
4869                 if (!priv->use_riwt)
4870                         use_rx_wd = false;
4871
4872                 dma_wmb();
4873                 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4874
4875                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4876         }
4877
4878         if (rx_desc) {
4879                 rx_q->dirty_rx = entry;
4880                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4881                                      (rx_q->dirty_rx * sizeof(struct dma_desc));
4882                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4883         }
4884
4885         return ret;
4886 }
4887
4888 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
4889 {
4890         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4891         unsigned int count = 0, error = 0, len = 0;
4892         int dirty = stmmac_rx_dirty(priv, queue);
4893         unsigned int next_entry = rx_q->cur_rx;
4894         unsigned int desc_size;
4895         struct bpf_prog *prog;
4896         bool failure = false;
4897         int xdp_status = 0;
4898         int status = 0;
4899
4900         if (netif_msg_rx_status(priv)) {
4901                 void *rx_head;
4902
4903                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
4904                 if (priv->extend_desc) {
4905                         rx_head = (void *)rx_q->dma_erx;
4906                         desc_size = sizeof(struct dma_extended_desc);
4907                 } else {
4908                         rx_head = (void *)rx_q->dma_rx;
4909                         desc_size = sizeof(struct dma_desc);
4910                 }
4911
4912                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
4913                                     rx_q->dma_rx_phy, desc_size);
4914         }
4915         while (count < limit) {
4916                 struct stmmac_rx_buffer *buf;
4917                 unsigned int buf1_len = 0;
4918                 struct dma_desc *np, *p;
4919                 int entry;
4920                 int res;
4921
4922                 if (!count && rx_q->state_saved) {
4923                         error = rx_q->state.error;
4924                         len = rx_q->state.len;
4925                 } else {
4926                         rx_q->state_saved = false;
4927                         error = 0;
4928                         len = 0;
4929                 }
4930
4931                 if (count >= limit)
4932                         break;
4933
4934 read_again:
4935                 buf1_len = 0;
4936                 entry = next_entry;
4937                 buf = &rx_q->buf_pool[entry];
4938
4939                 if (dirty >= STMMAC_RX_FILL_BATCH) {
4940                         failure = failure ||
4941                                   !stmmac_rx_refill_zc(priv, queue, dirty);
4942                         dirty = 0;
4943                 }
4944
4945                 if (priv->extend_desc)
4946                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4947                 else
4948                         p = rx_q->dma_rx + entry;
4949
4950                 /* read the status of the incoming frame */
4951                 status = stmmac_rx_status(priv, &priv->dev->stats,
4952                                           &priv->xstats, p);
4953                 /* check if managed by the DMA otherwise go ahead */
4954                 if (unlikely(status & dma_own))
4955                         break;
4956
4957                 /* Prefetch the next RX descriptor */
4958                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
4959                                                 priv->dma_rx_size);
4960                 next_entry = rx_q->cur_rx;
4961
4962                 if (priv->extend_desc)
4963                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
4964                 else
4965                         np = rx_q->dma_rx + next_entry;
4966
4967                 prefetch(np);
4968
4969                 /* Ensure a valid XSK buffer before proceed */
4970                 if (!buf->xdp)
4971                         break;
4972
4973                 if (priv->extend_desc)
4974                         stmmac_rx_extended_status(priv, &priv->dev->stats,
4975                                                   &priv->xstats,
4976                                                   rx_q->dma_erx + entry);
4977                 if (unlikely(status == discard_frame)) {
4978                         xsk_buff_free(buf->xdp);
4979                         buf->xdp = NULL;
4980                         dirty++;
4981                         error = 1;
4982                         if (!priv->hwts_rx_en)
4983                                 priv->dev->stats.rx_errors++;
4984                 }
4985
4986                 if (unlikely(error && (status & rx_not_ls)))
4987                         goto read_again;
4988                 if (unlikely(error)) {
4989                         count++;
4990                         continue;
4991                 }
4992
4993                 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
4994                 if (likely(status & rx_not_ls)) {
4995                         xsk_buff_free(buf->xdp);
4996                         buf->xdp = NULL;
4997                         dirty++;
4998                         count++;
4999                         goto read_again;
5000                 }
5001
5002                 /* XDP ZC Frame only support primary buffers for now */
5003                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5004                 len += buf1_len;
5005
5006                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5007                  * Type frames (LLC/LLC-SNAP)
5008                  *
5009                  * llc_snap is never checked in GMAC >= 4, so this ACS
5010                  * feature is always disabled and packets need to be
5011                  * stripped manually.
5012                  */
5013                 if (likely(!(status & rx_not_ls)) &&
5014                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5015                      unlikely(status != llc_snap))) {
5016                         buf1_len -= ETH_FCS_LEN;
5017                         len -= ETH_FCS_LEN;
5018                 }
5019
5020                 /* RX buffer is good and fit into a XSK pool buffer */
5021                 buf->xdp->data_end = buf->xdp->data + buf1_len;
5022                 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
5023
5024                 prog = READ_ONCE(priv->xdp_prog);
5025                 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
5026
5027                 switch (res) {
5028                 case STMMAC_XDP_PASS:
5029                         stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
5030                         xsk_buff_free(buf->xdp);
5031                         break;
5032                 case STMMAC_XDP_CONSUMED:
5033                         xsk_buff_free(buf->xdp);
5034                         priv->dev->stats.rx_dropped++;
5035                         break;
5036                 case STMMAC_XDP_TX:
5037                 case STMMAC_XDP_REDIRECT:
5038                         xdp_status |= res;
5039                         break;
5040                 }
5041
5042                 buf->xdp = NULL;
5043                 dirty++;
5044                 count++;
5045         }
5046
5047         if (status & rx_not_ls) {
5048                 rx_q->state_saved = true;
5049                 rx_q->state.error = error;
5050                 rx_q->state.len = len;
5051         }
5052
5053         stmmac_finalize_xdp_rx(priv, xdp_status);
5054
5055         priv->xstats.rx_pkt_n += count;
5056         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5057
5058         if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5059                 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5060                         xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5061                 else
5062                         xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5063
5064                 return (int)count;
5065         }
5066
5067         return failure ? limit : (int)count;
5068 }
5069
5070 /**
5071  * stmmac_rx - manage the receive process
5072  * @priv: driver private structure
5073  * @limit: napi bugget
5074  * @queue: RX queue index.
5075  * Description :  this the function called by the napi poll method.
5076  * It gets all the frames inside the ring.
5077  */
5078 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5079 {
5080         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5081         struct stmmac_channel *ch = &priv->channel[queue];
5082         unsigned int count = 0, error = 0, len = 0;
5083         int status = 0, coe = priv->hw->rx_csum;
5084         unsigned int next_entry = rx_q->cur_rx;
5085         enum dma_data_direction dma_dir;
5086         unsigned int desc_size;
5087         struct sk_buff *skb = NULL;
5088         struct xdp_buff xdp;
5089         int xdp_status = 0;
5090         int buf_sz;
5091
5092         dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5093         buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5094
5095         if (netif_msg_rx_status(priv)) {
5096                 void *rx_head;
5097
5098                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5099                 if (priv->extend_desc) {
5100                         rx_head = (void *)rx_q->dma_erx;
5101                         desc_size = sizeof(struct dma_extended_desc);
5102                 } else {
5103                         rx_head = (void *)rx_q->dma_rx;
5104                         desc_size = sizeof(struct dma_desc);
5105                 }
5106
5107                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
5108                                     rx_q->dma_rx_phy, desc_size);
5109         }
5110         while (count < limit) {
5111                 unsigned int buf1_len = 0, buf2_len = 0;
5112                 enum pkt_hash_types hash_type;
5113                 struct stmmac_rx_buffer *buf;
5114                 struct dma_desc *np, *p;
5115                 int entry;
5116                 u32 hash;
5117
5118                 if (!count && rx_q->state_saved) {
5119                         skb = rx_q->state.skb;
5120                         error = rx_q->state.error;
5121                         len = rx_q->state.len;
5122                 } else {
5123                         rx_q->state_saved = false;
5124                         skb = NULL;
5125                         error = 0;
5126                         len = 0;
5127                 }
5128
5129                 if (count >= limit)
5130                         break;
5131
5132 read_again:
5133                 buf1_len = 0;
5134                 buf2_len = 0;
5135                 entry = next_entry;
5136                 buf = &rx_q->buf_pool[entry];
5137
5138                 if (priv->extend_desc)
5139                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
5140                 else
5141                         p = rx_q->dma_rx + entry;
5142
5143                 /* read the status of the incoming frame */
5144                 status = stmmac_rx_status(priv, &priv->dev->stats,
5145                                 &priv->xstats, p);
5146                 /* check if managed by the DMA otherwise go ahead */
5147                 if (unlikely(status & dma_own))
5148                         break;
5149
5150                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5151                                                 priv->dma_rx_size);
5152                 next_entry = rx_q->cur_rx;
5153
5154                 if (priv->extend_desc)
5155                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5156                 else
5157                         np = rx_q->dma_rx + next_entry;
5158
5159                 prefetch(np);
5160
5161                 if (priv->extend_desc)
5162                         stmmac_rx_extended_status(priv, &priv->dev->stats,
5163                                         &priv->xstats, rx_q->dma_erx + entry);
5164                 if (unlikely(status == discard_frame)) {
5165                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5166                         buf->page = NULL;
5167                         error = 1;
5168                         if (!priv->hwts_rx_en)
5169                                 priv->dev->stats.rx_errors++;
5170                 }
5171
5172                 if (unlikely(error && (status & rx_not_ls)))
5173                         goto read_again;
5174                 if (unlikely(error)) {
5175                         dev_kfree_skb(skb);
5176                         skb = NULL;
5177                         count++;
5178                         continue;
5179                 }
5180
5181                 /* Buffer is good. Go on. */
5182
5183                 prefetch(page_address(buf->page) + buf->page_offset);
5184                 if (buf->sec_page)
5185                         prefetch(page_address(buf->sec_page));
5186
5187                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5188                 len += buf1_len;
5189                 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5190                 len += buf2_len;
5191
5192                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5193                  * Type frames (LLC/LLC-SNAP)
5194                  *
5195                  * llc_snap is never checked in GMAC >= 4, so this ACS
5196                  * feature is always disabled and packets need to be
5197                  * stripped manually.
5198                  */
5199                 if (likely(!(status & rx_not_ls)) &&
5200                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5201                      unlikely(status != llc_snap))) {
5202                         if (buf2_len) {
5203                                 buf2_len -= ETH_FCS_LEN;
5204                                 len -= ETH_FCS_LEN;
5205                         } else if (buf1_len) {
5206                                 buf1_len -= ETH_FCS_LEN;
5207                                 len -= ETH_FCS_LEN;
5208                         }
5209                 }
5210
5211                 if (!skb) {
5212                         unsigned int pre_len, sync_len;
5213
5214                         dma_sync_single_for_cpu(priv->device, buf->addr,
5215                                                 buf1_len, dma_dir);
5216
5217                         xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq);
5218                         xdp_prepare_buff(&xdp, page_address(buf->page),
5219                                          buf->page_offset, buf1_len, false);
5220
5221                         pre_len = xdp.data_end - xdp.data_hard_start -
5222                                   buf->page_offset;
5223                         skb = stmmac_xdp_run_prog(priv, &xdp);
5224                         /* Due xdp_adjust_tail: DMA sync for_device
5225                          * cover max len CPU touch
5226                          */
5227                         sync_len = xdp.data_end - xdp.data_hard_start -
5228                                    buf->page_offset;
5229                         sync_len = max(sync_len, pre_len);
5230
5231                         /* For Not XDP_PASS verdict */
5232                         if (IS_ERR(skb)) {
5233                                 unsigned int xdp_res = -PTR_ERR(skb);
5234
5235                                 if (xdp_res & STMMAC_XDP_CONSUMED) {
5236                                         page_pool_put_page(rx_q->page_pool,
5237                                                            virt_to_head_page(xdp.data),
5238                                                            sync_len, true);
5239                                         buf->page = NULL;
5240                                         priv->dev->stats.rx_dropped++;
5241
5242                                         /* Clear skb as it was set as
5243                                          * status by XDP program.
5244                                          */
5245                                         skb = NULL;
5246
5247                                         if (unlikely((status & rx_not_ls)))
5248                                                 goto read_again;
5249
5250                                         count++;
5251                                         continue;
5252                                 } else if (xdp_res & (STMMAC_XDP_TX |
5253                                                       STMMAC_XDP_REDIRECT)) {
5254                                         xdp_status |= xdp_res;
5255                                         buf->page = NULL;
5256                                         skb = NULL;
5257                                         count++;
5258                                         continue;
5259                                 }
5260                         }
5261                 }
5262
5263                 if (!skb) {
5264                         /* XDP program may expand or reduce tail */
5265                         buf1_len = xdp.data_end - xdp.data;
5266
5267                         skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5268                         if (!skb) {
5269                                 priv->dev->stats.rx_dropped++;
5270                                 count++;
5271                                 goto drain_data;
5272                         }
5273
5274                         /* XDP program may adjust header */
5275                         skb_copy_to_linear_data(skb, xdp.data, buf1_len);
5276                         skb_put(skb, buf1_len);
5277
5278                         /* Data payload copied into SKB, page ready for recycle */
5279                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5280                         buf->page = NULL;
5281                 } else if (buf1_len) {
5282                         dma_sync_single_for_cpu(priv->device, buf->addr,
5283                                                 buf1_len, dma_dir);
5284                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5285                                         buf->page, buf->page_offset, buf1_len,
5286                                         priv->dma_buf_sz);
5287
5288                         /* Data payload appended into SKB */
5289                         page_pool_release_page(rx_q->page_pool, buf->page);
5290                         buf->page = NULL;
5291                 }
5292
5293                 if (buf2_len) {
5294                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5295                                                 buf2_len, dma_dir);
5296                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5297                                         buf->sec_page, 0, buf2_len,
5298                                         priv->dma_buf_sz);
5299
5300                         /* Data payload appended into SKB */
5301                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
5302                         buf->sec_page = NULL;
5303                 }
5304
5305 drain_data:
5306                 if (likely(status & rx_not_ls))
5307                         goto read_again;
5308                 if (!skb)
5309                         continue;
5310
5311                 /* Got entire packet into SKB. Finish it. */
5312
5313                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5314                 stmmac_rx_vlan(priv->dev, skb);
5315                 skb->protocol = eth_type_trans(skb, priv->dev);
5316
5317                 if (unlikely(!coe))
5318                         skb_checksum_none_assert(skb);
5319                 else
5320                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5321
5322                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5323                         skb_set_hash(skb, hash, hash_type);
5324
5325                 skb_record_rx_queue(skb, queue);
5326                 napi_gro_receive(&ch->rx_napi, skb);
5327                 skb = NULL;
5328
5329                 priv->dev->stats.rx_packets++;
5330                 priv->dev->stats.rx_bytes += len;
5331                 count++;
5332         }
5333
5334         if (status & rx_not_ls || skb) {
5335                 rx_q->state_saved = true;
5336                 rx_q->state.skb = skb;
5337                 rx_q->state.error = error;
5338                 rx_q->state.len = len;
5339         }
5340
5341         stmmac_finalize_xdp_rx(priv, xdp_status);
5342
5343         stmmac_rx_refill(priv, queue);
5344
5345         priv->xstats.rx_pkt_n += count;
5346         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5347
5348         return count;
5349 }
5350
5351 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5352 {
5353         struct stmmac_channel *ch =
5354                 container_of(napi, struct stmmac_channel, rx_napi);
5355         struct stmmac_priv *priv = ch->priv_data;
5356         u32 chan = ch->index;
5357         int work_done;
5358
5359         priv->xstats.napi_poll++;
5360
5361         work_done = stmmac_rx(priv, budget, chan);
5362         if (work_done < budget && napi_complete_done(napi, work_done)) {
5363                 unsigned long flags;
5364
5365                 spin_lock_irqsave(&ch->lock, flags);
5366                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5367                 spin_unlock_irqrestore(&ch->lock, flags);
5368         }
5369
5370         return work_done;
5371 }
5372
5373 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5374 {
5375         struct stmmac_channel *ch =
5376                 container_of(napi, struct stmmac_channel, tx_napi);
5377         struct stmmac_priv *priv = ch->priv_data;
5378         u32 chan = ch->index;
5379         int work_done;
5380
5381         priv->xstats.napi_poll++;
5382
5383         work_done = stmmac_tx_clean(priv, budget, chan);
5384         work_done = min(work_done, budget);
5385
5386         if (work_done < budget && napi_complete_done(napi, work_done)) {
5387                 unsigned long flags;
5388
5389                 spin_lock_irqsave(&ch->lock, flags);
5390                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5391                 spin_unlock_irqrestore(&ch->lock, flags);
5392         }
5393
5394         return work_done;
5395 }
5396
5397 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5398 {
5399         struct stmmac_channel *ch =
5400                 container_of(napi, struct stmmac_channel, rxtx_napi);
5401         struct stmmac_priv *priv = ch->priv_data;
5402         int rx_done, tx_done, rxtx_done;
5403         u32 chan = ch->index;
5404
5405         priv->xstats.napi_poll++;
5406
5407         tx_done = stmmac_tx_clean(priv, budget, chan);
5408         tx_done = min(tx_done, budget);
5409
5410         rx_done = stmmac_rx_zc(priv, budget, chan);
5411
5412         rxtx_done = max(tx_done, rx_done);
5413
5414         /* If either TX or RX work is not complete, return budget
5415          * and keep pooling
5416          */
5417         if (rxtx_done >= budget)
5418                 return budget;
5419
5420         /* all work done, exit the polling mode */
5421         if (napi_complete_done(napi, rxtx_done)) {
5422                 unsigned long flags;
5423
5424                 spin_lock_irqsave(&ch->lock, flags);
5425                 /* Both RX and TX work done are compelte,
5426                  * so enable both RX & TX IRQs.
5427                  */
5428                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5429                 spin_unlock_irqrestore(&ch->lock, flags);
5430         }
5431
5432         return min(rxtx_done, budget - 1);
5433 }
5434
5435 /**
5436  *  stmmac_tx_timeout
5437  *  @dev : Pointer to net device structure
5438  *  @txqueue: the index of the hanging transmit queue
5439  *  Description: this function is called when a packet transmission fails to
5440  *   complete within a reasonable time. The driver will mark the error in the
5441  *   netdev structure and arrange for the device to be reset to a sane state
5442  *   in order to transmit a new packet.
5443  */
5444 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5445 {
5446         struct stmmac_priv *priv = netdev_priv(dev);
5447
5448         stmmac_global_err(priv);
5449 }
5450
5451 /**
5452  *  stmmac_set_rx_mode - entry point for multicast addressing
5453  *  @dev : pointer to the device structure
5454  *  Description:
5455  *  This function is a driver entry point which gets called by the kernel
5456  *  whenever multicast addresses must be enabled/disabled.
5457  *  Return value:
5458  *  void.
5459  */
5460 static void stmmac_set_rx_mode(struct net_device *dev)
5461 {
5462         struct stmmac_priv *priv = netdev_priv(dev);
5463
5464         stmmac_set_filter(priv, priv->hw, dev);
5465 }
5466
5467 /**
5468  *  stmmac_change_mtu - entry point to change MTU size for the device.
5469  *  @dev : device pointer.
5470  *  @new_mtu : the new MTU size for the device.
5471  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
5472  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
5473  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
5474  *  Return value:
5475  *  0 on success and an appropriate (-)ve integer as defined in errno.h
5476  *  file on failure.
5477  */
5478 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5479 {
5480         struct stmmac_priv *priv = netdev_priv(dev);
5481         int txfifosz = priv->plat->tx_fifo_size;
5482         const int mtu = new_mtu;
5483
5484         if (txfifosz == 0)
5485                 txfifosz = priv->dma_cap.tx_fifo_size;
5486
5487         txfifosz /= priv->plat->tx_queues_to_use;
5488
5489         if (netif_running(dev)) {
5490                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
5491                 return -EBUSY;
5492         }
5493
5494         if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5495                 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5496                 return -EINVAL;
5497         }
5498
5499         new_mtu = STMMAC_ALIGN(new_mtu);
5500
5501         /* If condition true, FIFO is too small or MTU too large */
5502         if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5503                 return -EINVAL;
5504
5505         dev->mtu = mtu;
5506
5507         netdev_update_features(dev);
5508
5509         return 0;
5510 }
5511
5512 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5513                                              netdev_features_t features)
5514 {
5515         struct stmmac_priv *priv = netdev_priv(dev);
5516
5517         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5518                 features &= ~NETIF_F_RXCSUM;
5519
5520         if (!priv->plat->tx_coe)
5521                 features &= ~NETIF_F_CSUM_MASK;
5522
5523         /* Some GMAC devices have a bugged Jumbo frame support that
5524          * needs to have the Tx COE disabled for oversized frames
5525          * (due to limited buffer sizes). In this case we disable
5526          * the TX csum insertion in the TDES and not use SF.
5527          */
5528         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5529                 features &= ~NETIF_F_CSUM_MASK;
5530
5531         /* Disable tso if asked by ethtool */
5532         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
5533                 if (features & NETIF_F_TSO)
5534                         priv->tso = true;
5535                 else
5536                         priv->tso = false;
5537         }
5538
5539         return features;
5540 }
5541
5542 static int stmmac_set_features(struct net_device *netdev,
5543                                netdev_features_t features)
5544 {
5545         struct stmmac_priv *priv = netdev_priv(netdev);
5546
5547         /* Keep the COE Type in case of csum is supporting */
5548         if (features & NETIF_F_RXCSUM)
5549                 priv->hw->rx_csum = priv->plat->rx_coe;
5550         else
5551                 priv->hw->rx_csum = 0;
5552         /* No check needed because rx_coe has been set before and it will be
5553          * fixed in case of issue.
5554          */
5555         stmmac_rx_ipc(priv, priv->hw);
5556
5557         if (priv->sph_cap) {
5558                 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5559                 u32 chan;
5560
5561                 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5562                         stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5563         }
5564
5565         return 0;
5566 }
5567
5568 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5569 {
5570         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5571         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5572         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5573         bool *hs_enable = &fpe_cfg->hs_enable;
5574
5575         if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5576                 return;
5577
5578         /* If LP has sent verify mPacket, LP is FPE capable */
5579         if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5580                 if (*lp_state < FPE_STATE_CAPABLE)
5581                         *lp_state = FPE_STATE_CAPABLE;
5582
5583                 /* If user has requested FPE enable, quickly response */
5584                 if (*hs_enable)
5585                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5586                                                 MPACKET_RESPONSE);
5587         }
5588
5589         /* If Local has sent verify mPacket, Local is FPE capable */
5590         if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5591                 if (*lo_state < FPE_STATE_CAPABLE)
5592                         *lo_state = FPE_STATE_CAPABLE;
5593         }
5594
5595         /* If LP has sent response mPacket, LP is entering FPE ON */
5596         if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5597                 *lp_state = FPE_STATE_ENTERING_ON;
5598
5599         /* If Local has sent response mPacket, Local is entering FPE ON */
5600         if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5601                 *lo_state = FPE_STATE_ENTERING_ON;
5602
5603         if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5604             !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5605             priv->fpe_wq) {
5606                 queue_work(priv->fpe_wq, &priv->fpe_task);
5607         }
5608 }
5609
5610 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5611 {
5612         u32 rx_cnt = priv->plat->rx_queues_to_use;
5613         u32 tx_cnt = priv->plat->tx_queues_to_use;
5614         u32 queues_count;
5615         u32 queue;
5616         bool xmac;
5617
5618         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5619         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5620
5621         if (priv->irq_wake)
5622                 pm_wakeup_event(priv->device, 0);
5623
5624         if (priv->dma_cap.estsel)
5625                 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5626                                       &priv->xstats, tx_cnt);
5627
5628         if (priv->dma_cap.fpesel) {
5629                 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5630                                                    priv->dev);
5631
5632                 stmmac_fpe_event_status(priv, status);
5633         }
5634
5635         /* To handle GMAC own interrupts */
5636         if ((priv->plat->has_gmac) || xmac) {
5637                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5638
5639                 if (unlikely(status)) {
5640                         /* For LPI we need to save the tx status */
5641                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5642                                 priv->tx_path_in_lpi_mode = true;
5643                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5644                                 priv->tx_path_in_lpi_mode = false;
5645                 }
5646
5647                 for (queue = 0; queue < queues_count; queue++) {
5648                         status = stmmac_host_mtl_irq_status(priv, priv->hw,
5649                                                             queue);
5650                 }
5651
5652                 /* PCS link status */
5653                 if (priv->hw->pcs) {
5654                         if (priv->xstats.pcs_link)
5655                                 netif_carrier_on(priv->dev);
5656                         else
5657                                 netif_carrier_off(priv->dev);
5658                 }
5659
5660                 stmmac_timestamp_interrupt(priv, priv);
5661         }
5662 }
5663
5664 /**
5665  *  stmmac_interrupt - main ISR
5666  *  @irq: interrupt number.
5667  *  @dev_id: to pass the net device pointer.
5668  *  Description: this is the main driver interrupt service routine.
5669  *  It can call:
5670  *  o DMA service routine (to manage incoming frame reception and transmission
5671  *    status)
5672  *  o Core interrupts to manage: remote wake-up, management counter, LPI
5673  *    interrupts.
5674  */
5675 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5676 {
5677         struct net_device *dev = (struct net_device *)dev_id;
5678         struct stmmac_priv *priv = netdev_priv(dev);
5679
5680         /* Check if adapter is up */
5681         if (test_bit(STMMAC_DOWN, &priv->state))
5682                 return IRQ_HANDLED;
5683
5684         /* Check if a fatal error happened */
5685         if (stmmac_safety_feat_interrupt(priv))
5686                 return IRQ_HANDLED;
5687
5688         /* To handle Common interrupts */
5689         stmmac_common_interrupt(priv);
5690
5691         /* To handle DMA interrupts */
5692         stmmac_dma_interrupt(priv);
5693
5694         return IRQ_HANDLED;
5695 }
5696
5697 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5698 {
5699         struct net_device *dev = (struct net_device *)dev_id;
5700         struct stmmac_priv *priv = netdev_priv(dev);
5701
5702         if (unlikely(!dev)) {
5703                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5704                 return IRQ_NONE;
5705         }
5706
5707         /* Check if adapter is up */
5708         if (test_bit(STMMAC_DOWN, &priv->state))
5709                 return IRQ_HANDLED;
5710
5711         /* To handle Common interrupts */
5712         stmmac_common_interrupt(priv);
5713
5714         return IRQ_HANDLED;
5715 }
5716
5717 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5718 {
5719         struct net_device *dev = (struct net_device *)dev_id;
5720         struct stmmac_priv *priv = netdev_priv(dev);
5721
5722         if (unlikely(!dev)) {
5723                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5724                 return IRQ_NONE;
5725         }
5726
5727         /* Check if adapter is up */
5728         if (test_bit(STMMAC_DOWN, &priv->state))
5729                 return IRQ_HANDLED;
5730
5731         /* Check if a fatal error happened */
5732         stmmac_safety_feat_interrupt(priv);
5733
5734         return IRQ_HANDLED;
5735 }
5736
5737 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5738 {
5739         struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5740         int chan = tx_q->queue_index;
5741         struct stmmac_priv *priv;
5742         int status;
5743
5744         priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]);
5745
5746         if (unlikely(!data)) {
5747                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5748                 return IRQ_NONE;
5749         }
5750
5751         /* Check if adapter is up */
5752         if (test_bit(STMMAC_DOWN, &priv->state))
5753                 return IRQ_HANDLED;
5754
5755         status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5756
5757         if (unlikely(status & tx_hard_error_bump_tc)) {
5758                 /* Try to bump up the dma threshold on this failure */
5759                 stmmac_bump_dma_threshold(priv, chan);
5760         } else if (unlikely(status == tx_hard_error)) {
5761                 stmmac_tx_err(priv, chan);
5762         }
5763
5764         return IRQ_HANDLED;
5765 }
5766
5767 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5768 {
5769         struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5770         int chan = rx_q->queue_index;
5771         struct stmmac_priv *priv;
5772
5773         priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]);
5774
5775         if (unlikely(!data)) {
5776                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5777                 return IRQ_NONE;
5778         }
5779
5780         /* Check if adapter is up */
5781         if (test_bit(STMMAC_DOWN, &priv->state))
5782                 return IRQ_HANDLED;
5783
5784         stmmac_napi_check(priv, chan, DMA_DIR_RX);
5785
5786         return IRQ_HANDLED;
5787 }
5788
5789 #ifdef CONFIG_NET_POLL_CONTROLLER
5790 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5791  * to allow network I/O with interrupts disabled.
5792  */
5793 static void stmmac_poll_controller(struct net_device *dev)
5794 {
5795         struct stmmac_priv *priv = netdev_priv(dev);
5796         int i;
5797
5798         /* If adapter is down, do nothing */
5799         if (test_bit(STMMAC_DOWN, &priv->state))
5800                 return;
5801
5802         if (priv->plat->multi_msi_en) {
5803                 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5804                         stmmac_msi_intr_rx(0, &priv->rx_queue[i]);
5805
5806                 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5807                         stmmac_msi_intr_tx(0, &priv->tx_queue[i]);
5808         } else {
5809                 disable_irq(dev->irq);
5810                 stmmac_interrupt(dev->irq, dev);
5811                 enable_irq(dev->irq);
5812         }
5813 }
5814 #endif
5815
5816 /**
5817  *  stmmac_ioctl - Entry point for the Ioctl
5818  *  @dev: Device pointer.
5819  *  @rq: An IOCTL specefic structure, that can contain a pointer to
5820  *  a proprietary structure used to pass information to the driver.
5821  *  @cmd: IOCTL command
5822  *  Description:
5823  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5824  */
5825 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5826 {
5827         struct stmmac_priv *priv = netdev_priv (dev);
5828         int ret = -EOPNOTSUPP;
5829
5830         if (!netif_running(dev))
5831                 return -EINVAL;
5832
5833         switch (cmd) {
5834         case SIOCGMIIPHY:
5835         case SIOCGMIIREG:
5836         case SIOCSMIIREG:
5837                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5838                 break;
5839         case SIOCSHWTSTAMP:
5840                 ret = stmmac_hwtstamp_set(dev, rq);
5841                 break;
5842         case SIOCGHWTSTAMP:
5843                 ret = stmmac_hwtstamp_get(dev, rq);
5844                 break;
5845         default:
5846                 break;
5847         }
5848
5849         return ret;
5850 }
5851
5852 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5853                                     void *cb_priv)
5854 {
5855         struct stmmac_priv *priv = cb_priv;
5856         int ret = -EOPNOTSUPP;
5857
5858         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
5859                 return ret;
5860
5861         __stmmac_disable_all_queues(priv);
5862
5863         switch (type) {
5864         case TC_SETUP_CLSU32:
5865                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
5866                 break;
5867         case TC_SETUP_CLSFLOWER:
5868                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
5869                 break;
5870         default:
5871                 break;
5872         }
5873
5874         stmmac_enable_all_queues(priv);
5875         return ret;
5876 }
5877
5878 static LIST_HEAD(stmmac_block_cb_list);
5879
5880 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
5881                            void *type_data)
5882 {
5883         struct stmmac_priv *priv = netdev_priv(ndev);
5884
5885         switch (type) {
5886         case TC_SETUP_BLOCK:
5887                 return flow_block_cb_setup_simple(type_data,
5888                                                   &stmmac_block_cb_list,
5889                                                   stmmac_setup_tc_block_cb,
5890                                                   priv, priv, true);
5891         case TC_SETUP_QDISC_CBS:
5892                 return stmmac_tc_setup_cbs(priv, priv, type_data);
5893         case TC_SETUP_QDISC_TAPRIO:
5894                 return stmmac_tc_setup_taprio(priv, priv, type_data);
5895         case TC_SETUP_QDISC_ETF:
5896                 return stmmac_tc_setup_etf(priv, priv, type_data);
5897         default:
5898                 return -EOPNOTSUPP;
5899         }
5900 }
5901
5902 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
5903                                struct net_device *sb_dev)
5904 {
5905         int gso = skb_shinfo(skb)->gso_type;
5906
5907         if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
5908                 /*
5909                  * There is no way to determine the number of TSO/USO
5910                  * capable Queues. Let's use always the Queue 0
5911                  * because if TSO/USO is supported then at least this
5912                  * one will be capable.
5913                  */
5914                 return 0;
5915         }
5916
5917         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
5918 }
5919
5920 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
5921 {
5922         struct stmmac_priv *priv = netdev_priv(ndev);
5923         int ret = 0;
5924
5925         ret = pm_runtime_get_sync(priv->device);
5926         if (ret < 0) {
5927                 pm_runtime_put_noidle(priv->device);
5928                 return ret;
5929         }
5930
5931         ret = eth_mac_addr(ndev, addr);
5932         if (ret)
5933                 goto set_mac_error;
5934
5935         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
5936
5937 set_mac_error:
5938         pm_runtime_put(priv->device);
5939
5940         return ret;
5941 }
5942
5943 #ifdef CONFIG_DEBUG_FS
5944 static struct dentry *stmmac_fs_dir;
5945
5946 static void sysfs_display_ring(void *head, int size, int extend_desc,
5947                                struct seq_file *seq, dma_addr_t dma_phy_addr)
5948 {
5949         int i;
5950         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
5951         struct dma_desc *p = (struct dma_desc *)head;
5952         dma_addr_t dma_addr;
5953
5954         for (i = 0; i < size; i++) {
5955                 if (extend_desc) {
5956                         dma_addr = dma_phy_addr + i * sizeof(*ep);
5957                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5958                                    i, &dma_addr,
5959                                    le32_to_cpu(ep->basic.des0),
5960                                    le32_to_cpu(ep->basic.des1),
5961                                    le32_to_cpu(ep->basic.des2),
5962                                    le32_to_cpu(ep->basic.des3));
5963                         ep++;
5964                 } else {
5965                         dma_addr = dma_phy_addr + i * sizeof(*p);
5966                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5967                                    i, &dma_addr,
5968                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
5969                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
5970                         p++;
5971                 }
5972                 seq_printf(seq, "\n");
5973         }
5974 }
5975
5976 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
5977 {
5978         struct net_device *dev = seq->private;
5979         struct stmmac_priv *priv = netdev_priv(dev);
5980         u32 rx_count = priv->plat->rx_queues_to_use;
5981         u32 tx_count = priv->plat->tx_queues_to_use;
5982         u32 queue;
5983
5984         if ((dev->flags & IFF_UP) == 0)
5985                 return 0;
5986
5987         for (queue = 0; queue < rx_count; queue++) {
5988                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5989
5990                 seq_printf(seq, "RX Queue %d:\n", queue);
5991
5992                 if (priv->extend_desc) {
5993                         seq_printf(seq, "Extended descriptor ring:\n");
5994                         sysfs_display_ring((void *)rx_q->dma_erx,
5995                                            priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy);
5996                 } else {
5997                         seq_printf(seq, "Descriptor ring:\n");
5998                         sysfs_display_ring((void *)rx_q->dma_rx,
5999                                            priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy);
6000                 }
6001         }
6002
6003         for (queue = 0; queue < tx_count; queue++) {
6004                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6005
6006                 seq_printf(seq, "TX Queue %d:\n", queue);
6007
6008                 if (priv->extend_desc) {
6009                         seq_printf(seq, "Extended descriptor ring:\n");
6010                         sysfs_display_ring((void *)tx_q->dma_etx,
6011                                            priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy);
6012                 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
6013                         seq_printf(seq, "Descriptor ring:\n");
6014                         sysfs_display_ring((void *)tx_q->dma_tx,
6015                                            priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy);
6016                 }
6017         }
6018
6019         return 0;
6020 }
6021 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
6022
6023 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
6024 {
6025         struct net_device *dev = seq->private;
6026         struct stmmac_priv *priv = netdev_priv(dev);
6027
6028         if (!priv->hw_cap_support) {
6029                 seq_printf(seq, "DMA HW features not supported\n");
6030                 return 0;
6031         }
6032
6033         seq_printf(seq, "==============================\n");
6034         seq_printf(seq, "\tDMA HW features\n");
6035         seq_printf(seq, "==============================\n");
6036
6037         seq_printf(seq, "\t10/100 Mbps: %s\n",
6038                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6039         seq_printf(seq, "\t1000 Mbps: %s\n",
6040                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
6041         seq_printf(seq, "\tHalf duplex: %s\n",
6042                    (priv->dma_cap.half_duplex) ? "Y" : "N");
6043         seq_printf(seq, "\tHash Filter: %s\n",
6044                    (priv->dma_cap.hash_filter) ? "Y" : "N");
6045         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6046                    (priv->dma_cap.multi_addr) ? "Y" : "N");
6047         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6048                    (priv->dma_cap.pcs) ? "Y" : "N");
6049         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6050                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
6051         seq_printf(seq, "\tPMT Remote wake up: %s\n",
6052                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6053         seq_printf(seq, "\tPMT Magic Frame: %s\n",
6054                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6055         seq_printf(seq, "\tRMON module: %s\n",
6056                    (priv->dma_cap.rmon) ? "Y" : "N");
6057         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6058                    (priv->dma_cap.time_stamp) ? "Y" : "N");
6059         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6060                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
6061         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6062                    (priv->dma_cap.eee) ? "Y" : "N");
6063         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6064         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6065                    (priv->dma_cap.tx_coe) ? "Y" : "N");
6066         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6067                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6068                            (priv->dma_cap.rx_coe) ? "Y" : "N");
6069         } else {
6070                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6071                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6072                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6073                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6074         }
6075         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6076                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6077         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6078                    priv->dma_cap.number_rx_channel);
6079         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6080                    priv->dma_cap.number_tx_channel);
6081         seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6082                    priv->dma_cap.number_rx_queues);
6083         seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6084                    priv->dma_cap.number_tx_queues);
6085         seq_printf(seq, "\tEnhanced descriptors: %s\n",
6086                    (priv->dma_cap.enh_desc) ? "Y" : "N");
6087         seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6088         seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6089         seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6090         seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6091         seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6092                    priv->dma_cap.pps_out_num);
6093         seq_printf(seq, "\tSafety Features: %s\n",
6094                    priv->dma_cap.asp ? "Y" : "N");
6095         seq_printf(seq, "\tFlexible RX Parser: %s\n",
6096                    priv->dma_cap.frpsel ? "Y" : "N");
6097         seq_printf(seq, "\tEnhanced Addressing: %d\n",
6098                    priv->dma_cap.addr64);
6099         seq_printf(seq, "\tReceive Side Scaling: %s\n",
6100                    priv->dma_cap.rssen ? "Y" : "N");
6101         seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6102                    priv->dma_cap.vlhash ? "Y" : "N");
6103         seq_printf(seq, "\tSplit Header: %s\n",
6104                    priv->dma_cap.sphen ? "Y" : "N");
6105         seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6106                    priv->dma_cap.vlins ? "Y" : "N");
6107         seq_printf(seq, "\tDouble VLAN: %s\n",
6108                    priv->dma_cap.dvlan ? "Y" : "N");
6109         seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6110                    priv->dma_cap.l3l4fnum);
6111         seq_printf(seq, "\tARP Offloading: %s\n",
6112                    priv->dma_cap.arpoffsel ? "Y" : "N");
6113         seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6114                    priv->dma_cap.estsel ? "Y" : "N");
6115         seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6116                    priv->dma_cap.fpesel ? "Y" : "N");
6117         seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6118                    priv->dma_cap.tbssel ? "Y" : "N");
6119         return 0;
6120 }
6121 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6122
6123 /* Use network device events to rename debugfs file entries.
6124  */
6125 static int stmmac_device_event(struct notifier_block *unused,
6126                                unsigned long event, void *ptr)
6127 {
6128         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6129         struct stmmac_priv *priv = netdev_priv(dev);
6130
6131         if (dev->netdev_ops != &stmmac_netdev_ops)
6132                 goto done;
6133
6134         switch (event) {
6135         case NETDEV_CHANGENAME:
6136                 if (priv->dbgfs_dir)
6137                         priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6138                                                          priv->dbgfs_dir,
6139                                                          stmmac_fs_dir,
6140                                                          dev->name);
6141                 break;
6142         }
6143 done:
6144         return NOTIFY_DONE;
6145 }
6146
6147 static struct notifier_block stmmac_notifier = {
6148         .notifier_call = stmmac_device_event,
6149 };
6150
6151 static void stmmac_init_fs(struct net_device *dev)
6152 {
6153         struct stmmac_priv *priv = netdev_priv(dev);
6154
6155         rtnl_lock();
6156
6157         /* Create per netdev entries */
6158         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6159
6160         /* Entry to report DMA RX/TX rings */
6161         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6162                             &stmmac_rings_status_fops);
6163
6164         /* Entry to report the DMA HW features */
6165         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6166                             &stmmac_dma_cap_fops);
6167
6168         rtnl_unlock();
6169 }
6170
6171 static void stmmac_exit_fs(struct net_device *dev)
6172 {
6173         struct stmmac_priv *priv = netdev_priv(dev);
6174
6175         debugfs_remove_recursive(priv->dbgfs_dir);
6176 }
6177 #endif /* CONFIG_DEBUG_FS */
6178
6179 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6180 {
6181         unsigned char *data = (unsigned char *)&vid_le;
6182         unsigned char data_byte = 0;
6183         u32 crc = ~0x0;
6184         u32 temp = 0;
6185         int i, bits;
6186
6187         bits = get_bitmask_order(VLAN_VID_MASK);
6188         for (i = 0; i < bits; i++) {
6189                 if ((i % 8) == 0)
6190                         data_byte = data[i / 8];
6191
6192                 temp = ((crc & 1) ^ data_byte) & 1;
6193                 crc >>= 1;
6194                 data_byte >>= 1;
6195
6196                 if (temp)
6197                         crc ^= 0xedb88320;
6198         }
6199
6200         return crc;
6201 }
6202
6203 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6204 {
6205         u32 crc, hash = 0;
6206         __le16 pmatch = 0;
6207         int count = 0;
6208         u16 vid = 0;
6209
6210         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6211                 __le16 vid_le = cpu_to_le16(vid);
6212                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6213                 hash |= (1 << crc);
6214                 count++;
6215         }
6216
6217         if (!priv->dma_cap.vlhash) {
6218                 if (count > 2) /* VID = 0 always passes filter */
6219                         return -EOPNOTSUPP;
6220
6221                 pmatch = cpu_to_le16(vid);
6222                 hash = 0;
6223         }
6224
6225         return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6226 }
6227
6228 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6229 {
6230         struct stmmac_priv *priv = netdev_priv(ndev);
6231         bool is_double = false;
6232         int ret;
6233
6234         if (be16_to_cpu(proto) == ETH_P_8021AD)
6235                 is_double = true;
6236
6237         set_bit(vid, priv->active_vlans);
6238         ret = stmmac_vlan_update(priv, is_double);
6239         if (ret) {
6240                 clear_bit(vid, priv->active_vlans);
6241                 return ret;
6242         }
6243
6244         if (priv->hw->num_vlan) {
6245                 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6246                 if (ret)
6247                         return ret;
6248         }
6249
6250         return 0;
6251 }
6252
6253 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6254 {
6255         struct stmmac_priv *priv = netdev_priv(ndev);
6256         bool is_double = false;
6257         int ret;
6258
6259         ret = pm_runtime_get_sync(priv->device);
6260         if (ret < 0) {
6261                 pm_runtime_put_noidle(priv->device);
6262                 return ret;
6263         }
6264
6265         if (be16_to_cpu(proto) == ETH_P_8021AD)
6266                 is_double = true;
6267
6268         clear_bit(vid, priv->active_vlans);
6269
6270         if (priv->hw->num_vlan) {
6271                 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6272                 if (ret)
6273                         goto del_vlan_error;
6274         }
6275
6276         ret = stmmac_vlan_update(priv, is_double);
6277
6278 del_vlan_error:
6279         pm_runtime_put(priv->device);
6280
6281         return ret;
6282 }
6283
6284 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6285 {
6286         struct stmmac_priv *priv = netdev_priv(dev);
6287
6288         switch (bpf->command) {
6289         case XDP_SETUP_PROG:
6290                 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6291         case XDP_SETUP_XSK_POOL:
6292                 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6293                                              bpf->xsk.queue_id);
6294         default:
6295                 return -EOPNOTSUPP;
6296         }
6297 }
6298
6299 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6300                            struct xdp_frame **frames, u32 flags)
6301 {
6302         struct stmmac_priv *priv = netdev_priv(dev);
6303         int cpu = smp_processor_id();
6304         struct netdev_queue *nq;
6305         int i, nxmit = 0;
6306         int queue;
6307
6308         if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6309                 return -ENETDOWN;
6310
6311         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6312                 return -EINVAL;
6313
6314         queue = stmmac_xdp_get_tx_queue(priv, cpu);
6315         nq = netdev_get_tx_queue(priv->dev, queue);
6316
6317         __netif_tx_lock(nq, cpu);
6318         /* Avoids TX time-out as we are sharing with slow path */
6319         txq_trans_cond_update(nq);
6320
6321         for (i = 0; i < num_frames; i++) {
6322                 int res;
6323
6324                 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6325                 if (res == STMMAC_XDP_CONSUMED)
6326                         break;
6327
6328                 nxmit++;
6329         }
6330
6331         if (flags & XDP_XMIT_FLUSH) {
6332                 stmmac_flush_tx_descriptors(priv, queue);
6333                 stmmac_tx_timer_arm(priv, queue);
6334         }
6335
6336         __netif_tx_unlock(nq);
6337
6338         return nxmit;
6339 }
6340
6341 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6342 {
6343         struct stmmac_channel *ch = &priv->channel[queue];
6344         unsigned long flags;
6345
6346         spin_lock_irqsave(&ch->lock, flags);
6347         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6348         spin_unlock_irqrestore(&ch->lock, flags);
6349
6350         stmmac_stop_rx_dma(priv, queue);
6351         __free_dma_rx_desc_resources(priv, queue);
6352 }
6353
6354 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6355 {
6356         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
6357         struct stmmac_channel *ch = &priv->channel[queue];
6358         unsigned long flags;
6359         u32 buf_size;
6360         int ret;
6361
6362         ret = __alloc_dma_rx_desc_resources(priv, queue);
6363         if (ret) {
6364                 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6365                 return;
6366         }
6367
6368         ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL);
6369         if (ret) {
6370                 __free_dma_rx_desc_resources(priv, queue);
6371                 netdev_err(priv->dev, "Failed to init RX desc.\n");
6372                 return;
6373         }
6374
6375         stmmac_clear_rx_descriptors(priv, queue);
6376
6377         stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6378                             rx_q->dma_rx_phy, rx_q->queue_index);
6379
6380         rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6381                              sizeof(struct dma_desc));
6382         stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6383                                rx_q->rx_tail_addr, rx_q->queue_index);
6384
6385         if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6386                 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6387                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6388                                       buf_size,
6389                                       rx_q->queue_index);
6390         } else {
6391                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6392                                       priv->dma_buf_sz,
6393                                       rx_q->queue_index);
6394         }
6395
6396         stmmac_start_rx_dma(priv, queue);
6397
6398         spin_lock_irqsave(&ch->lock, flags);
6399         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6400         spin_unlock_irqrestore(&ch->lock, flags);
6401 }
6402
6403 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6404 {
6405         struct stmmac_channel *ch = &priv->channel[queue];
6406         unsigned long flags;
6407
6408         spin_lock_irqsave(&ch->lock, flags);
6409         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6410         spin_unlock_irqrestore(&ch->lock, flags);
6411
6412         stmmac_stop_tx_dma(priv, queue);
6413         __free_dma_tx_desc_resources(priv, queue);
6414 }
6415
6416 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6417 {
6418         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6419         struct stmmac_channel *ch = &priv->channel[queue];
6420         unsigned long flags;
6421         int ret;
6422
6423         ret = __alloc_dma_tx_desc_resources(priv, queue);
6424         if (ret) {
6425                 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6426                 return;
6427         }
6428
6429         ret = __init_dma_tx_desc_rings(priv, queue);
6430         if (ret) {
6431                 __free_dma_tx_desc_resources(priv, queue);
6432                 netdev_err(priv->dev, "Failed to init TX desc.\n");
6433                 return;
6434         }
6435
6436         stmmac_clear_tx_descriptors(priv, queue);
6437
6438         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6439                             tx_q->dma_tx_phy, tx_q->queue_index);
6440
6441         if (tx_q->tbs & STMMAC_TBS_AVAIL)
6442                 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6443
6444         tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6445         stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6446                                tx_q->tx_tail_addr, tx_q->queue_index);
6447
6448         stmmac_start_tx_dma(priv, queue);
6449
6450         spin_lock_irqsave(&ch->lock, flags);
6451         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6452         spin_unlock_irqrestore(&ch->lock, flags);
6453 }
6454
6455 void stmmac_xdp_release(struct net_device *dev)
6456 {
6457         struct stmmac_priv *priv = netdev_priv(dev);
6458         u32 chan;
6459
6460         /* Disable NAPI process */
6461         stmmac_disable_all_queues(priv);
6462
6463         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6464                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
6465
6466         /* Free the IRQ lines */
6467         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
6468
6469         /* Stop TX/RX DMA channels */
6470         stmmac_stop_all_dma(priv);
6471
6472         /* Release and free the Rx/Tx resources */
6473         free_dma_desc_resources(priv);
6474
6475         /* Disable the MAC Rx/Tx */
6476         stmmac_mac_set(priv, priv->ioaddr, false);
6477
6478         /* set trans_start so we don't get spurious
6479          * watchdogs during reset
6480          */
6481         netif_trans_update(dev);
6482         netif_carrier_off(dev);
6483 }
6484
6485 int stmmac_xdp_open(struct net_device *dev)
6486 {
6487         struct stmmac_priv *priv = netdev_priv(dev);
6488         u32 rx_cnt = priv->plat->rx_queues_to_use;
6489         u32 tx_cnt = priv->plat->tx_queues_to_use;
6490         u32 dma_csr_ch = max(rx_cnt, tx_cnt);
6491         struct stmmac_rx_queue *rx_q;
6492         struct stmmac_tx_queue *tx_q;
6493         u32 buf_size;
6494         bool sph_en;
6495         u32 chan;
6496         int ret;
6497
6498         ret = alloc_dma_desc_resources(priv);
6499         if (ret < 0) {
6500                 netdev_err(dev, "%s: DMA descriptors allocation failed\n",
6501                            __func__);
6502                 goto dma_desc_error;
6503         }
6504
6505         ret = init_dma_desc_rings(dev, GFP_KERNEL);
6506         if (ret < 0) {
6507                 netdev_err(dev, "%s: DMA descriptors initialization failed\n",
6508                            __func__);
6509                 goto init_error;
6510         }
6511
6512         /* DMA CSR Channel configuration */
6513         for (chan = 0; chan < dma_csr_ch; chan++)
6514                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
6515
6516         /* Adjust Split header */
6517         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
6518
6519         /* DMA RX Channel Configuration */
6520         for (chan = 0; chan < rx_cnt; chan++) {
6521                 rx_q = &priv->rx_queue[chan];
6522
6523                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6524                                     rx_q->dma_rx_phy, chan);
6525
6526                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
6527                                      (rx_q->buf_alloc_num *
6528                                       sizeof(struct dma_desc));
6529                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6530                                        rx_q->rx_tail_addr, chan);
6531
6532                 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6533                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6534                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
6535                                               buf_size,
6536                                               rx_q->queue_index);
6537                 } else {
6538                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
6539                                               priv->dma_buf_sz,
6540                                               rx_q->queue_index);
6541                 }
6542
6543                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
6544         }
6545
6546         /* DMA TX Channel Configuration */
6547         for (chan = 0; chan < tx_cnt; chan++) {
6548                 tx_q = &priv->tx_queue[chan];
6549
6550                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6551                                     tx_q->dma_tx_phy, chan);
6552
6553                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6554                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6555                                        tx_q->tx_tail_addr, chan);
6556
6557                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
6558                 tx_q->txtimer.function = stmmac_tx_timer;
6559         }
6560
6561         /* Enable the MAC Rx/Tx */
6562         stmmac_mac_set(priv, priv->ioaddr, true);
6563
6564         /* Start Rx & Tx DMA Channels */
6565         stmmac_start_all_dma(priv);
6566
6567         ret = stmmac_request_irq(dev);
6568         if (ret)
6569                 goto irq_error;
6570
6571         /* Enable NAPI process*/
6572         stmmac_enable_all_queues(priv);
6573         netif_carrier_on(dev);
6574         netif_tx_start_all_queues(dev);
6575
6576         return 0;
6577
6578 irq_error:
6579         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6580                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
6581
6582         stmmac_hw_teardown(dev);
6583 init_error:
6584         free_dma_desc_resources(priv);
6585 dma_desc_error:
6586         return ret;
6587 }
6588
6589 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6590 {
6591         struct stmmac_priv *priv = netdev_priv(dev);
6592         struct stmmac_rx_queue *rx_q;
6593         struct stmmac_tx_queue *tx_q;
6594         struct stmmac_channel *ch;
6595
6596         if (test_bit(STMMAC_DOWN, &priv->state) ||
6597             !netif_carrier_ok(priv->dev))
6598                 return -ENETDOWN;
6599
6600         if (!stmmac_xdp_is_enabled(priv))
6601                 return -ENXIO;
6602
6603         if (queue >= priv->plat->rx_queues_to_use ||
6604             queue >= priv->plat->tx_queues_to_use)
6605                 return -EINVAL;
6606
6607         rx_q = &priv->rx_queue[queue];
6608         tx_q = &priv->tx_queue[queue];
6609         ch = &priv->channel[queue];
6610
6611         if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6612                 return -ENXIO;
6613
6614         if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6615                 /* EQoS does not have per-DMA channel SW interrupt,
6616                  * so we schedule RX Napi straight-away.
6617                  */
6618                 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6619                         __napi_schedule(&ch->rxtx_napi);
6620         }
6621
6622         return 0;
6623 }
6624
6625 static const struct net_device_ops stmmac_netdev_ops = {
6626         .ndo_open = stmmac_open,
6627         .ndo_start_xmit = stmmac_xmit,
6628         .ndo_stop = stmmac_release,
6629         .ndo_change_mtu = stmmac_change_mtu,
6630         .ndo_fix_features = stmmac_fix_features,
6631         .ndo_set_features = stmmac_set_features,
6632         .ndo_set_rx_mode = stmmac_set_rx_mode,
6633         .ndo_tx_timeout = stmmac_tx_timeout,
6634         .ndo_eth_ioctl = stmmac_ioctl,
6635         .ndo_setup_tc = stmmac_setup_tc,
6636         .ndo_select_queue = stmmac_select_queue,
6637 #ifdef CONFIG_NET_POLL_CONTROLLER
6638         .ndo_poll_controller = stmmac_poll_controller,
6639 #endif
6640         .ndo_set_mac_address = stmmac_set_mac_address,
6641         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6642         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6643         .ndo_bpf = stmmac_bpf,
6644         .ndo_xdp_xmit = stmmac_xdp_xmit,
6645         .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6646 };
6647
6648 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6649 {
6650         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6651                 return;
6652         if (test_bit(STMMAC_DOWN, &priv->state))
6653                 return;
6654
6655         netdev_err(priv->dev, "Reset adapter.\n");
6656
6657         rtnl_lock();
6658         netif_trans_update(priv->dev);
6659         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6660                 usleep_range(1000, 2000);
6661
6662         set_bit(STMMAC_DOWN, &priv->state);
6663         dev_close(priv->dev);
6664         dev_open(priv->dev, NULL);
6665         clear_bit(STMMAC_DOWN, &priv->state);
6666         clear_bit(STMMAC_RESETING, &priv->state);
6667         rtnl_unlock();
6668 }
6669
6670 static void stmmac_service_task(struct work_struct *work)
6671 {
6672         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6673                         service_task);
6674
6675         stmmac_reset_subtask(priv);
6676         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6677 }
6678
6679 /**
6680  *  stmmac_hw_init - Init the MAC device
6681  *  @priv: driver private structure
6682  *  Description: this function is to configure the MAC device according to
6683  *  some platform parameters or the HW capability register. It prepares the
6684  *  driver to use either ring or chain modes and to setup either enhanced or
6685  *  normal descriptors.
6686  */
6687 static int stmmac_hw_init(struct stmmac_priv *priv)
6688 {
6689         int ret;
6690
6691         /* dwmac-sun8i only work in chain mode */
6692         if (priv->plat->has_sun8i)
6693                 chain_mode = 1;
6694         priv->chain_mode = chain_mode;
6695
6696         /* Initialize HW Interface */
6697         ret = stmmac_hwif_init(priv);
6698         if (ret)
6699                 return ret;
6700
6701         /* Get the HW capability (new GMAC newer than 3.50a) */
6702         priv->hw_cap_support = stmmac_get_hw_features(priv);
6703         if (priv->hw_cap_support) {
6704                 dev_info(priv->device, "DMA HW capability register supported\n");
6705
6706                 /* We can override some gmac/dma configuration fields: e.g.
6707                  * enh_desc, tx_coe (e.g. that are passed through the
6708                  * platform) with the values from the HW capability
6709                  * register (if supported).
6710                  */
6711                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6712                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6713                                 !priv->plat->use_phy_wol;
6714                 priv->hw->pmt = priv->plat->pmt;
6715                 if (priv->dma_cap.hash_tb_sz) {
6716                         priv->hw->multicast_filter_bins =
6717                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
6718                         priv->hw->mcast_bits_log2 =
6719                                         ilog2(priv->hw->multicast_filter_bins);
6720                 }
6721
6722                 /* TXCOE doesn't work in thresh DMA mode */
6723                 if (priv->plat->force_thresh_dma_mode)
6724                         priv->plat->tx_coe = 0;
6725                 else
6726                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
6727
6728                 /* In case of GMAC4 rx_coe is from HW cap register. */
6729                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6730
6731                 if (priv->dma_cap.rx_coe_type2)
6732                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6733                 else if (priv->dma_cap.rx_coe_type1)
6734                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6735
6736         } else {
6737                 dev_info(priv->device, "No HW DMA feature register supported\n");
6738         }
6739
6740         if (priv->plat->rx_coe) {
6741                 priv->hw->rx_csum = priv->plat->rx_coe;
6742                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6743                 if (priv->synopsys_id < DWMAC_CORE_4_00)
6744                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6745         }
6746         if (priv->plat->tx_coe)
6747                 dev_info(priv->device, "TX Checksum insertion supported\n");
6748
6749         if (priv->plat->pmt) {
6750                 dev_info(priv->device, "Wake-Up On Lan supported\n");
6751                 device_set_wakeup_capable(priv->device, 1);
6752         }
6753
6754         if (priv->dma_cap.tsoen)
6755                 dev_info(priv->device, "TSO supported\n");
6756
6757         priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6758         priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6759
6760         /* Run HW quirks, if any */
6761         if (priv->hwif_quirks) {
6762                 ret = priv->hwif_quirks(priv);
6763                 if (ret)
6764                         return ret;
6765         }
6766
6767         /* Rx Watchdog is available in the COREs newer than the 3.40.
6768          * In some case, for example on bugged HW this feature
6769          * has to be disable and this can be done by passing the
6770          * riwt_off field from the platform.
6771          */
6772         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6773             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6774                 priv->use_riwt = 1;
6775                 dev_info(priv->device,
6776                          "Enable RX Mitigation via HW Watchdog Timer\n");
6777         }
6778
6779         return 0;
6780 }
6781
6782 static void stmmac_napi_add(struct net_device *dev)
6783 {
6784         struct stmmac_priv *priv = netdev_priv(dev);
6785         u32 queue, maxq;
6786
6787         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6788
6789         for (queue = 0; queue < maxq; queue++) {
6790                 struct stmmac_channel *ch = &priv->channel[queue];
6791
6792                 ch->priv_data = priv;
6793                 ch->index = queue;
6794                 spin_lock_init(&ch->lock);
6795
6796                 if (queue < priv->plat->rx_queues_to_use) {
6797                         netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
6798                                        NAPI_POLL_WEIGHT);
6799                 }
6800                 if (queue < priv->plat->tx_queues_to_use) {
6801                         netif_tx_napi_add(dev, &ch->tx_napi,
6802                                           stmmac_napi_poll_tx,
6803                                           NAPI_POLL_WEIGHT);
6804                 }
6805                 if (queue < priv->plat->rx_queues_to_use &&
6806                     queue < priv->plat->tx_queues_to_use) {
6807                         netif_napi_add(dev, &ch->rxtx_napi,
6808                                        stmmac_napi_poll_rxtx,
6809                                        NAPI_POLL_WEIGHT);
6810                 }
6811         }
6812 }
6813
6814 static void stmmac_napi_del(struct net_device *dev)
6815 {
6816         struct stmmac_priv *priv = netdev_priv(dev);
6817         u32 queue, maxq;
6818
6819         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6820
6821         for (queue = 0; queue < maxq; queue++) {
6822                 struct stmmac_channel *ch = &priv->channel[queue];
6823
6824                 if (queue < priv->plat->rx_queues_to_use)
6825                         netif_napi_del(&ch->rx_napi);
6826                 if (queue < priv->plat->tx_queues_to_use)
6827                         netif_napi_del(&ch->tx_napi);
6828                 if (queue < priv->plat->rx_queues_to_use &&
6829                     queue < priv->plat->tx_queues_to_use) {
6830                         netif_napi_del(&ch->rxtx_napi);
6831                 }
6832         }
6833 }
6834
6835 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
6836 {
6837         struct stmmac_priv *priv = netdev_priv(dev);
6838         int ret = 0;
6839
6840         if (netif_running(dev))
6841                 stmmac_release(dev);
6842
6843         stmmac_napi_del(dev);
6844
6845         priv->plat->rx_queues_to_use = rx_cnt;
6846         priv->plat->tx_queues_to_use = tx_cnt;
6847
6848         stmmac_napi_add(dev);
6849
6850         if (netif_running(dev))
6851                 ret = stmmac_open(dev);
6852
6853         return ret;
6854 }
6855
6856 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
6857 {
6858         struct stmmac_priv *priv = netdev_priv(dev);
6859         int ret = 0;
6860
6861         if (netif_running(dev))
6862                 stmmac_release(dev);
6863
6864         priv->dma_rx_size = rx_size;
6865         priv->dma_tx_size = tx_size;
6866
6867         if (netif_running(dev))
6868                 ret = stmmac_open(dev);
6869
6870         return ret;
6871 }
6872
6873 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
6874 static void stmmac_fpe_lp_task(struct work_struct *work)
6875 {
6876         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6877                                                 fpe_task);
6878         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
6879         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
6880         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
6881         bool *hs_enable = &fpe_cfg->hs_enable;
6882         bool *enable = &fpe_cfg->enable;
6883         int retries = 20;
6884
6885         while (retries-- > 0) {
6886                 /* Bail out immediately if FPE handshake is OFF */
6887                 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
6888                         break;
6889
6890                 if (*lo_state == FPE_STATE_ENTERING_ON &&
6891                     *lp_state == FPE_STATE_ENTERING_ON) {
6892                         stmmac_fpe_configure(priv, priv->ioaddr,
6893                                              priv->plat->tx_queues_to_use,
6894                                              priv->plat->rx_queues_to_use,
6895                                              *enable);
6896
6897                         netdev_info(priv->dev, "configured FPE\n");
6898
6899                         *lo_state = FPE_STATE_ON;
6900                         *lp_state = FPE_STATE_ON;
6901                         netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
6902                         break;
6903                 }
6904
6905                 if ((*lo_state == FPE_STATE_CAPABLE ||
6906                      *lo_state == FPE_STATE_ENTERING_ON) &&
6907                      *lp_state != FPE_STATE_ON) {
6908                         netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
6909                                     *lo_state, *lp_state);
6910                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6911                                                 MPACKET_VERIFY);
6912                 }
6913                 /* Sleep then retry */
6914                 msleep(500);
6915         }
6916
6917         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
6918 }
6919
6920 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
6921 {
6922         if (priv->plat->fpe_cfg->hs_enable != enable) {
6923                 if (enable) {
6924                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6925                                                 MPACKET_VERIFY);
6926                 } else {
6927                         priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
6928                         priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
6929                 }
6930
6931                 priv->plat->fpe_cfg->hs_enable = enable;
6932         }
6933 }
6934
6935 /**
6936  * stmmac_dvr_probe
6937  * @device: device pointer
6938  * @plat_dat: platform data pointer
6939  * @res: stmmac resource pointer
6940  * Description: this is the main probe function used to
6941  * call the alloc_etherdev, allocate the priv structure.
6942  * Return:
6943  * returns 0 on success, otherwise errno.
6944  */
6945 int stmmac_dvr_probe(struct device *device,
6946                      struct plat_stmmacenet_data *plat_dat,
6947                      struct stmmac_resources *res)
6948 {
6949         struct net_device *ndev = NULL;
6950         struct stmmac_priv *priv;
6951         u32 rxq;
6952         int i, ret = 0;
6953
6954         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
6955                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
6956         if (!ndev)
6957                 return -ENOMEM;
6958
6959         SET_NETDEV_DEV(ndev, device);
6960
6961         priv = netdev_priv(ndev);
6962         priv->device = device;
6963         priv->dev = ndev;
6964
6965         stmmac_set_ethtool_ops(ndev);
6966         priv->pause = pause;
6967         priv->plat = plat_dat;
6968         priv->ioaddr = res->addr;
6969         priv->dev->base_addr = (unsigned long)res->addr;
6970         priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
6971
6972         priv->dev->irq = res->irq;
6973         priv->wol_irq = res->wol_irq;
6974         priv->lpi_irq = res->lpi_irq;
6975         priv->sfty_ce_irq = res->sfty_ce_irq;
6976         priv->sfty_ue_irq = res->sfty_ue_irq;
6977         for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
6978                 priv->rx_irq[i] = res->rx_irq[i];
6979         for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
6980                 priv->tx_irq[i] = res->tx_irq[i];
6981
6982         if (!is_zero_ether_addr(res->mac))
6983                 eth_hw_addr_set(priv->dev, res->mac);
6984
6985         dev_set_drvdata(device, priv->dev);
6986
6987         /* Verify driver arguments */
6988         stmmac_verify_args();
6989
6990         priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
6991         if (!priv->af_xdp_zc_qps)
6992                 return -ENOMEM;
6993
6994         /* Allocate workqueue */
6995         priv->wq = create_singlethread_workqueue("stmmac_wq");
6996         if (!priv->wq) {
6997                 dev_err(priv->device, "failed to create workqueue\n");
6998                 return -ENOMEM;
6999         }
7000
7001         INIT_WORK(&priv->service_task, stmmac_service_task);
7002
7003         /* Initialize Link Partner FPE workqueue */
7004         INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
7005
7006         /* Override with kernel parameters if supplied XXX CRS XXX
7007          * this needs to have multiple instances
7008          */
7009         if ((phyaddr >= 0) && (phyaddr <= 31))
7010                 priv->plat->phy_addr = phyaddr;
7011
7012         if (priv->plat->stmmac_rst) {
7013                 ret = reset_control_assert(priv->plat->stmmac_rst);
7014                 reset_control_deassert(priv->plat->stmmac_rst);
7015                 /* Some reset controllers have only reset callback instead of
7016                  * assert + deassert callbacks pair.
7017                  */
7018                 if (ret == -ENOTSUPP)
7019                         reset_control_reset(priv->plat->stmmac_rst);
7020         }
7021
7022         ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
7023         if (ret == -ENOTSUPP)
7024                 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
7025                         ERR_PTR(ret));
7026
7027         /* Init MAC and get the capabilities */
7028         ret = stmmac_hw_init(priv);
7029         if (ret)
7030                 goto error_hw_init;
7031
7032         /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
7033          */
7034         if (priv->synopsys_id < DWMAC_CORE_5_20)
7035                 priv->plat->dma_cfg->dche = false;
7036
7037         stmmac_check_ether_addr(priv);
7038
7039         ndev->netdev_ops = &stmmac_netdev_ops;
7040
7041         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
7042                             NETIF_F_RXCSUM;
7043
7044         ret = stmmac_tc_init(priv, priv);
7045         if (!ret) {
7046                 ndev->hw_features |= NETIF_F_HW_TC;
7047         }
7048
7049         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
7050                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
7051                 if (priv->plat->has_gmac4)
7052                         ndev->hw_features |= NETIF_F_GSO_UDP_L4;
7053                 priv->tso = true;
7054                 dev_info(priv->device, "TSO feature enabled\n");
7055         }
7056
7057         if (priv->dma_cap.sphen) {
7058                 ndev->hw_features |= NETIF_F_GRO;
7059                 priv->sph_cap = true;
7060                 priv->sph = priv->sph_cap;
7061                 dev_info(priv->device, "SPH feature enabled\n");
7062         }
7063
7064         /* The current IP register MAC_HW_Feature1[ADDR64] only define
7065          * 32/40/64 bit width, but some SOC support others like i.MX8MP
7066          * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
7067          * So overwrite dma_cap.addr64 according to HW real design.
7068          */
7069         if (priv->plat->addr64)
7070                 priv->dma_cap.addr64 = priv->plat->addr64;
7071
7072         if (priv->dma_cap.addr64) {
7073                 ret = dma_set_mask_and_coherent(device,
7074                                 DMA_BIT_MASK(priv->dma_cap.addr64));
7075                 if (!ret) {
7076                         dev_info(priv->device, "Using %d bits DMA width\n",
7077                                  priv->dma_cap.addr64);
7078
7079                         /*
7080                          * If more than 32 bits can be addressed, make sure to
7081                          * enable enhanced addressing mode.
7082                          */
7083                         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
7084                                 priv->plat->dma_cfg->eame = true;
7085                 } else {
7086                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
7087                         if (ret) {
7088                                 dev_err(priv->device, "Failed to set DMA Mask\n");
7089                                 goto error_hw_init;
7090                         }
7091
7092                         priv->dma_cap.addr64 = 32;
7093                 }
7094         }
7095
7096         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
7097         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
7098 #ifdef STMMAC_VLAN_TAG_USED
7099         /* Both mac100 and gmac support receive VLAN tag detection */
7100         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
7101         if (priv->dma_cap.vlhash) {
7102                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7103                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
7104         }
7105         if (priv->dma_cap.vlins) {
7106                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
7107                 if (priv->dma_cap.dvlan)
7108                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
7109         }
7110 #endif
7111         priv->msg_enable = netif_msg_init(debug, default_msg_level);
7112
7113         /* Initialize RSS */
7114         rxq = priv->plat->rx_queues_to_use;
7115         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
7116         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7117                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
7118
7119         if (priv->dma_cap.rssen && priv->plat->rss_en)
7120                 ndev->features |= NETIF_F_RXHASH;
7121
7122         /* MTU range: 46 - hw-specific max */
7123         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
7124         if (priv->plat->has_xgmac)
7125                 ndev->max_mtu = XGMAC_JUMBO_LEN;
7126         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
7127                 ndev->max_mtu = JUMBO_LEN;
7128         else
7129                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
7130         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
7131          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
7132          */
7133         if ((priv->plat->maxmtu < ndev->max_mtu) &&
7134             (priv->plat->maxmtu >= ndev->min_mtu))
7135                 ndev->max_mtu = priv->plat->maxmtu;
7136         else if (priv->plat->maxmtu < ndev->min_mtu)
7137                 dev_warn(priv->device,
7138                          "%s: warning: maxmtu having invalid value (%d)\n",
7139                          __func__, priv->plat->maxmtu);
7140
7141         if (flow_ctrl)
7142                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
7143
7144         /* Setup channels NAPI */
7145         stmmac_napi_add(ndev);
7146
7147         mutex_init(&priv->lock);
7148
7149         /* If a specific clk_csr value is passed from the platform
7150          * this means that the CSR Clock Range selection cannot be
7151          * changed at run-time and it is fixed. Viceversa the driver'll try to
7152          * set the MDC clock dynamically according to the csr actual
7153          * clock input.
7154          */
7155         if (priv->plat->clk_csr >= 0)
7156                 priv->clk_csr = priv->plat->clk_csr;
7157         else
7158                 stmmac_clk_csr_set(priv);
7159
7160         stmmac_check_pcs_mode(priv);
7161
7162         pm_runtime_get_noresume(device);
7163         pm_runtime_set_active(device);
7164         if (!pm_runtime_enabled(device))
7165                 pm_runtime_enable(device);
7166
7167         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7168             priv->hw->pcs != STMMAC_PCS_RTBI) {
7169                 /* MDIO bus Registration */
7170                 ret = stmmac_mdio_register(ndev);
7171                 if (ret < 0) {
7172                         dev_err(priv->device,
7173                                 "%s: MDIO bus (id: %d) registration failed",
7174                                 __func__, priv->plat->bus_id);
7175                         goto error_mdio_register;
7176                 }
7177         }
7178
7179         if (priv->plat->speed_mode_2500)
7180                 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7181
7182         if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7183                 ret = stmmac_xpcs_setup(priv->mii);
7184                 if (ret)
7185                         goto error_xpcs_setup;
7186         }
7187
7188         ret = stmmac_phy_setup(priv);
7189         if (ret) {
7190                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7191                 goto error_phy_setup;
7192         }
7193
7194         ret = register_netdev(ndev);
7195         if (ret) {
7196                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7197                         __func__, ret);
7198                 goto error_netdev_register;
7199         }
7200
7201         if (priv->plat->serdes_powerup) {
7202                 ret = priv->plat->serdes_powerup(ndev,
7203                                                  priv->plat->bsp_priv);
7204
7205                 if (ret < 0)
7206                         goto error_serdes_powerup;
7207         }
7208
7209 #ifdef CONFIG_DEBUG_FS
7210         stmmac_init_fs(ndev);
7211 #endif
7212
7213         if (priv->plat->dump_debug_regs)
7214                 priv->plat->dump_debug_regs(priv->plat->bsp_priv);
7215
7216         /* Let pm_runtime_put() disable the clocks.
7217          * If CONFIG_PM is not enabled, the clocks will stay powered.
7218          */
7219         pm_runtime_put(device);
7220
7221         return ret;
7222
7223 error_serdes_powerup:
7224         unregister_netdev(ndev);
7225 error_netdev_register:
7226         phylink_destroy(priv->phylink);
7227 error_xpcs_setup:
7228 error_phy_setup:
7229         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7230             priv->hw->pcs != STMMAC_PCS_RTBI)
7231                 stmmac_mdio_unregister(ndev);
7232 error_mdio_register:
7233         stmmac_napi_del(ndev);
7234 error_hw_init:
7235         destroy_workqueue(priv->wq);
7236         bitmap_free(priv->af_xdp_zc_qps);
7237
7238         return ret;
7239 }
7240 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7241
7242 /**
7243  * stmmac_dvr_remove
7244  * @dev: device pointer
7245  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7246  * changes the link status, releases the DMA descriptor rings.
7247  */
7248 int stmmac_dvr_remove(struct device *dev)
7249 {
7250         struct net_device *ndev = dev_get_drvdata(dev);
7251         struct stmmac_priv *priv = netdev_priv(ndev);
7252
7253         netdev_info(priv->dev, "%s: removing driver", __func__);
7254
7255         pm_runtime_get_sync(dev);
7256         pm_runtime_disable(dev);
7257         pm_runtime_put_noidle(dev);
7258
7259         stmmac_stop_all_dma(priv);
7260         stmmac_mac_set(priv, priv->ioaddr, false);
7261         netif_carrier_off(ndev);
7262         unregister_netdev(ndev);
7263
7264         /* Serdes power down needs to happen after VLAN filter
7265          * is deleted that is triggered by unregister_netdev().
7266          */
7267         if (priv->plat->serdes_powerdown)
7268                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7269
7270 #ifdef CONFIG_DEBUG_FS
7271         stmmac_exit_fs(ndev);
7272 #endif
7273         phylink_destroy(priv->phylink);
7274         if (priv->plat->stmmac_rst)
7275                 reset_control_assert(priv->plat->stmmac_rst);
7276         reset_control_assert(priv->plat->stmmac_ahb_rst);
7277         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7278             priv->hw->pcs != STMMAC_PCS_RTBI)
7279                 stmmac_mdio_unregister(ndev);
7280         destroy_workqueue(priv->wq);
7281         mutex_destroy(&priv->lock);
7282         bitmap_free(priv->af_xdp_zc_qps);
7283
7284         return 0;
7285 }
7286 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7287
7288 /**
7289  * stmmac_suspend - suspend callback
7290  * @dev: device pointer
7291  * Description: this is the function to suspend the device and it is called
7292  * by the platform driver to stop the network queue, release the resources,
7293  * program the PMT register (for WoL), clean and release driver resources.
7294  */
7295 int stmmac_suspend(struct device *dev)
7296 {
7297         struct net_device *ndev = dev_get_drvdata(dev);
7298         struct stmmac_priv *priv = netdev_priv(ndev);
7299         u32 chan;
7300
7301         if (!ndev || !netif_running(ndev))
7302                 return 0;
7303
7304         mutex_lock(&priv->lock);
7305
7306         netif_device_detach(ndev);
7307
7308         stmmac_disable_all_queues(priv);
7309
7310         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7311                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
7312
7313         if (priv->eee_enabled) {
7314                 priv->tx_path_in_lpi_mode = false;
7315                 del_timer_sync(&priv->eee_ctrl_timer);
7316         }
7317
7318         /* Stop TX/RX DMA */
7319         stmmac_stop_all_dma(priv);
7320
7321         if (priv->plat->serdes_powerdown)
7322                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7323
7324         /* Enable Power down mode by programming the PMT regs */
7325         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7326                 stmmac_pmt(priv, priv->hw, priv->wolopts);
7327                 priv->irq_wake = 1;
7328         } else {
7329                 stmmac_mac_set(priv, priv->ioaddr, false);
7330                 pinctrl_pm_select_sleep_state(priv->device);
7331         }
7332
7333         mutex_unlock(&priv->lock);
7334
7335         rtnl_lock();
7336         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7337                 phylink_suspend(priv->phylink, true);
7338         } else {
7339                 if (device_may_wakeup(priv->device))
7340                         phylink_speed_down(priv->phylink, false);
7341                 phylink_suspend(priv->phylink, false);
7342         }
7343         rtnl_unlock();
7344
7345         if (priv->dma_cap.fpesel) {
7346                 /* Disable FPE */
7347                 stmmac_fpe_configure(priv, priv->ioaddr,
7348                                      priv->plat->tx_queues_to_use,
7349                                      priv->plat->rx_queues_to_use, false);
7350
7351                 stmmac_fpe_handshake(priv, false);
7352                 stmmac_fpe_stop_wq(priv);
7353         }
7354
7355         priv->speed = SPEED_UNKNOWN;
7356         return 0;
7357 }
7358 EXPORT_SYMBOL_GPL(stmmac_suspend);
7359
7360 /**
7361  * stmmac_reset_queues_param - reset queue parameters
7362  * @priv: device pointer
7363  */
7364 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7365 {
7366         u32 rx_cnt = priv->plat->rx_queues_to_use;
7367         u32 tx_cnt = priv->plat->tx_queues_to_use;
7368         u32 queue;
7369
7370         for (queue = 0; queue < rx_cnt; queue++) {
7371                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
7372
7373                 rx_q->cur_rx = 0;
7374                 rx_q->dirty_rx = 0;
7375         }
7376
7377         for (queue = 0; queue < tx_cnt; queue++) {
7378                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
7379
7380                 tx_q->cur_tx = 0;
7381                 tx_q->dirty_tx = 0;
7382                 tx_q->mss = 0;
7383
7384                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7385         }
7386 }
7387
7388 /**
7389  * stmmac_resume - resume callback
7390  * @dev: device pointer
7391  * Description: when resume this function is invoked to setup the DMA and CORE
7392  * in a usable state.
7393  */
7394 int stmmac_resume(struct device *dev)
7395 {
7396         struct net_device *ndev = dev_get_drvdata(dev);
7397         struct stmmac_priv *priv = netdev_priv(ndev);
7398         int ret;
7399
7400         if (!netif_running(ndev))
7401                 return 0;
7402
7403         /* Power Down bit, into the PM register, is cleared
7404          * automatically as soon as a magic packet or a Wake-up frame
7405          * is received. Anyway, it's better to manually clear
7406          * this bit because it can generate problems while resuming
7407          * from another devices (e.g. serial console).
7408          */
7409         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7410                 mutex_lock(&priv->lock);
7411                 stmmac_pmt(priv, priv->hw, 0);
7412                 mutex_unlock(&priv->lock);
7413                 priv->irq_wake = 0;
7414         } else {
7415                 pinctrl_pm_select_default_state(priv->device);
7416                 /* reset the phy so that it's ready */
7417                 if (priv->mii)
7418                         stmmac_mdio_reset(priv->mii);
7419         }
7420
7421         if (priv->plat->serdes_powerup) {
7422                 ret = priv->plat->serdes_powerup(ndev,
7423                                                  priv->plat->bsp_priv);
7424
7425                 if (ret < 0)
7426                         return ret;
7427         }
7428
7429         rtnl_lock();
7430         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7431                 phylink_resume(priv->phylink);
7432         } else {
7433                 phylink_resume(priv->phylink);
7434                 if (device_may_wakeup(priv->device))
7435                         phylink_speed_up(priv->phylink);
7436         }
7437         rtnl_unlock();
7438
7439         rtnl_lock();
7440         mutex_lock(&priv->lock);
7441
7442         stmmac_reset_queues_param(priv);
7443
7444         stmmac_free_tx_skbufs(priv);
7445         stmmac_clear_descriptors(priv);
7446
7447         stmmac_hw_setup(ndev, false);
7448         stmmac_init_coalesce(priv);
7449         stmmac_set_rx_mode(ndev);
7450
7451         stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7452
7453         stmmac_enable_all_queues(priv);
7454
7455         mutex_unlock(&priv->lock);
7456         rtnl_unlock();
7457
7458         netif_device_attach(ndev);
7459
7460         return 0;
7461 }
7462 EXPORT_SYMBOL_GPL(stmmac_resume);
7463
7464 #ifndef MODULE
7465 static int __init stmmac_cmdline_opt(char *str)
7466 {
7467         char *opt;
7468
7469         if (!str || !*str)
7470                 return -EINVAL;
7471         while ((opt = strsep(&str, ",")) != NULL) {
7472                 if (!strncmp(opt, "debug:", 6)) {
7473                         if (kstrtoint(opt + 6, 0, &debug))
7474                                 goto err;
7475                 } else if (!strncmp(opt, "phyaddr:", 8)) {
7476                         if (kstrtoint(opt + 8, 0, &phyaddr))
7477                                 goto err;
7478                 } else if (!strncmp(opt, "buf_sz:", 7)) {
7479                         if (kstrtoint(opt + 7, 0, &buf_sz))
7480                                 goto err;
7481                 } else if (!strncmp(opt, "tc:", 3)) {
7482                         if (kstrtoint(opt + 3, 0, &tc))
7483                                 goto err;
7484                 } else if (!strncmp(opt, "watchdog:", 9)) {
7485                         if (kstrtoint(opt + 9, 0, &watchdog))
7486                                 goto err;
7487                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7488                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
7489                                 goto err;
7490                 } else if (!strncmp(opt, "pause:", 6)) {
7491                         if (kstrtoint(opt + 6, 0, &pause))
7492                                 goto err;
7493                 } else if (!strncmp(opt, "eee_timer:", 10)) {
7494                         if (kstrtoint(opt + 10, 0, &eee_timer))
7495                                 goto err;
7496                 } else if (!strncmp(opt, "chain_mode:", 11)) {
7497                         if (kstrtoint(opt + 11, 0, &chain_mode))
7498                                 goto err;
7499                 }
7500         }
7501         return 0;
7502
7503 err:
7504         pr_err("%s: ERROR broken module parameter conversion", __func__);
7505         return -EINVAL;
7506 }
7507
7508 __setup("stmmaceth=", stmmac_cmdline_opt);
7509 #endif /* MODULE */
7510
7511 static int __init stmmac_init(void)
7512 {
7513 #ifdef CONFIG_DEBUG_FS
7514         /* Create debugfs main directory if it doesn't exist yet */
7515         if (!stmmac_fs_dir)
7516                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7517         register_netdevice_notifier(&stmmac_notifier);
7518 #endif
7519
7520         return 0;
7521 }
7522
7523 static void __exit stmmac_exit(void)
7524 {
7525 #ifdef CONFIG_DEBUG_FS
7526         unregister_netdevice_notifier(&stmmac_notifier);
7527         debugfs_remove_recursive(stmmac_fs_dir);
7528 #endif
7529 }
7530
7531 module_init(stmmac_init)
7532 module_exit(stmmac_exit)
7533
7534 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7535 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7536 MODULE_LICENSE("GPL");