drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <net/pkt_cls.h>
  40 #include "stmmac_ptp.h"
  41 #include "stmmac.h"
  42 #include <linux/reset.h>
  43 #include <linux/of_mdio.h>
  44 #include "dwmac1000.h"
  45 #include "dwxgmac2.h"
  46 #include "hwif.h"
  47
  48 #define STMMAC_ALIGN(x)         __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
  49 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  50
  51 /* Module parameters */
  52 #define TX_TIMEO        5000
  53 static int watchdog = TX_TIMEO;
  54 module_param(watchdog, int, 0644);
  55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  56
  57 static int debug = -1;
  58 module_param(debug, int, 0644);
  59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  60
  61 static int phyaddr = -1;
  62 module_param(phyaddr, int, 0444);
  63 MODULE_PARM_DESC(phyaddr, "Physical device address");
  64
  65 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  66 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  67
  68 static int flow_ctrl = FLOW_AUTO;
  69 module_param(flow_ctrl, int, 0644);
  70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  71
  72 static int pause = PAUSE_TIME;
  73 module_param(pause, int, 0644);
  74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  75
  76 #define TC_DEFAULT 64
  77 static int tc = TC_DEFAULT;
  78 module_param(tc, int, 0644);
  79 MODULE_PARM_DESC(tc, "DMA threshold control value");
  80
  81 #define DEFAULT_BUFSIZE 1536
  82 static int buf_sz = DEFAULT_BUFSIZE;
  83 module_param(buf_sz, int, 0644);
  84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  85
  86 #define STMMAC_RX_COPYBREAK     256
  87
  88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  89                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  90                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  91
  92 #define STMMAC_DEFAULT_LPI_TIMER        1000
  93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  94 module_param(eee_timer, int, 0644);
  95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  97
  98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
  99  * but allow user to force to use the chain instead of the ring
 100  */
 101 static unsigned int chain_mode;
 102 module_param(chain_mode, int, 0444);
 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 104
 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 106
 107 #ifdef CONFIG_DEBUG_FS
 108 static void stmmac_init_fs(struct net_device *dev);
 109 static void stmmac_exit_fs(struct net_device *dev);
 110 #endif
 111
 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 113
 114 /**
 115  * stmmac_verify_args - verify the driver parameters.
 116  * Description: it checks the driver parameters and set a default in case of
 117  * errors.
 118  */
 119 static void stmmac_verify_args(void)
 120 {
 121         if (unlikely(watchdog < 0))
 122                 watchdog = TX_TIMEO;
 123         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 124                 buf_sz = DEFAULT_BUFSIZE;
 125         if (unlikely(flow_ctrl > 1))
 126                 flow_ctrl = FLOW_AUTO;
 127         else if (likely(flow_ctrl < 0))
 128                 flow_ctrl = FLOW_OFF;
 129         if (unlikely((pause < 0) || (pause > 0xffff)))
 130                 pause = PAUSE_TIME;
 131         if (eee_timer < 0)
 132                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 133 }
 134
 135 /**
 136  * stmmac_disable_all_queues - Disable all queues
 137  * @priv: driver private structure
 138  */
 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 140 {
 141         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 142         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 143         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 144         u32 queue;
 145
 146         for (queue = 0; queue < maxq; queue++) {
 147                 struct stmmac_channel *ch = &priv->channel[queue];
 148
 149                 if (queue < rx_queues_cnt)
 150                         napi_disable(&ch->rx_napi);
 151                 if (queue < tx_queues_cnt)
 152                         napi_disable(&ch->tx_napi);
 153         }
 154 }
 155
 156 /**
 157  * stmmac_enable_all_queues - Enable all queues
 158  * @priv: driver private structure
 159  */
 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 161 {
 162         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 163         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 164         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 165         u32 queue;
 166
 167         for (queue = 0; queue < maxq; queue++) {
 168                 struct stmmac_channel *ch = &priv->channel[queue];
 169
 170                 if (queue < rx_queues_cnt)
 171                         napi_enable(&ch->rx_napi);
 172                 if (queue < tx_queues_cnt)
 173                         napi_enable(&ch->tx_napi);
 174         }
 175 }
 176
 177 /**
 178  * stmmac_stop_all_queues - Stop all queues
 179  * @priv: driver private structure
 180  */
 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 182 {
 183         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 184         u32 queue;
 185
 186         for (queue = 0; queue < tx_queues_cnt; queue++)
 187                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 188 }
 189
 190 /**
 191  * stmmac_start_all_queues - Start all queues
 192  * @priv: driver private structure
 193  */
 194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 195 {
 196         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 197         u32 queue;
 198
 199         for (queue = 0; queue < tx_queues_cnt; queue++)
 200                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 201 }
 202
 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 204 {
 205         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 206             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 207                 queue_work(priv->wq, &priv->service_task);
 208 }
 209
 210 static void stmmac_global_err(struct stmmac_priv *priv)
 211 {
 212         netif_carrier_off(priv->dev);
 213         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 214         stmmac_service_event_schedule(priv);
 215 }
 216
 217 /**
 218  * stmmac_clk_csr_set - dynamically set the MDC clock
 219  * @priv: driver private structure
 220  * Description: this is to dynamically set the MDC clock according to the csr
 221  * clock input.
 222  * Note:
 223  *      If a specific clk_csr value is passed from the platform
 224  *      this means that the CSR Clock Range selection cannot be
 225  *      changed at run-time and it is fixed (as reported in the driver
 226  *      documentation). Viceversa the driver will try to set the MDC
 227  *      clock dynamically according to the actual clock input.
 228  */
 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 230 {
 231         u32 clk_rate;
 232
 233         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 234
 235         /* Platform provided default clk_csr would be assumed valid
 236          * for all other cases except for the below mentioned ones.
 237          * For values higher than the IEEE 802.3 specified frequency
 238          * we can not estimate the proper divider as it is not known
 239          * the frequency of clk_csr_i. So we do not change the default
 240          * divider.
 241          */
 242         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 243                 if (clk_rate < CSR_F_35M)
 244                         priv->clk_csr = STMMAC_CSR_20_35M;
 245                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 246                         priv->clk_csr = STMMAC_CSR_35_60M;
 247                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 248                         priv->clk_csr = STMMAC_CSR_60_100M;
 249                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 250                         priv->clk_csr = STMMAC_CSR_100_150M;
 251                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 252                         priv->clk_csr = STMMAC_CSR_150_250M;
 253                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 254                         priv->clk_csr = STMMAC_CSR_250_300M;
 255         }
 256
 257         if (priv->plat->has_sun8i) {
 258                 if (clk_rate > 160000000)
 259                         priv->clk_csr = 0x03;
 260                 else if (clk_rate > 80000000)
 261                         priv->clk_csr = 0x02;
 262                 else if (clk_rate > 40000000)
 263                         priv->clk_csr = 0x01;
 264                 else
 265                         priv->clk_csr = 0;
 266         }
 267
 268         if (priv->plat->has_xgmac) {
 269                 if (clk_rate > 400000000)
 270                         priv->clk_csr = 0x5;
 271                 else if (clk_rate > 350000000)
 272                         priv->clk_csr = 0x4;
 273                 else if (clk_rate > 300000000)
 274                         priv->clk_csr = 0x3;
 275                 else if (clk_rate > 250000000)
 276                         priv->clk_csr = 0x2;
 277                 else if (clk_rate > 150000000)
 278                         priv->clk_csr = 0x1;
 279                 else
 280                         priv->clk_csr = 0x0;
 281         }
 282 }
 283
 284 static void print_pkt(unsigned char *buf, int len)
 285 {
 286         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 287         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 288 }
 289
 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 291 {
 292         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 293         u32 avail;
 294
 295         if (tx_q->dirty_tx > tx_q->cur_tx)
 296                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 297         else
 298                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 299
 300         return avail;
 301 }
 302
 303 /**
 304  * stmmac_rx_dirty - Get RX queue dirty
 305  * @priv: driver private structure
 306  * @queue: RX queue index
 307  */
 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 309 {
 310         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 311         u32 dirty;
 312
 313         if (rx_q->dirty_rx <= rx_q->cur_rx)
 314                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 315         else
 316                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 317
 318         return dirty;
 319 }
 320
 321 /**
 322  * stmmac_enable_eee_mode - check and enter in LPI mode
 323  * @priv: driver private structure
 324  * Description: this function is to verify and enter in LPI mode in case of
 325  * EEE.
 326  */
 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 328 {
 329         u32 tx_cnt = priv->plat->tx_queues_to_use;
 330         u32 queue;
 331
 332         /* check if all TX queues have the work finished */
 333         for (queue = 0; queue < tx_cnt; queue++) {
 334                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 335
 336                 if (tx_q->dirty_tx != tx_q->cur_tx)
 337                         return; /* still unfinished work */
 338         }
 339
 340         /* Check and enter in LPI mode */
 341         if (!priv->tx_path_in_lpi_mode)
 342                 stmmac_set_eee_mode(priv, priv->hw,
 343                                 priv->plat->en_tx_lpi_clockgating);
 344 }
 345
 346 /**
 347  * stmmac_disable_eee_mode - disable and exit from LPI mode
 348  * @priv: driver private structure
 349  * Description: this function is to exit and disable EEE in case of
 350  * LPI state is true. This is called by the xmit.
 351  */
 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 353 {
 354         stmmac_reset_eee_mode(priv, priv->hw);
 355         del_timer_sync(&priv->eee_ctrl_timer);
 356         priv->tx_path_in_lpi_mode = false;
 357 }
 358
 359 /**
 360  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 361  * @arg : data hook
 362  * Description:
 363  *  if there is no data transfer and if we are not in LPI state,
 364  *  then MAC Transmitter can be moved to LPI state.
 365  */
 366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 367 {
 368         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 369
 370         stmmac_enable_eee_mode(priv);
 371         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 372 }
 373
 374 /**
 375  * stmmac_eee_init - init EEE
 376  * @priv: driver private structure
 377  * Description:
 378  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 379  *  can also manage EEE, this function enable the LPI state and start related
 380  *  timer.
 381  */
 382 bool stmmac_eee_init(struct stmmac_priv *priv)
 383 {
 384         int tx_lpi_timer = priv->tx_lpi_timer;
 385
 386         /* Using PCS we cannot dial with the phy registers at this stage
 387          * so we do not support extra feature like EEE.
 388          */
 389         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 390             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 391             (priv->hw->pcs == STMMAC_PCS_RTBI))
 392                 return false;
 393
 394         /* Check if MAC core supports the EEE feature. */
 395         if (!priv->dma_cap.eee)
 396                 return false;
 397
 398         mutex_lock(&priv->lock);
 399
 400         /* Check if it needs to be deactivated */
 401         if (!priv->eee_active) {
 402                 if (priv->eee_enabled) {
 403                         netdev_dbg(priv->dev, "disable EEE\n");
 404                         del_timer_sync(&priv->eee_ctrl_timer);
 405                         stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 406                 }
 407                 mutex_unlock(&priv->lock);
 408                 return false;
 409         }
 410
 411         if (priv->eee_active && !priv->eee_enabled) {
 412                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 413                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 414                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 415                                      tx_lpi_timer);
 416         }
 417
 418         mutex_unlock(&priv->lock);
 419         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 420         return true;
 421 }
 422
 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 424  * @priv: driver private structure
 425  * @p : descriptor pointer
 426  * @skb : the socket buffer
 427  * Description :
 428  * This function will read timestamp from the descriptor & pass it to stack.
 429  * and also perform some sanity checks.
 430  */
 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 432                                    struct dma_desc *p, struct sk_buff *skb)
 433 {
 434         struct skb_shared_hwtstamps shhwtstamp;
 435         bool found = false;
 436         u64 ns = 0;
 437
 438         if (!priv->hwts_tx_en)
 439                 return;
 440
 441         /* exit if skb doesn't support hw tstamp */
 442         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 443                 return;
 444
 445         /* check tx tstamp status */
 446         if (stmmac_get_tx_timestamp_status(priv, p)) {
 447                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 448                 found = true;
 449         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 450                 found = true;
 451         }
 452
 453         if (found) {
 454                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 455                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 456
 457                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 458                 /* pass tstamp to stack */
 459                 skb_tstamp_tx(skb, &shhwtstamp);
 460         }
 461 }
 462
 463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 464  * @priv: driver private structure
 465  * @p : descriptor pointer
 466  * @np : next descriptor pointer
 467  * @skb : the socket buffer
 468  * Description :
 469  * This function will read received packet's timestamp from the descriptor
 470  * and pass it to stack. It also perform some sanity checks.
 471  */
 472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 473                                    struct dma_desc *np, struct sk_buff *skb)
 474 {
 475         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 476         struct dma_desc *desc = p;
 477         u64 ns = 0;
 478
 479         if (!priv->hwts_rx_en)
 480                 return;
 481         /* For GMAC4, the valid timestamp is from CTX next desc. */
 482         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 483                 desc = np;
 484
 485         /* Check if timestamp is available */
 486         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 487                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 488                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 489                 shhwtstamp = skb_hwtstamps(skb);
 490                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 491                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 492         } else  {
 493                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 494         }
 495 }
 496
 497 /**
 498  *  stmmac_hwtstamp_set - control hardware timestamping.
 499  *  @dev: device pointer.
 500  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 501  *  a proprietary structure used to pass information to the driver.
 502  *  Description:
 503  *  This function configures the MAC to enable/disable both outgoing(TX)
 504  *  and incoming(RX) packets time stamping based on user input.
 505  *  Return Value:
 506  *  0 on success and an appropriate -ve integer on failure.
 507  */
 508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 509 {
 510         struct stmmac_priv *priv = netdev_priv(dev);
 511         struct hwtstamp_config config;
 512         struct timespec64 now;
 513         u64 temp = 0;
 514         u32 ptp_v2 = 0;
 515         u32 tstamp_all = 0;
 516         u32 ptp_over_ipv4_udp = 0;
 517         u32 ptp_over_ipv6_udp = 0;
 518         u32 ptp_over_ethernet = 0;
 519         u32 snap_type_sel = 0;
 520         u32 ts_master_en = 0;
 521         u32 ts_event_en = 0;
 522         u32 sec_inc = 0;
 523         u32 value = 0;
 524         bool xmac;
 525
 526         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 527
 528         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 529                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 530                 priv->hwts_tx_en = 0;
 531                 priv->hwts_rx_en = 0;
 532
 533                 return -EOPNOTSUPP;
 534         }
 535
 536         if (copy_from_user(&config, ifr->ifr_data,
 537                            sizeof(config)))
 538                 return -EFAULT;
 539
 540         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 541                    __func__, config.flags, config.tx_type, config.rx_filter);
 542
 543         /* reserved for future extensions */
 544         if (config.flags)
 545                 return -EINVAL;
 546
 547         if (config.tx_type != HWTSTAMP_TX_OFF &&
 548             config.tx_type != HWTSTAMP_TX_ON)
 549                 return -ERANGE;
 550
 551         if (priv->adv_ts) {
 552                 switch (config.rx_filter) {
 553                 case HWTSTAMP_FILTER_NONE:
 554                         /* time stamp no incoming packet at all */
 555                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 556                         break;
 557
 558                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 559                         /* PTP v1, UDP, any kind of event packet */
 560                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 561                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 562                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 563                          * This leaves Delay_Req timestamps out.
 564                          * Enable all events *and* general purpose message
 565                          * timestamping
 566                          */
 567                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 568                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 569                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 570                         break;
 571
 572                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 573                         /* PTP v1, UDP, Sync packet */
 574                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 575                         /* take time stamp for SYNC messages only */
 576                         ts_event_en = PTP_TCR_TSEVNTENA;
 577
 578                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 579                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 580                         break;
 581
 582                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 583                         /* PTP v1, UDP, Delay_req packet */
 584                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 585                         /* take time stamp for Delay_Req messages only */
 586                         ts_master_en = PTP_TCR_TSMSTRENA;
 587                         ts_event_en = PTP_TCR_TSEVNTENA;
 588
 589                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 590                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 591                         break;
 592
 593                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 594                         /* PTP v2, UDP, any kind of event packet */
 595                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 596                         ptp_v2 = PTP_TCR_TSVER2ENA;
 597                         /* take time stamp for all event messages */
 598                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 599
 600                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 601                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 602                         break;
 603
 604                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 605                         /* PTP v2, UDP, Sync packet */
 606                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 607                         ptp_v2 = PTP_TCR_TSVER2ENA;
 608                         /* take time stamp for SYNC messages only */
 609                         ts_event_en = PTP_TCR_TSEVNTENA;
 610
 611                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 612                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 613                         break;
 614
 615                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 616                         /* PTP v2, UDP, Delay_req packet */
 617                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 618                         ptp_v2 = PTP_TCR_TSVER2ENA;
 619                         /* take time stamp for Delay_Req messages only */
 620                         ts_master_en = PTP_TCR_TSMSTRENA;
 621                         ts_event_en = PTP_TCR_TSEVNTENA;
 622
 623                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 624                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 625                         break;
 626
 627                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 628                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 629                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 630                         ptp_v2 = PTP_TCR_TSVER2ENA;
 631                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 632                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 633                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 634                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 635                         break;
 636
 637                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 638                         /* PTP v2/802.AS1, any layer, Sync packet */
 639                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 640                         ptp_v2 = PTP_TCR_TSVER2ENA;
 641                         /* take time stamp for SYNC messages only */
 642                         ts_event_en = PTP_TCR_TSEVNTENA;
 643
 644                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 645                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 646                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 647                         break;
 648
 649                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 650                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 651                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 652                         ptp_v2 = PTP_TCR_TSVER2ENA;
 653                         /* take time stamp for Delay_Req messages only */
 654                         ts_master_en = PTP_TCR_TSMSTRENA;
 655                         ts_event_en = PTP_TCR_TSEVNTENA;
 656
 657                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 658                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 659                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 660                         break;
 661
 662                 case HWTSTAMP_FILTER_NTP_ALL:
 663                 case HWTSTAMP_FILTER_ALL:
 664                         /* time stamp any incoming packet */
 665                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 666                         tstamp_all = PTP_TCR_TSENALL;
 667                         break;
 668
 669                 default:
 670                         return -ERANGE;
 671                 }
 672         } else {
 673                 switch (config.rx_filter) {
 674                 case HWTSTAMP_FILTER_NONE:
 675                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 676                         break;
 677                 default:
 678                         /* PTP v1, UDP, any kind of event packet */
 679                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 680                         break;
 681                 }
 682         }
 683         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 684         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 685
 686         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 687                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 688         else {
 689                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 690                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 691                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 692                          ts_master_en | snap_type_sel);
 693                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 694
 695                 /* program Sub Second Increment reg */
 696                 stmmac_config_sub_second_increment(priv,
 697                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 698                                 xmac, &sec_inc);
 699                 temp = div_u64(1000000000ULL, sec_inc);
 700
 701                 /* Store sub second increment and flags for later use */
 702                 priv->sub_second_inc = sec_inc;
 703                 priv->systime_flags = value;
 704
 705                 /* calculate default added value:
 706                  * formula is :
 707                  * addend = (2^32)/freq_div_ratio;
 708                  * where, freq_div_ratio = 1e9ns/sec_inc
 709                  */
 710                 temp = (u64)(temp << 32);
 711                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 712                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 713
 714                 /* initialize system time */
 715                 ktime_get_real_ts64(&now);
 716
 717                 /* lower 32 bits of tv_sec are safe until y2106 */
 718                 stmmac_init_systime(priv, priv->ptpaddr,
 719                                 (u32)now.tv_sec, now.tv_nsec);
 720         }
 721
 722         memcpy(&priv->tstamp_config, &config, sizeof(config));
 723
 724         return copy_to_user(ifr->ifr_data, &config,
 725                             sizeof(config)) ? -EFAULT : 0;
 726 }
 727
 728 /**
 729  *  stmmac_hwtstamp_get - read hardware timestamping.
 730  *  @dev: device pointer.
 731  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 732  *  a proprietary structure used to pass information to the driver.
 733  *  Description:
 734  *  This function obtain the current hardware timestamping settings
 735     as requested.
 736  */
 737 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 738 {
 739         struct stmmac_priv *priv = netdev_priv(dev);
 740         struct hwtstamp_config *config = &priv->tstamp_config;
 741
 742         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 743                 return -EOPNOTSUPP;
 744
 745         return copy_to_user(ifr->ifr_data, config,
 746                             sizeof(*config)) ? -EFAULT : 0;
 747 }
 748
 749 /**
 750  * stmmac_init_ptp - init PTP
 751  * @priv: driver private structure
 752  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 753  * This is done by looking at the HW cap. register.
 754  * This function also registers the ptp driver.
 755  */
 756 static int stmmac_init_ptp(struct stmmac_priv *priv)
 757 {
 758         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 759
 760         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 761                 return -EOPNOTSUPP;
 762
 763         priv->adv_ts = 0;
 764         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 765         if (xmac && priv->dma_cap.atime_stamp)
 766                 priv->adv_ts = 1;
 767         /* Dwmac 3.x core with extend_desc can support adv_ts */
 768         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 769                 priv->adv_ts = 1;
 770
 771         if (priv->dma_cap.time_stamp)
 772                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 773
 774         if (priv->adv_ts)
 775                 netdev_info(priv->dev,
 776                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 777
 778         priv->hwts_tx_en = 0;
 779         priv->hwts_rx_en = 0;
 780
 781         stmmac_ptp_register(priv);
 782
 783         return 0;
 784 }
 785
 786 static void stmmac_release_ptp(struct stmmac_priv *priv)
 787 {
 788         if (priv->plat->clk_ptp_ref)
 789                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 790         stmmac_ptp_unregister(priv);
 791 }
 792
 793 /**
 794  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 795  *  @priv: driver private structure
 796  *  Description: It is used for configuring the flow control in all queues
 797  */
 798 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 799 {
 800         u32 tx_cnt = priv->plat->tx_queues_to_use;
 801
 802         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 803                         priv->pause, tx_cnt);
 804 }
 805
 806 static void stmmac_validate(struct phylink_config *config,
 807                             unsigned long *supported,
 808                             struct phylink_link_state *state)
 809 {
 810         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 811         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 812         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 813         int tx_cnt = priv->plat->tx_queues_to_use;
 814         int max_speed = priv->plat->max_speed;
 815
 816         phylink_set(mac_supported, 10baseT_Half);
 817         phylink_set(mac_supported, 10baseT_Full);
 818         phylink_set(mac_supported, 100baseT_Half);
 819         phylink_set(mac_supported, 100baseT_Full);
 820         phylink_set(mac_supported, 1000baseT_Half);
 821         phylink_set(mac_supported, 1000baseT_Full);
 822         phylink_set(mac_supported, 1000baseKX_Full);
 823
 824         phylink_set(mac_supported, Autoneg);
 825         phylink_set(mac_supported, Pause);
 826         phylink_set(mac_supported, Asym_Pause);
 827         phylink_set_port_modes(mac_supported);
 828
 829         /* Cut down 1G if asked to */
 830         if ((max_speed > 0) && (max_speed < 1000)) {
 831                 phylink_set(mask, 1000baseT_Full);
 832                 phylink_set(mask, 1000baseX_Full);
 833         } else if (priv->plat->has_xgmac) {
 834                 if (!max_speed || (max_speed >= 2500)) {
 835                         phylink_set(mac_supported, 2500baseT_Full);
 836                         phylink_set(mac_supported, 2500baseX_Full);
 837                 }
 838                 if (!max_speed || (max_speed >= 5000)) {
 839                         phylink_set(mac_supported, 5000baseT_Full);
 840                 }
 841                 if (!max_speed || (max_speed >= 10000)) {
 842                         phylink_set(mac_supported, 10000baseSR_Full);
 843                         phylink_set(mac_supported, 10000baseLR_Full);
 844                         phylink_set(mac_supported, 10000baseER_Full);
 845                         phylink_set(mac_supported, 10000baseLRM_Full);
 846                         phylink_set(mac_supported, 10000baseT_Full);
 847                         phylink_set(mac_supported, 10000baseKX4_Full);
 848                         phylink_set(mac_supported, 10000baseKR_Full);
 849                 }
 850         }
 851
 852         /* Half-Duplex can only work with single queue */
 853         if (tx_cnt > 1) {
 854                 phylink_set(mask, 10baseT_Half);
 855                 phylink_set(mask, 100baseT_Half);
 856                 phylink_set(mask, 1000baseT_Half);
 857         }
 858
 859         bitmap_and(supported, supported, mac_supported,
 860                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 861         bitmap_andnot(supported, supported, mask,
 862                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 863         bitmap_and(state->advertising, state->advertising, mac_supported,
 864                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 865         bitmap_andnot(state->advertising, state->advertising, mask,
 866                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 867 }
 868
 869 static int stmmac_mac_link_state(struct phylink_config *config,
 870                                  struct phylink_link_state *state)
 871 {
 872         return -EOPNOTSUPP;
 873 }
 874
 875 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 876                               const struct phylink_link_state *state)
 877 {
 878         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 879         u32 ctrl;
 880
 881         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 882         ctrl &= ~priv->hw->link.speed_mask;
 883
 884         if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
 885                 switch (state->speed) {
 886                 case SPEED_10000:
 887                         ctrl |= priv->hw->link.xgmii.speed10000;
 888                         break;
 889                 case SPEED_5000:
 890                         ctrl |= priv->hw->link.xgmii.speed5000;
 891                         break;
 892                 case SPEED_2500:
 893                         ctrl |= priv->hw->link.xgmii.speed2500;
 894                         break;
 895                 default:
 896                         return;
 897                 }
 898         } else {
 899                 switch (state->speed) {
 900                 case SPEED_2500:
 901                         ctrl |= priv->hw->link.speed2500;
 902                         break;
 903                 case SPEED_1000:
 904                         ctrl |= priv->hw->link.speed1000;
 905                         break;
 906                 case SPEED_100:
 907                         ctrl |= priv->hw->link.speed100;
 908                         break;
 909                 case SPEED_10:
 910                         ctrl |= priv->hw->link.speed10;
 911                         break;
 912                 default:
 913                         return;
 914                 }
 915         }
 916
 917         priv->speed = state->speed;
 918
 919         if (priv->plat->fix_mac_speed)
 920                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
 921
 922         if (!state->duplex)
 923                 ctrl &= ~priv->hw->link.duplex;
 924         else
 925                 ctrl |= priv->hw->link.duplex;
 926
 927         /* Flow Control operation */
 928         if (state->pause)
 929                 stmmac_mac_flow_ctrl(priv, state->duplex);
 930
 931         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 932 }
 933
 934 static void stmmac_mac_an_restart(struct phylink_config *config)
 935 {
 936         /* Not Supported */
 937 }
 938
 939 static void stmmac_mac_link_down(struct phylink_config *config,
 940                                  unsigned int mode, phy_interface_t interface)
 941 {
 942         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 943
 944         stmmac_mac_set(priv, priv->ioaddr, false);
 945         priv->eee_active = false;
 946         stmmac_eee_init(priv);
 947         stmmac_set_eee_pls(priv, priv->hw, false);
 948 }
 949
 950 static void stmmac_mac_link_up(struct phylink_config *config,
 951                                unsigned int mode, phy_interface_t interface,
 952                                struct phy_device *phy)
 953 {
 954         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 955
 956         stmmac_mac_set(priv, priv->ioaddr, true);
 957         if (phy && priv->dma_cap.eee) {
 958                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
 959                 priv->eee_enabled = stmmac_eee_init(priv);
 960                 stmmac_set_eee_pls(priv, priv->hw, true);
 961         }
 962 }
 963
 964 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
 965         .validate = stmmac_validate,
 966         .mac_link_state = stmmac_mac_link_state,
 967         .mac_config = stmmac_mac_config,
 968         .mac_an_restart = stmmac_mac_an_restart,
 969         .mac_link_down = stmmac_mac_link_down,
 970         .mac_link_up = stmmac_mac_link_up,
 971 };
 972
 973 /**
 974  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 975  * @priv: driver private structure
 976  * Description: this is to verify if the HW supports the PCS.
 977  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 978  * configured for the TBI, RTBI, or SGMII PHY interface.
 979  */
 980 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 981 {
 982         int interface = priv->plat->interface;
 983
 984         if (priv->dma_cap.pcs) {
 985                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 986                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 987                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 988                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 989                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 990                         priv->hw->pcs = STMMAC_PCS_RGMII;
 991                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 992                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 993                         priv->hw->pcs = STMMAC_PCS_SGMII;
 994                 }
 995         }
 996 }
 997
 998 /**
 999  * stmmac_init_phy - PHY initialization
1000  * @dev: net device structure
1001  * Description: it initializes the driver's PHY state, and attaches the PHY
1002  * to the mac driver.
1003  *  Return value:
1004  *  0 on success
1005  */
1006 static int stmmac_init_phy(struct net_device *dev)
1007 {
1008         struct stmmac_priv *priv = netdev_priv(dev);
1009         struct device_node *node;
1010         int ret;
1011
1012         node = priv->plat->phylink_node;
1013
1014         if (node)
1015                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1016
1017         /* Some DT bindings do not set-up the PHY handle. Let's try to
1018          * manually parse it
1019          */
1020         if (!node || ret) {
1021                 int addr = priv->plat->phy_addr;
1022                 struct phy_device *phydev;
1023
1024                 phydev = mdiobus_get_phy(priv->mii, addr);
1025                 if (!phydev) {
1026                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1027                         return -ENODEV;
1028                 }
1029
1030                 ret = phylink_connect_phy(priv->phylink, phydev);
1031         }
1032
1033         return ret;
1034 }
1035
1036 static int stmmac_phy_setup(struct stmmac_priv *priv)
1037 {
1038         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1039         int mode = priv->plat->phy_interface;
1040         struct phylink *phylink;
1041
1042         priv->phylink_config.dev = &priv->dev->dev;
1043         priv->phylink_config.type = PHYLINK_NETDEV;
1044
1045         phylink = phylink_create(&priv->phylink_config, fwnode,
1046                                  mode, &stmmac_phylink_mac_ops);
1047         if (IS_ERR(phylink))
1048                 return PTR_ERR(phylink);
1049
1050         priv->phylink = phylink;
1051         return 0;
1052 }
1053
1054 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1055 {
1056         u32 rx_cnt = priv->plat->rx_queues_to_use;
1057         void *head_rx;
1058         u32 queue;
1059
1060         /* Display RX rings */
1061         for (queue = 0; queue < rx_cnt; queue++) {
1062                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1063
1064                 pr_info("\tRX Queue %u rings\n", queue);
1065
1066                 if (priv->extend_desc)
1067                         head_rx = (void *)rx_q->dma_erx;
1068                 else
1069                         head_rx = (void *)rx_q->dma_rx;
1070
1071                 /* Display RX ring */
1072                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1073         }
1074 }
1075
1076 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1077 {
1078         u32 tx_cnt = priv->plat->tx_queues_to_use;
1079         void *head_tx;
1080         u32 queue;
1081
1082         /* Display TX rings */
1083         for (queue = 0; queue < tx_cnt; queue++) {
1084                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1085
1086                 pr_info("\tTX Queue %d rings\n", queue);
1087
1088                 if (priv->extend_desc)
1089                         head_tx = (void *)tx_q->dma_etx;
1090                 else
1091                         head_tx = (void *)tx_q->dma_tx;
1092
1093                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1094         }
1095 }
1096
1097 static void stmmac_display_rings(struct stmmac_priv *priv)
1098 {
1099         /* Display RX ring */
1100         stmmac_display_rx_rings(priv);
1101
1102         /* Display TX ring */
1103         stmmac_display_tx_rings(priv);
1104 }
1105
1106 static int stmmac_set_bfsize(int mtu, int bufsize)
1107 {
1108         int ret = bufsize;
1109
1110         if (mtu >= BUF_SIZE_4KiB)
1111                 ret = BUF_SIZE_8KiB;
1112         else if (mtu >= BUF_SIZE_2KiB)
1113                 ret = BUF_SIZE_4KiB;
1114         else if (mtu > DEFAULT_BUFSIZE)
1115                 ret = BUF_SIZE_2KiB;
1116         else
1117                 ret = DEFAULT_BUFSIZE;
1118
1119         return ret;
1120 }
1121
1122 /**
1123  * stmmac_clear_rx_descriptors - clear RX descriptors
1124  * @priv: driver private structure
1125  * @queue: RX queue index
1126  * Description: this function is called to clear the RX descriptors
1127  * in case of both basic and extended descriptors are used.
1128  */
1129 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1130 {
1131         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1132         int i;
1133
1134         /* Clear the RX descriptors */
1135         for (i = 0; i < DMA_RX_SIZE; i++)
1136                 if (priv->extend_desc)
1137                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1138                                         priv->use_riwt, priv->mode,
1139                                         (i == DMA_RX_SIZE - 1),
1140                                         priv->dma_buf_sz);
1141                 else
1142                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1143                                         priv->use_riwt, priv->mode,
1144                                         (i == DMA_RX_SIZE - 1),
1145                                         priv->dma_buf_sz);
1146 }
1147
1148 /**
1149  * stmmac_clear_tx_descriptors - clear tx descriptors
1150  * @priv: driver private structure
1151  * @queue: TX queue index.
1152  * Description: this function is called to clear the TX descriptors
1153  * in case of both basic and extended descriptors are used.
1154  */
1155 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1156 {
1157         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1158         int i;
1159
1160         /* Clear the TX descriptors */
1161         for (i = 0; i < DMA_TX_SIZE; i++)
1162                 if (priv->extend_desc)
1163                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1164                                         priv->mode, (i == DMA_TX_SIZE - 1));
1165                 else
1166                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1167                                         priv->mode, (i == DMA_TX_SIZE - 1));
1168 }
1169
1170 /**
1171  * stmmac_clear_descriptors - clear descriptors
1172  * @priv: driver private structure
1173  * Description: this function is called to clear the TX and RX descriptors
1174  * in case of both basic and extended descriptors are used.
1175  */
1176 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1177 {
1178         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1179         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1180         u32 queue;
1181
1182         /* Clear the RX descriptors */
1183         for (queue = 0; queue < rx_queue_cnt; queue++)
1184                 stmmac_clear_rx_descriptors(priv, queue);
1185
1186         /* Clear the TX descriptors */
1187         for (queue = 0; queue < tx_queue_cnt; queue++)
1188                 stmmac_clear_tx_descriptors(priv, queue);
1189 }
1190
1191 /**
1192  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1193  * @priv: driver private structure
1194  * @p: descriptor pointer
1195  * @i: descriptor index
1196  * @flags: gfp flag
1197  * @queue: RX queue index
1198  * Description: this function is called to allocate a receive buffer, perform
1199  * the DMA mapping and init the descriptor.
1200  */
1201 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1202                                   int i, gfp_t flags, u32 queue)
1203 {
1204         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1205         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1206
1207         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1208         if (!buf->page)
1209                 return -ENOMEM;
1210
1211         if (priv->sph) {
1212                 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1213                 if (!buf->sec_page)
1214                         return -ENOMEM;
1215
1216                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1217                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
1218         } else {
1219                 buf->sec_page = NULL;
1220         }
1221
1222         buf->addr = page_pool_get_dma_addr(buf->page);
1223         stmmac_set_desc_addr(priv, p, buf->addr);
1224         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1225                 stmmac_init_desc3(priv, p);
1226
1227         return 0;
1228 }
1229
1230 /**
1231  * stmmac_free_rx_buffer - free RX dma buffers
1232  * @priv: private structure
1233  * @queue: RX queue index
1234  * @i: buffer index.
1235  */
1236 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1237 {
1238         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1239         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1240
1241         if (buf->page)
1242                 page_pool_put_page(rx_q->page_pool, buf->page, false);
1243         buf->page = NULL;
1244
1245         if (buf->sec_page)
1246                 page_pool_put_page(rx_q->page_pool, buf->sec_page, false);
1247         buf->sec_page = NULL;
1248 }
1249
1250 /**
1251  * stmmac_free_tx_buffer - free RX dma buffers
1252  * @priv: private structure
1253  * @queue: RX queue index
1254  * @i: buffer index.
1255  */
1256 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1257 {
1258         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1259
1260         if (tx_q->tx_skbuff_dma[i].buf) {
1261                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1262                         dma_unmap_page(priv->device,
1263                                        tx_q->tx_skbuff_dma[i].buf,
1264                                        tx_q->tx_skbuff_dma[i].len,
1265                                        DMA_TO_DEVICE);
1266                 else
1267                         dma_unmap_single(priv->device,
1268                                          tx_q->tx_skbuff_dma[i].buf,
1269                                          tx_q->tx_skbuff_dma[i].len,
1270                                          DMA_TO_DEVICE);
1271         }
1272
1273         if (tx_q->tx_skbuff[i]) {
1274                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1275                 tx_q->tx_skbuff[i] = NULL;
1276                 tx_q->tx_skbuff_dma[i].buf = 0;
1277                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1278         }
1279 }
1280
1281 /**
1282  * init_dma_rx_desc_rings - init the RX descriptor rings
1283  * @dev: net device structure
1284  * @flags: gfp flag.
1285  * Description: this function initializes the DMA RX descriptors
1286  * and allocates the socket buffers. It supports the chained and ring
1287  * modes.
1288  */
1289 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1290 {
1291         struct stmmac_priv *priv = netdev_priv(dev);
1292         u32 rx_count = priv->plat->rx_queues_to_use;
1293         int ret = -ENOMEM;
1294         int bfsize = 0;
1295         int queue;
1296         int i;
1297
1298         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1299         if (bfsize < 0)
1300                 bfsize = 0;
1301
1302         if (bfsize < BUF_SIZE_16KiB)
1303                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1304
1305         priv->dma_buf_sz = bfsize;
1306
1307         /* RX INITIALIZATION */
1308         netif_dbg(priv, probe, priv->dev,
1309                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1310
1311         for (queue = 0; queue < rx_count; queue++) {
1312                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1313
1314                 netif_dbg(priv, probe, priv->dev,
1315                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1316                           (u32)rx_q->dma_rx_phy);
1317
1318                 stmmac_clear_rx_descriptors(priv, queue);
1319
1320                 for (i = 0; i < DMA_RX_SIZE; i++) {
1321                         struct dma_desc *p;
1322
1323                         if (priv->extend_desc)
1324                                 p = &((rx_q->dma_erx + i)->basic);
1325                         else
1326                                 p = rx_q->dma_rx + i;
1327
1328                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1329                                                      queue);
1330                         if (ret)
1331                                 goto err_init_rx_buffers;
1332                 }
1333
1334                 rx_q->cur_rx = 0;
1335                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1336
1337                 /* Setup the chained descriptor addresses */
1338                 if (priv->mode == STMMAC_CHAIN_MODE) {
1339                         if (priv->extend_desc)
1340                                 stmmac_mode_init(priv, rx_q->dma_erx,
1341                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1342                         else
1343                                 stmmac_mode_init(priv, rx_q->dma_rx,
1344                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1345                 }
1346         }
1347
1348         buf_sz = bfsize;
1349
1350         return 0;
1351
1352 err_init_rx_buffers:
1353         while (queue >= 0) {
1354                 while (--i >= 0)
1355                         stmmac_free_rx_buffer(priv, queue, i);
1356
1357                 if (queue == 0)
1358                         break;
1359
1360                 i = DMA_RX_SIZE;
1361                 queue--;
1362         }
1363
1364         return ret;
1365 }
1366
1367 /**
1368  * init_dma_tx_desc_rings - init the TX descriptor rings
1369  * @dev: net device structure.
1370  * Description: this function initializes the DMA TX descriptors
1371  * and allocates the socket buffers. It supports the chained and ring
1372  * modes.
1373  */
1374 static int init_dma_tx_desc_rings(struct net_device *dev)
1375 {
1376         struct stmmac_priv *priv = netdev_priv(dev);
1377         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1378         u32 queue;
1379         int i;
1380
1381         for (queue = 0; queue < tx_queue_cnt; queue++) {
1382                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1383
1384                 netif_dbg(priv, probe, priv->dev,
1385                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1386                          (u32)tx_q->dma_tx_phy);
1387
1388                 /* Setup the chained descriptor addresses */
1389                 if (priv->mode == STMMAC_CHAIN_MODE) {
1390                         if (priv->extend_desc)
1391                                 stmmac_mode_init(priv, tx_q->dma_etx,
1392                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1393                         else
1394                                 stmmac_mode_init(priv, tx_q->dma_tx,
1395                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1396                 }
1397
1398                 for (i = 0; i < DMA_TX_SIZE; i++) {
1399                         struct dma_desc *p;
1400                         if (priv->extend_desc)
1401                                 p = &((tx_q->dma_etx + i)->basic);
1402                         else
1403                                 p = tx_q->dma_tx + i;
1404
1405                         stmmac_clear_desc(priv, p);
1406
1407                         tx_q->tx_skbuff_dma[i].buf = 0;
1408                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1409                         tx_q->tx_skbuff_dma[i].len = 0;
1410                         tx_q->tx_skbuff_dma[i].last_segment = false;
1411                         tx_q->tx_skbuff[i] = NULL;
1412                 }
1413
1414                 tx_q->dirty_tx = 0;
1415                 tx_q->cur_tx = 0;
1416                 tx_q->mss = 0;
1417
1418                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1419         }
1420
1421         return 0;
1422 }
1423
1424 /**
1425  * init_dma_desc_rings - init the RX/TX descriptor rings
1426  * @dev: net device structure
1427  * @flags: gfp flag.
1428  * Description: this function initializes the DMA RX/TX descriptors
1429  * and allocates the socket buffers. It supports the chained and ring
1430  * modes.
1431  */
1432 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1433 {
1434         struct stmmac_priv *priv = netdev_priv(dev);
1435         int ret;
1436
1437         ret = init_dma_rx_desc_rings(dev, flags);
1438         if (ret)
1439                 return ret;
1440
1441         ret = init_dma_tx_desc_rings(dev);
1442
1443         stmmac_clear_descriptors(priv);
1444
1445         if (netif_msg_hw(priv))
1446                 stmmac_display_rings(priv);
1447
1448         return ret;
1449 }
1450
1451 /**
1452  * dma_free_rx_skbufs - free RX dma buffers
1453  * @priv: private structure
1454  * @queue: RX queue index
1455  */
1456 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1457 {
1458         int i;
1459
1460         for (i = 0; i < DMA_RX_SIZE; i++)
1461                 stmmac_free_rx_buffer(priv, queue, i);
1462 }
1463
1464 /**
1465  * dma_free_tx_skbufs - free TX dma buffers
1466  * @priv: private structure
1467  * @queue: TX queue index
1468  */
1469 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1470 {
1471         int i;
1472
1473         for (i = 0; i < DMA_TX_SIZE; i++)
1474                 stmmac_free_tx_buffer(priv, queue, i);
1475 }
1476
1477 /**
1478  * free_dma_rx_desc_resources - free RX dma desc resources
1479  * @priv: private structure
1480  */
1481 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1482 {
1483         u32 rx_count = priv->plat->rx_queues_to_use;
1484         u32 queue;
1485
1486         /* Free RX queue resources */
1487         for (queue = 0; queue < rx_count; queue++) {
1488                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1489
1490                 /* Release the DMA RX socket buffers */
1491                 dma_free_rx_skbufs(priv, queue);
1492
1493                 /* Free DMA regions of consistent memory previously allocated */
1494                 if (!priv->extend_desc)
1495                         dma_free_coherent(priv->device,
1496                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1497                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1498                 else
1499                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1500                                           sizeof(struct dma_extended_desc),
1501                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1502
1503                 kfree(rx_q->buf_pool);
1504                 if (rx_q->page_pool) {
1505                         page_pool_request_shutdown(rx_q->page_pool);
1506                         page_pool_destroy(rx_q->page_pool);
1507                 }
1508         }
1509 }
1510
1511 /**
1512  * free_dma_tx_desc_resources - free TX dma desc resources
1513  * @priv: private structure
1514  */
1515 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1516 {
1517         u32 tx_count = priv->plat->tx_queues_to_use;
1518         u32 queue;
1519
1520         /* Free TX queue resources */
1521         for (queue = 0; queue < tx_count; queue++) {
1522                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1523
1524                 /* Release the DMA TX socket buffers */
1525                 dma_free_tx_skbufs(priv, queue);
1526
1527                 /* Free DMA regions of consistent memory previously allocated */
1528                 if (!priv->extend_desc)
1529                         dma_free_coherent(priv->device,
1530                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1531                                           tx_q->dma_tx, tx_q->dma_tx_phy);
1532                 else
1533                         dma_free_coherent(priv->device, DMA_TX_SIZE *
1534                                           sizeof(struct dma_extended_desc),
1535                                           tx_q->dma_etx, tx_q->dma_tx_phy);
1536
1537                 kfree(tx_q->tx_skbuff_dma);
1538                 kfree(tx_q->tx_skbuff);
1539         }
1540 }
1541
1542 /**
1543  * alloc_dma_rx_desc_resources - alloc RX resources.
1544  * @priv: private structure
1545  * Description: according to which descriptor can be used (extend or basic)
1546  * this function allocates the resources for TX and RX paths. In case of
1547  * reception, for example, it pre-allocated the RX socket buffer in order to
1548  * allow zero-copy mechanism.
1549  */
1550 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1551 {
1552         u32 rx_count = priv->plat->rx_queues_to_use;
1553         int ret = -ENOMEM;
1554         u32 queue;
1555
1556         /* RX queues buffers and DMA */
1557         for (queue = 0; queue < rx_count; queue++) {
1558                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1559                 struct page_pool_params pp_params = { 0 };
1560
1561                 rx_q->queue_index = queue;
1562                 rx_q->priv_data = priv;
1563
1564                 pp_params.flags = PP_FLAG_DMA_MAP;
1565                 pp_params.pool_size = DMA_RX_SIZE;
1566                 pp_params.order = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1567                 pp_params.nid = dev_to_node(priv->device);
1568                 pp_params.dev = priv->device;
1569                 pp_params.dma_dir = DMA_FROM_DEVICE;
1570
1571                 rx_q->page_pool = page_pool_create(&pp_params);
1572                 if (IS_ERR(rx_q->page_pool)) {
1573                         ret = PTR_ERR(rx_q->page_pool);
1574                         rx_q->page_pool = NULL;
1575                         goto err_dma;
1576                 }
1577
1578                 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool),
1579                                          GFP_KERNEL);
1580                 if (!rx_q->buf_pool)
1581                         goto err_dma;
1582
1583                 if (priv->extend_desc) {
1584                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1585                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1586                                                            &rx_q->dma_rx_phy,
1587                                                            GFP_KERNEL);
1588                         if (!rx_q->dma_erx)
1589                                 goto err_dma;
1590
1591                 } else {
1592                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1593                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1594                                                           &rx_q->dma_rx_phy,
1595                                                           GFP_KERNEL);
1596                         if (!rx_q->dma_rx)
1597                                 goto err_dma;
1598                 }
1599         }
1600
1601         return 0;
1602
1603 err_dma:
1604         free_dma_rx_desc_resources(priv);
1605
1606         return ret;
1607 }
1608
1609 /**
1610  * alloc_dma_tx_desc_resources - alloc TX resources.
1611  * @priv: private structure
1612  * Description: according to which descriptor can be used (extend or basic)
1613  * this function allocates the resources for TX and RX paths. In case of
1614  * reception, for example, it pre-allocated the RX socket buffer in order to
1615  * allow zero-copy mechanism.
1616  */
1617 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1618 {
1619         u32 tx_count = priv->plat->tx_queues_to_use;
1620         int ret = -ENOMEM;
1621         u32 queue;
1622
1623         /* TX queues buffers and DMA */
1624         for (queue = 0; queue < tx_count; queue++) {
1625                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1626
1627                 tx_q->queue_index = queue;
1628                 tx_q->priv_data = priv;
1629
1630                 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE,
1631                                               sizeof(*tx_q->tx_skbuff_dma),
1632                                               GFP_KERNEL);
1633                 if (!tx_q->tx_skbuff_dma)
1634                         goto err_dma;
1635
1636                 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE,
1637                                           sizeof(struct sk_buff *),
1638                                           GFP_KERNEL);
1639                 if (!tx_q->tx_skbuff)
1640                         goto err_dma;
1641
1642                 if (priv->extend_desc) {
1643                         tx_q->dma_etx = dma_alloc_coherent(priv->device,
1644                                                            DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1645                                                            &tx_q->dma_tx_phy,
1646                                                            GFP_KERNEL);
1647                         if (!tx_q->dma_etx)
1648                                 goto err_dma;
1649                 } else {
1650                         tx_q->dma_tx = dma_alloc_coherent(priv->device,
1651                                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1652                                                           &tx_q->dma_tx_phy,
1653                                                           GFP_KERNEL);
1654                         if (!tx_q->dma_tx)
1655                                 goto err_dma;
1656                 }
1657         }
1658
1659         return 0;
1660
1661 err_dma:
1662         free_dma_tx_desc_resources(priv);
1663
1664         return ret;
1665 }
1666
1667 /**
1668  * alloc_dma_desc_resources - alloc TX/RX resources.
1669  * @priv: private structure
1670  * Description: according to which descriptor can be used (extend or basic)
1671  * this function allocates the resources for TX and RX paths. In case of
1672  * reception, for example, it pre-allocated the RX socket buffer in order to
1673  * allow zero-copy mechanism.
1674  */
1675 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1676 {
1677         /* RX Allocation */
1678         int ret = alloc_dma_rx_desc_resources(priv);
1679
1680         if (ret)
1681                 return ret;
1682
1683         ret = alloc_dma_tx_desc_resources(priv);
1684
1685         return ret;
1686 }
1687
1688 /**
1689  * free_dma_desc_resources - free dma desc resources
1690  * @priv: private structure
1691  */
1692 static void free_dma_desc_resources(struct stmmac_priv *priv)
1693 {
1694         /* Release the DMA RX socket buffers */
1695         free_dma_rx_desc_resources(priv);
1696
1697         /* Release the DMA TX socket buffers */
1698         free_dma_tx_desc_resources(priv);
1699 }
1700
1701 /**
1702  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1703  *  @priv: driver private structure
1704  *  Description: It is used for enabling the rx queues in the MAC
1705  */
1706 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1707 {
1708         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1709         int queue;
1710         u8 mode;
1711
1712         for (queue = 0; queue < rx_queues_count; queue++) {
1713                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1714                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1715         }
1716 }
1717
1718 /**
1719  * stmmac_start_rx_dma - start RX DMA channel
1720  * @priv: driver private structure
1721  * @chan: RX channel index
1722  * Description:
1723  * This starts a RX DMA channel
1724  */
1725 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1726 {
1727         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1728         stmmac_start_rx(priv, priv->ioaddr, chan);
1729 }
1730
1731 /**
1732  * stmmac_start_tx_dma - start TX DMA channel
1733  * @priv: driver private structure
1734  * @chan: TX channel index
1735  * Description:
1736  * This starts a TX DMA channel
1737  */
1738 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1739 {
1740         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1741         stmmac_start_tx(priv, priv->ioaddr, chan);
1742 }
1743
1744 /**
1745  * stmmac_stop_rx_dma - stop RX DMA channel
1746  * @priv: driver private structure
1747  * @chan: RX channel index
1748  * Description:
1749  * This stops a RX DMA channel
1750  */
1751 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1752 {
1753         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1754         stmmac_stop_rx(priv, priv->ioaddr, chan);
1755 }
1756
1757 /**
1758  * stmmac_stop_tx_dma - stop TX DMA channel
1759  * @priv: driver private structure
1760  * @chan: TX channel index
1761  * Description:
1762  * This stops a TX DMA channel
1763  */
1764 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1765 {
1766         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1767         stmmac_stop_tx(priv, priv->ioaddr, chan);
1768 }
1769
1770 /**
1771  * stmmac_start_all_dma - start all RX and TX DMA channels
1772  * @priv: driver private structure
1773  * Description:
1774  * This starts all the RX and TX DMA channels
1775  */
1776 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1777 {
1778         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1779         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1780         u32 chan = 0;
1781
1782         for (chan = 0; chan < rx_channels_count; chan++)
1783                 stmmac_start_rx_dma(priv, chan);
1784
1785         for (chan = 0; chan < tx_channels_count; chan++)
1786                 stmmac_start_tx_dma(priv, chan);
1787 }
1788
1789 /**
1790  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1791  * @priv: driver private structure
1792  * Description:
1793  * This stops the RX and TX DMA channels
1794  */
1795 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1796 {
1797         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1798         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1799         u32 chan = 0;
1800
1801         for (chan = 0; chan < rx_channels_count; chan++)
1802                 stmmac_stop_rx_dma(priv, chan);
1803
1804         for (chan = 0; chan < tx_channels_count; chan++)
1805                 stmmac_stop_tx_dma(priv, chan);
1806 }
1807
1808 /**
1809  *  stmmac_dma_operation_mode - HW DMA operation mode
1810  *  @priv: driver private structure
1811  *  Description: it is used for configuring the DMA operation mode register in
1812  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1813  */
1814 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1815 {
1816         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1817         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1818         int rxfifosz = priv->plat->rx_fifo_size;
1819         int txfifosz = priv->plat->tx_fifo_size;
1820         u32 txmode = 0;
1821         u32 rxmode = 0;
1822         u32 chan = 0;
1823         u8 qmode = 0;
1824
1825         if (rxfifosz == 0)
1826                 rxfifosz = priv->dma_cap.rx_fifo_size;
1827         if (txfifosz == 0)
1828                 txfifosz = priv->dma_cap.tx_fifo_size;
1829
1830         /* Adjust for real per queue fifo size */
1831         rxfifosz /= rx_channels_count;
1832         txfifosz /= tx_channels_count;
1833
1834         if (priv->plat->force_thresh_dma_mode) {
1835                 txmode = tc;
1836                 rxmode = tc;
1837         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1838                 /*
1839                  * In case of GMAC, SF mode can be enabled
1840                  * to perform the TX COE in HW. This depends on:
1841                  * 1) TX COE if actually supported
1842                  * 2) There is no bugged Jumbo frame support
1843                  *    that needs to not insert csum in the TDES.
1844                  */
1845                 txmode = SF_DMA_MODE;
1846                 rxmode = SF_DMA_MODE;
1847                 priv->xstats.threshold = SF_DMA_MODE;
1848         } else {
1849                 txmode = tc;
1850                 rxmode = SF_DMA_MODE;
1851         }
1852
1853         /* configure all channels */
1854         for (chan = 0; chan < rx_channels_count; chan++) {
1855                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1856
1857                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1858                                 rxfifosz, qmode);
1859                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1860                                 chan);
1861         }
1862
1863         for (chan = 0; chan < tx_channels_count; chan++) {
1864                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1865
1866                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1867                                 txfifosz, qmode);
1868         }
1869 }
1870
1871 /**
1872  * stmmac_tx_clean - to manage the transmission completion
1873  * @priv: driver private structure
1874  * @queue: TX queue index
1875  * Description: it reclaims the transmit resources after transmission completes.
1876  */
1877 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1878 {
1879         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1880         unsigned int bytes_compl = 0, pkts_compl = 0;
1881         unsigned int entry, count = 0;
1882
1883         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1884
1885         priv->xstats.tx_clean++;
1886
1887         entry = tx_q->dirty_tx;
1888         while ((entry != tx_q->cur_tx) && (count < budget)) {
1889                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1890                 struct dma_desc *p;
1891                 int status;
1892
1893                 if (priv->extend_desc)
1894                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1895                 else
1896                         p = tx_q->dma_tx + entry;
1897
1898                 status = stmmac_tx_status(priv, &priv->dev->stats,
1899                                 &priv->xstats, p, priv->ioaddr);
1900                 /* Check if the descriptor is owned by the DMA */
1901                 if (unlikely(status & tx_dma_own))
1902                         break;
1903
1904                 count++;
1905
1906                 /* Make sure descriptor fields are read after reading
1907                  * the own bit.
1908                  */
1909                 dma_rmb();
1910
1911                 /* Just consider the last segment and ...*/
1912                 if (likely(!(status & tx_not_ls))) {
1913                         /* ... verify the status error condition */
1914                         if (unlikely(status & tx_err)) {
1915                                 priv->dev->stats.tx_errors++;
1916                         } else {
1917                                 priv->dev->stats.tx_packets++;
1918                                 priv->xstats.tx_pkt_n++;
1919                         }
1920                         stmmac_get_tx_hwtstamp(priv, p, skb);
1921                 }
1922
1923                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1924                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
1925                                 dma_unmap_page(priv->device,
1926                                                tx_q->tx_skbuff_dma[entry].buf,
1927                                                tx_q->tx_skbuff_dma[entry].len,
1928                                                DMA_TO_DEVICE);
1929                         else
1930                                 dma_unmap_single(priv->device,
1931                                                  tx_q->tx_skbuff_dma[entry].buf,
1932                                                  tx_q->tx_skbuff_dma[entry].len,
1933                                                  DMA_TO_DEVICE);
1934                         tx_q->tx_skbuff_dma[entry].buf = 0;
1935                         tx_q->tx_skbuff_dma[entry].len = 0;
1936                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
1937                 }
1938
1939                 stmmac_clean_desc3(priv, tx_q, p);
1940
1941                 tx_q->tx_skbuff_dma[entry].last_segment = false;
1942                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1943
1944                 if (likely(skb != NULL)) {
1945                         pkts_compl++;
1946                         bytes_compl += skb->len;
1947                         dev_consume_skb_any(skb);
1948                         tx_q->tx_skbuff[entry] = NULL;
1949                 }
1950
1951                 stmmac_release_tx_desc(priv, p, priv->mode);
1952
1953                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1954         }
1955         tx_q->dirty_tx = entry;
1956
1957         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1958                                   pkts_compl, bytes_compl);
1959
1960         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1961                                                                 queue))) &&
1962             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1963
1964                 netif_dbg(priv, tx_done, priv->dev,
1965                           "%s: restart transmit\n", __func__);
1966                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1967         }
1968
1969         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1970                 stmmac_enable_eee_mode(priv);
1971                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1972         }
1973
1974         /* We still have pending packets, let's call for a new scheduling */
1975         if (tx_q->dirty_tx != tx_q->cur_tx)
1976                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1977
1978         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1979
1980         return count;
1981 }
1982
1983 /**
1984  * stmmac_tx_err - to manage the tx error
1985  * @priv: driver private structure
1986  * @chan: channel index
1987  * Description: it cleans the descriptors and restarts the transmission
1988  * in case of transmission errors.
1989  */
1990 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1991 {
1992         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1993         int i;
1994
1995         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1996
1997         stmmac_stop_tx_dma(priv, chan);
1998         dma_free_tx_skbufs(priv, chan);
1999         for (i = 0; i < DMA_TX_SIZE; i++)
2000                 if (priv->extend_desc)
2001                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
2002                                         priv->mode, (i == DMA_TX_SIZE - 1));
2003                 else
2004                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
2005                                         priv->mode, (i == DMA_TX_SIZE - 1));
2006         tx_q->dirty_tx = 0;
2007         tx_q->cur_tx = 0;
2008         tx_q->mss = 0;
2009         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2010         stmmac_start_tx_dma(priv, chan);
2011
2012         priv->dev->stats.tx_errors++;
2013         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2014 }
2015
2016 /**
2017  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2018  *  @priv: driver private structure
2019  *  @txmode: TX operating mode
2020  *  @rxmode: RX operating mode
2021  *  @chan: channel index
2022  *  Description: it is used for configuring of the DMA operation mode in
2023  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2024  *  mode.
2025  */
2026 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2027                                           u32 rxmode, u32 chan)
2028 {
2029         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2030         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2031         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2032         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2033         int rxfifosz = priv->plat->rx_fifo_size;
2034         int txfifosz = priv->plat->tx_fifo_size;
2035
2036         if (rxfifosz == 0)
2037                 rxfifosz = priv->dma_cap.rx_fifo_size;
2038         if (txfifosz == 0)
2039                 txfifosz = priv->dma_cap.tx_fifo_size;
2040
2041         /* Adjust for real per queue fifo size */
2042         rxfifosz /= rx_channels_count;
2043         txfifosz /= tx_channels_count;
2044
2045         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2046         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2047 }
2048
2049 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2050 {
2051         int ret;
2052
2053         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2054                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2055         if (ret && (ret != -EINVAL)) {
2056                 stmmac_global_err(priv);
2057                 return true;
2058         }
2059
2060         return false;
2061 }
2062
2063 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2064 {
2065         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2066                                                  &priv->xstats, chan);
2067         struct stmmac_channel *ch = &priv->channel[chan];
2068
2069         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2070                 if (napi_schedule_prep(&ch->rx_napi)) {
2071                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2072                         __napi_schedule_irqoff(&ch->rx_napi);
2073                         status |= handle_tx;
2074                 }
2075         }
2076
2077         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
2078                 napi_schedule_irqoff(&ch->tx_napi);
2079
2080         return status;
2081 }
2082
2083 /**
2084  * stmmac_dma_interrupt - DMA ISR
2085  * @priv: driver private structure
2086  * Description: this is the DMA ISR. It is called by the main ISR.
2087  * It calls the dwmac dma routine and schedule poll method in case of some
2088  * work can be done.
2089  */
2090 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2091 {
2092         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2093         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2094         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2095                                 tx_channel_count : rx_channel_count;
2096         u32 chan;
2097         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2098
2099         /* Make sure we never check beyond our status buffer. */
2100         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2101                 channels_to_check = ARRAY_SIZE(status);
2102
2103         for (chan = 0; chan < channels_to_check; chan++)
2104                 status[chan] = stmmac_napi_check(priv, chan);
2105
2106         for (chan = 0; chan < tx_channel_count; chan++) {
2107                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2108                         /* Try to bump up the dma threshold on this failure */
2109                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2110                             (tc <= 256)) {
2111                                 tc += 64;
2112                                 if (priv->plat->force_thresh_dma_mode)
2113                                         stmmac_set_dma_operation_mode(priv,
2114                                                                       tc,
2115                                                                       tc,
2116                                                                       chan);
2117                                 else
2118                                         stmmac_set_dma_operation_mode(priv,
2119                                                                     tc,
2120                                                                     SF_DMA_MODE,
2121                                                                     chan);
2122                                 priv->xstats.threshold = tc;
2123                         }
2124                 } else if (unlikely(status[chan] == tx_hard_error)) {
2125                         stmmac_tx_err(priv, chan);
2126                 }
2127         }
2128 }
2129
2130 /**
2131  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2132  * @priv: driver private structure
2133  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2134  */
2135 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2136 {
2137         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2138                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2139
2140         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2141
2142         if (priv->dma_cap.rmon) {
2143                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2144                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2145         } else
2146                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2147 }
2148
2149 /**
2150  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2151  * @priv: driver private structure
2152  * Description:
2153  *  new GMAC chip generations have a new register to indicate the
2154  *  presence of the optional feature/functions.
2155  *  This can be also used to override the value passed through the
2156  *  platform and necessary for old MAC10/100 and GMAC chips.
2157  */
2158 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2159 {
2160         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2161 }
2162
2163 /**
2164  * stmmac_check_ether_addr - check if the MAC addr is valid
2165  * @priv: driver private structure
2166  * Description:
2167  * it is to verify if the MAC address is valid, in case of failures it
2168  * generates a random MAC address
2169  */
2170 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2171 {
2172         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2173                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2174                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2175                         eth_hw_addr_random(priv->dev);
2176                 dev_info(priv->device, "device MAC address %pM\n",
2177                          priv->dev->dev_addr);
2178         }
2179 }
2180
2181 /**
2182  * stmmac_init_dma_engine - DMA init.
2183  * @priv: driver private structure
2184  * Description:
2185  * It inits the DMA invoking the specific MAC/GMAC callback.
2186  * Some DMA parameters can be passed from the platform;
2187  * in case of these are not passed a default is kept for the MAC or GMAC.
2188  */
2189 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2190 {
2191         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2192         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2193         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2194         struct stmmac_rx_queue *rx_q;
2195         struct stmmac_tx_queue *tx_q;
2196         u32 chan = 0;
2197         int atds = 0;
2198         int ret = 0;
2199
2200         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2201                 dev_err(priv->device, "Invalid DMA configuration\n");
2202                 return -EINVAL;
2203         }
2204
2205         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2206                 atds = 1;
2207
2208         ret = stmmac_reset(priv, priv->ioaddr);
2209         if (ret) {
2210                 dev_err(priv->device, "Failed to reset the dma\n");
2211                 return ret;
2212         }
2213
2214         /* DMA Configuration */
2215         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2216
2217         if (priv->plat->axi)
2218                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2219
2220         /* DMA CSR Channel configuration */
2221         for (chan = 0; chan < dma_csr_ch; chan++)
2222                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2223
2224         /* DMA RX Channel Configuration */
2225         for (chan = 0; chan < rx_channels_count; chan++) {
2226                 rx_q = &priv->rx_queue[chan];
2227
2228                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2229                                     rx_q->dma_rx_phy, chan);
2230
2231                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2232                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2233                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2234                                        rx_q->rx_tail_addr, chan);
2235         }
2236
2237         /* DMA TX Channel Configuration */
2238         for (chan = 0; chan < tx_channels_count; chan++) {
2239                 tx_q = &priv->tx_queue[chan];
2240
2241                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2242                                     tx_q->dma_tx_phy, chan);
2243
2244                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2245                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2246                                        tx_q->tx_tail_addr, chan);
2247         }
2248
2249         return ret;
2250 }
2251
2252 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2253 {
2254         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2255
2256         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2257 }
2258
2259 /**
2260  * stmmac_tx_timer - mitigation sw timer for tx.
2261  * @data: data pointer
2262  * Description:
2263  * This is the timer handler to directly invoke the stmmac_tx_clean.
2264  */
2265 static void stmmac_tx_timer(struct timer_list *t)
2266 {
2267         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2268         struct stmmac_priv *priv = tx_q->priv_data;
2269         struct stmmac_channel *ch;
2270
2271         ch = &priv->channel[tx_q->queue_index];
2272
2273         /*
2274          * If NAPI is already running we can miss some events. Let's rearm
2275          * the timer and try again.
2276          */
2277         if (likely(napi_schedule_prep(&ch->tx_napi)))
2278                 __napi_schedule(&ch->tx_napi);
2279         else
2280                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2281 }
2282
2283 /**
2284  * stmmac_init_coalesce - init mitigation options.
2285  * @priv: driver private structure
2286  * Description:
2287  * This inits the coalesce parameters: i.e. timer rate,
2288  * timer handler and default threshold used for enabling the
2289  * interrupt on completion bit.
2290  */
2291 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2292 {
2293         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2294         u32 chan;
2295
2296         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2297         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2298         priv->rx_coal_frames = STMMAC_RX_FRAMES;
2299
2300         for (chan = 0; chan < tx_channel_count; chan++) {
2301                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2302
2303                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2304         }
2305 }
2306
2307 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2308 {
2309         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2310         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2311         u32 chan;
2312
2313         /* set TX ring length */
2314         for (chan = 0; chan < tx_channels_count; chan++)
2315                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2316                                 (DMA_TX_SIZE - 1), chan);
2317
2318         /* set RX ring length */
2319         for (chan = 0; chan < rx_channels_count; chan++)
2320                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2321                                 (DMA_RX_SIZE - 1), chan);
2322 }
2323
2324 /**
2325  *  stmmac_set_tx_queue_weight - Set TX queue weight
2326  *  @priv: driver private structure
2327  *  Description: It is used for setting TX queues weight
2328  */
2329 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2330 {
2331         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2332         u32 weight;
2333         u32 queue;
2334
2335         for (queue = 0; queue < tx_queues_count; queue++) {
2336                 weight = priv->plat->tx_queues_cfg[queue].weight;
2337                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2338         }
2339 }
2340
2341 /**
2342  *  stmmac_configure_cbs - Configure CBS in TX queue
2343  *  @priv: driver private structure
2344  *  Description: It is used for configuring CBS in AVB TX queues
2345  */
2346 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2347 {
2348         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2349         u32 mode_to_use;
2350         u32 queue;
2351
2352         /* queue 0 is reserved for legacy traffic */
2353         for (queue = 1; queue < tx_queues_count; queue++) {
2354                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2355                 if (mode_to_use == MTL_QUEUE_DCB)
2356                         continue;
2357
2358                 stmmac_config_cbs(priv, priv->hw,
2359                                 priv->plat->tx_queues_cfg[queue].send_slope,
2360                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2361                                 priv->plat->tx_queues_cfg[queue].high_credit,
2362                                 priv->plat->tx_queues_cfg[queue].low_credit,
2363                                 queue);
2364         }
2365 }
2366
2367 /**
2368  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2369  *  @priv: driver private structure
2370  *  Description: It is used for mapping RX queues to RX dma channels
2371  */
2372 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2373 {
2374         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2375         u32 queue;
2376         u32 chan;
2377
2378         for (queue = 0; queue < rx_queues_count; queue++) {
2379                 chan = priv->plat->rx_queues_cfg[queue].chan;
2380                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2381         }
2382 }
2383
2384 /**
2385  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2386  *  @priv: driver private structure
2387  *  Description: It is used for configuring the RX Queue Priority
2388  */
2389 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2390 {
2391         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2392         u32 queue;
2393         u32 prio;
2394
2395         for (queue = 0; queue < rx_queues_count; queue++) {
2396                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2397                         continue;
2398
2399                 prio = priv->plat->rx_queues_cfg[queue].prio;
2400                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2401         }
2402 }
2403
2404 /**
2405  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2406  *  @priv: driver private structure
2407  *  Description: It is used for configuring the TX Queue Priority
2408  */
2409 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2410 {
2411         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2412         u32 queue;
2413         u32 prio;
2414
2415         for (queue = 0; queue < tx_queues_count; queue++) {
2416                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2417                         continue;
2418
2419                 prio = priv->plat->tx_queues_cfg[queue].prio;
2420                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2421         }
2422 }
2423
2424 /**
2425  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2426  *  @priv: driver private structure
2427  *  Description: It is used for configuring the RX queue routing
2428  */
2429 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2430 {
2431         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2432         u32 queue;
2433         u8 packet;
2434
2435         for (queue = 0; queue < rx_queues_count; queue++) {
2436                 /* no specific packet type routing specified for the queue */
2437                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2438                         continue;
2439
2440                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2441                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2442         }
2443 }
2444
2445 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
2446 {
2447         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
2448                 priv->rss.enable = false;
2449                 return;
2450         }
2451
2452         if (priv->dev->features & NETIF_F_RXHASH)
2453                 priv->rss.enable = true;
2454         else
2455                 priv->rss.enable = false;
2456
2457         stmmac_rss_configure(priv, priv->hw, &priv->rss,
2458                              priv->plat->rx_queues_to_use);
2459 }
2460
2461 /**
2462  *  stmmac_mtl_configuration - Configure MTL
2463  *  @priv: driver private structure
2464  *  Description: It is used for configurring MTL
2465  */
2466 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2467 {
2468         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2469         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2470
2471         if (tx_queues_count > 1)
2472                 stmmac_set_tx_queue_weight(priv);
2473
2474         /* Configure MTL RX algorithms */
2475         if (rx_queues_count > 1)
2476                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2477                                 priv->plat->rx_sched_algorithm);
2478
2479         /* Configure MTL TX algorithms */
2480         if (tx_queues_count > 1)
2481                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2482                                 priv->plat->tx_sched_algorithm);
2483
2484         /* Configure CBS in AVB TX queues */
2485         if (tx_queues_count > 1)
2486                 stmmac_configure_cbs(priv);
2487
2488         /* Map RX MTL to DMA channels */
2489         stmmac_rx_queue_dma_chan_map(priv);
2490
2491         /* Enable MAC RX Queues */
2492         stmmac_mac_enable_rx_queues(priv);
2493
2494         /* Set RX priorities */
2495         if (rx_queues_count > 1)
2496                 stmmac_mac_config_rx_queues_prio(priv);
2497
2498         /* Set TX priorities */
2499         if (tx_queues_count > 1)
2500                 stmmac_mac_config_tx_queues_prio(priv);
2501
2502         /* Set RX routing */
2503         if (rx_queues_count > 1)
2504                 stmmac_mac_config_rx_queues_routing(priv);
2505
2506         /* Receive Side Scaling */
2507         if (rx_queues_count > 1)
2508                 stmmac_mac_config_rss(priv);
2509 }
2510
2511 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2512 {
2513         if (priv->dma_cap.asp) {
2514                 netdev_info(priv->dev, "Enabling Safety Features\n");
2515                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2516         } else {
2517                 netdev_info(priv->dev, "No Safety Features support found\n");
2518         }
2519 }
2520
2521 /**
2522  * stmmac_hw_setup - setup mac in a usable state.
2523  *  @dev : pointer to the device structure.
2524  *  Description:
2525  *  this is the main function to setup the HW in a usable state because the
2526  *  dma engine is reset, the core registers are configured (e.g. AXI,
2527  *  Checksum features, timers). The DMA is ready to start receiving and
2528  *  transmitting.
2529  *  Return value:
2530  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2531  *  file on failure.
2532  */
2533 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2534 {
2535         struct stmmac_priv *priv = netdev_priv(dev);
2536         u32 rx_cnt = priv->plat->rx_queues_to_use;
2537         u32 tx_cnt = priv->plat->tx_queues_to_use;
2538         u32 chan;
2539         int ret;
2540
2541         /* DMA initialization and SW reset */
2542         ret = stmmac_init_dma_engine(priv);
2543         if (ret < 0) {
2544                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2545                            __func__);
2546                 return ret;
2547         }
2548
2549         /* Copy the MAC addr into the HW  */
2550         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2551
2552         /* PS and related bits will be programmed according to the speed */
2553         if (priv->hw->pcs) {
2554                 int speed = priv->plat->mac_port_sel_speed;
2555
2556                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2557                     (speed == SPEED_1000)) {
2558                         priv->hw->ps = speed;
2559                 } else {
2560                         dev_warn(priv->device, "invalid port speed\n");
2561                         priv->hw->ps = 0;
2562                 }
2563         }
2564
2565         /* Initialize the MAC Core */
2566         stmmac_core_init(priv, priv->hw, dev);
2567
2568         /* Initialize MTL*/
2569         stmmac_mtl_configuration(priv);
2570
2571         /* Initialize Safety Features */
2572         stmmac_safety_feat_configuration(priv);
2573
2574         ret = stmmac_rx_ipc(priv, priv->hw);
2575         if (!ret) {
2576                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2577                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2578                 priv->hw->rx_csum = 0;
2579         }
2580
2581         /* Enable the MAC Rx/Tx */
2582         stmmac_mac_set(priv, priv->ioaddr, true);
2583
2584         /* Set the HW DMA mode and the COE */
2585         stmmac_dma_operation_mode(priv);
2586
2587         stmmac_mmc_setup(priv);
2588
2589         if (init_ptp) {
2590                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2591                 if (ret < 0)
2592                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2593
2594                 ret = stmmac_init_ptp(priv);
2595                 if (ret == -EOPNOTSUPP)
2596                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2597                 else if (ret)
2598                         netdev_warn(priv->dev, "PTP init failed\n");
2599         }
2600
2601         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2602
2603         if (priv->use_riwt) {
2604                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt);
2605                 if (!ret)
2606                         priv->rx_riwt = MIN_DMA_RIWT;
2607         }
2608
2609         if (priv->hw->pcs)
2610                 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2611
2612         /* set TX and RX rings length */
2613         stmmac_set_rings_length(priv);
2614
2615         /* Enable TSO */
2616         if (priv->tso) {
2617                 for (chan = 0; chan < tx_cnt; chan++)
2618                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2619         }
2620
2621         /* Enable Split Header */
2622         if (priv->sph && priv->hw->rx_csum) {
2623                 for (chan = 0; chan < rx_cnt; chan++)
2624                         stmmac_enable_sph(priv, priv->ioaddr, 1, chan);
2625         }
2626
2627         /* VLAN Tag Insertion */
2628         if (priv->dma_cap.vlins)
2629                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
2630
2631         /* Start the ball rolling... */
2632         stmmac_start_all_dma(priv);
2633
2634         return 0;
2635 }
2636
2637 static void stmmac_hw_teardown(struct net_device *dev)
2638 {
2639         struct stmmac_priv *priv = netdev_priv(dev);
2640
2641         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2642 }
2643
2644 /**
2645  *  stmmac_open - open entry point of the driver
2646  *  @dev : pointer to the device structure.
2647  *  Description:
2648  *  This function is the open entry point of the driver.
2649  *  Return value:
2650  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2651  *  file on failure.
2652  */
2653 static int stmmac_open(struct net_device *dev)
2654 {
2655         struct stmmac_priv *priv = netdev_priv(dev);
2656         u32 chan;
2657         int ret;
2658
2659         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2660             priv->hw->pcs != STMMAC_PCS_TBI &&
2661             priv->hw->pcs != STMMAC_PCS_RTBI) {
2662                 ret = stmmac_init_phy(dev);
2663                 if (ret) {
2664                         netdev_err(priv->dev,
2665                                    "%s: Cannot attach to PHY (error: %d)\n",
2666                                    __func__, ret);
2667                         return ret;
2668                 }
2669         }
2670
2671         /* Extra statistics */
2672         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2673         priv->xstats.threshold = tc;
2674
2675         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2676         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2677
2678         ret = alloc_dma_desc_resources(priv);
2679         if (ret < 0) {
2680                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2681                            __func__);
2682                 goto dma_desc_error;
2683         }
2684
2685         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2686         if (ret < 0) {
2687                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2688                            __func__);
2689                 goto init_error;
2690         }
2691
2692         ret = stmmac_hw_setup(dev, true);
2693         if (ret < 0) {
2694                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2695                 goto init_error;
2696         }
2697
2698         stmmac_init_coalesce(priv);
2699
2700         phylink_start(priv->phylink);
2701
2702         /* Request the IRQ lines */
2703         ret = request_irq(dev->irq, stmmac_interrupt,
2704                           IRQF_SHARED, dev->name, dev);
2705         if (unlikely(ret < 0)) {
2706                 netdev_err(priv->dev,
2707                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2708                            __func__, dev->irq, ret);
2709                 goto irq_error;
2710         }
2711
2712         /* Request the Wake IRQ in case of another line is used for WoL */
2713         if (priv->wol_irq != dev->irq) {
2714                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2715                                   IRQF_SHARED, dev->name, dev);
2716                 if (unlikely(ret < 0)) {
2717                         netdev_err(priv->dev,
2718                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2719                                    __func__, priv->wol_irq, ret);
2720                         goto wolirq_error;
2721                 }
2722         }
2723
2724         /* Request the IRQ lines */
2725         if (priv->lpi_irq > 0) {
2726                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2727                                   dev->name, dev);
2728                 if (unlikely(ret < 0)) {
2729                         netdev_err(priv->dev,
2730                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2731                                    __func__, priv->lpi_irq, ret);
2732                         goto lpiirq_error;
2733                 }
2734         }
2735
2736         stmmac_enable_all_queues(priv);
2737         stmmac_start_all_queues(priv);
2738
2739         return 0;
2740
2741 lpiirq_error:
2742         if (priv->wol_irq != dev->irq)
2743                 free_irq(priv->wol_irq, dev);
2744 wolirq_error:
2745         free_irq(dev->irq, dev);
2746 irq_error:
2747         phylink_stop(priv->phylink);
2748
2749         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2750                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2751
2752         stmmac_hw_teardown(dev);
2753 init_error:
2754         free_dma_desc_resources(priv);
2755 dma_desc_error:
2756         phylink_disconnect_phy(priv->phylink);
2757         return ret;
2758 }
2759
2760 /**
2761  *  stmmac_release - close entry point of the driver
2762  *  @dev : device pointer.
2763  *  Description:
2764  *  This is the stop entry point of the driver.
2765  */
2766 static int stmmac_release(struct net_device *dev)
2767 {
2768         struct stmmac_priv *priv = netdev_priv(dev);
2769         u32 chan;
2770
2771         if (priv->eee_enabled)
2772                 del_timer_sync(&priv->eee_ctrl_timer);
2773
2774         /* Stop and disconnect the PHY */
2775         phylink_stop(priv->phylink);
2776         phylink_disconnect_phy(priv->phylink);
2777
2778         stmmac_stop_all_queues(priv);
2779
2780         stmmac_disable_all_queues(priv);
2781
2782         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2783                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2784
2785         /* Free the IRQ lines */
2786         free_irq(dev->irq, dev);
2787         if (priv->wol_irq != dev->irq)
2788                 free_irq(priv->wol_irq, dev);
2789         if (priv->lpi_irq > 0)
2790                 free_irq(priv->lpi_irq, dev);
2791
2792         /* Stop TX/RX DMA and clear the descriptors */
2793         stmmac_stop_all_dma(priv);
2794
2795         /* Release and free the Rx/Tx resources */
2796         free_dma_desc_resources(priv);
2797
2798         /* Disable the MAC Rx/Tx */
2799         stmmac_mac_set(priv, priv->ioaddr, false);
2800
2801         netif_carrier_off(dev);
2802
2803         stmmac_release_ptp(priv);
2804
2805         return 0;
2806 }
2807
2808 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
2809                                struct stmmac_tx_queue *tx_q)
2810 {
2811         u16 tag = 0x0, inner_tag = 0x0;
2812         u32 inner_type = 0x0;
2813         struct dma_desc *p;
2814
2815         if (!priv->dma_cap.vlins)
2816                 return false;
2817         if (!skb_vlan_tag_present(skb))
2818                 return false;
2819         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
2820                 inner_tag = skb_vlan_tag_get(skb);
2821                 inner_type = STMMAC_VLAN_INSERT;
2822         }
2823
2824         tag = skb_vlan_tag_get(skb);
2825
2826         p = tx_q->dma_tx + tx_q->cur_tx;
2827         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
2828                 return false;
2829
2830         stmmac_set_tx_owner(priv, p);
2831         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2832         return true;
2833 }
2834
2835 /**
2836  *  stmmac_tso_allocator - close entry point of the driver
2837  *  @priv: driver private structure
2838  *  @des: buffer start address
2839  *  @total_len: total length to fill in descriptors
2840  *  @last_segmant: condition for the last descriptor
2841  *  @queue: TX queue index
2842  *  Description:
2843  *  This function fills descriptor and request new descriptors according to
2844  *  buffer length to fill
2845  */
2846 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2847                                  int total_len, bool last_segment, u32 queue)
2848 {
2849         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2850         struct dma_desc *desc;
2851         u32 buff_size;
2852         int tmp_len;
2853
2854         tmp_len = total_len;
2855
2856         while (tmp_len > 0) {
2857                 dma_addr_t curr_addr;
2858
2859                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2860                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2861                 desc = tx_q->dma_tx + tx_q->cur_tx;
2862
2863                 curr_addr = des + (total_len - tmp_len);
2864                 if (priv->dma_cap.addr64 <= 32)
2865                         desc->des0 = cpu_to_le32(curr_addr);
2866                 else
2867                         stmmac_set_desc_addr(priv, desc, curr_addr);
2868
2869                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2870                             TSO_MAX_BUFF_SIZE : tmp_len;
2871
2872                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2873                                 0, 1,
2874                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2875                                 0, 0);
2876
2877                 tmp_len -= TSO_MAX_BUFF_SIZE;
2878         }
2879 }
2880
2881 /**
2882  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2883  *  @skb : the socket buffer
2884  *  @dev : device pointer
2885  *  Description: this is the transmit function that is called on TSO frames
2886  *  (support available on GMAC4 and newer chips).
2887  *  Diagram below show the ring programming in case of TSO frames:
2888  *
2889  *  First Descriptor
2890  *   --------
2891  *   | DES0 |---> buffer1 = L2/L3/L4 header
2892  *   | DES1 |---> TCP Payload (can continue on next descr...)
2893  *   | DES2 |---> buffer 1 and 2 len
2894  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2895  *   --------
2896  *      |
2897  *     ...
2898  *      |
2899  *   --------
2900  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2901  *   | DES1 | --|
2902  *   | DES2 | --> buffer 1 and 2 len
2903  *   | DES3 |
2904  *   --------
2905  *
2906  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2907  */
2908 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2909 {
2910         struct dma_desc *desc, *first, *mss_desc = NULL;
2911         struct stmmac_priv *priv = netdev_priv(dev);
2912         int nfrags = skb_shinfo(skb)->nr_frags;
2913         u32 queue = skb_get_queue_mapping(skb);
2914         struct stmmac_tx_queue *tx_q;
2915         unsigned int first_entry;
2916         int tmp_pay_len = 0;
2917         u32 pay_len, mss;
2918         u8 proto_hdr_len;
2919         dma_addr_t des;
2920         bool has_vlan;
2921         int i;
2922
2923         tx_q = &priv->tx_queue[queue];
2924
2925         /* Compute header lengths */
2926         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2927
2928         /* Desc availability based on threshold should be enough safe */
2929         if (unlikely(stmmac_tx_avail(priv, queue) <
2930                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2931                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2932                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2933                                                                 queue));
2934                         /* This is a hard error, log it. */
2935                         netdev_err(priv->dev,
2936                                    "%s: Tx Ring full when queue awake\n",
2937                                    __func__);
2938                 }
2939                 return NETDEV_TX_BUSY;
2940         }
2941
2942         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2943
2944         mss = skb_shinfo(skb)->gso_size;
2945
2946         /* set new MSS value if needed */
2947         if (mss != tx_q->mss) {
2948                 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2949                 stmmac_set_mss(priv, mss_desc, mss);
2950                 tx_q->mss = mss;
2951                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2952                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2953         }
2954
2955         if (netif_msg_tx_queued(priv)) {
2956                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2957                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2958                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2959                         skb->data_len);
2960         }
2961
2962         /* Check if VLAN can be inserted by HW */
2963         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
2964
2965         first_entry = tx_q->cur_tx;
2966         WARN_ON(tx_q->tx_skbuff[first_entry]);
2967
2968         desc = tx_q->dma_tx + first_entry;
2969         first = desc;
2970
2971         if (has_vlan)
2972                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
2973
2974         /* first descriptor: fill Headers on Buf1 */
2975         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2976                              DMA_TO_DEVICE);
2977         if (dma_mapping_error(priv->device, des))
2978                 goto dma_map_err;
2979
2980         tx_q->tx_skbuff_dma[first_entry].buf = des;
2981         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2982
2983         if (priv->dma_cap.addr64 <= 32) {
2984                 first->des0 = cpu_to_le32(des);
2985
2986                 /* Fill start of payload in buff2 of first descriptor */
2987                 if (pay_len)
2988                         first->des1 = cpu_to_le32(des + proto_hdr_len);
2989
2990                 /* If needed take extra descriptors to fill the remaining payload */
2991                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2992         } else {
2993                 stmmac_set_desc_addr(priv, first, des);
2994                 tmp_pay_len = pay_len;
2995         }
2996
2997         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2998
2999         /* Prepare fragments */
3000         for (i = 0; i < nfrags; i++) {
3001                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3002
3003                 des = skb_frag_dma_map(priv->device, frag, 0,
3004                                        skb_frag_size(frag),
3005                                        DMA_TO_DEVICE);
3006                 if (dma_mapping_error(priv->device, des))
3007                         goto dma_map_err;
3008
3009                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
3010                                      (i == nfrags - 1), queue);
3011
3012                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
3013                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
3014                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
3015         }
3016
3017         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
3018
3019         /* Only the last descriptor gets to point to the skb. */
3020         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
3021
3022         /* We've used all descriptors we need for this skb, however,
3023          * advance cur_tx so that it references a fresh descriptor.
3024          * ndo_start_xmit will fill this descriptor the next time it's
3025          * called and stmmac_tx_clean may clean up to this descriptor.
3026          */
3027         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
3028
3029         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3030                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3031                           __func__);
3032                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3033         }
3034
3035         dev->stats.tx_bytes += skb->len;
3036         priv->xstats.tx_tso_frames++;
3037         priv->xstats.tx_tso_nfrags += nfrags;
3038
3039         /* Manage tx mitigation */
3040         tx_q->tx_count_frames += nfrags + 1;
3041         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3042             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3043             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3044             priv->hwts_tx_en)) {
3045                 stmmac_tx_timer_arm(priv, queue);
3046         } else {
3047                 tx_q->tx_count_frames = 0;
3048                 stmmac_set_tx_ic(priv, desc);
3049                 priv->xstats.tx_set_ic_bit++;
3050         }
3051
3052         if (priv->sarc_type)
3053                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3054
3055         skb_tx_timestamp(skb);
3056
3057         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3058                      priv->hwts_tx_en)) {
3059                 /* declare that device is doing timestamping */
3060                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3061                 stmmac_enable_tx_timestamp(priv, first);
3062         }
3063
3064         /* Complete the first descriptor before granting the DMA */
3065         stmmac_prepare_tso_tx_desc(priv, first, 1,
3066                         proto_hdr_len,
3067                         pay_len,
3068                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
3069                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
3070
3071         /* If context desc is used to change MSS */
3072         if (mss_desc) {
3073                 /* Make sure that first descriptor has been completely
3074                  * written, including its own bit. This is because MSS is
3075                  * actually before first descriptor, so we need to make
3076                  * sure that MSS's own bit is the last thing written.
3077                  */
3078                 dma_wmb();
3079                 stmmac_set_tx_owner(priv, mss_desc);
3080         }
3081
3082         /* The own bit must be the latest setting done when prepare the
3083          * descriptor and then barrier is needed to make sure that
3084          * all is coherent before granting the DMA engine.
3085          */
3086         wmb();
3087
3088         if (netif_msg_pktdata(priv)) {
3089                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3090                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3091                         tx_q->cur_tx, first, nfrags);
3092
3093                 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3094
3095                 pr_info(">>> frame to be transmitted: ");
3096                 print_pkt(skb->data, skb_headlen(skb));
3097         }
3098
3099         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3100
3101         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3102         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3103
3104         return NETDEV_TX_OK;
3105
3106 dma_map_err:
3107         dev_err(priv->device, "Tx dma map failed\n");
3108         dev_kfree_skb(skb);
3109         priv->dev->stats.tx_dropped++;
3110         return NETDEV_TX_OK;
3111 }
3112
3113 /**
3114  *  stmmac_xmit - Tx entry point of the driver
3115  *  @skb : the socket buffer
3116  *  @dev : device pointer
3117  *  Description : this is the tx entry point of the driver.
3118  *  It programs the chain or the ring and supports oversized frames
3119  *  and SG feature.
3120  */
3121 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3122 {
3123         struct stmmac_priv *priv = netdev_priv(dev);
3124         unsigned int nopaged_len = skb_headlen(skb);
3125         int i, csum_insertion = 0, is_jumbo = 0;
3126         u32 queue = skb_get_queue_mapping(skb);
3127         int nfrags = skb_shinfo(skb)->nr_frags;
3128         struct dma_desc *desc, *first;
3129         struct stmmac_tx_queue *tx_q;
3130         unsigned int first_entry;
3131         unsigned int enh_desc;
3132         dma_addr_t des;
3133         bool has_vlan;
3134         int entry;
3135
3136         tx_q = &priv->tx_queue[queue];
3137
3138         if (priv->tx_path_in_lpi_mode)
3139                 stmmac_disable_eee_mode(priv);
3140
3141         /* Manage oversized TCP frames for GMAC4 device */
3142         if (skb_is_gso(skb) && priv->tso) {
3143                 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3144                         return stmmac_tso_xmit(skb, dev);
3145         }
3146
3147         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3148                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3149                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3150                                                                 queue));
3151                         /* This is a hard error, log it. */
3152                         netdev_err(priv->dev,
3153                                    "%s: Tx Ring full when queue awake\n",
3154                                    __func__);
3155                 }
3156                 return NETDEV_TX_BUSY;
3157         }
3158
3159         /* Check if VLAN can be inserted by HW */
3160         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3161
3162         entry = tx_q->cur_tx;
3163         first_entry = entry;
3164         WARN_ON(tx_q->tx_skbuff[first_entry]);
3165
3166         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3167
3168         if (likely(priv->extend_desc))
3169                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3170         else
3171                 desc = tx_q->dma_tx + entry;
3172
3173         first = desc;
3174
3175         if (has_vlan)
3176                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
3177
3178         enh_desc = priv->plat->enh_desc;
3179         /* To program the descriptors according to the size of the frame */
3180         if (enh_desc)
3181                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3182
3183         if (unlikely(is_jumbo)) {
3184                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3185                 if (unlikely(entry < 0) && (entry != -EINVAL))
3186                         goto dma_map_err;
3187         }
3188
3189         for (i = 0; i < nfrags; i++) {
3190                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3191                 int len = skb_frag_size(frag);
3192                 bool last_segment = (i == (nfrags - 1));
3193
3194                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3195                 WARN_ON(tx_q->tx_skbuff[entry]);
3196
3197                 if (likely(priv->extend_desc))
3198                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3199                 else
3200                         desc = tx_q->dma_tx + entry;
3201
3202                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3203                                        DMA_TO_DEVICE);
3204                 if (dma_mapping_error(priv->device, des))
3205                         goto dma_map_err; /* should reuse desc w/o issues */
3206
3207                 tx_q->tx_skbuff_dma[entry].buf = des;
3208
3209                 stmmac_set_desc_addr(priv, desc, des);
3210
3211                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3212                 tx_q->tx_skbuff_dma[entry].len = len;
3213                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3214
3215                 /* Prepare the descriptor and set the own bit too */
3216                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3217                                 priv->mode, 1, last_segment, skb->len);
3218         }
3219
3220         /* Only the last descriptor gets to point to the skb. */
3221         tx_q->tx_skbuff[entry] = skb;
3222
3223         /* We've used all descriptors we need for this skb, however,
3224          * advance cur_tx so that it references a fresh descriptor.
3225          * ndo_start_xmit will fill this descriptor the next time it's
3226          * called and stmmac_tx_clean may clean up to this descriptor.
3227          */
3228         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3229         tx_q->cur_tx = entry;
3230
3231         if (netif_msg_pktdata(priv)) {
3232                 void *tx_head;
3233
3234                 netdev_dbg(priv->dev,
3235                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3236                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3237                            entry, first, nfrags);
3238
3239                 if (priv->extend_desc)
3240                         tx_head = (void *)tx_q->dma_etx;
3241                 else
3242                         tx_head = (void *)tx_q->dma_tx;
3243
3244                 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3245
3246                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3247                 print_pkt(skb->data, skb->len);
3248         }
3249
3250         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3251                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3252                           __func__);
3253                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3254         }
3255
3256         dev->stats.tx_bytes += skb->len;
3257
3258         /* According to the coalesce parameter the IC bit for the latest
3259          * segment is reset and the timer re-started to clean the tx status.
3260          * This approach takes care about the fragments: desc is the first
3261          * element in case of no SG.
3262          */
3263         tx_q->tx_count_frames += nfrags + 1;
3264         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3265             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3266             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3267             priv->hwts_tx_en)) {
3268                 stmmac_tx_timer_arm(priv, queue);
3269         } else {
3270                 tx_q->tx_count_frames = 0;
3271                 stmmac_set_tx_ic(priv, desc);
3272                 priv->xstats.tx_set_ic_bit++;
3273         }
3274
3275         if (priv->sarc_type)
3276                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3277
3278         skb_tx_timestamp(skb);
3279
3280         /* Ready to fill the first descriptor and set the OWN bit w/o any
3281          * problems because all the descriptors are actually ready to be
3282          * passed to the DMA engine.
3283          */
3284         if (likely(!is_jumbo)) {
3285                 bool last_segment = (nfrags == 0);
3286
3287                 des = dma_map_single(priv->device, skb->data,
3288                                      nopaged_len, DMA_TO_DEVICE);
3289                 if (dma_mapping_error(priv->device, des))
3290                         goto dma_map_err;
3291
3292                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3293
3294                 stmmac_set_desc_addr(priv, first, des);
3295
3296                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3297                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3298
3299                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3300                              priv->hwts_tx_en)) {
3301                         /* declare that device is doing timestamping */
3302                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3303                         stmmac_enable_tx_timestamp(priv, first);
3304                 }
3305
3306                 /* Prepare the first descriptor setting the OWN bit too */
3307                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3308                                 csum_insertion, priv->mode, 1, last_segment,
3309                                 skb->len);
3310         } else {
3311                 stmmac_set_tx_owner(priv, first);
3312         }
3313
3314         /* The own bit must be the latest setting done when prepare the
3315          * descriptor and then barrier is needed to make sure that
3316          * all is coherent before granting the DMA engine.
3317          */
3318         wmb();
3319
3320         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3321
3322         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3323
3324         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3325         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3326
3327         return NETDEV_TX_OK;
3328
3329 dma_map_err:
3330         netdev_err(priv->dev, "Tx DMA map failed\n");
3331         dev_kfree_skb(skb);
3332         priv->dev->stats.tx_dropped++;
3333         return NETDEV_TX_OK;
3334 }
3335
3336 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3337 {
3338         struct vlan_ethhdr *veth;
3339         __be16 vlan_proto;
3340         u16 vlanid;
3341
3342         veth = (struct vlan_ethhdr *)skb->data;
3343         vlan_proto = veth->h_vlan_proto;
3344
3345         if ((vlan_proto == htons(ETH_P_8021Q) &&
3346              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3347             (vlan_proto == htons(ETH_P_8021AD) &&
3348              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3349                 /* pop the vlan tag */
3350                 vlanid = ntohs(veth->h_vlan_TCI);
3351                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3352                 skb_pull(skb, VLAN_HLEN);
3353                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3354         }
3355 }
3356
3357
3358 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3359 {
3360         if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3361                 return 0;
3362
3363         return 1;
3364 }
3365
3366 /**
3367  * stmmac_rx_refill - refill used skb preallocated buffers
3368  * @priv: driver private structure
3369  * @queue: RX queue index
3370  * Description : this is to reallocate the skb for the reception process
3371  * that is based on zero-copy.
3372  */
3373 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3374 {
3375         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3376         int len, dirty = stmmac_rx_dirty(priv, queue);
3377         unsigned int entry = rx_q->dirty_rx;
3378
3379         len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
3380
3381         while (dirty-- > 0) {
3382                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
3383                 struct dma_desc *p;
3384                 bool use_rx_wd;
3385
3386                 if (priv->extend_desc)
3387                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3388                 else
3389                         p = rx_q->dma_rx + entry;
3390
3391                 if (!buf->page) {
3392                         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
3393                         if (!buf->page)
3394                                 break;
3395                 }
3396
3397                 if (priv->sph && !buf->sec_page) {
3398                         buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
3399                         if (!buf->sec_page)
3400                                 break;
3401
3402                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
3403
3404                         dma_sync_single_for_device(priv->device, buf->sec_addr,
3405                                                    len, DMA_FROM_DEVICE);
3406                 }
3407
3408                 buf->addr = page_pool_get_dma_addr(buf->page);
3409
3410                 /* Sync whole allocation to device. This will invalidate old
3411                  * data.
3412                  */
3413                 dma_sync_single_for_device(priv->device, buf->addr, len,
3414                                            DMA_FROM_DEVICE);
3415
3416                 stmmac_set_desc_addr(priv, p, buf->addr);
3417                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
3418                 stmmac_refill_desc3(priv, rx_q, p);
3419
3420                 rx_q->rx_count_frames++;
3421                 rx_q->rx_count_frames += priv->rx_coal_frames;
3422                 if (rx_q->rx_count_frames > priv->rx_coal_frames)
3423                         rx_q->rx_count_frames = 0;
3424                 use_rx_wd = priv->use_riwt && rx_q->rx_count_frames;
3425
3426                 dma_wmb();
3427                 stmmac_set_rx_owner(priv, p, use_rx_wd);
3428
3429                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3430         }
3431         rx_q->dirty_rx = entry;
3432         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3433                             (rx_q->dirty_rx * sizeof(struct dma_desc));
3434         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3435 }
3436
3437 /**
3438  * stmmac_rx - manage the receive process
3439  * @priv: driver private structure
3440  * @limit: napi bugget
3441  * @queue: RX queue index.
3442  * Description :  this the function called by the napi poll method.
3443  * It gets all the frames inside the ring.
3444  */
3445 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3446 {
3447         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3448         struct stmmac_channel *ch = &priv->channel[queue];
3449         unsigned int count = 0, error = 0, len = 0;
3450         int status = 0, coe = priv->hw->rx_csum;
3451         unsigned int next_entry = rx_q->cur_rx;
3452         struct sk_buff *skb = NULL;
3453
3454         if (netif_msg_rx_status(priv)) {
3455                 void *rx_head;
3456
3457                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3458                 if (priv->extend_desc)
3459                         rx_head = (void *)rx_q->dma_erx;
3460                 else
3461                         rx_head = (void *)rx_q->dma_rx;
3462
3463                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3464         }
3465         while (count < limit) {
3466                 unsigned int hlen = 0, prev_len = 0;
3467                 enum pkt_hash_types hash_type;
3468                 struct stmmac_rx_buffer *buf;
3469                 struct dma_desc *np, *p;
3470                 unsigned int sec_len;
3471                 int entry;
3472                 u32 hash;
3473
3474                 if (!count && rx_q->state_saved) {
3475                         skb = rx_q->state.skb;
3476                         error = rx_q->state.error;
3477                         len = rx_q->state.len;
3478                 } else {
3479                         rx_q->state_saved = false;
3480                         skb = NULL;
3481                         error = 0;
3482                         len = 0;
3483                 }
3484
3485                 if (count >= limit)
3486                         break;
3487
3488 read_again:
3489                 sec_len = 0;
3490                 entry = next_entry;
3491                 buf = &rx_q->buf_pool[entry];
3492
3493                 if (priv->extend_desc)
3494                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3495                 else
3496                         p = rx_q->dma_rx + entry;
3497
3498                 /* read the status of the incoming frame */
3499                 status = stmmac_rx_status(priv, &priv->dev->stats,
3500                                 &priv->xstats, p);
3501                 /* check if managed by the DMA otherwise go ahead */
3502                 if (unlikely(status & dma_own))
3503                         break;
3504
3505                 count++;
3506
3507                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3508                 next_entry = rx_q->cur_rx;
3509
3510                 if (priv->extend_desc)
3511                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3512                 else
3513                         np = rx_q->dma_rx + next_entry;
3514
3515                 prefetch(np);
3516                 prefetch(page_address(buf->page));
3517
3518                 if (priv->extend_desc)
3519                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3520                                         &priv->xstats, rx_q->dma_erx + entry);
3521                 if (unlikely(status == discard_frame)) {
3522                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3523                         buf->page = NULL;
3524                         error = 1;
3525                         if (!priv->hwts_rx_en)
3526                                 priv->dev->stats.rx_errors++;
3527                 }
3528
3529                 if (unlikely(error && (status & rx_not_ls)))
3530                         goto read_again;
3531                 if (unlikely(error)) {
3532                         dev_kfree_skb(skb);
3533                         continue;
3534                 }
3535
3536                 /* Buffer is good. Go on. */
3537
3538                 if (likely(status & rx_not_ls)) {
3539                         len += priv->dma_buf_sz;
3540                 } else {
3541                         prev_len = len;
3542                         len = stmmac_get_rx_frame_len(priv, p, coe);
3543
3544                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3545                          * Type frames (LLC/LLC-SNAP)
3546                          *
3547                          * llc_snap is never checked in GMAC >= 4, so this ACS
3548                          * feature is always disabled and packets need to be
3549                          * stripped manually.
3550                          */
3551                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3552                             unlikely(status != llc_snap))
3553                                 len -= ETH_FCS_LEN;
3554                 }
3555
3556                 if (!skb) {
3557                         int ret = stmmac_get_rx_header_len(priv, p, &hlen);
3558
3559                         if (priv->sph && !ret && (hlen > 0)) {
3560                                 sec_len = len;
3561                                 if (!(status & rx_not_ls))
3562                                         sec_len = sec_len - hlen;
3563                                 len = hlen;
3564
3565                                 prefetch(page_address(buf->sec_page));
3566                                 priv->xstats.rx_split_hdr_pkt_n++;
3567                         }
3568
3569                         skb = napi_alloc_skb(&ch->rx_napi, len);
3570                         if (!skb) {
3571                                 priv->dev->stats.rx_dropped++;
3572                                 continue;
3573                         }
3574
3575                         dma_sync_single_for_cpu(priv->device, buf->addr, len,
3576                                                 DMA_FROM_DEVICE);
3577                         skb_copy_to_linear_data(skb, page_address(buf->page),
3578                                                 len);
3579                         skb_put(skb, len);
3580
3581                         /* Data payload copied into SKB, page ready for recycle */
3582                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3583                         buf->page = NULL;
3584                 } else {
3585                         unsigned int buf_len = len - prev_len;
3586
3587                         if (likely(status & rx_not_ls))
3588                                 buf_len = priv->dma_buf_sz;
3589
3590                         dma_sync_single_for_cpu(priv->device, buf->addr,
3591                                                 buf_len, DMA_FROM_DEVICE);
3592                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3593                                         buf->page, 0, buf_len,
3594                                         priv->dma_buf_sz);
3595
3596                         /* Data payload appended into SKB */
3597                         page_pool_release_page(rx_q->page_pool, buf->page);
3598                         buf->page = NULL;
3599                 }
3600
3601                 if (sec_len > 0) {
3602                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
3603                                                 sec_len, DMA_FROM_DEVICE);
3604                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3605                                         buf->sec_page, 0, sec_len,
3606                                         priv->dma_buf_sz);
3607
3608                         len += sec_len;
3609
3610                         /* Data payload appended into SKB */
3611                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
3612                         buf->sec_page = NULL;
3613                 }
3614
3615                 if (likely(status & rx_not_ls))
3616                         goto read_again;
3617
3618                 /* Got entire packet into SKB. Finish it. */
3619
3620                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3621                 stmmac_rx_vlan(priv->dev, skb);
3622                 skb->protocol = eth_type_trans(skb, priv->dev);
3623
3624                 if (unlikely(!coe))
3625                         skb_checksum_none_assert(skb);
3626                 else
3627                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3628
3629                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
3630                         skb_set_hash(skb, hash, hash_type);
3631
3632                 skb_record_rx_queue(skb, queue);
3633                 napi_gro_receive(&ch->rx_napi, skb);
3634
3635                 priv->dev->stats.rx_packets++;
3636                 priv->dev->stats.rx_bytes += len;
3637         }
3638
3639         if (status & rx_not_ls) {
3640                 rx_q->state_saved = true;
3641                 rx_q->state.skb = skb;
3642                 rx_q->state.error = error;
3643                 rx_q->state.len = len;
3644         }
3645
3646         stmmac_rx_refill(priv, queue);
3647
3648         priv->xstats.rx_pkt_n += count;
3649
3650         return count;
3651 }
3652
3653 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3654 {
3655         struct stmmac_channel *ch =
3656                 container_of(napi, struct stmmac_channel, rx_napi);
3657         struct stmmac_priv *priv = ch->priv_data;
3658         u32 chan = ch->index;
3659         int work_done;
3660
3661         priv->xstats.napi_poll++;
3662
3663         work_done = stmmac_rx(priv, budget, chan);
3664         if (work_done < budget && napi_complete_done(napi, work_done))
3665                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3666         return work_done;
3667 }
3668
3669 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3670 {
3671         struct stmmac_channel *ch =
3672                 container_of(napi, struct stmmac_channel, tx_napi);
3673         struct stmmac_priv *priv = ch->priv_data;
3674         struct stmmac_tx_queue *tx_q;
3675         u32 chan = ch->index;
3676         int work_done;
3677
3678         priv->xstats.napi_poll++;
3679
3680         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3681         work_done = min(work_done, budget);
3682
3683         if (work_done < budget)
3684                 napi_complete_done(napi, work_done);
3685
3686         /* Force transmission restart */
3687         tx_q = &priv->tx_queue[chan];
3688         if (tx_q->cur_tx != tx_q->dirty_tx) {
3689                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3690                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3691                                        chan);
3692         }
3693
3694         return work_done;
3695 }
3696
3697 /**
3698  *  stmmac_tx_timeout
3699  *  @dev : Pointer to net device structure
3700  *  Description: this function is called when a packet transmission fails to
3701  *   complete within a reasonable time. The driver will mark the error in the
3702  *   netdev structure and arrange for the device to be reset to a sane state
3703  *   in order to transmit a new packet.
3704  */
3705 static void stmmac_tx_timeout(struct net_device *dev)
3706 {
3707         struct stmmac_priv *priv = netdev_priv(dev);
3708
3709         stmmac_global_err(priv);
3710 }
3711
3712 /**
3713  *  stmmac_set_rx_mode - entry point for multicast addressing
3714  *  @dev : pointer to the device structure
3715  *  Description:
3716  *  This function is a driver entry point which gets called by the kernel
3717  *  whenever multicast addresses must be enabled/disabled.
3718  *  Return value:
3719  *  void.
3720  */
3721 static void stmmac_set_rx_mode(struct net_device *dev)
3722 {
3723         struct stmmac_priv *priv = netdev_priv(dev);
3724
3725         stmmac_set_filter(priv, priv->hw, dev);
3726 }
3727
3728 /**
3729  *  stmmac_change_mtu - entry point to change MTU size for the device.
3730  *  @dev : device pointer.
3731  *  @new_mtu : the new MTU size for the device.
3732  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3733  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3734  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3735  *  Return value:
3736  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3737  *  file on failure.
3738  */
3739 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3740 {
3741         struct stmmac_priv *priv = netdev_priv(dev);
3742
3743         if (netif_running(dev)) {
3744                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3745                 return -EBUSY;
3746         }
3747
3748         dev->mtu = new_mtu;
3749
3750         netdev_update_features(dev);
3751
3752         return 0;
3753 }
3754
3755 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3756                                              netdev_features_t features)
3757 {
3758         struct stmmac_priv *priv = netdev_priv(dev);
3759
3760         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3761                 features &= ~NETIF_F_RXCSUM;
3762
3763         if (!priv->plat->tx_coe)
3764                 features &= ~NETIF_F_CSUM_MASK;
3765
3766         /* Some GMAC devices have a bugged Jumbo frame support that
3767          * needs to have the Tx COE disabled for oversized frames
3768          * (due to limited buffer sizes). In this case we disable
3769          * the TX csum insertion in the TDES and not use SF.
3770          */
3771         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3772                 features &= ~NETIF_F_CSUM_MASK;
3773
3774         /* Disable tso if asked by ethtool */
3775         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3776                 if (features & NETIF_F_TSO)
3777                         priv->tso = true;
3778                 else
3779                         priv->tso = false;
3780         }
3781
3782         return features;
3783 }
3784
3785 static int stmmac_set_features(struct net_device *netdev,
3786                                netdev_features_t features)
3787 {
3788         struct stmmac_priv *priv = netdev_priv(netdev);
3789         bool sph_en;
3790         u32 chan;
3791
3792         /* Keep the COE Type in case of csum is supporting */
3793         if (features & NETIF_F_RXCSUM)
3794                 priv->hw->rx_csum = priv->plat->rx_coe;
3795         else
3796                 priv->hw->rx_csum = 0;
3797         /* No check needed because rx_coe has been set before and it will be
3798          * fixed in case of issue.
3799          */
3800         stmmac_rx_ipc(priv, priv->hw);
3801
3802         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3803         for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
3804                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3805
3806         return 0;
3807 }
3808
3809 /**
3810  *  stmmac_interrupt - main ISR
3811  *  @irq: interrupt number.
3812  *  @dev_id: to pass the net device pointer.
3813  *  Description: this is the main driver interrupt service routine.
3814  *  It can call:
3815  *  o DMA service routine (to manage incoming frame reception and transmission
3816  *    status)
3817  *  o Core interrupts to manage: remote wake-up, management counter, LPI
3818  *    interrupts.
3819  */
3820 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3821 {
3822         struct net_device *dev = (struct net_device *)dev_id;
3823         struct stmmac_priv *priv = netdev_priv(dev);
3824         u32 rx_cnt = priv->plat->rx_queues_to_use;
3825         u32 tx_cnt = priv->plat->tx_queues_to_use;
3826         u32 queues_count;
3827         u32 queue;
3828         bool xmac;
3829
3830         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3831         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3832
3833         if (priv->irq_wake)
3834                 pm_wakeup_event(priv->device, 0);
3835
3836         if (unlikely(!dev)) {
3837                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3838                 return IRQ_NONE;
3839         }
3840
3841         /* Check if adapter is up */
3842         if (test_bit(STMMAC_DOWN, &priv->state))
3843                 return IRQ_HANDLED;
3844         /* Check if a fatal error happened */
3845         if (stmmac_safety_feat_interrupt(priv))
3846                 return IRQ_HANDLED;
3847
3848         /* To handle GMAC own interrupts */
3849         if ((priv->plat->has_gmac) || xmac) {
3850                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3851                 int mtl_status;
3852
3853                 if (unlikely(status)) {
3854                         /* For LPI we need to save the tx status */
3855                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3856                                 priv->tx_path_in_lpi_mode = true;
3857                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3858                                 priv->tx_path_in_lpi_mode = false;
3859                 }
3860
3861                 for (queue = 0; queue < queues_count; queue++) {
3862                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3863
3864                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3865                                                                 queue);
3866                         if (mtl_status != -EINVAL)
3867                                 status |= mtl_status;
3868
3869                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3870                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3871                                                        rx_q->rx_tail_addr,
3872                                                        queue);
3873                 }
3874
3875                 /* PCS link status */
3876                 if (priv->hw->pcs) {
3877                         if (priv->xstats.pcs_link)
3878                                 netif_carrier_on(dev);
3879                         else
3880                                 netif_carrier_off(dev);
3881                 }
3882         }
3883
3884         /* To handle DMA interrupts */
3885         stmmac_dma_interrupt(priv);
3886
3887         return IRQ_HANDLED;
3888 }
3889
3890 #ifdef CONFIG_NET_POLL_CONTROLLER
3891 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3892  * to allow network I/O with interrupts disabled.
3893  */
3894 static void stmmac_poll_controller(struct net_device *dev)
3895 {
3896         disable_irq(dev->irq);
3897         stmmac_interrupt(dev->irq, dev);
3898         enable_irq(dev->irq);
3899 }
3900 #endif
3901
3902 /**
3903  *  stmmac_ioctl - Entry point for the Ioctl
3904  *  @dev: Device pointer.
3905  *  @rq: An IOCTL specefic structure, that can contain a pointer to
3906  *  a proprietary structure used to pass information to the driver.
3907  *  @cmd: IOCTL command
3908  *  Description:
3909  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3910  */
3911 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3912 {
3913         struct stmmac_priv *priv = netdev_priv (dev);
3914         int ret = -EOPNOTSUPP;
3915
3916         if (!netif_running(dev))
3917                 return -EINVAL;
3918
3919         switch (cmd) {
3920         case SIOCGMIIPHY:
3921         case SIOCGMIIREG:
3922         case SIOCSMIIREG:
3923                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3924                 break;
3925         case SIOCSHWTSTAMP:
3926                 ret = stmmac_hwtstamp_set(dev, rq);
3927                 break;
3928         case SIOCGHWTSTAMP:
3929                 ret = stmmac_hwtstamp_get(dev, rq);
3930                 break;
3931         default:
3932                 break;
3933         }
3934
3935         return ret;
3936 }
3937
3938 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3939                                     void *cb_priv)
3940 {
3941         struct stmmac_priv *priv = cb_priv;
3942         int ret = -EOPNOTSUPP;
3943
3944         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
3945                 return ret;
3946
3947         stmmac_disable_all_queues(priv);
3948
3949         switch (type) {
3950         case TC_SETUP_CLSU32:
3951                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3952                 break;
3953         case TC_SETUP_CLSFLOWER:
3954                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
3955                 break;
3956         default:
3957                 break;
3958         }
3959
3960         stmmac_enable_all_queues(priv);
3961         return ret;
3962 }
3963
3964 static LIST_HEAD(stmmac_block_cb_list);
3965
3966 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3967                            void *type_data)
3968 {
3969         struct stmmac_priv *priv = netdev_priv(ndev);
3970
3971         switch (type) {
3972         case TC_SETUP_BLOCK:
3973                 return flow_block_cb_setup_simple(type_data,
3974                                                   &stmmac_block_cb_list,
3975                                                   stmmac_setup_tc_block_cb,
3976                                                   priv, priv, true);
3977         case TC_SETUP_QDISC_CBS:
3978                 return stmmac_tc_setup_cbs(priv, priv, type_data);
3979         default:
3980                 return -EOPNOTSUPP;
3981         }
3982 }
3983
3984 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
3985                                struct net_device *sb_dev)
3986 {
3987         if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3988                 /*
3989                  * There is no way to determine the number of TSO
3990                  * capable Queues. Let's use always the Queue 0
3991                  * because if TSO is supported then at least this
3992                  * one will be capable.
3993                  */
3994                 return 0;
3995         }
3996
3997         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
3998 }
3999
4000 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
4001 {
4002         struct stmmac_priv *priv = netdev_priv(ndev);
4003         int ret = 0;
4004
4005         ret = eth_mac_addr(ndev, addr);
4006         if (ret)
4007                 return ret;
4008
4009         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
4010
4011         return ret;
4012 }
4013
4014 #ifdef CONFIG_DEBUG_FS
4015 static struct dentry *stmmac_fs_dir;
4016
4017 static void sysfs_display_ring(void *head, int size, int extend_desc,
4018                                struct seq_file *seq)
4019 {
4020         int i;
4021         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
4022         struct dma_desc *p = (struct dma_desc *)head;
4023
4024         for (i = 0; i < size; i++) {
4025                 if (extend_desc) {
4026                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4027                                    i, (unsigned int)virt_to_phys(ep),
4028                                    le32_to_cpu(ep->basic.des0),
4029                                    le32_to_cpu(ep->basic.des1),
4030                                    le32_to_cpu(ep->basic.des2),
4031                                    le32_to_cpu(ep->basic.des3));
4032                         ep++;
4033                 } else {
4034                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4035                                    i, (unsigned int)virt_to_phys(p),
4036                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
4037                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
4038                         p++;
4039                 }
4040                 seq_printf(seq, "\n");
4041         }
4042 }
4043
4044 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
4045 {
4046         struct net_device *dev = seq->private;
4047         struct stmmac_priv *priv = netdev_priv(dev);
4048         u32 rx_count = priv->plat->rx_queues_to_use;
4049         u32 tx_count = priv->plat->tx_queues_to_use;
4050         u32 queue;
4051
4052         if ((dev->flags & IFF_UP) == 0)
4053                 return 0;
4054
4055         for (queue = 0; queue < rx_count; queue++) {
4056                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4057
4058                 seq_printf(seq, "RX Queue %d:\n", queue);
4059
4060                 if (priv->extend_desc) {
4061                         seq_printf(seq, "Extended descriptor ring:\n");
4062                         sysfs_display_ring((void *)rx_q->dma_erx,
4063                                            DMA_RX_SIZE, 1, seq);
4064                 } else {
4065                         seq_printf(seq, "Descriptor ring:\n");
4066                         sysfs_display_ring((void *)rx_q->dma_rx,
4067                                            DMA_RX_SIZE, 0, seq);
4068                 }
4069         }
4070
4071         for (queue = 0; queue < tx_count; queue++) {
4072                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4073
4074                 seq_printf(seq, "TX Queue %d:\n", queue);
4075
4076                 if (priv->extend_desc) {
4077                         seq_printf(seq, "Extended descriptor ring:\n");
4078                         sysfs_display_ring((void *)tx_q->dma_etx,
4079                                            DMA_TX_SIZE, 1, seq);
4080                 } else {
4081                         seq_printf(seq, "Descriptor ring:\n");
4082                         sysfs_display_ring((void *)tx_q->dma_tx,
4083                                            DMA_TX_SIZE, 0, seq);
4084                 }
4085         }
4086
4087         return 0;
4088 }
4089 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
4090
4091 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
4092 {
4093         struct net_device *dev = seq->private;
4094         struct stmmac_priv *priv = netdev_priv(dev);
4095
4096         if (!priv->hw_cap_support) {
4097                 seq_printf(seq, "DMA HW features not supported\n");
4098                 return 0;
4099         }
4100
4101         seq_printf(seq, "==============================\n");
4102         seq_printf(seq, "\tDMA HW features\n");
4103         seq_printf(seq, "==============================\n");
4104
4105         seq_printf(seq, "\t10/100 Mbps: %s\n",
4106                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
4107         seq_printf(seq, "\t1000 Mbps: %s\n",
4108                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
4109         seq_printf(seq, "\tHalf duplex: %s\n",
4110                    (priv->dma_cap.half_duplex) ? "Y" : "N");
4111         seq_printf(seq, "\tHash Filter: %s\n",
4112                    (priv->dma_cap.hash_filter) ? "Y" : "N");
4113         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4114                    (priv->dma_cap.multi_addr) ? "Y" : "N");
4115         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
4116                    (priv->dma_cap.pcs) ? "Y" : "N");
4117         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4118                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
4119         seq_printf(seq, "\tPMT Remote wake up: %s\n",
4120                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4121         seq_printf(seq, "\tPMT Magic Frame: %s\n",
4122                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4123         seq_printf(seq, "\tRMON module: %s\n",
4124                    (priv->dma_cap.rmon) ? "Y" : "N");
4125         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4126                    (priv->dma_cap.time_stamp) ? "Y" : "N");
4127         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4128                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
4129         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4130                    (priv->dma_cap.eee) ? "Y" : "N");
4131         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4132         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4133                    (priv->dma_cap.tx_coe) ? "Y" : "N");
4134         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4135                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4136                            (priv->dma_cap.rx_coe) ? "Y" : "N");
4137         } else {
4138                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4139                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4140                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4141                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4142         }
4143         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4144                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4145         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4146                    priv->dma_cap.number_rx_channel);
4147         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4148                    priv->dma_cap.number_tx_channel);
4149         seq_printf(seq, "\tEnhanced descriptors: %s\n",
4150                    (priv->dma_cap.enh_desc) ? "Y" : "N");
4151
4152         return 0;
4153 }
4154 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4155
4156 static void stmmac_init_fs(struct net_device *dev)
4157 {
4158         struct stmmac_priv *priv = netdev_priv(dev);
4159
4160         /* Create per netdev entries */
4161         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4162
4163         /* Entry to report DMA RX/TX rings */
4164         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
4165                             &stmmac_rings_status_fops);
4166
4167         /* Entry to report the DMA HW features */
4168         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
4169                             &stmmac_dma_cap_fops);
4170 }
4171
4172 static void stmmac_exit_fs(struct net_device *dev)
4173 {
4174         struct stmmac_priv *priv = netdev_priv(dev);
4175
4176         debugfs_remove_recursive(priv->dbgfs_dir);
4177 }
4178 #endif /* CONFIG_DEBUG_FS */
4179
4180 static u32 stmmac_vid_crc32_le(__le16 vid_le)
4181 {
4182         unsigned char *data = (unsigned char *)&vid_le;
4183         unsigned char data_byte = 0;
4184         u32 crc = ~0x0;
4185         u32 temp = 0;
4186         int i, bits;
4187
4188         bits = get_bitmask_order(VLAN_VID_MASK);
4189         for (i = 0; i < bits; i++) {
4190                 if ((i % 8) == 0)
4191                         data_byte = data[i / 8];
4192
4193                 temp = ((crc & 1) ^ data_byte) & 1;
4194                 crc >>= 1;
4195                 data_byte >>= 1;
4196
4197                 if (temp)
4198                         crc ^= 0xedb88320;
4199         }
4200
4201         return crc;
4202 }
4203
4204 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
4205 {
4206         u32 crc, hash = 0;
4207         u16 vid;
4208
4209         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
4210                 __le16 vid_le = cpu_to_le16(vid);
4211                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
4212                 hash |= (1 << crc);
4213         }
4214
4215         return stmmac_update_vlan_hash(priv, priv->hw, hash, is_double);
4216 }
4217
4218 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
4219 {
4220         struct stmmac_priv *priv = netdev_priv(ndev);
4221         bool is_double = false;
4222         int ret;
4223
4224         if (!priv->dma_cap.vlhash)
4225                 return -EOPNOTSUPP;
4226         if (be16_to_cpu(proto) == ETH_P_8021AD)
4227                 is_double = true;
4228
4229         set_bit(vid, priv->active_vlans);
4230         ret = stmmac_vlan_update(priv, is_double);
4231         if (ret) {
4232                 clear_bit(vid, priv->active_vlans);
4233                 return ret;
4234         }
4235
4236         return ret;
4237 }
4238
4239 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
4240 {
4241         struct stmmac_priv *priv = netdev_priv(ndev);
4242         bool is_double = false;
4243
4244         if (!priv->dma_cap.vlhash)
4245                 return -EOPNOTSUPP;
4246         if (be16_to_cpu(proto) == ETH_P_8021AD)
4247                 is_double = true;
4248
4249         clear_bit(vid, priv->active_vlans);
4250         return stmmac_vlan_update(priv, is_double);
4251 }
4252
4253 static const struct net_device_ops stmmac_netdev_ops = {
4254         .ndo_open = stmmac_open,
4255         .ndo_start_xmit = stmmac_xmit,
4256         .ndo_stop = stmmac_release,
4257         .ndo_change_mtu = stmmac_change_mtu,
4258         .ndo_fix_features = stmmac_fix_features,
4259         .ndo_set_features = stmmac_set_features,
4260         .ndo_set_rx_mode = stmmac_set_rx_mode,
4261         .ndo_tx_timeout = stmmac_tx_timeout,
4262         .ndo_do_ioctl = stmmac_ioctl,
4263         .ndo_setup_tc = stmmac_setup_tc,
4264         .ndo_select_queue = stmmac_select_queue,
4265 #ifdef CONFIG_NET_POLL_CONTROLLER
4266         .ndo_poll_controller = stmmac_poll_controller,
4267 #endif
4268         .ndo_set_mac_address = stmmac_set_mac_address,
4269         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
4270         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
4271 };
4272
4273 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4274 {
4275         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4276                 return;
4277         if (test_bit(STMMAC_DOWN, &priv->state))
4278                 return;
4279
4280         netdev_err(priv->dev, "Reset adapter.\n");
4281
4282         rtnl_lock();
4283         netif_trans_update(priv->dev);
4284         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4285                 usleep_range(1000, 2000);
4286
4287         set_bit(STMMAC_DOWN, &priv->state);
4288         dev_close(priv->dev);
4289         dev_open(priv->dev, NULL);
4290         clear_bit(STMMAC_DOWN, &priv->state);
4291         clear_bit(STMMAC_RESETING, &priv->state);
4292         rtnl_unlock();
4293 }
4294
4295 static void stmmac_service_task(struct work_struct *work)
4296 {
4297         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4298                         service_task);
4299
4300         stmmac_reset_subtask(priv);
4301         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4302 }
4303
4304 /**
4305  *  stmmac_hw_init - Init the MAC device
4306  *  @priv: driver private structure
4307  *  Description: this function is to configure the MAC device according to
4308  *  some platform parameters or the HW capability register. It prepares the
4309  *  driver to use either ring or chain modes and to setup either enhanced or
4310  *  normal descriptors.
4311  */
4312 static int stmmac_hw_init(struct stmmac_priv *priv)
4313 {
4314         int ret;
4315
4316         /* dwmac-sun8i only work in chain mode */
4317         if (priv->plat->has_sun8i)
4318                 chain_mode = 1;
4319         priv->chain_mode = chain_mode;
4320
4321         /* Initialize HW Interface */
4322         ret = stmmac_hwif_init(priv);
4323         if (ret)
4324                 return ret;
4325
4326         /* Get the HW capability (new GMAC newer than 3.50a) */
4327         priv->hw_cap_support = stmmac_get_hw_features(priv);
4328         if (priv->hw_cap_support) {
4329                 dev_info(priv->device, "DMA HW capability register supported\n");
4330
4331                 /* We can override some gmac/dma configuration fields: e.g.
4332                  * enh_desc, tx_coe (e.g. that are passed through the
4333                  * platform) with the values from the HW capability
4334                  * register (if supported).
4335                  */
4336                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4337                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4338                 priv->hw->pmt = priv->plat->pmt;
4339                 if (priv->dma_cap.hash_tb_sz) {
4340                         priv->hw->multicast_filter_bins =
4341                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
4342                         priv->hw->mcast_bits_log2 =
4343                                         ilog2(priv->hw->multicast_filter_bins);
4344                 }
4345
4346                 /* TXCOE doesn't work in thresh DMA mode */
4347                 if (priv->plat->force_thresh_dma_mode)
4348                         priv->plat->tx_coe = 0;
4349                 else
4350                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4351
4352                 /* In case of GMAC4 rx_coe is from HW cap register. */
4353                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4354
4355                 if (priv->dma_cap.rx_coe_type2)
4356                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4357                 else if (priv->dma_cap.rx_coe_type1)
4358                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4359
4360         } else {
4361                 dev_info(priv->device, "No HW DMA feature register supported\n");
4362         }
4363
4364         if (priv->plat->rx_coe) {
4365                 priv->hw->rx_csum = priv->plat->rx_coe;
4366                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4367                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4368                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4369         }
4370         if (priv->plat->tx_coe)
4371                 dev_info(priv->device, "TX Checksum insertion supported\n");
4372
4373         if (priv->plat->pmt) {
4374                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4375                 device_set_wakeup_capable(priv->device, 1);
4376         }
4377
4378         if (priv->dma_cap.tsoen)
4379                 dev_info(priv->device, "TSO supported\n");
4380
4381         /* Run HW quirks, if any */
4382         if (priv->hwif_quirks) {
4383                 ret = priv->hwif_quirks(priv);
4384                 if (ret)
4385                         return ret;
4386         }
4387
4388         /* Rx Watchdog is available in the COREs newer than the 3.40.
4389          * In some case, for example on bugged HW this feature
4390          * has to be disable and this can be done by passing the
4391          * riwt_off field from the platform.
4392          */
4393         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4394             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4395                 priv->use_riwt = 1;
4396                 dev_info(priv->device,
4397                          "Enable RX Mitigation via HW Watchdog Timer\n");
4398         }
4399
4400         return 0;
4401 }
4402
4403 /**
4404  * stmmac_dvr_probe
4405  * @device: device pointer
4406  * @plat_dat: platform data pointer
4407  * @res: stmmac resource pointer
4408  * Description: this is the main probe function used to
4409  * call the alloc_etherdev, allocate the priv structure.
4410  * Return:
4411  * returns 0 on success, otherwise errno.
4412  */
4413 int stmmac_dvr_probe(struct device *device,
4414                      struct plat_stmmacenet_data *plat_dat,
4415                      struct stmmac_resources *res)
4416 {
4417         struct net_device *ndev = NULL;
4418         struct stmmac_priv *priv;
4419         u32 queue, rxq, maxq;
4420         int i, ret = 0;
4421
4422         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4423                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4424         if (!ndev)
4425                 return -ENOMEM;
4426
4427         SET_NETDEV_DEV(ndev, device);
4428
4429         priv = netdev_priv(ndev);
4430         priv->device = device;
4431         priv->dev = ndev;
4432
4433         stmmac_set_ethtool_ops(ndev);
4434         priv->pause = pause;
4435         priv->plat = plat_dat;
4436         priv->ioaddr = res->addr;
4437         priv->dev->base_addr = (unsigned long)res->addr;
4438
4439         priv->dev->irq = res->irq;
4440         priv->wol_irq = res->wol_irq;
4441         priv->lpi_irq = res->lpi_irq;
4442
4443         if (!IS_ERR_OR_NULL(res->mac))
4444                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4445
4446         dev_set_drvdata(device, priv->dev);
4447
4448         /* Verify driver arguments */
4449         stmmac_verify_args();
4450
4451         /* Allocate workqueue */
4452         priv->wq = create_singlethread_workqueue("stmmac_wq");
4453         if (!priv->wq) {
4454                 dev_err(priv->device, "failed to create workqueue\n");
4455                 return -ENOMEM;
4456         }
4457
4458         INIT_WORK(&priv->service_task, stmmac_service_task);
4459
4460         /* Override with kernel parameters if supplied XXX CRS XXX
4461          * this needs to have multiple instances
4462          */
4463         if ((phyaddr >= 0) && (phyaddr <= 31))
4464                 priv->plat->phy_addr = phyaddr;
4465
4466         if (priv->plat->stmmac_rst) {
4467                 ret = reset_control_assert(priv->plat->stmmac_rst);
4468                 reset_control_deassert(priv->plat->stmmac_rst);
4469                 /* Some reset controllers have only reset callback instead of
4470                  * assert + deassert callbacks pair.
4471                  */
4472                 if (ret == -ENOTSUPP)
4473                         reset_control_reset(priv->plat->stmmac_rst);
4474         }
4475
4476         /* Init MAC and get the capabilities */
4477         ret = stmmac_hw_init(priv);
4478         if (ret)
4479                 goto error_hw_init;
4480
4481         stmmac_check_ether_addr(priv);
4482
4483         /* Configure real RX and TX queues */
4484         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4485         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4486
4487         ndev->netdev_ops = &stmmac_netdev_ops;
4488
4489         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4490                             NETIF_F_RXCSUM;
4491
4492         ret = stmmac_tc_init(priv, priv);
4493         if (!ret) {
4494                 ndev->hw_features |= NETIF_F_HW_TC;
4495         }
4496
4497         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4498                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4499                 priv->tso = true;
4500                 dev_info(priv->device, "TSO feature enabled\n");
4501         }
4502
4503         if (priv->dma_cap.sphen) {
4504                 ndev->hw_features |= NETIF_F_GRO;
4505                 priv->sph = true;
4506                 dev_info(priv->device, "SPH feature enabled\n");
4507         }
4508
4509         if (priv->dma_cap.addr64) {
4510                 ret = dma_set_mask_and_coherent(device,
4511                                 DMA_BIT_MASK(priv->dma_cap.addr64));
4512                 if (!ret) {
4513                         dev_info(priv->device, "Using %d bits DMA width\n",
4514                                  priv->dma_cap.addr64);
4515                 } else {
4516                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4517                         if (ret) {
4518                                 dev_err(priv->device, "Failed to set DMA Mask\n");
4519                                 goto error_hw_init;
4520                         }
4521
4522                         priv->dma_cap.addr64 = 32;
4523                 }
4524         }
4525
4526         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4527         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4528 #ifdef STMMAC_VLAN_TAG_USED
4529         /* Both mac100 and gmac support receive VLAN tag detection */
4530         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4531         if (priv->dma_cap.vlhash) {
4532                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4533                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4534         }
4535         if (priv->dma_cap.vlins) {
4536                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4537                 if (priv->dma_cap.dvlan)
4538                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
4539         }
4540 #endif
4541         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4542
4543         /* Initialize RSS */
4544         rxq = priv->plat->rx_queues_to_use;
4545         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
4546         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
4547                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
4548
4549         if (priv->dma_cap.rssen && priv->plat->rss_en)
4550                 ndev->features |= NETIF_F_RXHASH;
4551
4552         /* MTU range: 46 - hw-specific max */
4553         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4554         if (priv->plat->has_xgmac)
4555                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4556         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4557                 ndev->max_mtu = JUMBO_LEN;
4558         else
4559                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4560         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4561          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4562          */
4563         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4564             (priv->plat->maxmtu >= ndev->min_mtu))
4565                 ndev->max_mtu = priv->plat->maxmtu;
4566         else if (priv->plat->maxmtu < ndev->min_mtu)
4567                 dev_warn(priv->device,
4568                          "%s: warning: maxmtu having invalid value (%d)\n",
4569                          __func__, priv->plat->maxmtu);
4570
4571         if (flow_ctrl)
4572                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4573
4574         /* Setup channels NAPI */
4575         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4576
4577         for (queue = 0; queue < maxq; queue++) {
4578                 struct stmmac_channel *ch = &priv->channel[queue];
4579
4580                 ch->priv_data = priv;
4581                 ch->index = queue;
4582
4583                 if (queue < priv->plat->rx_queues_to_use) {
4584                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4585                                        NAPI_POLL_WEIGHT);
4586                 }
4587                 if (queue < priv->plat->tx_queues_to_use) {
4588                         netif_tx_napi_add(ndev, &ch->tx_napi,
4589                                           stmmac_napi_poll_tx,
4590                                           NAPI_POLL_WEIGHT);
4591                 }
4592         }
4593
4594         mutex_init(&priv->lock);
4595
4596         /* If a specific clk_csr value is passed from the platform
4597          * this means that the CSR Clock Range selection cannot be
4598          * changed at run-time and it is fixed. Viceversa the driver'll try to
4599          * set the MDC clock dynamically according to the csr actual
4600          * clock input.
4601          */
4602         if (priv->plat->clk_csr >= 0)
4603                 priv->clk_csr = priv->plat->clk_csr;
4604         else
4605                 stmmac_clk_csr_set(priv);
4606
4607         stmmac_check_pcs_mode(priv);
4608
4609         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
4610             priv->hw->pcs != STMMAC_PCS_TBI &&
4611             priv->hw->pcs != STMMAC_PCS_RTBI) {
4612                 /* MDIO bus Registration */
4613                 ret = stmmac_mdio_register(ndev);
4614                 if (ret < 0) {
4615                         dev_err(priv->device,
4616                                 "%s: MDIO bus (id: %d) registration failed",
4617                                 __func__, priv->plat->bus_id);
4618                         goto error_mdio_register;
4619                 }
4620         }
4621
4622         ret = stmmac_phy_setup(priv);
4623         if (ret) {
4624                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4625                 goto error_phy_setup;
4626         }
4627
4628         ret = register_netdev(ndev);
4629         if (ret) {
4630                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4631                         __func__, ret);
4632                 goto error_netdev_register;
4633         }
4634
4635 #ifdef CONFIG_DEBUG_FS
4636         stmmac_init_fs(ndev);
4637 #endif
4638
4639         return ret;
4640
4641 error_netdev_register:
4642         phylink_destroy(priv->phylink);
4643 error_phy_setup:
4644         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4645             priv->hw->pcs != STMMAC_PCS_TBI &&
4646             priv->hw->pcs != STMMAC_PCS_RTBI)
4647                 stmmac_mdio_unregister(ndev);
4648 error_mdio_register:
4649         for (queue = 0; queue < maxq; queue++) {
4650                 struct stmmac_channel *ch = &priv->channel[queue];
4651
4652                 if (queue < priv->plat->rx_queues_to_use)
4653                         netif_napi_del(&ch->rx_napi);
4654                 if (queue < priv->plat->tx_queues_to_use)
4655                         netif_napi_del(&ch->tx_napi);
4656         }
4657 error_hw_init:
4658         destroy_workqueue(priv->wq);
4659
4660         return ret;
4661 }
4662 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4663
4664 /**
4665  * stmmac_dvr_remove
4666  * @dev: device pointer
4667  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4668  * changes the link status, releases the DMA descriptor rings.
4669  */
4670 int stmmac_dvr_remove(struct device *dev)
4671 {
4672         struct net_device *ndev = dev_get_drvdata(dev);
4673         struct stmmac_priv *priv = netdev_priv(ndev);
4674
4675         netdev_info(priv->dev, "%s: removing driver", __func__);
4676
4677 #ifdef CONFIG_DEBUG_FS
4678         stmmac_exit_fs(ndev);
4679 #endif
4680         stmmac_stop_all_dma(priv);
4681
4682         stmmac_mac_set(priv, priv->ioaddr, false);
4683         netif_carrier_off(ndev);
4684         unregister_netdev(ndev);
4685         phylink_destroy(priv->phylink);
4686         if (priv->plat->stmmac_rst)
4687                 reset_control_assert(priv->plat->stmmac_rst);
4688         clk_disable_unprepare(priv->plat->pclk);
4689         clk_disable_unprepare(priv->plat->stmmac_clk);
4690         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4691             priv->hw->pcs != STMMAC_PCS_TBI &&
4692             priv->hw->pcs != STMMAC_PCS_RTBI)
4693                 stmmac_mdio_unregister(ndev);
4694         destroy_workqueue(priv->wq);
4695         mutex_destroy(&priv->lock);
4696
4697         return 0;
4698 }
4699 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4700
4701 /**
4702  * stmmac_suspend - suspend callback
4703  * @dev: device pointer
4704  * Description: this is the function to suspend the device and it is called
4705  * by the platform driver to stop the network queue, release the resources,
4706  * program the PMT register (for WoL), clean and release driver resources.
4707  */
4708 int stmmac_suspend(struct device *dev)
4709 {
4710         struct net_device *ndev = dev_get_drvdata(dev);
4711         struct stmmac_priv *priv = netdev_priv(ndev);
4712
4713         if (!ndev || !netif_running(ndev))
4714                 return 0;
4715
4716         mutex_lock(&priv->lock);
4717
4718         rtnl_lock();
4719         phylink_stop(priv->phylink);
4720         rtnl_unlock();
4721
4722         netif_device_detach(ndev);
4723         stmmac_stop_all_queues(priv);
4724
4725         stmmac_disable_all_queues(priv);
4726
4727         /* Stop TX/RX DMA */
4728         stmmac_stop_all_dma(priv);
4729
4730         /* Enable Power down mode by programming the PMT regs */
4731         if (device_may_wakeup(priv->device)) {
4732                 stmmac_pmt(priv, priv->hw, priv->wolopts);
4733                 priv->irq_wake = 1;
4734         } else {
4735                 stmmac_mac_set(priv, priv->ioaddr, false);
4736                 pinctrl_pm_select_sleep_state(priv->device);
4737                 /* Disable clock in case of PWM is off */
4738                 clk_disable(priv->plat->pclk);
4739                 clk_disable(priv->plat->stmmac_clk);
4740         }
4741         mutex_unlock(&priv->lock);
4742
4743         priv->speed = SPEED_UNKNOWN;
4744         return 0;
4745 }
4746 EXPORT_SYMBOL_GPL(stmmac_suspend);
4747
4748 /**
4749  * stmmac_reset_queues_param - reset queue parameters
4750  * @dev: device pointer
4751  */
4752 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4753 {
4754         u32 rx_cnt = priv->plat->rx_queues_to_use;
4755         u32 tx_cnt = priv->plat->tx_queues_to_use;
4756         u32 queue;
4757
4758         for (queue = 0; queue < rx_cnt; queue++) {
4759                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4760
4761                 rx_q->cur_rx = 0;
4762                 rx_q->dirty_rx = 0;
4763         }
4764
4765         for (queue = 0; queue < tx_cnt; queue++) {
4766                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4767
4768                 tx_q->cur_tx = 0;
4769                 tx_q->dirty_tx = 0;
4770                 tx_q->mss = 0;
4771         }
4772 }
4773
4774 /**
4775  * stmmac_resume - resume callback
4776  * @dev: device pointer
4777  * Description: when resume this function is invoked to setup the DMA and CORE
4778  * in a usable state.
4779  */
4780 int stmmac_resume(struct device *dev)
4781 {
4782         struct net_device *ndev = dev_get_drvdata(dev);
4783         struct stmmac_priv *priv = netdev_priv(ndev);
4784
4785         if (!netif_running(ndev))
4786                 return 0;
4787
4788         /* Power Down bit, into the PM register, is cleared
4789          * automatically as soon as a magic packet or a Wake-up frame
4790          * is received. Anyway, it's better to manually clear
4791          * this bit because it can generate problems while resuming
4792          * from another devices (e.g. serial console).
4793          */
4794         if (device_may_wakeup(priv->device)) {
4795                 mutex_lock(&priv->lock);
4796                 stmmac_pmt(priv, priv->hw, 0);
4797                 mutex_unlock(&priv->lock);
4798                 priv->irq_wake = 0;
4799         } else {
4800                 pinctrl_pm_select_default_state(priv->device);
4801                 /* enable the clk previously disabled */
4802                 clk_enable(priv->plat->stmmac_clk);
4803                 clk_enable(priv->plat->pclk);
4804                 /* reset the phy so that it's ready */
4805                 if (priv->mii)
4806                         stmmac_mdio_reset(priv->mii);
4807         }
4808
4809         netif_device_attach(ndev);
4810
4811         mutex_lock(&priv->lock);
4812
4813         stmmac_reset_queues_param(priv);
4814
4815         stmmac_clear_descriptors(priv);
4816
4817         stmmac_hw_setup(ndev, false);
4818         stmmac_init_coalesce(priv);
4819         stmmac_set_rx_mode(ndev);
4820
4821         stmmac_enable_all_queues(priv);
4822
4823         stmmac_start_all_queues(priv);
4824
4825         rtnl_lock();
4826         phylink_start(priv->phylink);
4827         rtnl_unlock();
4828
4829         mutex_unlock(&priv->lock);
4830
4831         return 0;
4832 }
4833 EXPORT_SYMBOL_GPL(stmmac_resume);
4834
4835 #ifndef MODULE
4836 static int __init stmmac_cmdline_opt(char *str)
4837 {
4838         char *opt;
4839
4840         if (!str || !*str)
4841                 return -EINVAL;
4842         while ((opt = strsep(&str, ",")) != NULL) {
4843                 if (!strncmp(opt, "debug:", 6)) {
4844                         if (kstrtoint(opt + 6, 0, &debug))
4845                                 goto err;
4846                 } else if (!strncmp(opt, "phyaddr:", 8)) {
4847                         if (kstrtoint(opt + 8, 0, &phyaddr))
4848                                 goto err;
4849                 } else if (!strncmp(opt, "buf_sz:", 7)) {
4850                         if (kstrtoint(opt + 7, 0, &buf_sz))
4851                                 goto err;
4852                 } else if (!strncmp(opt, "tc:", 3)) {
4853                         if (kstrtoint(opt + 3, 0, &tc))
4854                                 goto err;
4855                 } else if (!strncmp(opt, "watchdog:", 9)) {
4856                         if (kstrtoint(opt + 9, 0, &watchdog))
4857                                 goto err;
4858                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4859                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
4860                                 goto err;
4861                 } else if (!strncmp(opt, "pause:", 6)) {
4862                         if (kstrtoint(opt + 6, 0, &pause))
4863                                 goto err;
4864                 } else if (!strncmp(opt, "eee_timer:", 10)) {
4865                         if (kstrtoint(opt + 10, 0, &eee_timer))
4866                                 goto err;
4867                 } else if (!strncmp(opt, "chain_mode:", 11)) {
4868                         if (kstrtoint(opt + 11, 0, &chain_mode))
4869                                 goto err;
4870                 }
4871         }
4872         return 0;
4873
4874 err:
4875         pr_err("%s: ERROR broken module parameter conversion", __func__);
4876         return -EINVAL;
4877 }
4878
4879 __setup("stmmaceth=", stmmac_cmdline_opt);
4880 #endif /* MODULE */
4881
4882 static int __init stmmac_init(void)
4883 {
4884 #ifdef CONFIG_DEBUG_FS
4885         /* Create debugfs main directory if it doesn't exist yet */
4886         if (!stmmac_fs_dir)
4887                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4888 #endif
4889
4890         return 0;
4891 }
4892
4893 static void __exit stmmac_exit(void)
4894 {
4895 #ifdef CONFIG_DEBUG_FS
4896         debugfs_remove_recursive(stmmac_fs_dir);
4897 #endif
4898 }
4899
4900 module_init(stmmac_init)
4901 module_exit(stmmac_exit)
4902
4903 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4904 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4905 MODULE_LICENSE("GPL");