1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/prefetch.h>
33 #include <linux/pinctrl/consumer.h>
34 #ifdef CONFIG_DEBUG_FS
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #endif /* CONFIG_DEBUG_FS */
38 #include <linux/net_tstamp.h>
39 #include <linux/phylink.h>
40 #include <linux/udp.h>
41 #include <linux/bpf_trace.h>
42 #include <net/pkt_cls.h>
43 #include <net/xdp_sock_drv.h>
44 #include "stmmac_ptp.h"
46 #include "stmmac_xdp.h"
47 #include <linux/reset.h>
48 #include <linux/of_mdio.h>
49 #include "dwmac1000.h"
53 /* As long as the interface is active, we keep the timestamping counter enabled
54 * with fine resolution and binary rollover. This avoid non-monotonic behavior
55 * (clock jumps) when changing timestamping settings at runtime.
57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
63 /* Module parameters */
65 static int watchdog = TX_TIMEO;
66 module_param(watchdog, int, 0644);
67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
69 static int debug = -1;
70 module_param(debug, int, 0644);
71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
73 static int phyaddr = -1;
74 module_param(phyaddr, int, 0444);
75 MODULE_PARM_DESC(phyaddr, "Physical device address");
77 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4)
78 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4)
80 /* Limit to make sure XDP TX and slow path can coexist */
81 #define STMMAC_XSK_TX_BUDGET_MAX 256
82 #define STMMAC_TX_XSK_AVAIL 16
83 #define STMMAC_RX_FILL_BATCH 16
85 #define STMMAC_XDP_PASS 0
86 #define STMMAC_XDP_CONSUMED BIT(0)
87 #define STMMAC_XDP_TX BIT(1)
88 #define STMMAC_XDP_REDIRECT BIT(2)
90 static int flow_ctrl = FLOW_AUTO;
91 module_param(flow_ctrl, int, 0644);
92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
94 static int pause = PAUSE_TIME;
95 module_param(pause, int, 0644);
96 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
99 static int tc = TC_DEFAULT;
100 module_param(tc, int, 0644);
101 MODULE_PARM_DESC(tc, "DMA threshold control value");
103 #define DEFAULT_BUFSIZE 1536
104 static int buf_sz = DEFAULT_BUFSIZE;
105 module_param(buf_sz, int, 0644);
106 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
108 #define STMMAC_RX_COPYBREAK 256
110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
111 NETIF_MSG_LINK | NETIF_MSG_IFUP |
112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
114 #define STMMAC_DEFAULT_LPI_TIMER 1000
115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
116 module_param(eee_timer, int, 0644);
117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
120 /* By default the driver will use the ring mode to manage tx and rx descriptors,
121 * but allow user to force to use the chain instead of the ring
123 static unsigned int chain_mode;
124 module_param(chain_mode, int, 0444);
125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
128 /* For MSI interrupts handling */
129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
133 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
134 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
135 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
136 u32 rxmode, u32 chan);
138 #ifdef CONFIG_DEBUG_FS
139 static const struct net_device_ops stmmac_netdev_ops;
140 static void stmmac_init_fs(struct net_device *dev);
141 static void stmmac_exit_fs(struct net_device *dev);
144 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
146 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
151 ret = clk_prepare_enable(priv->plat->stmmac_clk);
154 ret = clk_prepare_enable(priv->plat->pclk);
156 clk_disable_unprepare(priv->plat->stmmac_clk);
159 if (priv->plat->clks_config) {
160 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
162 clk_disable_unprepare(priv->plat->stmmac_clk);
163 clk_disable_unprepare(priv->plat->pclk);
168 clk_disable_unprepare(priv->plat->stmmac_clk);
169 clk_disable_unprepare(priv->plat->pclk);
170 if (priv->plat->clks_config)
171 priv->plat->clks_config(priv->plat->bsp_priv, enabled);
176 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
179 * stmmac_verify_args - verify the driver parameters.
180 * Description: it checks the driver parameters and set a default in case of
183 static void stmmac_verify_args(void)
185 if (unlikely(watchdog < 0))
187 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
188 buf_sz = DEFAULT_BUFSIZE;
189 if (unlikely(flow_ctrl > 1))
190 flow_ctrl = FLOW_AUTO;
191 else if (likely(flow_ctrl < 0))
192 flow_ctrl = FLOW_OFF;
193 if (unlikely((pause < 0) || (pause > 0xffff)))
196 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
199 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
201 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
202 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
203 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
206 for (queue = 0; queue < maxq; queue++) {
207 struct stmmac_channel *ch = &priv->channel[queue];
209 if (stmmac_xdp_is_enabled(priv) &&
210 test_bit(queue, priv->af_xdp_zc_qps)) {
211 napi_disable(&ch->rxtx_napi);
215 if (queue < rx_queues_cnt)
216 napi_disable(&ch->rx_napi);
217 if (queue < tx_queues_cnt)
218 napi_disable(&ch->tx_napi);
223 * stmmac_disable_all_queues - Disable all queues
224 * @priv: driver private structure
226 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
228 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
229 struct stmmac_rx_queue *rx_q;
232 /* synchronize_rcu() needed for pending XDP buffers to drain */
233 for (queue = 0; queue < rx_queues_cnt; queue++) {
234 rx_q = &priv->rx_queue[queue];
235 if (rx_q->xsk_pool) {
241 __stmmac_disable_all_queues(priv);
245 * stmmac_enable_all_queues - Enable all queues
246 * @priv: driver private structure
248 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
250 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
251 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
252 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
255 for (queue = 0; queue < maxq; queue++) {
256 struct stmmac_channel *ch = &priv->channel[queue];
258 if (stmmac_xdp_is_enabled(priv) &&
259 test_bit(queue, priv->af_xdp_zc_qps)) {
260 napi_enable(&ch->rxtx_napi);
264 if (queue < rx_queues_cnt)
265 napi_enable(&ch->rx_napi);
266 if (queue < tx_queues_cnt)
267 napi_enable(&ch->tx_napi);
271 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
273 if (!test_bit(STMMAC_DOWN, &priv->state) &&
274 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
275 queue_work(priv->wq, &priv->service_task);
278 static void stmmac_global_err(struct stmmac_priv *priv)
280 netif_carrier_off(priv->dev);
281 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
282 stmmac_service_event_schedule(priv);
286 * stmmac_clk_csr_set - dynamically set the MDC clock
287 * @priv: driver private structure
288 * Description: this is to dynamically set the MDC clock according to the csr
291 * If a specific clk_csr value is passed from the platform
292 * this means that the CSR Clock Range selection cannot be
293 * changed at run-time and it is fixed (as reported in the driver
294 * documentation). Viceversa the driver will try to set the MDC
295 * clock dynamically according to the actual clock input.
297 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
301 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
303 /* Platform provided default clk_csr would be assumed valid
304 * for all other cases except for the below mentioned ones.
305 * For values higher than the IEEE 802.3 specified frequency
306 * we can not estimate the proper divider as it is not known
307 * the frequency of clk_csr_i. So we do not change the default
310 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
311 if (clk_rate < CSR_F_35M)
312 priv->clk_csr = STMMAC_CSR_20_35M;
313 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
314 priv->clk_csr = STMMAC_CSR_35_60M;
315 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
316 priv->clk_csr = STMMAC_CSR_60_100M;
317 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
318 priv->clk_csr = STMMAC_CSR_100_150M;
319 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
320 priv->clk_csr = STMMAC_CSR_150_250M;
321 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
322 priv->clk_csr = STMMAC_CSR_250_300M;
325 if (priv->plat->has_sun8i) {
326 if (clk_rate > 160000000)
327 priv->clk_csr = 0x03;
328 else if (clk_rate > 80000000)
329 priv->clk_csr = 0x02;
330 else if (clk_rate > 40000000)
331 priv->clk_csr = 0x01;
336 if (priv->plat->has_xgmac) {
337 if (clk_rate > 400000000)
339 else if (clk_rate > 350000000)
341 else if (clk_rate > 300000000)
343 else if (clk_rate > 250000000)
345 else if (clk_rate > 150000000)
352 static void print_pkt(unsigned char *buf, int len)
354 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
355 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
358 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
360 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
363 if (tx_q->dirty_tx > tx_q->cur_tx)
364 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
366 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
372 * stmmac_rx_dirty - Get RX queue dirty
373 * @priv: driver private structure
374 * @queue: RX queue index
376 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
378 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
381 if (rx_q->dirty_rx <= rx_q->cur_rx)
382 dirty = rx_q->cur_rx - rx_q->dirty_rx;
384 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
389 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
393 /* Clear/set the SW EEE timer flag based on LPI ET enablement */
394 priv->eee_sw_timer_en = en ? 0 : 1;
395 tx_lpi_timer = en ? priv->tx_lpi_timer : 0;
396 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
400 * stmmac_enable_eee_mode - check and enter in LPI mode
401 * @priv: driver private structure
402 * Description: this function is to verify and enter in LPI mode in case of
405 static int stmmac_enable_eee_mode(struct stmmac_priv *priv)
407 u32 tx_cnt = priv->plat->tx_queues_to_use;
410 /* check if all TX queues have the work finished */
411 for (queue = 0; queue < tx_cnt; queue++) {
412 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
414 if (tx_q->dirty_tx != tx_q->cur_tx)
415 return -EBUSY; /* still unfinished work */
418 /* Check and enter in LPI mode */
419 if (!priv->tx_path_in_lpi_mode)
420 stmmac_set_eee_mode(priv, priv->hw,
421 priv->plat->en_tx_lpi_clockgating);
426 * stmmac_disable_eee_mode - disable and exit from LPI mode
427 * @priv: driver private structure
428 * Description: this function is to exit and disable EEE in case of
429 * LPI state is true. This is called by the xmit.
431 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
433 if (!priv->eee_sw_timer_en) {
434 stmmac_lpi_entry_timer_config(priv, 0);
438 stmmac_reset_eee_mode(priv, priv->hw);
439 del_timer_sync(&priv->eee_ctrl_timer);
440 priv->tx_path_in_lpi_mode = false;
444 * stmmac_eee_ctrl_timer - EEE TX SW timer.
445 * @t: timer_list struct containing private info
447 * if there is no data transfer and if we are not in LPI state,
448 * then MAC Transmitter can be moved to LPI state.
450 static void stmmac_eee_ctrl_timer(struct timer_list *t)
452 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
454 if (stmmac_enable_eee_mode(priv))
455 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
459 * stmmac_eee_init - init EEE
460 * @priv: driver private structure
462 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
463 * can also manage EEE, this function enable the LPI state and start related
466 bool stmmac_eee_init(struct stmmac_priv *priv)
468 int eee_tw_timer = priv->eee_tw_timer;
470 /* Using PCS we cannot dial with the phy registers at this stage
471 * so we do not support extra feature like EEE.
473 if (priv->hw->pcs == STMMAC_PCS_TBI ||
474 priv->hw->pcs == STMMAC_PCS_RTBI)
477 /* Check if MAC core supports the EEE feature. */
478 if (!priv->dma_cap.eee)
481 mutex_lock(&priv->lock);
483 /* Check if it needs to be deactivated */
484 if (!priv->eee_active) {
485 if (priv->eee_enabled) {
486 netdev_dbg(priv->dev, "disable EEE\n");
487 stmmac_lpi_entry_timer_config(priv, 0);
488 del_timer_sync(&priv->eee_ctrl_timer);
489 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
491 xpcs_config_eee(priv->hw->xpcs,
492 priv->plat->mult_fact_100ns,
495 mutex_unlock(&priv->lock);
499 if (priv->eee_active && !priv->eee_enabled) {
500 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
501 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
504 xpcs_config_eee(priv->hw->xpcs,
505 priv->plat->mult_fact_100ns,
509 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
510 del_timer_sync(&priv->eee_ctrl_timer);
511 priv->tx_path_in_lpi_mode = false;
512 stmmac_lpi_entry_timer_config(priv, 1);
514 stmmac_lpi_entry_timer_config(priv, 0);
515 mod_timer(&priv->eee_ctrl_timer,
516 STMMAC_LPI_T(priv->tx_lpi_timer));
519 mutex_unlock(&priv->lock);
520 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
524 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
525 * @priv: driver private structure
526 * @p : descriptor pointer
527 * @skb : the socket buffer
529 * This function will read timestamp from the descriptor & pass it to stack.
530 * and also perform some sanity checks.
532 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
533 struct dma_desc *p, struct sk_buff *skb)
535 struct skb_shared_hwtstamps shhwtstamp;
539 if (!priv->hwts_tx_en)
542 /* exit if skb doesn't support hw tstamp */
543 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
546 /* check tx tstamp status */
547 if (stmmac_get_tx_timestamp_status(priv, p)) {
548 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
550 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
555 ns -= priv->plat->cdc_error_adj;
557 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
558 shhwtstamp.hwtstamp = ns_to_ktime(ns);
560 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
561 /* pass tstamp to stack */
562 skb_tstamp_tx(skb, &shhwtstamp);
566 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
567 * @priv: driver private structure
568 * @p : descriptor pointer
569 * @np : next descriptor pointer
570 * @skb : the socket buffer
572 * This function will read received packet's timestamp from the descriptor
573 * and pass it to stack. It also perform some sanity checks.
575 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
576 struct dma_desc *np, struct sk_buff *skb)
578 struct skb_shared_hwtstamps *shhwtstamp = NULL;
579 struct dma_desc *desc = p;
582 if (!priv->hwts_rx_en)
584 /* For GMAC4, the valid timestamp is from CTX next desc. */
585 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
588 /* Check if timestamp is available */
589 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
590 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
592 ns -= priv->plat->cdc_error_adj;
594 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
595 shhwtstamp = skb_hwtstamps(skb);
596 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
597 shhwtstamp->hwtstamp = ns_to_ktime(ns);
599 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
604 * stmmac_hwtstamp_set - control hardware timestamping.
605 * @dev: device pointer.
606 * @ifr: An IOCTL specific structure, that can contain a pointer to
607 * a proprietary structure used to pass information to the driver.
609 * This function configures the MAC to enable/disable both outgoing(TX)
610 * and incoming(RX) packets time stamping based on user input.
612 * 0 on success and an appropriate -ve integer on failure.
614 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
616 struct stmmac_priv *priv = netdev_priv(dev);
617 struct hwtstamp_config config;
620 u32 ptp_over_ipv4_udp = 0;
621 u32 ptp_over_ipv6_udp = 0;
622 u32 ptp_over_ethernet = 0;
623 u32 snap_type_sel = 0;
624 u32 ts_master_en = 0;
627 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
628 netdev_alert(priv->dev, "No support for HW time stamping\n");
629 priv->hwts_tx_en = 0;
630 priv->hwts_rx_en = 0;
635 if (copy_from_user(&config, ifr->ifr_data,
639 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
640 __func__, config.flags, config.tx_type, config.rx_filter);
642 if (config.tx_type != HWTSTAMP_TX_OFF &&
643 config.tx_type != HWTSTAMP_TX_ON)
647 switch (config.rx_filter) {
648 case HWTSTAMP_FILTER_NONE:
649 /* time stamp no incoming packet at all */
650 config.rx_filter = HWTSTAMP_FILTER_NONE;
653 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
654 /* PTP v1, UDP, any kind of event packet */
655 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
656 /* 'xmac' hardware can support Sync, Pdelay_Req and
657 * Pdelay_resp by setting bit14 and bits17/16 to 01
658 * This leaves Delay_Req timestamps out.
659 * Enable all events *and* general purpose message
662 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
663 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
664 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
667 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
668 /* PTP v1, UDP, Sync packet */
669 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
670 /* take time stamp for SYNC messages only */
671 ts_event_en = PTP_TCR_TSEVNTENA;
673 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
674 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
677 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
678 /* PTP v1, UDP, Delay_req packet */
679 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
680 /* take time stamp for Delay_Req messages only */
681 ts_master_en = PTP_TCR_TSMSTRENA;
682 ts_event_en = PTP_TCR_TSEVNTENA;
684 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
685 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
688 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
689 /* PTP v2, UDP, any kind of event packet */
690 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
691 ptp_v2 = PTP_TCR_TSVER2ENA;
692 /* take time stamp for all event messages */
693 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
695 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
696 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
699 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
700 /* PTP v2, UDP, Sync packet */
701 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
702 ptp_v2 = PTP_TCR_TSVER2ENA;
703 /* take time stamp for SYNC messages only */
704 ts_event_en = PTP_TCR_TSEVNTENA;
706 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
707 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
710 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
711 /* PTP v2, UDP, Delay_req packet */
712 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
713 ptp_v2 = PTP_TCR_TSVER2ENA;
714 /* take time stamp for Delay_Req messages only */
715 ts_master_en = PTP_TCR_TSMSTRENA;
716 ts_event_en = PTP_TCR_TSEVNTENA;
718 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
719 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
722 case HWTSTAMP_FILTER_PTP_V2_EVENT:
723 /* PTP v2/802.AS1 any layer, any kind of event packet */
724 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
725 ptp_v2 = PTP_TCR_TSVER2ENA;
726 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
727 if (priv->synopsys_id < DWMAC_CORE_4_10)
728 ts_event_en = PTP_TCR_TSEVNTENA;
729 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
730 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
731 ptp_over_ethernet = PTP_TCR_TSIPENA;
734 case HWTSTAMP_FILTER_PTP_V2_SYNC:
735 /* PTP v2/802.AS1, any layer, Sync packet */
736 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
737 ptp_v2 = PTP_TCR_TSVER2ENA;
738 /* take time stamp for SYNC messages only */
739 ts_event_en = PTP_TCR_TSEVNTENA;
741 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
742 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
743 ptp_over_ethernet = PTP_TCR_TSIPENA;
746 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
747 /* PTP v2/802.AS1, any layer, Delay_req packet */
748 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
749 ptp_v2 = PTP_TCR_TSVER2ENA;
750 /* take time stamp for Delay_Req messages only */
751 ts_master_en = PTP_TCR_TSMSTRENA;
752 ts_event_en = PTP_TCR_TSEVNTENA;
754 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
755 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
756 ptp_over_ethernet = PTP_TCR_TSIPENA;
759 case HWTSTAMP_FILTER_NTP_ALL:
760 case HWTSTAMP_FILTER_ALL:
761 /* time stamp any incoming packet */
762 config.rx_filter = HWTSTAMP_FILTER_ALL;
763 tstamp_all = PTP_TCR_TSENALL;
770 switch (config.rx_filter) {
771 case HWTSTAMP_FILTER_NONE:
772 config.rx_filter = HWTSTAMP_FILTER_NONE;
775 /* PTP v1, UDP, any kind of event packet */
776 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
780 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
781 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
783 priv->systime_flags = STMMAC_HWTS_ACTIVE;
785 if (priv->hwts_tx_en || priv->hwts_rx_en) {
786 priv->systime_flags |= tstamp_all | ptp_v2 |
787 ptp_over_ethernet | ptp_over_ipv6_udp |
788 ptp_over_ipv4_udp | ts_event_en |
789 ts_master_en | snap_type_sel;
792 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags);
794 memcpy(&priv->tstamp_config, &config, sizeof(config));
796 return copy_to_user(ifr->ifr_data, &config,
797 sizeof(config)) ? -EFAULT : 0;
801 * stmmac_hwtstamp_get - read hardware timestamping.
802 * @dev: device pointer.
803 * @ifr: An IOCTL specific structure, that can contain a pointer to
804 * a proprietary structure used to pass information to the driver.
806 * This function obtain the current hardware timestamping settings
809 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
811 struct stmmac_priv *priv = netdev_priv(dev);
812 struct hwtstamp_config *config = &priv->tstamp_config;
814 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
817 return copy_to_user(ifr->ifr_data, config,
818 sizeof(*config)) ? -EFAULT : 0;
822 * stmmac_init_tstamp_counter - init hardware timestamping counter
823 * @priv: driver private structure
824 * @systime_flags: timestamping flags
826 * Initialize hardware counter for packet timestamping.
827 * This is valid as long as the interface is open and not suspended.
828 * Will be rerun after resuming from suspend, case in which the timestamping
829 * flags updated by stmmac_hwtstamp_set() also need to be restored.
831 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)
833 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
834 struct timespec64 now;
839 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
842 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
844 netdev_warn(priv->dev,
845 "failed to enable PTP reference clock: %pe\n",
850 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags);
851 priv->systime_flags = systime_flags;
853 /* program Sub Second Increment reg */
854 stmmac_config_sub_second_increment(priv, priv->ptpaddr,
855 priv->plat->clk_ptp_rate,
857 temp = div_u64(1000000000ULL, sec_inc);
859 /* Store sub second increment for later use */
860 priv->sub_second_inc = sec_inc;
862 /* calculate default added value:
864 * addend = (2^32)/freq_div_ratio;
865 * where, freq_div_ratio = 1e9ns/sec_inc
867 temp = (u64)(temp << 32);
868 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
869 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
871 /* initialize system time */
872 ktime_get_real_ts64(&now);
874 /* lower 32 bits of tv_sec are safe until y2106 */
875 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec);
879 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter);
882 * stmmac_init_ptp - init PTP
883 * @priv: driver private structure
884 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
885 * This is done by looking at the HW cap. register.
886 * This function also registers the ptp driver.
888 static int stmmac_init_ptp(struct stmmac_priv *priv)
890 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
893 if (priv->plat->ptp_clk_freq_config)
894 priv->plat->ptp_clk_freq_config(priv);
896 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
901 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
902 if (xmac && priv->dma_cap.atime_stamp)
904 /* Dwmac 3.x core with extend_desc can support adv_ts */
905 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
908 if (priv->dma_cap.time_stamp)
909 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
912 netdev_info(priv->dev,
913 "IEEE 1588-2008 Advanced Timestamp supported\n");
915 priv->hwts_tx_en = 0;
916 priv->hwts_rx_en = 0;
921 static void stmmac_release_ptp(struct stmmac_priv *priv)
923 clk_disable_unprepare(priv->plat->clk_ptp_ref);
924 stmmac_ptp_unregister(priv);
928 * stmmac_mac_flow_ctrl - Configure flow control in all queues
929 * @priv: driver private structure
930 * @duplex: duplex passed to the next function
931 * Description: It is used for configuring the flow control in all queues
933 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
935 u32 tx_cnt = priv->plat->tx_queues_to_use;
937 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
938 priv->pause, tx_cnt);
941 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config,
942 phy_interface_t interface)
944 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
949 return &priv->hw->xpcs->pcs;
952 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
953 const struct phylink_link_state *state)
955 /* Nothing to do, xpcs_config() handles everything */
958 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
960 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
961 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
962 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
963 bool *hs_enable = &fpe_cfg->hs_enable;
965 if (is_up && *hs_enable) {
966 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
968 *lo_state = FPE_STATE_OFF;
969 *lp_state = FPE_STATE_OFF;
973 static void stmmac_mac_link_down(struct phylink_config *config,
974 unsigned int mode, phy_interface_t interface)
976 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
978 stmmac_mac_set(priv, priv->ioaddr, false);
979 priv->eee_active = false;
980 priv->tx_lpi_enabled = false;
981 priv->eee_enabled = stmmac_eee_init(priv);
982 stmmac_set_eee_pls(priv, priv->hw, false);
984 if (priv->dma_cap.fpesel)
985 stmmac_fpe_link_state_handle(priv, false);
988 static void stmmac_mac_link_up(struct phylink_config *config,
989 struct phy_device *phy,
990 unsigned int mode, phy_interface_t interface,
991 int speed, int duplex,
992 bool tx_pause, bool rx_pause)
994 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
997 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
998 ctrl &= ~priv->hw->link.speed_mask;
1000 if (interface == PHY_INTERFACE_MODE_USXGMII) {
1003 ctrl |= priv->hw->link.xgmii.speed10000;
1006 ctrl |= priv->hw->link.xgmii.speed5000;
1009 ctrl |= priv->hw->link.xgmii.speed2500;
1014 } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1017 ctrl |= priv->hw->link.xlgmii.speed100000;
1020 ctrl |= priv->hw->link.xlgmii.speed50000;
1023 ctrl |= priv->hw->link.xlgmii.speed40000;
1026 ctrl |= priv->hw->link.xlgmii.speed25000;
1029 ctrl |= priv->hw->link.xgmii.speed10000;
1032 ctrl |= priv->hw->link.speed2500;
1035 ctrl |= priv->hw->link.speed1000;
1043 ctrl |= priv->hw->link.speed2500;
1046 ctrl |= priv->hw->link.speed1000;
1049 ctrl |= priv->hw->link.speed100;
1052 ctrl |= priv->hw->link.speed10;
1059 priv->speed = speed;
1061 if (priv->plat->fix_mac_speed)
1062 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1065 ctrl &= ~priv->hw->link.duplex;
1067 ctrl |= priv->hw->link.duplex;
1069 /* Flow Control operation */
1070 if (tx_pause && rx_pause)
1071 stmmac_mac_flow_ctrl(priv, duplex);
1073 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1075 stmmac_mac_set(priv, priv->ioaddr, true);
1076 if (phy && priv->dma_cap.eee) {
1077 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1078 priv->eee_enabled = stmmac_eee_init(priv);
1079 priv->tx_lpi_enabled = priv->eee_enabled;
1080 stmmac_set_eee_pls(priv, priv->hw, true);
1083 if (priv->dma_cap.fpesel)
1084 stmmac_fpe_link_state_handle(priv, true);
1087 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1088 .validate = phylink_generic_validate,
1089 .mac_select_pcs = stmmac_mac_select_pcs,
1090 .mac_config = stmmac_mac_config,
1091 .mac_link_down = stmmac_mac_link_down,
1092 .mac_link_up = stmmac_mac_link_up,
1096 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1097 * @priv: driver private structure
1098 * Description: this is to verify if the HW supports the PCS.
1099 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1100 * configured for the TBI, RTBI, or SGMII PHY interface.
1102 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1104 int interface = priv->plat->interface;
1106 if (priv->dma_cap.pcs) {
1107 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1108 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1109 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1110 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1111 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1112 priv->hw->pcs = STMMAC_PCS_RGMII;
1113 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1114 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1115 priv->hw->pcs = STMMAC_PCS_SGMII;
1121 * stmmac_init_phy - PHY initialization
1122 * @dev: net device structure
1123 * Description: it initializes the driver's PHY state, and attaches the PHY
1124 * to the mac driver.
1128 static int stmmac_init_phy(struct net_device *dev)
1130 struct stmmac_priv *priv = netdev_priv(dev);
1131 struct device_node *node;
1134 node = priv->plat->phylink_node;
1137 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1139 /* Some DT bindings do not set-up the PHY handle. Let's try to
1143 int addr = priv->plat->phy_addr;
1144 struct phy_device *phydev;
1146 phydev = mdiobus_get_phy(priv->mii, addr);
1148 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1152 ret = phylink_connect_phy(priv->phylink, phydev);
1155 if (!priv->plat->pmt) {
1156 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1158 phylink_ethtool_get_wol(priv->phylink, &wol);
1159 device_set_wakeup_capable(priv->device, !!wol.supported);
1165 static int stmmac_phy_setup(struct stmmac_priv *priv)
1167 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1168 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1169 int max_speed = priv->plat->max_speed;
1170 int mode = priv->plat->phy_interface;
1171 struct phylink *phylink;
1173 priv->phylink_config.dev = &priv->dev->dev;
1174 priv->phylink_config.type = PHYLINK_NETDEV;
1175 if (priv->plat->mdio_bus_data)
1176 priv->phylink_config.ovr_an_inband =
1177 mdio_bus_data->xpcs_an_inband;
1180 fwnode = dev_fwnode(priv->device);
1182 /* Set the platform/firmware specified interface mode */
1183 __set_bit(mode, priv->phylink_config.supported_interfaces);
1185 /* If we have an xpcs, it defines which PHY interfaces are supported. */
1187 xpcs_get_interfaces(priv->hw->xpcs,
1188 priv->phylink_config.supported_interfaces);
1190 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1193 if (!max_speed || max_speed >= 1000)
1194 priv->phylink_config.mac_capabilities |= MAC_1000;
1196 if (priv->plat->has_gmac4) {
1197 if (!max_speed || max_speed >= 2500)
1198 priv->phylink_config.mac_capabilities |= MAC_2500FD;
1199 } else if (priv->plat->has_xgmac) {
1200 if (!max_speed || max_speed >= 2500)
1201 priv->phylink_config.mac_capabilities |= MAC_2500FD;
1202 if (!max_speed || max_speed >= 5000)
1203 priv->phylink_config.mac_capabilities |= MAC_5000FD;
1204 if (!max_speed || max_speed >= 10000)
1205 priv->phylink_config.mac_capabilities |= MAC_10000FD;
1206 if (!max_speed || max_speed >= 25000)
1207 priv->phylink_config.mac_capabilities |= MAC_25000FD;
1208 if (!max_speed || max_speed >= 40000)
1209 priv->phylink_config.mac_capabilities |= MAC_40000FD;
1210 if (!max_speed || max_speed >= 50000)
1211 priv->phylink_config.mac_capabilities |= MAC_50000FD;
1212 if (!max_speed || max_speed >= 100000)
1213 priv->phylink_config.mac_capabilities |= MAC_100000FD;
1216 /* Half-Duplex can only work with single queue */
1217 if (priv->plat->tx_queues_to_use > 1)
1218 priv->phylink_config.mac_capabilities &=
1219 ~(MAC_10HD | MAC_100HD | MAC_1000HD);
1221 phylink = phylink_create(&priv->phylink_config, fwnode,
1222 mode, &stmmac_phylink_mac_ops);
1223 if (IS_ERR(phylink))
1224 return PTR_ERR(phylink);
1226 priv->phylink = phylink;
1230 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1232 u32 rx_cnt = priv->plat->rx_queues_to_use;
1233 unsigned int desc_size;
1237 /* Display RX rings */
1238 for (queue = 0; queue < rx_cnt; queue++) {
1239 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1241 pr_info("\tRX Queue %u rings\n", queue);
1243 if (priv->extend_desc) {
1244 head_rx = (void *)rx_q->dma_erx;
1245 desc_size = sizeof(struct dma_extended_desc);
1247 head_rx = (void *)rx_q->dma_rx;
1248 desc_size = sizeof(struct dma_desc);
1251 /* Display RX ring */
1252 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
1253 rx_q->dma_rx_phy, desc_size);
1257 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1259 u32 tx_cnt = priv->plat->tx_queues_to_use;
1260 unsigned int desc_size;
1264 /* Display TX rings */
1265 for (queue = 0; queue < tx_cnt; queue++) {
1266 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1268 pr_info("\tTX Queue %d rings\n", queue);
1270 if (priv->extend_desc) {
1271 head_tx = (void *)tx_q->dma_etx;
1272 desc_size = sizeof(struct dma_extended_desc);
1273 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1274 head_tx = (void *)tx_q->dma_entx;
1275 desc_size = sizeof(struct dma_edesc);
1277 head_tx = (void *)tx_q->dma_tx;
1278 desc_size = sizeof(struct dma_desc);
1281 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
1282 tx_q->dma_tx_phy, desc_size);
1286 static void stmmac_display_rings(struct stmmac_priv *priv)
1288 /* Display RX ring */
1289 stmmac_display_rx_rings(priv);
1291 /* Display TX ring */
1292 stmmac_display_tx_rings(priv);
1295 static int stmmac_set_bfsize(int mtu, int bufsize)
1299 if (mtu >= BUF_SIZE_8KiB)
1300 ret = BUF_SIZE_16KiB;
1301 else if (mtu >= BUF_SIZE_4KiB)
1302 ret = BUF_SIZE_8KiB;
1303 else if (mtu >= BUF_SIZE_2KiB)
1304 ret = BUF_SIZE_4KiB;
1305 else if (mtu > DEFAULT_BUFSIZE)
1306 ret = BUF_SIZE_2KiB;
1308 ret = DEFAULT_BUFSIZE;
1314 * stmmac_clear_rx_descriptors - clear RX descriptors
1315 * @priv: driver private structure
1316 * @queue: RX queue index
1317 * Description: this function is called to clear the RX descriptors
1318 * in case of both basic and extended descriptors are used.
1320 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1322 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1325 /* Clear the RX descriptors */
1326 for (i = 0; i < priv->dma_rx_size; i++)
1327 if (priv->extend_desc)
1328 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1329 priv->use_riwt, priv->mode,
1330 (i == priv->dma_rx_size - 1),
1333 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1334 priv->use_riwt, priv->mode,
1335 (i == priv->dma_rx_size - 1),
1340 * stmmac_clear_tx_descriptors - clear tx descriptors
1341 * @priv: driver private structure
1342 * @queue: TX queue index.
1343 * Description: this function is called to clear the TX descriptors
1344 * in case of both basic and extended descriptors are used.
1346 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1348 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1351 /* Clear the TX descriptors */
1352 for (i = 0; i < priv->dma_tx_size; i++) {
1353 int last = (i == (priv->dma_tx_size - 1));
1356 if (priv->extend_desc)
1357 p = &tx_q->dma_etx[i].basic;
1358 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1359 p = &tx_q->dma_entx[i].basic;
1361 p = &tx_q->dma_tx[i];
1363 stmmac_init_tx_desc(priv, p, priv->mode, last);
1368 * stmmac_clear_descriptors - clear descriptors
1369 * @priv: driver private structure
1370 * Description: this function is called to clear the TX and RX descriptors
1371 * in case of both basic and extended descriptors are used.
1373 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1375 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1376 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1379 /* Clear the RX descriptors */
1380 for (queue = 0; queue < rx_queue_cnt; queue++)
1381 stmmac_clear_rx_descriptors(priv, queue);
1383 /* Clear the TX descriptors */
1384 for (queue = 0; queue < tx_queue_cnt; queue++)
1385 stmmac_clear_tx_descriptors(priv, queue);
1389 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1390 * @priv: driver private structure
1391 * @p: descriptor pointer
1392 * @i: descriptor index
1394 * @queue: RX queue index
1395 * Description: this function is called to allocate a receive buffer, perform
1396 * the DMA mapping and init the descriptor.
1398 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1399 int i, gfp_t flags, u32 queue)
1401 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1402 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1403 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
1405 if (priv->dma_cap.addr64 <= 32)
1409 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1412 buf->page_offset = stmmac_rx_offset(priv);
1415 if (priv->sph && !buf->sec_page) {
1416 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1420 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1421 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1423 buf->sec_page = NULL;
1424 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1427 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1429 stmmac_set_desc_addr(priv, p, buf->addr);
1430 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1431 stmmac_init_desc3(priv, p);
1437 * stmmac_free_rx_buffer - free RX dma buffers
1438 * @priv: private structure
1439 * @queue: RX queue index
1442 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1444 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1445 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1448 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1452 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1453 buf->sec_page = NULL;
1457 * stmmac_free_tx_buffer - free RX dma buffers
1458 * @priv: private structure
1459 * @queue: RX queue index
1462 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1464 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1466 if (tx_q->tx_skbuff_dma[i].buf &&
1467 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1468 if (tx_q->tx_skbuff_dma[i].map_as_page)
1469 dma_unmap_page(priv->device,
1470 tx_q->tx_skbuff_dma[i].buf,
1471 tx_q->tx_skbuff_dma[i].len,
1474 dma_unmap_single(priv->device,
1475 tx_q->tx_skbuff_dma[i].buf,
1476 tx_q->tx_skbuff_dma[i].len,
1480 if (tx_q->xdpf[i] &&
1481 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1482 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1483 xdp_return_frame(tx_q->xdpf[i]);
1484 tx_q->xdpf[i] = NULL;
1487 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1488 tx_q->xsk_frames_done++;
1490 if (tx_q->tx_skbuff[i] &&
1491 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1492 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1493 tx_q->tx_skbuff[i] = NULL;
1496 tx_q->tx_skbuff_dma[i].buf = 0;
1497 tx_q->tx_skbuff_dma[i].map_as_page = false;
1501 * dma_free_rx_skbufs - free RX dma buffers
1502 * @priv: private structure
1503 * @queue: RX queue index
1505 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1509 for (i = 0; i < priv->dma_rx_size; i++)
1510 stmmac_free_rx_buffer(priv, queue, i);
1513 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
1516 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1519 for (i = 0; i < priv->dma_rx_size; i++) {
1523 if (priv->extend_desc)
1524 p = &((rx_q->dma_erx + i)->basic);
1526 p = rx_q->dma_rx + i;
1528 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1533 rx_q->buf_alloc_num++;
1540 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1541 * @priv: private structure
1542 * @queue: RX queue index
1544 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
1546 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1549 for (i = 0; i < priv->dma_rx_size; i++) {
1550 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1555 xsk_buff_free(buf->xdp);
1560 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
1562 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1565 for (i = 0; i < priv->dma_rx_size; i++) {
1566 struct stmmac_rx_buffer *buf;
1567 dma_addr_t dma_addr;
1570 if (priv->extend_desc)
1571 p = (struct dma_desc *)(rx_q->dma_erx + i);
1573 p = rx_q->dma_rx + i;
1575 buf = &rx_q->buf_pool[i];
1577 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1581 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1582 stmmac_set_desc_addr(priv, p, dma_addr);
1583 rx_q->buf_alloc_num++;
1589 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1591 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1594 return xsk_get_pool_from_qid(priv->dev, queue);
1598 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1599 * @priv: driver private structure
1600 * @queue: RX queue index
1602 * Description: this function initializes the DMA RX descriptors
1603 * and allocates the socket buffers. It supports the chained and ring
1606 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
1608 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1611 netif_dbg(priv, probe, priv->dev,
1612 "(%s) dma_rx_phy=0x%08x\n", __func__,
1613 (u32)rx_q->dma_rx_phy);
1615 stmmac_clear_rx_descriptors(priv, queue);
1617 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1619 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1621 if (rx_q->xsk_pool) {
1622 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1623 MEM_TYPE_XSK_BUFF_POOL,
1625 netdev_info(priv->dev,
1626 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1628 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1630 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1633 netdev_info(priv->dev,
1634 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1638 if (rx_q->xsk_pool) {
1639 /* RX XDP ZC buffer pool may not be populated, e.g.
1642 stmmac_alloc_rx_buffers_zc(priv, queue);
1644 ret = stmmac_alloc_rx_buffers(priv, queue, flags);
1652 /* Setup the chained descriptor addresses */
1653 if (priv->mode == STMMAC_CHAIN_MODE) {
1654 if (priv->extend_desc)
1655 stmmac_mode_init(priv, rx_q->dma_erx,
1657 priv->dma_rx_size, 1);
1659 stmmac_mode_init(priv, rx_q->dma_rx,
1661 priv->dma_rx_size, 0);
1667 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1669 struct stmmac_priv *priv = netdev_priv(dev);
1670 u32 rx_count = priv->plat->rx_queues_to_use;
1674 /* RX INITIALIZATION */
1675 netif_dbg(priv, probe, priv->dev,
1676 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1678 for (queue = 0; queue < rx_count; queue++) {
1679 ret = __init_dma_rx_desc_rings(priv, queue, flags);
1681 goto err_init_rx_buffers;
1686 err_init_rx_buffers:
1687 while (queue >= 0) {
1688 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1691 dma_free_rx_xskbufs(priv, queue);
1693 dma_free_rx_skbufs(priv, queue);
1695 rx_q->buf_alloc_num = 0;
1696 rx_q->xsk_pool = NULL;
1705 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1706 * @priv: driver private structure
1707 * @queue : TX queue index
1708 * Description: this function initializes the DMA TX descriptors
1709 * and allocates the socket buffers. It supports the chained and ring
1712 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
1714 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1717 netif_dbg(priv, probe, priv->dev,
1718 "(%s) dma_tx_phy=0x%08x\n", __func__,
1719 (u32)tx_q->dma_tx_phy);
1721 /* Setup the chained descriptor addresses */
1722 if (priv->mode == STMMAC_CHAIN_MODE) {
1723 if (priv->extend_desc)
1724 stmmac_mode_init(priv, tx_q->dma_etx,
1726 priv->dma_tx_size, 1);
1727 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1728 stmmac_mode_init(priv, tx_q->dma_tx,
1730 priv->dma_tx_size, 0);
1733 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1735 for (i = 0; i < priv->dma_tx_size; i++) {
1738 if (priv->extend_desc)
1739 p = &((tx_q->dma_etx + i)->basic);
1740 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1741 p = &((tx_q->dma_entx + i)->basic);
1743 p = tx_q->dma_tx + i;
1745 stmmac_clear_desc(priv, p);
1747 tx_q->tx_skbuff_dma[i].buf = 0;
1748 tx_q->tx_skbuff_dma[i].map_as_page = false;
1749 tx_q->tx_skbuff_dma[i].len = 0;
1750 tx_q->tx_skbuff_dma[i].last_segment = false;
1751 tx_q->tx_skbuff[i] = NULL;
1758 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1763 static int init_dma_tx_desc_rings(struct net_device *dev)
1765 struct stmmac_priv *priv = netdev_priv(dev);
1769 tx_queue_cnt = priv->plat->tx_queues_to_use;
1771 for (queue = 0; queue < tx_queue_cnt; queue++)
1772 __init_dma_tx_desc_rings(priv, queue);
1778 * init_dma_desc_rings - init the RX/TX descriptor rings
1779 * @dev: net device structure
1781 * Description: this function initializes the DMA RX/TX descriptors
1782 * and allocates the socket buffers. It supports the chained and ring
1785 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1787 struct stmmac_priv *priv = netdev_priv(dev);
1790 ret = init_dma_rx_desc_rings(dev, flags);
1794 ret = init_dma_tx_desc_rings(dev);
1796 stmmac_clear_descriptors(priv);
1798 if (netif_msg_hw(priv))
1799 stmmac_display_rings(priv);
1805 * dma_free_tx_skbufs - free TX dma buffers
1806 * @priv: private structure
1807 * @queue: TX queue index
1809 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1811 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1814 tx_q->xsk_frames_done = 0;
1816 for (i = 0; i < priv->dma_tx_size; i++)
1817 stmmac_free_tx_buffer(priv, queue, i);
1819 if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1820 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1821 tx_q->xsk_frames_done = 0;
1822 tx_q->xsk_pool = NULL;
1827 * stmmac_free_tx_skbufs - free TX skb buffers
1828 * @priv: private structure
1830 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1832 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1835 for (queue = 0; queue < tx_queue_cnt; queue++)
1836 dma_free_tx_skbufs(priv, queue);
1840 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1841 * @priv: private structure
1842 * @queue: RX queue index
1844 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1846 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1848 /* Release the DMA RX socket buffers */
1850 dma_free_rx_xskbufs(priv, queue);
1852 dma_free_rx_skbufs(priv, queue);
1854 rx_q->buf_alloc_num = 0;
1855 rx_q->xsk_pool = NULL;
1857 /* Free DMA regions of consistent memory previously allocated */
1858 if (!priv->extend_desc)
1859 dma_free_coherent(priv->device, priv->dma_rx_size *
1860 sizeof(struct dma_desc),
1861 rx_q->dma_rx, rx_q->dma_rx_phy);
1863 dma_free_coherent(priv->device, priv->dma_rx_size *
1864 sizeof(struct dma_extended_desc),
1865 rx_q->dma_erx, rx_q->dma_rx_phy);
1867 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1868 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1870 kfree(rx_q->buf_pool);
1871 if (rx_q->page_pool)
1872 page_pool_destroy(rx_q->page_pool);
1875 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1877 u32 rx_count = priv->plat->rx_queues_to_use;
1880 /* Free RX queue resources */
1881 for (queue = 0; queue < rx_count; queue++)
1882 __free_dma_rx_desc_resources(priv, queue);
1886 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1887 * @priv: private structure
1888 * @queue: TX queue index
1890 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
1892 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1896 /* Release the DMA TX socket buffers */
1897 dma_free_tx_skbufs(priv, queue);
1899 if (priv->extend_desc) {
1900 size = sizeof(struct dma_extended_desc);
1901 addr = tx_q->dma_etx;
1902 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1903 size = sizeof(struct dma_edesc);
1904 addr = tx_q->dma_entx;
1906 size = sizeof(struct dma_desc);
1907 addr = tx_q->dma_tx;
1910 size *= priv->dma_tx_size;
1912 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1914 kfree(tx_q->tx_skbuff_dma);
1915 kfree(tx_q->tx_skbuff);
1918 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1920 u32 tx_count = priv->plat->tx_queues_to_use;
1923 /* Free TX queue resources */
1924 for (queue = 0; queue < tx_count; queue++)
1925 __free_dma_tx_desc_resources(priv, queue);
1929 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
1930 * @priv: private structure
1931 * @queue: RX queue index
1932 * Description: according to which descriptor can be used (extend or basic)
1933 * this function allocates the resources for TX and RX paths. In case of
1934 * reception, for example, it pre-allocated the RX socket buffer in order to
1935 * allow zero-copy mechanism.
1937 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1939 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1940 struct stmmac_channel *ch = &priv->channel[queue];
1941 bool xdp_prog = stmmac_xdp_is_enabled(priv);
1942 struct page_pool_params pp_params = { 0 };
1943 unsigned int num_pages;
1944 unsigned int napi_id;
1947 rx_q->queue_index = queue;
1948 rx_q->priv_data = priv;
1950 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
1951 pp_params.pool_size = priv->dma_rx_size;
1952 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1953 pp_params.order = ilog2(num_pages);
1954 pp_params.nid = dev_to_node(priv->device);
1955 pp_params.dev = priv->device;
1956 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
1957 pp_params.offset = stmmac_rx_offset(priv);
1958 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
1960 rx_q->page_pool = page_pool_create(&pp_params);
1961 if (IS_ERR(rx_q->page_pool)) {
1962 ret = PTR_ERR(rx_q->page_pool);
1963 rx_q->page_pool = NULL;
1967 rx_q->buf_pool = kcalloc(priv->dma_rx_size,
1968 sizeof(*rx_q->buf_pool),
1970 if (!rx_q->buf_pool)
1973 if (priv->extend_desc) {
1974 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1976 sizeof(struct dma_extended_desc),
1983 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1985 sizeof(struct dma_desc),
1992 if (stmmac_xdp_is_enabled(priv) &&
1993 test_bit(queue, priv->af_xdp_zc_qps))
1994 napi_id = ch->rxtx_napi.napi_id;
1996 napi_id = ch->rx_napi.napi_id;
1998 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2002 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2009 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
2011 u32 rx_count = priv->plat->rx_queues_to_use;
2015 /* RX queues buffers and DMA */
2016 for (queue = 0; queue < rx_count; queue++) {
2017 ret = __alloc_dma_rx_desc_resources(priv, queue);
2025 free_dma_rx_desc_resources(priv);
2031 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2032 * @priv: private structure
2033 * @queue: TX queue index
2034 * Description: according to which descriptor can be used (extend or basic)
2035 * this function allocates the resources for TX and RX paths. In case of
2036 * reception, for example, it pre-allocated the RX socket buffer in order to
2037 * allow zero-copy mechanism.
2039 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
2041 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2045 tx_q->queue_index = queue;
2046 tx_q->priv_data = priv;
2048 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
2049 sizeof(*tx_q->tx_skbuff_dma),
2051 if (!tx_q->tx_skbuff_dma)
2054 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
2055 sizeof(struct sk_buff *),
2057 if (!tx_q->tx_skbuff)
2060 if (priv->extend_desc)
2061 size = sizeof(struct dma_extended_desc);
2062 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2063 size = sizeof(struct dma_edesc);
2065 size = sizeof(struct dma_desc);
2067 size *= priv->dma_tx_size;
2069 addr = dma_alloc_coherent(priv->device, size,
2070 &tx_q->dma_tx_phy, GFP_KERNEL);
2074 if (priv->extend_desc)
2075 tx_q->dma_etx = addr;
2076 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2077 tx_q->dma_entx = addr;
2079 tx_q->dma_tx = addr;
2084 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
2086 u32 tx_count = priv->plat->tx_queues_to_use;
2090 /* TX queues buffers and DMA */
2091 for (queue = 0; queue < tx_count; queue++) {
2092 ret = __alloc_dma_tx_desc_resources(priv, queue);
2100 free_dma_tx_desc_resources(priv);
2105 * alloc_dma_desc_resources - alloc TX/RX resources.
2106 * @priv: private structure
2107 * Description: according to which descriptor can be used (extend or basic)
2108 * this function allocates the resources for TX and RX paths. In case of
2109 * reception, for example, it pre-allocated the RX socket buffer in order to
2110 * allow zero-copy mechanism.
2112 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
2115 int ret = alloc_dma_rx_desc_resources(priv);
2120 ret = alloc_dma_tx_desc_resources(priv);
2126 * free_dma_desc_resources - free dma desc resources
2127 * @priv: private structure
2129 static void free_dma_desc_resources(struct stmmac_priv *priv)
2131 /* Release the DMA TX socket buffers */
2132 free_dma_tx_desc_resources(priv);
2134 /* Release the DMA RX socket buffers later
2135 * to ensure all pending XDP_TX buffers are returned.
2137 free_dma_rx_desc_resources(priv);
2141 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
2142 * @priv: driver private structure
2143 * Description: It is used for enabling the rx queues in the MAC
2145 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2147 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2151 for (queue = 0; queue < rx_queues_count; queue++) {
2152 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2153 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2158 * stmmac_start_rx_dma - start RX DMA channel
2159 * @priv: driver private structure
2160 * @chan: RX channel index
2162 * This starts a RX DMA channel
2164 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2166 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2167 stmmac_start_rx(priv, priv->ioaddr, chan);
2171 * stmmac_start_tx_dma - start TX DMA channel
2172 * @priv: driver private structure
2173 * @chan: TX channel index
2175 * This starts a TX DMA channel
2177 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2179 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2180 stmmac_start_tx(priv, priv->ioaddr, chan);
2184 * stmmac_stop_rx_dma - stop RX DMA channel
2185 * @priv: driver private structure
2186 * @chan: RX channel index
2188 * This stops a RX DMA channel
2190 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2192 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2193 stmmac_stop_rx(priv, priv->ioaddr, chan);
2197 * stmmac_stop_tx_dma - stop TX DMA channel
2198 * @priv: driver private structure
2199 * @chan: TX channel index
2201 * This stops a TX DMA channel
2203 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2205 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2206 stmmac_stop_tx(priv, priv->ioaddr, chan);
2209 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
2211 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2212 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2213 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2216 for (chan = 0; chan < dma_csr_ch; chan++) {
2217 struct stmmac_channel *ch = &priv->channel[chan];
2218 unsigned long flags;
2220 spin_lock_irqsave(&ch->lock, flags);
2221 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
2222 spin_unlock_irqrestore(&ch->lock, flags);
2227 * stmmac_start_all_dma - start all RX and TX DMA channels
2228 * @priv: driver private structure
2230 * This starts all the RX and TX DMA channels
2232 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2234 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2235 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2238 for (chan = 0; chan < rx_channels_count; chan++)
2239 stmmac_start_rx_dma(priv, chan);
2241 for (chan = 0; chan < tx_channels_count; chan++)
2242 stmmac_start_tx_dma(priv, chan);
2246 * stmmac_stop_all_dma - stop all RX and TX DMA channels
2247 * @priv: driver private structure
2249 * This stops the RX and TX DMA channels
2251 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2253 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2254 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2257 for (chan = 0; chan < rx_channels_count; chan++)
2258 stmmac_stop_rx_dma(priv, chan);
2260 for (chan = 0; chan < tx_channels_count; chan++)
2261 stmmac_stop_tx_dma(priv, chan);
2265 * stmmac_dma_operation_mode - HW DMA operation mode
2266 * @priv: driver private structure
2267 * Description: it is used for configuring the DMA operation mode register in
2268 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2270 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2272 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2273 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2274 int rxfifosz = priv->plat->rx_fifo_size;
2275 int txfifosz = priv->plat->tx_fifo_size;
2282 rxfifosz = priv->dma_cap.rx_fifo_size;
2284 txfifosz = priv->dma_cap.tx_fifo_size;
2286 /* Adjust for real per queue fifo size */
2287 rxfifosz /= rx_channels_count;
2288 txfifosz /= tx_channels_count;
2290 if (priv->plat->force_thresh_dma_mode) {
2293 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2295 * In case of GMAC, SF mode can be enabled
2296 * to perform the TX COE in HW. This depends on:
2297 * 1) TX COE if actually supported
2298 * 2) There is no bugged Jumbo frame support
2299 * that needs to not insert csum in the TDES.
2301 txmode = SF_DMA_MODE;
2302 rxmode = SF_DMA_MODE;
2303 priv->xstats.threshold = SF_DMA_MODE;
2306 rxmode = SF_DMA_MODE;
2309 /* configure all channels */
2310 for (chan = 0; chan < rx_channels_count; chan++) {
2311 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2314 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2316 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2319 if (rx_q->xsk_pool) {
2320 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2321 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2325 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2331 for (chan = 0; chan < tx_channels_count; chan++) {
2332 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2334 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2339 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2341 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2342 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2343 struct xsk_buff_pool *pool = tx_q->xsk_pool;
2344 unsigned int entry = tx_q->cur_tx;
2345 struct dma_desc *tx_desc = NULL;
2346 struct xdp_desc xdp_desc;
2347 bool work_done = true;
2349 /* Avoids TX time-out as we are sharing with slow path */
2350 txq_trans_cond_update(nq);
2352 budget = min(budget, stmmac_tx_avail(priv, queue));
2354 while (budget-- > 0) {
2355 dma_addr_t dma_addr;
2358 /* We are sharing with slow path and stop XSK TX desc submission when
2359 * available TX ring is less than threshold.
2361 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2362 !netif_carrier_ok(priv->dev)) {
2367 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2370 if (likely(priv->extend_desc))
2371 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2372 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2373 tx_desc = &tx_q->dma_entx[entry].basic;
2375 tx_desc = tx_q->dma_tx + entry;
2377 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2378 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2380 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2382 /* To return XDP buffer to XSK pool, we simple call
2383 * xsk_tx_completed(), so we don't need to fill up
2386 tx_q->tx_skbuff_dma[entry].buf = 0;
2387 tx_q->xdpf[entry] = NULL;
2389 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2390 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2391 tx_q->tx_skbuff_dma[entry].last_segment = true;
2392 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2394 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2396 tx_q->tx_count_frames++;
2398 if (!priv->tx_coal_frames[queue])
2400 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2406 tx_q->tx_count_frames = 0;
2407 stmmac_set_tx_ic(priv, tx_desc);
2408 priv->xstats.tx_set_ic_bit++;
2411 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2412 true, priv->mode, true, true,
2415 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2417 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
2418 entry = tx_q->cur_tx;
2422 stmmac_flush_tx_descriptors(priv, queue);
2423 xsk_tx_release(pool);
2426 /* Return true if all of the 3 conditions are met
2427 * a) TX Budget is still available
2428 * b) work_done = true when XSK TX desc peek is empty (no more
2429 * pending XSK TX for transmission)
2431 return !!budget && work_done;
2434 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan)
2436 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) {
2439 if (priv->plat->force_thresh_dma_mode)
2440 stmmac_set_dma_operation_mode(priv, tc, tc, chan);
2442 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE,
2445 priv->xstats.threshold = tc;
2450 * stmmac_tx_clean - to manage the transmission completion
2451 * @priv: driver private structure
2452 * @budget: napi budget limiting this functions packet handling
2453 * @queue: TX queue index
2454 * Description: it reclaims the transmit resources after transmission completes.
2456 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2458 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2459 unsigned int bytes_compl = 0, pkts_compl = 0;
2460 unsigned int entry, xmits = 0, count = 0;
2462 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2464 priv->xstats.tx_clean++;
2466 tx_q->xsk_frames_done = 0;
2468 entry = tx_q->dirty_tx;
2470 /* Try to clean all TX complete frame in 1 shot */
2471 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
2472 struct xdp_frame *xdpf;
2473 struct sk_buff *skb;
2477 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2478 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2479 xdpf = tx_q->xdpf[entry];
2481 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2483 skb = tx_q->tx_skbuff[entry];
2489 if (priv->extend_desc)
2490 p = (struct dma_desc *)(tx_q->dma_etx + entry);
2491 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2492 p = &tx_q->dma_entx[entry].basic;
2494 p = tx_q->dma_tx + entry;
2496 status = stmmac_tx_status(priv, &priv->dev->stats,
2497 &priv->xstats, p, priv->ioaddr);
2498 /* Check if the descriptor is owned by the DMA */
2499 if (unlikely(status & tx_dma_own))
2504 /* Make sure descriptor fields are read after reading
2509 /* Just consider the last segment and ...*/
2510 if (likely(!(status & tx_not_ls))) {
2511 /* ... verify the status error condition */
2512 if (unlikely(status & tx_err)) {
2513 priv->dev->stats.tx_errors++;
2514 if (unlikely(status & tx_err_bump_tc))
2515 stmmac_bump_dma_threshold(priv, queue);
2517 priv->dev->stats.tx_packets++;
2518 priv->xstats.tx_pkt_n++;
2519 priv->xstats.txq_stats[queue].tx_pkt_n++;
2522 stmmac_get_tx_hwtstamp(priv, p, skb);
2525 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2526 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2527 if (tx_q->tx_skbuff_dma[entry].map_as_page)
2528 dma_unmap_page(priv->device,
2529 tx_q->tx_skbuff_dma[entry].buf,
2530 tx_q->tx_skbuff_dma[entry].len,
2533 dma_unmap_single(priv->device,
2534 tx_q->tx_skbuff_dma[entry].buf,
2535 tx_q->tx_skbuff_dma[entry].len,
2537 tx_q->tx_skbuff_dma[entry].buf = 0;
2538 tx_q->tx_skbuff_dma[entry].len = 0;
2539 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2542 stmmac_clean_desc3(priv, tx_q, p);
2544 tx_q->tx_skbuff_dma[entry].last_segment = false;
2545 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2548 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2549 xdp_return_frame_rx_napi(xdpf);
2550 tx_q->xdpf[entry] = NULL;
2554 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2555 xdp_return_frame(xdpf);
2556 tx_q->xdpf[entry] = NULL;
2559 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2560 tx_q->xsk_frames_done++;
2562 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2565 bytes_compl += skb->len;
2566 dev_consume_skb_any(skb);
2567 tx_q->tx_skbuff[entry] = NULL;
2571 stmmac_release_tx_desc(priv, p, priv->mode);
2573 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
2575 tx_q->dirty_tx = entry;
2577 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2578 pkts_compl, bytes_compl);
2580 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2582 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2584 netif_dbg(priv, tx_done, priv->dev,
2585 "%s: restart transmit\n", __func__);
2586 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2589 if (tx_q->xsk_pool) {
2592 if (tx_q->xsk_frames_done)
2593 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2595 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2596 xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2598 /* For XSK TX, we try to send as many as possible.
2599 * If XSK work done (XSK TX desc empty and budget still
2600 * available), return "budget - 1" to reenable TX IRQ.
2601 * Else, return "budget" to make NAPI continue polling.
2603 work_done = stmmac_xdp_xmit_zc(priv, queue,
2604 STMMAC_XSK_TX_BUDGET_MAX);
2611 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2612 priv->eee_sw_timer_en) {
2613 if (stmmac_enable_eee_mode(priv))
2614 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2617 /* We still have pending packets, let's call for a new scheduling */
2618 if (tx_q->dirty_tx != tx_q->cur_tx)
2619 hrtimer_start(&tx_q->txtimer,
2620 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2623 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2625 /* Combine decisions from TX clean and XSK TX */
2626 return max(count, xmits);
2630 * stmmac_tx_err - to manage the tx error
2631 * @priv: driver private structure
2632 * @chan: channel index
2633 * Description: it cleans the descriptors and restarts the transmission
2634 * in case of transmission errors.
2636 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2638 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2640 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2642 stmmac_stop_tx_dma(priv, chan);
2643 dma_free_tx_skbufs(priv, chan);
2644 stmmac_clear_tx_descriptors(priv, chan);
2648 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2649 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2650 tx_q->dma_tx_phy, chan);
2651 stmmac_start_tx_dma(priv, chan);
2653 priv->dev->stats.tx_errors++;
2654 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2658 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2659 * @priv: driver private structure
2660 * @txmode: TX operating mode
2661 * @rxmode: RX operating mode
2662 * @chan: channel index
2663 * Description: it is used for configuring of the DMA operation mode in
2664 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2667 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2668 u32 rxmode, u32 chan)
2670 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2671 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2672 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2673 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2674 int rxfifosz = priv->plat->rx_fifo_size;
2675 int txfifosz = priv->plat->tx_fifo_size;
2678 rxfifosz = priv->dma_cap.rx_fifo_size;
2680 txfifosz = priv->dma_cap.tx_fifo_size;
2682 /* Adjust for real per queue fifo size */
2683 rxfifosz /= rx_channels_count;
2684 txfifosz /= tx_channels_count;
2686 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2687 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2690 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2694 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2695 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2696 if (ret && (ret != -EINVAL)) {
2697 stmmac_global_err(priv);
2704 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2706 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2707 &priv->xstats, chan, dir);
2708 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2709 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2710 struct stmmac_channel *ch = &priv->channel[chan];
2711 struct napi_struct *rx_napi;
2712 struct napi_struct *tx_napi;
2713 unsigned long flags;
2715 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2716 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2718 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2719 if (napi_schedule_prep(rx_napi)) {
2720 spin_lock_irqsave(&ch->lock, flags);
2721 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2722 spin_unlock_irqrestore(&ch->lock, flags);
2723 __napi_schedule(rx_napi);
2727 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2728 if (napi_schedule_prep(tx_napi)) {
2729 spin_lock_irqsave(&ch->lock, flags);
2730 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2731 spin_unlock_irqrestore(&ch->lock, flags);
2732 __napi_schedule(tx_napi);
2740 * stmmac_dma_interrupt - DMA ISR
2741 * @priv: driver private structure
2742 * Description: this is the DMA ISR. It is called by the main ISR.
2743 * It calls the dwmac dma routine and schedule poll method in case of some
2746 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2748 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2749 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2750 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2751 tx_channel_count : rx_channel_count;
2753 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2755 /* Make sure we never check beyond our status buffer. */
2756 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2757 channels_to_check = ARRAY_SIZE(status);
2759 for (chan = 0; chan < channels_to_check; chan++)
2760 status[chan] = stmmac_napi_check(priv, chan,
2763 for (chan = 0; chan < tx_channel_count; chan++) {
2764 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2765 /* Try to bump up the dma threshold on this failure */
2766 stmmac_bump_dma_threshold(priv, chan);
2767 } else if (unlikely(status[chan] == tx_hard_error)) {
2768 stmmac_tx_err(priv, chan);
2774 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2775 * @priv: driver private structure
2776 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2778 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2780 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2781 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2783 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2785 if (priv->dma_cap.rmon) {
2786 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2787 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2789 netdev_info(priv->dev, "No MAC Management Counters available\n");
2793 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2794 * @priv: driver private structure
2796 * new GMAC chip generations have a new register to indicate the
2797 * presence of the optional feature/functions.
2798 * This can be also used to override the value passed through the
2799 * platform and necessary for old MAC10/100 and GMAC chips.
2801 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2803 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2807 * stmmac_check_ether_addr - check if the MAC addr is valid
2808 * @priv: driver private structure
2810 * it is to verify if the MAC address is valid, in case of failures it
2811 * generates a random MAC address
2813 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2817 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2818 stmmac_get_umac_addr(priv, priv->hw, addr, 0);
2819 if (is_valid_ether_addr(addr))
2820 eth_hw_addr_set(priv->dev, addr);
2822 eth_hw_addr_random(priv->dev);
2823 dev_info(priv->device, "device MAC address %pM\n",
2824 priv->dev->dev_addr);
2829 * stmmac_init_dma_engine - DMA init.
2830 * @priv: driver private structure
2832 * It inits the DMA invoking the specific MAC/GMAC callback.
2833 * Some DMA parameters can be passed from the platform;
2834 * in case of these are not passed a default is kept for the MAC or GMAC.
2836 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2838 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2839 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2840 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2841 struct stmmac_rx_queue *rx_q;
2842 struct stmmac_tx_queue *tx_q;
2847 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2848 dev_err(priv->device, "Invalid DMA configuration\n");
2852 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2855 ret = stmmac_reset(priv, priv->ioaddr);
2857 dev_err(priv->device, "Failed to reset the dma\n");
2861 /* DMA Configuration */
2862 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2864 if (priv->plat->axi)
2865 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2867 /* DMA CSR Channel configuration */
2868 for (chan = 0; chan < dma_csr_ch; chan++) {
2869 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2870 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
2873 /* DMA RX Channel Configuration */
2874 for (chan = 0; chan < rx_channels_count; chan++) {
2875 rx_q = &priv->rx_queue[chan];
2877 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2878 rx_q->dma_rx_phy, chan);
2880 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2881 (rx_q->buf_alloc_num *
2882 sizeof(struct dma_desc));
2883 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2884 rx_q->rx_tail_addr, chan);
2887 /* DMA TX Channel Configuration */
2888 for (chan = 0; chan < tx_channels_count; chan++) {
2889 tx_q = &priv->tx_queue[chan];
2891 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2892 tx_q->dma_tx_phy, chan);
2894 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2895 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2896 tx_q->tx_tail_addr, chan);
2902 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2904 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2906 hrtimer_start(&tx_q->txtimer,
2907 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2912 * stmmac_tx_timer - mitigation sw timer for tx.
2915 * This is the timer handler to directly invoke the stmmac_tx_clean.
2917 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
2919 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
2920 struct stmmac_priv *priv = tx_q->priv_data;
2921 struct stmmac_channel *ch;
2922 struct napi_struct *napi;
2924 ch = &priv->channel[tx_q->queue_index];
2925 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2927 if (likely(napi_schedule_prep(napi))) {
2928 unsigned long flags;
2930 spin_lock_irqsave(&ch->lock, flags);
2931 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2932 spin_unlock_irqrestore(&ch->lock, flags);
2933 __napi_schedule(napi);
2936 return HRTIMER_NORESTART;
2940 * stmmac_init_coalesce - init mitigation options.
2941 * @priv: driver private structure
2943 * This inits the coalesce parameters: i.e. timer rate,
2944 * timer handler and default threshold used for enabling the
2945 * interrupt on completion bit.
2947 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2949 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2950 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2953 for (chan = 0; chan < tx_channel_count; chan++) {
2954 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2956 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
2957 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
2959 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2960 tx_q->txtimer.function = stmmac_tx_timer;
2963 for (chan = 0; chan < rx_channel_count; chan++)
2964 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
2967 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2969 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2970 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2973 /* set TX ring length */
2974 for (chan = 0; chan < tx_channels_count; chan++)
2975 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2976 (priv->dma_tx_size - 1), chan);
2978 /* set RX ring length */
2979 for (chan = 0; chan < rx_channels_count; chan++)
2980 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2981 (priv->dma_rx_size - 1), chan);
2985 * stmmac_set_tx_queue_weight - Set TX queue weight
2986 * @priv: driver private structure
2987 * Description: It is used for setting TX queues weight
2989 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2991 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2995 for (queue = 0; queue < tx_queues_count; queue++) {
2996 weight = priv->plat->tx_queues_cfg[queue].weight;
2997 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
3002 * stmmac_configure_cbs - Configure CBS in TX queue
3003 * @priv: driver private structure
3004 * Description: It is used for configuring CBS in AVB TX queues
3006 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3008 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3012 /* queue 0 is reserved for legacy traffic */
3013 for (queue = 1; queue < tx_queues_count; queue++) {
3014 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3015 if (mode_to_use == MTL_QUEUE_DCB)
3018 stmmac_config_cbs(priv, priv->hw,
3019 priv->plat->tx_queues_cfg[queue].send_slope,
3020 priv->plat->tx_queues_cfg[queue].idle_slope,
3021 priv->plat->tx_queues_cfg[queue].high_credit,
3022 priv->plat->tx_queues_cfg[queue].low_credit,
3028 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3029 * @priv: driver private structure
3030 * Description: It is used for mapping RX queues to RX dma channels
3032 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3034 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3038 for (queue = 0; queue < rx_queues_count; queue++) {
3039 chan = priv->plat->rx_queues_cfg[queue].chan;
3040 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3045 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3046 * @priv: driver private structure
3047 * Description: It is used for configuring the RX Queue Priority
3049 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3051 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3055 for (queue = 0; queue < rx_queues_count; queue++) {
3056 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3059 prio = priv->plat->rx_queues_cfg[queue].prio;
3060 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3065 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3066 * @priv: driver private structure
3067 * Description: It is used for configuring the TX Queue Priority
3069 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3071 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3075 for (queue = 0; queue < tx_queues_count; queue++) {
3076 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3079 prio = priv->plat->tx_queues_cfg[queue].prio;
3080 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3085 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3086 * @priv: driver private structure
3087 * Description: It is used for configuring the RX queue routing
3089 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3091 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3095 for (queue = 0; queue < rx_queues_count; queue++) {
3096 /* no specific packet type routing specified for the queue */
3097 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3100 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3101 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3105 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3107 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3108 priv->rss.enable = false;
3112 if (priv->dev->features & NETIF_F_RXHASH)
3113 priv->rss.enable = true;
3115 priv->rss.enable = false;
3117 stmmac_rss_configure(priv, priv->hw, &priv->rss,
3118 priv->plat->rx_queues_to_use);
3122 * stmmac_mtl_configuration - Configure MTL
3123 * @priv: driver private structure
3124 * Description: It is used for configurring MTL
3126 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3128 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3129 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3131 if (tx_queues_count > 1)
3132 stmmac_set_tx_queue_weight(priv);
3134 /* Configure MTL RX algorithms */
3135 if (rx_queues_count > 1)
3136 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3137 priv->plat->rx_sched_algorithm);
3139 /* Configure MTL TX algorithms */
3140 if (tx_queues_count > 1)
3141 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3142 priv->plat->tx_sched_algorithm);
3144 /* Configure CBS in AVB TX queues */
3145 if (tx_queues_count > 1)
3146 stmmac_configure_cbs(priv);
3148 /* Map RX MTL to DMA channels */
3149 stmmac_rx_queue_dma_chan_map(priv);
3151 /* Enable MAC RX Queues */
3152 stmmac_mac_enable_rx_queues(priv);
3154 /* Set RX priorities */
3155 if (rx_queues_count > 1)
3156 stmmac_mac_config_rx_queues_prio(priv);
3158 /* Set TX priorities */
3159 if (tx_queues_count > 1)
3160 stmmac_mac_config_tx_queues_prio(priv);
3162 /* Set RX routing */
3163 if (rx_queues_count > 1)
3164 stmmac_mac_config_rx_queues_routing(priv);
3166 /* Receive Side Scaling */
3167 if (rx_queues_count > 1)
3168 stmmac_mac_config_rss(priv);
3171 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3173 if (priv->dma_cap.asp) {
3174 netdev_info(priv->dev, "Enabling Safety Features\n");
3175 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3176 priv->plat->safety_feat_cfg);
3178 netdev_info(priv->dev, "No Safety Features support found\n");
3182 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3186 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3187 clear_bit(__FPE_REMOVING, &priv->fpe_task_state);
3189 name = priv->wq_name;
3190 sprintf(name, "%s-fpe", priv->dev->name);
3192 priv->fpe_wq = create_singlethread_workqueue(name);
3193 if (!priv->fpe_wq) {
3194 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3198 netdev_info(priv->dev, "FPE workqueue start");
3204 * stmmac_hw_setup - setup mac in a usable state.
3205 * @dev : pointer to the device structure.
3206 * @ptp_register: register PTP if set
3208 * this is the main function to setup the HW in a usable state because the
3209 * dma engine is reset, the core registers are configured (e.g. AXI,
3210 * Checksum features, timers). The DMA is ready to start receiving and
3213 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3216 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register)
3218 struct stmmac_priv *priv = netdev_priv(dev);
3219 u32 rx_cnt = priv->plat->rx_queues_to_use;
3220 u32 tx_cnt = priv->plat->tx_queues_to_use;
3225 /* DMA initialization and SW reset */
3226 ret = stmmac_init_dma_engine(priv);
3228 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3233 /* Copy the MAC addr into the HW */
3234 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3236 /* PS and related bits will be programmed according to the speed */
3237 if (priv->hw->pcs) {
3238 int speed = priv->plat->mac_port_sel_speed;
3240 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3241 (speed == SPEED_1000)) {
3242 priv->hw->ps = speed;
3244 dev_warn(priv->device, "invalid port speed\n");
3249 /* Initialize the MAC Core */
3250 stmmac_core_init(priv, priv->hw, dev);
3253 stmmac_mtl_configuration(priv);
3255 /* Initialize Safety Features */
3256 stmmac_safety_feat_configuration(priv);
3258 ret = stmmac_rx_ipc(priv, priv->hw);
3260 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3261 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3262 priv->hw->rx_csum = 0;
3265 /* Enable the MAC Rx/Tx */
3266 stmmac_mac_set(priv, priv->ioaddr, true);
3268 /* Set the HW DMA mode and the COE */
3269 stmmac_dma_operation_mode(priv);
3271 stmmac_mmc_setup(priv);
3273 ret = stmmac_init_ptp(priv);
3274 if (ret == -EOPNOTSUPP)
3275 netdev_info(priv->dev, "PTP not supported by HW\n");
3277 netdev_warn(priv->dev, "PTP init failed\n");
3278 else if (ptp_register)
3279 stmmac_ptp_register(priv);
3281 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3283 /* Convert the timer from msec to usec */
3284 if (!priv->tx_lpi_timer)
3285 priv->tx_lpi_timer = eee_timer * 1000;
3287 if (priv->use_riwt) {
3290 for (queue = 0; queue < rx_cnt; queue++) {
3291 if (!priv->rx_riwt[queue])
3292 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3294 stmmac_rx_watchdog(priv, priv->ioaddr,
3295 priv->rx_riwt[queue], queue);
3300 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3302 /* set TX and RX rings length */
3303 stmmac_set_rings_length(priv);
3307 for (chan = 0; chan < tx_cnt; chan++) {
3308 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3310 /* TSO and TBS cannot co-exist */
3311 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3314 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3318 /* Enable Split Header */
3319 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3320 for (chan = 0; chan < rx_cnt; chan++)
3321 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3324 /* VLAN Tag Insertion */
3325 if (priv->dma_cap.vlins)
3326 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3329 for (chan = 0; chan < tx_cnt; chan++) {
3330 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3331 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3333 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3336 /* Configure real RX and TX queues */
3337 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3338 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3340 /* Start the ball rolling... */
3341 stmmac_start_all_dma(priv);
3343 if (priv->dma_cap.fpesel) {
3344 stmmac_fpe_start_wq(priv);
3346 if (priv->plat->fpe_cfg->enable)
3347 stmmac_fpe_handshake(priv, true);
3353 static void stmmac_hw_teardown(struct net_device *dev)
3355 struct stmmac_priv *priv = netdev_priv(dev);
3357 clk_disable_unprepare(priv->plat->clk_ptp_ref);
3360 static void stmmac_free_irq(struct net_device *dev,
3361 enum request_irq_err irq_err, int irq_idx)
3363 struct stmmac_priv *priv = netdev_priv(dev);
3367 case REQ_IRQ_ERR_ALL:
3368 irq_idx = priv->plat->tx_queues_to_use;
3370 case REQ_IRQ_ERR_TX:
3371 for (j = irq_idx - 1; j >= 0; j--) {
3372 if (priv->tx_irq[j] > 0) {
3373 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3374 free_irq(priv->tx_irq[j], &priv->tx_queue[j]);
3377 irq_idx = priv->plat->rx_queues_to_use;
3379 case REQ_IRQ_ERR_RX:
3380 for (j = irq_idx - 1; j >= 0; j--) {
3381 if (priv->rx_irq[j] > 0) {
3382 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3383 free_irq(priv->rx_irq[j], &priv->rx_queue[j]);
3387 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3388 free_irq(priv->sfty_ue_irq, dev);
3390 case REQ_IRQ_ERR_SFTY_UE:
3391 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3392 free_irq(priv->sfty_ce_irq, dev);
3394 case REQ_IRQ_ERR_SFTY_CE:
3395 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3396 free_irq(priv->lpi_irq, dev);
3398 case REQ_IRQ_ERR_LPI:
3399 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3400 free_irq(priv->wol_irq, dev);
3402 case REQ_IRQ_ERR_WOL:
3403 free_irq(dev->irq, dev);
3405 case REQ_IRQ_ERR_MAC:
3406 case REQ_IRQ_ERR_NO:
3407 /* If MAC IRQ request error, no more IRQ to free */
3412 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3414 struct stmmac_priv *priv = netdev_priv(dev);
3415 enum request_irq_err irq_err;
3422 /* For common interrupt */
3423 int_name = priv->int_name_mac;
3424 sprintf(int_name, "%s:%s", dev->name, "mac");
3425 ret = request_irq(dev->irq, stmmac_mac_interrupt,
3427 if (unlikely(ret < 0)) {
3428 netdev_err(priv->dev,
3429 "%s: alloc mac MSI %d (error: %d)\n",
3430 __func__, dev->irq, ret);
3431 irq_err = REQ_IRQ_ERR_MAC;
3435 /* Request the Wake IRQ in case of another line
3438 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3439 int_name = priv->int_name_wol;
3440 sprintf(int_name, "%s:%s", dev->name, "wol");
3441 ret = request_irq(priv->wol_irq,
3442 stmmac_mac_interrupt,
3444 if (unlikely(ret < 0)) {
3445 netdev_err(priv->dev,
3446 "%s: alloc wol MSI %d (error: %d)\n",
3447 __func__, priv->wol_irq, ret);
3448 irq_err = REQ_IRQ_ERR_WOL;
3453 /* Request the LPI IRQ in case of another line
3456 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3457 int_name = priv->int_name_lpi;
3458 sprintf(int_name, "%s:%s", dev->name, "lpi");
3459 ret = request_irq(priv->lpi_irq,
3460 stmmac_mac_interrupt,
3462 if (unlikely(ret < 0)) {
3463 netdev_err(priv->dev,
3464 "%s: alloc lpi MSI %d (error: %d)\n",
3465 __func__, priv->lpi_irq, ret);
3466 irq_err = REQ_IRQ_ERR_LPI;
3471 /* Request the Safety Feature Correctible Error line in
3472 * case of another line is used
3474 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3475 int_name = priv->int_name_sfty_ce;
3476 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3477 ret = request_irq(priv->sfty_ce_irq,
3478 stmmac_safety_interrupt,
3480 if (unlikely(ret < 0)) {
3481 netdev_err(priv->dev,
3482 "%s: alloc sfty ce MSI %d (error: %d)\n",
3483 __func__, priv->sfty_ce_irq, ret);
3484 irq_err = REQ_IRQ_ERR_SFTY_CE;
3489 /* Request the Safety Feature Uncorrectible Error line in
3490 * case of another line is used
3492 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3493 int_name = priv->int_name_sfty_ue;
3494 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3495 ret = request_irq(priv->sfty_ue_irq,
3496 stmmac_safety_interrupt,
3498 if (unlikely(ret < 0)) {
3499 netdev_err(priv->dev,
3500 "%s: alloc sfty ue MSI %d (error: %d)\n",
3501 __func__, priv->sfty_ue_irq, ret);
3502 irq_err = REQ_IRQ_ERR_SFTY_UE;
3507 /* Request Rx MSI irq */
3508 for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3509 if (i >= MTL_MAX_RX_QUEUES)
3511 if (priv->rx_irq[i] == 0)
3514 int_name = priv->int_name_rx_irq[i];
3515 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3516 ret = request_irq(priv->rx_irq[i],
3518 0, int_name, &priv->rx_queue[i]);
3519 if (unlikely(ret < 0)) {
3520 netdev_err(priv->dev,
3521 "%s: alloc rx-%d MSI %d (error: %d)\n",
3522 __func__, i, priv->rx_irq[i], ret);
3523 irq_err = REQ_IRQ_ERR_RX;
3527 cpumask_clear(&cpu_mask);
3528 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3529 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3532 /* Request Tx MSI irq */
3533 for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3534 if (i >= MTL_MAX_TX_QUEUES)
3536 if (priv->tx_irq[i] == 0)
3539 int_name = priv->int_name_tx_irq[i];
3540 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3541 ret = request_irq(priv->tx_irq[i],
3543 0, int_name, &priv->tx_queue[i]);
3544 if (unlikely(ret < 0)) {
3545 netdev_err(priv->dev,
3546 "%s: alloc tx-%d MSI %d (error: %d)\n",
3547 __func__, i, priv->tx_irq[i], ret);
3548 irq_err = REQ_IRQ_ERR_TX;
3552 cpumask_clear(&cpu_mask);
3553 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3554 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3560 stmmac_free_irq(dev, irq_err, irq_idx);
3564 static int stmmac_request_irq_single(struct net_device *dev)
3566 struct stmmac_priv *priv = netdev_priv(dev);
3567 enum request_irq_err irq_err;
3570 ret = request_irq(dev->irq, stmmac_interrupt,
3571 IRQF_SHARED, dev->name, dev);
3572 if (unlikely(ret < 0)) {
3573 netdev_err(priv->dev,
3574 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3575 __func__, dev->irq, ret);
3576 irq_err = REQ_IRQ_ERR_MAC;
3580 /* Request the Wake IRQ in case of another line
3583 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3584 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3585 IRQF_SHARED, dev->name, dev);
3586 if (unlikely(ret < 0)) {
3587 netdev_err(priv->dev,
3588 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3589 __func__, priv->wol_irq, ret);
3590 irq_err = REQ_IRQ_ERR_WOL;
3595 /* Request the IRQ lines */
3596 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3597 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3598 IRQF_SHARED, dev->name, dev);
3599 if (unlikely(ret < 0)) {
3600 netdev_err(priv->dev,
3601 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3602 __func__, priv->lpi_irq, ret);
3603 irq_err = REQ_IRQ_ERR_LPI;
3611 stmmac_free_irq(dev, irq_err, 0);
3615 static int stmmac_request_irq(struct net_device *dev)
3617 struct stmmac_priv *priv = netdev_priv(dev);
3620 /* Request the IRQ lines */
3621 if (priv->plat->multi_msi_en)
3622 ret = stmmac_request_irq_multi_msi(dev);
3624 ret = stmmac_request_irq_single(dev);
3630 * stmmac_open - open entry point of the driver
3631 * @dev : pointer to the device structure.
3633 * This function is the open entry point of the driver.
3635 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3638 static int stmmac_open(struct net_device *dev)
3640 struct stmmac_priv *priv = netdev_priv(dev);
3641 int mode = priv->plat->phy_interface;
3646 ret = pm_runtime_get_sync(priv->device);
3648 pm_runtime_put_noidle(priv->device);
3652 if (priv->hw->pcs != STMMAC_PCS_TBI &&
3653 priv->hw->pcs != STMMAC_PCS_RTBI &&
3655 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3656 ret = stmmac_init_phy(dev);
3658 netdev_err(priv->dev,
3659 "%s: Cannot attach to PHY (error: %d)\n",
3661 goto init_phy_error;
3665 /* Extra statistics */
3666 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3667 priv->xstats.threshold = tc;
3669 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
3673 if (bfsize < BUF_SIZE_16KiB)
3674 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
3676 priv->dma_buf_sz = bfsize;
3679 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3681 if (!priv->dma_tx_size)
3682 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3683 if (!priv->dma_rx_size)
3684 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3686 /* Earlier check for TBS */
3687 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3688 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3689 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3691 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3692 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3695 ret = alloc_dma_desc_resources(priv);
3697 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3699 goto dma_desc_error;
3702 ret = init_dma_desc_rings(dev, GFP_KERNEL);
3704 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3709 ret = stmmac_hw_setup(dev, true);
3711 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3715 stmmac_init_coalesce(priv);
3717 phylink_start(priv->phylink);
3718 /* We may have called phylink_speed_down before */
3719 phylink_speed_up(priv->phylink);
3721 ret = stmmac_request_irq(dev);
3725 stmmac_enable_all_queues(priv);
3726 netif_tx_start_all_queues(priv->dev);
3727 stmmac_enable_all_dma_irq(priv);
3732 phylink_stop(priv->phylink);
3734 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3735 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3737 stmmac_hw_teardown(dev);
3739 free_dma_desc_resources(priv);
3741 phylink_disconnect_phy(priv->phylink);
3743 pm_runtime_put(priv->device);
3747 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3749 set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3752 destroy_workqueue(priv->fpe_wq);
3754 netdev_info(priv->dev, "FPE workqueue stop");
3758 * stmmac_release - close entry point of the driver
3759 * @dev : device pointer.
3761 * This is the stop entry point of the driver.
3763 static int stmmac_release(struct net_device *dev)
3765 struct stmmac_priv *priv = netdev_priv(dev);
3768 netif_tx_disable(dev);
3770 if (device_may_wakeup(priv->device))
3771 phylink_speed_down(priv->phylink, false);
3772 /* Stop and disconnect the PHY */
3773 phylink_stop(priv->phylink);
3774 phylink_disconnect_phy(priv->phylink);
3776 stmmac_disable_all_queues(priv);
3778 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3779 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3781 /* Free the IRQ lines */
3782 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3784 if (priv->eee_enabled) {
3785 priv->tx_path_in_lpi_mode = false;
3786 del_timer_sync(&priv->eee_ctrl_timer);
3789 /* Stop TX/RX DMA and clear the descriptors */
3790 stmmac_stop_all_dma(priv);
3792 /* Release and free the Rx/Tx resources */
3793 free_dma_desc_resources(priv);
3795 /* Disable the MAC Rx/Tx */
3796 stmmac_mac_set(priv, priv->ioaddr, false);
3798 netif_carrier_off(dev);
3800 stmmac_release_ptp(priv);
3802 pm_runtime_put(priv->device);
3804 if (priv->dma_cap.fpesel)
3805 stmmac_fpe_stop_wq(priv);
3810 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3811 struct stmmac_tx_queue *tx_q)
3813 u16 tag = 0x0, inner_tag = 0x0;
3814 u32 inner_type = 0x0;
3817 if (!priv->dma_cap.vlins)
3819 if (!skb_vlan_tag_present(skb))
3821 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3822 inner_tag = skb_vlan_tag_get(skb);
3823 inner_type = STMMAC_VLAN_INSERT;
3826 tag = skb_vlan_tag_get(skb);
3828 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3829 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3831 p = &tx_q->dma_tx[tx_q->cur_tx];
3833 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3836 stmmac_set_tx_owner(priv, p);
3837 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
3842 * stmmac_tso_allocator - close entry point of the driver
3843 * @priv: driver private structure
3844 * @des: buffer start address
3845 * @total_len: total length to fill in descriptors
3846 * @last_segment: condition for the last descriptor
3847 * @queue: TX queue index
3849 * This function fills descriptor and request new descriptors according to
3850 * buffer length to fill
3852 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
3853 int total_len, bool last_segment, u32 queue)
3855 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3856 struct dma_desc *desc;
3860 tmp_len = total_len;
3862 while (tmp_len > 0) {
3863 dma_addr_t curr_addr;
3865 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3867 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3869 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3870 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3872 desc = &tx_q->dma_tx[tx_q->cur_tx];
3874 curr_addr = des + (total_len - tmp_len);
3875 if (priv->dma_cap.addr64 <= 32)
3876 desc->des0 = cpu_to_le32(curr_addr);
3878 stmmac_set_desc_addr(priv, desc, curr_addr);
3880 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
3881 TSO_MAX_BUFF_SIZE : tmp_len;
3883 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3885 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3888 tmp_len -= TSO_MAX_BUFF_SIZE;
3892 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
3894 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3897 if (likely(priv->extend_desc))
3898 desc_size = sizeof(struct dma_extended_desc);
3899 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3900 desc_size = sizeof(struct dma_edesc);
3902 desc_size = sizeof(struct dma_desc);
3904 /* The own bit must be the latest setting done when prepare the
3905 * descriptor and then barrier is needed to make sure that
3906 * all is coherent before granting the DMA engine.
3910 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3911 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3915 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3916 * @skb : the socket buffer
3917 * @dev : device pointer
3918 * Description: this is the transmit function that is called on TSO frames
3919 * (support available on GMAC4 and newer chips).
3920 * Diagram below show the ring programming in case of TSO frames:
3924 * | DES0 |---> buffer1 = L2/L3/L4 header
3925 * | DES1 |---> TCP Payload (can continue on next descr...)
3926 * | DES2 |---> buffer 1 and 2 len
3927 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3933 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
3935 * | DES2 | --> buffer 1 and 2 len
3939 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3941 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3943 struct dma_desc *desc, *first, *mss_desc = NULL;
3944 struct stmmac_priv *priv = netdev_priv(dev);
3945 int nfrags = skb_shinfo(skb)->nr_frags;
3946 u32 queue = skb_get_queue_mapping(skb);
3947 unsigned int first_entry, tx_packets;
3948 int tmp_pay_len = 0, first_tx;
3949 struct stmmac_tx_queue *tx_q;
3950 bool has_vlan, set_ic;
3951 u8 proto_hdr_len, hdr;
3956 tx_q = &priv->tx_queue[queue];
3957 first_tx = tx_q->cur_tx;
3959 /* Compute header lengths */
3960 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3961 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3962 hdr = sizeof(struct udphdr);
3964 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3965 hdr = tcp_hdrlen(skb);
3968 /* Desc availability based on threshold should be enough safe */
3969 if (unlikely(stmmac_tx_avail(priv, queue) <
3970 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
3971 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3972 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3974 /* This is a hard error, log it. */
3975 netdev_err(priv->dev,
3976 "%s: Tx Ring full when queue awake\n",
3979 return NETDEV_TX_BUSY;
3982 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
3984 mss = skb_shinfo(skb)->gso_size;
3986 /* set new MSS value if needed */
3987 if (mss != tx_q->mss) {
3988 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3989 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3991 mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
3993 stmmac_set_mss(priv, mss_desc, mss);
3995 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3997 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4000 if (netif_msg_tx_queued(priv)) {
4001 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
4002 __func__, hdr, proto_hdr_len, pay_len, mss);
4003 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
4007 /* Check if VLAN can be inserted by HW */
4008 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4010 first_entry = tx_q->cur_tx;
4011 WARN_ON(tx_q->tx_skbuff[first_entry]);
4013 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4014 desc = &tx_q->dma_entx[first_entry].basic;
4016 desc = &tx_q->dma_tx[first_entry];
4020 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4022 /* first descriptor: fill Headers on Buf1 */
4023 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4025 if (dma_mapping_error(priv->device, des))
4028 tx_q->tx_skbuff_dma[first_entry].buf = des;
4029 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4030 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4031 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4033 if (priv->dma_cap.addr64 <= 32) {
4034 first->des0 = cpu_to_le32(des);
4036 /* Fill start of payload in buff2 of first descriptor */
4038 first->des1 = cpu_to_le32(des + proto_hdr_len);
4040 /* If needed take extra descriptors to fill the remaining payload */
4041 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4043 stmmac_set_desc_addr(priv, first, des);
4044 tmp_pay_len = pay_len;
4045 des += proto_hdr_len;
4049 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4051 /* Prepare fragments */
4052 for (i = 0; i < nfrags; i++) {
4053 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4055 des = skb_frag_dma_map(priv->device, frag, 0,
4056 skb_frag_size(frag),
4058 if (dma_mapping_error(priv->device, des))
4061 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4062 (i == nfrags - 1), queue);
4064 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4065 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4066 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4067 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4070 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4072 /* Only the last descriptor gets to point to the skb. */
4073 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4074 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4076 /* Manage tx mitigation */
4077 tx_packets = (tx_q->cur_tx + 1) - first_tx;
4078 tx_q->tx_count_frames += tx_packets;
4080 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4082 else if (!priv->tx_coal_frames[queue])
4084 else if (tx_packets > priv->tx_coal_frames[queue])
4086 else if ((tx_q->tx_count_frames %
4087 priv->tx_coal_frames[queue]) < tx_packets)
4093 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4094 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4096 desc = &tx_q->dma_tx[tx_q->cur_tx];
4098 tx_q->tx_count_frames = 0;
4099 stmmac_set_tx_ic(priv, desc);
4100 priv->xstats.tx_set_ic_bit++;
4103 /* We've used all descriptors we need for this skb, however,
4104 * advance cur_tx so that it references a fresh descriptor.
4105 * ndo_start_xmit will fill this descriptor the next time it's
4106 * called and stmmac_tx_clean may clean up to this descriptor.
4108 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
4110 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4111 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4113 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4116 dev->stats.tx_bytes += skb->len;
4117 priv->xstats.tx_tso_frames++;
4118 priv->xstats.tx_tso_nfrags += nfrags;
4120 if (priv->sarc_type)
4121 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4123 skb_tx_timestamp(skb);
4125 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4126 priv->hwts_tx_en)) {
4127 /* declare that device is doing timestamping */
4128 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4129 stmmac_enable_tx_timestamp(priv, first);
4132 /* Complete the first descriptor before granting the DMA */
4133 stmmac_prepare_tso_tx_desc(priv, first, 1,
4136 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4137 hdr / 4, (skb->len - proto_hdr_len));
4139 /* If context desc is used to change MSS */
4141 /* Make sure that first descriptor has been completely
4142 * written, including its own bit. This is because MSS is
4143 * actually before first descriptor, so we need to make
4144 * sure that MSS's own bit is the last thing written.
4147 stmmac_set_tx_owner(priv, mss_desc);
4150 if (netif_msg_pktdata(priv)) {
4151 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4152 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4153 tx_q->cur_tx, first, nfrags);
4154 pr_info(">>> frame to be transmitted: ");
4155 print_pkt(skb->data, skb_headlen(skb));
4158 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4160 stmmac_flush_tx_descriptors(priv, queue);
4161 stmmac_tx_timer_arm(priv, queue);
4163 return NETDEV_TX_OK;
4166 dev_err(priv->device, "Tx dma map failed\n");
4168 priv->dev->stats.tx_dropped++;
4169 return NETDEV_TX_OK;
4173 * stmmac_xmit - Tx entry point of the driver
4174 * @skb : the socket buffer
4175 * @dev : device pointer
4176 * Description : this is the tx entry point of the driver.
4177 * It programs the chain or the ring and supports oversized frames
4180 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4182 unsigned int first_entry, tx_packets, enh_desc;
4183 struct stmmac_priv *priv = netdev_priv(dev);
4184 unsigned int nopaged_len = skb_headlen(skb);
4185 int i, csum_insertion = 0, is_jumbo = 0;
4186 u32 queue = skb_get_queue_mapping(skb);
4187 int nfrags = skb_shinfo(skb)->nr_frags;
4188 int gso = skb_shinfo(skb)->gso_type;
4189 struct dma_edesc *tbs_desc = NULL;
4190 struct dma_desc *desc, *first;
4191 struct stmmac_tx_queue *tx_q;
4192 bool has_vlan, set_ic;
4193 int entry, first_tx;
4196 tx_q = &priv->tx_queue[queue];
4197 first_tx = tx_q->cur_tx;
4199 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4200 stmmac_disable_eee_mode(priv);
4202 /* Manage oversized TCP frames for GMAC4 device */
4203 if (skb_is_gso(skb) && priv->tso) {
4204 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4205 return stmmac_tso_xmit(skb, dev);
4206 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4207 return stmmac_tso_xmit(skb, dev);
4210 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4211 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4212 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4214 /* This is a hard error, log it. */
4215 netdev_err(priv->dev,
4216 "%s: Tx Ring full when queue awake\n",
4219 return NETDEV_TX_BUSY;
4222 /* Check if VLAN can be inserted by HW */
4223 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4225 entry = tx_q->cur_tx;
4226 first_entry = entry;
4227 WARN_ON(tx_q->tx_skbuff[first_entry]);
4229 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4231 if (likely(priv->extend_desc))
4232 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4233 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4234 desc = &tx_q->dma_entx[entry].basic;
4236 desc = tx_q->dma_tx + entry;
4241 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4243 enh_desc = priv->plat->enh_desc;
4244 /* To program the descriptors according to the size of the frame */
4246 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4248 if (unlikely(is_jumbo)) {
4249 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4250 if (unlikely(entry < 0) && (entry != -EINVAL))
4254 for (i = 0; i < nfrags; i++) {
4255 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4256 int len = skb_frag_size(frag);
4257 bool last_segment = (i == (nfrags - 1));
4259 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4260 WARN_ON(tx_q->tx_skbuff[entry]);
4262 if (likely(priv->extend_desc))
4263 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4264 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4265 desc = &tx_q->dma_entx[entry].basic;
4267 desc = tx_q->dma_tx + entry;
4269 des = skb_frag_dma_map(priv->device, frag, 0, len,
4271 if (dma_mapping_error(priv->device, des))
4272 goto dma_map_err; /* should reuse desc w/o issues */
4274 tx_q->tx_skbuff_dma[entry].buf = des;
4276 stmmac_set_desc_addr(priv, desc, des);
4278 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4279 tx_q->tx_skbuff_dma[entry].len = len;
4280 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4281 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4283 /* Prepare the descriptor and set the own bit too */
4284 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4285 priv->mode, 1, last_segment, skb->len);
4288 /* Only the last descriptor gets to point to the skb. */
4289 tx_q->tx_skbuff[entry] = skb;
4290 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4292 /* According to the coalesce parameter the IC bit for the latest
4293 * segment is reset and the timer re-started to clean the tx status.
4294 * This approach takes care about the fragments: desc is the first
4295 * element in case of no SG.
4297 tx_packets = (entry + 1) - first_tx;
4298 tx_q->tx_count_frames += tx_packets;
4300 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4302 else if (!priv->tx_coal_frames[queue])
4304 else if (tx_packets > priv->tx_coal_frames[queue])
4306 else if ((tx_q->tx_count_frames %
4307 priv->tx_coal_frames[queue]) < tx_packets)
4313 if (likely(priv->extend_desc))
4314 desc = &tx_q->dma_etx[entry].basic;
4315 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4316 desc = &tx_q->dma_entx[entry].basic;
4318 desc = &tx_q->dma_tx[entry];
4320 tx_q->tx_count_frames = 0;
4321 stmmac_set_tx_ic(priv, desc);
4322 priv->xstats.tx_set_ic_bit++;
4325 /* We've used all descriptors we need for this skb, however,
4326 * advance cur_tx so that it references a fresh descriptor.
4327 * ndo_start_xmit will fill this descriptor the next time it's
4328 * called and stmmac_tx_clean may clean up to this descriptor.
4330 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4331 tx_q->cur_tx = entry;
4333 if (netif_msg_pktdata(priv)) {
4334 netdev_dbg(priv->dev,
4335 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4336 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4337 entry, first, nfrags);
4339 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4340 print_pkt(skb->data, skb->len);
4343 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4344 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4346 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4349 dev->stats.tx_bytes += skb->len;
4351 if (priv->sarc_type)
4352 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4354 skb_tx_timestamp(skb);
4356 /* Ready to fill the first descriptor and set the OWN bit w/o any
4357 * problems because all the descriptors are actually ready to be
4358 * passed to the DMA engine.
4360 if (likely(!is_jumbo)) {
4361 bool last_segment = (nfrags == 0);
4363 des = dma_map_single(priv->device, skb->data,
4364 nopaged_len, DMA_TO_DEVICE);
4365 if (dma_mapping_error(priv->device, des))
4368 tx_q->tx_skbuff_dma[first_entry].buf = des;
4369 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4370 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4372 stmmac_set_desc_addr(priv, first, des);
4374 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4375 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4377 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4378 priv->hwts_tx_en)) {
4379 /* declare that device is doing timestamping */
4380 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4381 stmmac_enable_tx_timestamp(priv, first);
4384 /* Prepare the first descriptor setting the OWN bit too */
4385 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4386 csum_insertion, priv->mode, 0, last_segment,
4390 if (tx_q->tbs & STMMAC_TBS_EN) {
4391 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4393 tbs_desc = &tx_q->dma_entx[first_entry];
4394 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4397 stmmac_set_tx_owner(priv, first);
4399 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4401 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4403 stmmac_flush_tx_descriptors(priv, queue);
4404 stmmac_tx_timer_arm(priv, queue);
4406 return NETDEV_TX_OK;
4409 netdev_err(priv->dev, "Tx DMA map failed\n");
4411 priv->dev->stats.tx_dropped++;
4412 return NETDEV_TX_OK;
4415 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4417 struct vlan_ethhdr *veth;
4421 veth = (struct vlan_ethhdr *)skb->data;
4422 vlan_proto = veth->h_vlan_proto;
4424 if ((vlan_proto == htons(ETH_P_8021Q) &&
4425 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4426 (vlan_proto == htons(ETH_P_8021AD) &&
4427 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4428 /* pop the vlan tag */
4429 vlanid = ntohs(veth->h_vlan_TCI);
4430 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4431 skb_pull(skb, VLAN_HLEN);
4432 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4437 * stmmac_rx_refill - refill used skb preallocated buffers
4438 * @priv: driver private structure
4439 * @queue: RX queue index
4440 * Description : this is to reallocate the skb for the reception process
4441 * that is based on zero-copy.
4443 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4445 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4446 int dirty = stmmac_rx_dirty(priv, queue);
4447 unsigned int entry = rx_q->dirty_rx;
4448 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
4450 if (priv->dma_cap.addr64 <= 32)
4453 while (dirty-- > 0) {
4454 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4458 if (priv->extend_desc)
4459 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4461 p = rx_q->dma_rx + entry;
4464 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4469 if (priv->sph && !buf->sec_page) {
4470 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4474 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4477 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4479 stmmac_set_desc_addr(priv, p, buf->addr);
4481 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4483 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4484 stmmac_refill_desc3(priv, rx_q, p);
4486 rx_q->rx_count_frames++;
4487 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4488 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4489 rx_q->rx_count_frames = 0;
4491 use_rx_wd = !priv->rx_coal_frames[queue];
4492 use_rx_wd |= rx_q->rx_count_frames > 0;
4493 if (!priv->use_riwt)
4497 stmmac_set_rx_owner(priv, p, use_rx_wd);
4499 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4501 rx_q->dirty_rx = entry;
4502 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4503 (rx_q->dirty_rx * sizeof(struct dma_desc));
4504 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4507 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4509 int status, unsigned int len)
4511 unsigned int plen = 0, hlen = 0;
4512 int coe = priv->hw->rx_csum;
4514 /* Not first descriptor, buffer is always zero */
4515 if (priv->sph && len)
4518 /* First descriptor, get split header length */
4519 stmmac_get_rx_header_len(priv, p, &hlen);
4520 if (priv->sph && hlen) {
4521 priv->xstats.rx_split_hdr_pkt_n++;
4525 /* First descriptor, not last descriptor and not split header */
4526 if (status & rx_not_ls)
4527 return priv->dma_buf_sz;
4529 plen = stmmac_get_rx_frame_len(priv, p, coe);
4531 /* First descriptor and last descriptor and not split header */
4532 return min_t(unsigned int, priv->dma_buf_sz, plen);
4535 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4537 int status, unsigned int len)
4539 int coe = priv->hw->rx_csum;
4540 unsigned int plen = 0;
4542 /* Not split header, buffer is not available */
4546 /* Not last descriptor */
4547 if (status & rx_not_ls)
4548 return priv->dma_buf_sz;
4550 plen = stmmac_get_rx_frame_len(priv, p, coe);
4552 /* Last descriptor */
4556 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4557 struct xdp_frame *xdpf, bool dma_map)
4559 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4560 unsigned int entry = tx_q->cur_tx;
4561 struct dma_desc *tx_desc;
4562 dma_addr_t dma_addr;
4565 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4566 return STMMAC_XDP_CONSUMED;
4568 if (likely(priv->extend_desc))
4569 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4570 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4571 tx_desc = &tx_q->dma_entx[entry].basic;
4573 tx_desc = tx_q->dma_tx + entry;
4576 dma_addr = dma_map_single(priv->device, xdpf->data,
4577 xdpf->len, DMA_TO_DEVICE);
4578 if (dma_mapping_error(priv->device, dma_addr))
4579 return STMMAC_XDP_CONSUMED;
4581 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4583 struct page *page = virt_to_page(xdpf->data);
4585 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4587 dma_sync_single_for_device(priv->device, dma_addr,
4588 xdpf->len, DMA_BIDIRECTIONAL);
4590 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4593 tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4594 tx_q->tx_skbuff_dma[entry].map_as_page = false;
4595 tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4596 tx_q->tx_skbuff_dma[entry].last_segment = true;
4597 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4599 tx_q->xdpf[entry] = xdpf;
4601 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4603 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4604 true, priv->mode, true, true,
4607 tx_q->tx_count_frames++;
4609 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4615 tx_q->tx_count_frames = 0;
4616 stmmac_set_tx_ic(priv, tx_desc);
4617 priv->xstats.tx_set_ic_bit++;
4620 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4622 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4623 tx_q->cur_tx = entry;
4625 return STMMAC_XDP_TX;
4628 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4633 if (unlikely(index < 0))
4636 while (index >= priv->plat->tx_queues_to_use)
4637 index -= priv->plat->tx_queues_to_use;
4642 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4643 struct xdp_buff *xdp)
4645 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4646 int cpu = smp_processor_id();
4647 struct netdev_queue *nq;
4651 if (unlikely(!xdpf))
4652 return STMMAC_XDP_CONSUMED;
4654 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4655 nq = netdev_get_tx_queue(priv->dev, queue);
4657 __netif_tx_lock(nq, cpu);
4658 /* Avoids TX time-out as we are sharing with slow path */
4659 txq_trans_cond_update(nq);
4661 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4662 if (res == STMMAC_XDP_TX)
4663 stmmac_flush_tx_descriptors(priv, queue);
4665 __netif_tx_unlock(nq);
4670 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4671 struct bpf_prog *prog,
4672 struct xdp_buff *xdp)
4677 act = bpf_prog_run_xdp(prog, xdp);
4680 res = STMMAC_XDP_PASS;
4683 res = stmmac_xdp_xmit_back(priv, xdp);
4686 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4687 res = STMMAC_XDP_CONSUMED;
4689 res = STMMAC_XDP_REDIRECT;
4692 bpf_warn_invalid_xdp_action(priv->dev, prog, act);
4695 trace_xdp_exception(priv->dev, prog, act);
4698 res = STMMAC_XDP_CONSUMED;
4705 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4706 struct xdp_buff *xdp)
4708 struct bpf_prog *prog;
4711 prog = READ_ONCE(priv->xdp_prog);
4713 res = STMMAC_XDP_PASS;
4717 res = __stmmac_xdp_run_prog(priv, prog, xdp);
4719 return ERR_PTR(-res);
4722 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4725 int cpu = smp_processor_id();
4728 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4730 if (xdp_status & STMMAC_XDP_TX)
4731 stmmac_tx_timer_arm(priv, queue);
4733 if (xdp_status & STMMAC_XDP_REDIRECT)
4737 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4738 struct xdp_buff *xdp)
4740 unsigned int metasize = xdp->data - xdp->data_meta;
4741 unsigned int datasize = xdp->data_end - xdp->data;
4742 struct sk_buff *skb;
4744 skb = __napi_alloc_skb(&ch->rxtx_napi,
4745 xdp->data_end - xdp->data_hard_start,
4746 GFP_ATOMIC | __GFP_NOWARN);
4750 skb_reserve(skb, xdp->data - xdp->data_hard_start);
4751 memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4753 skb_metadata_set(skb, metasize);
4758 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4759 struct dma_desc *p, struct dma_desc *np,
4760 struct xdp_buff *xdp)
4762 struct stmmac_channel *ch = &priv->channel[queue];
4763 unsigned int len = xdp->data_end - xdp->data;
4764 enum pkt_hash_types hash_type;
4765 int coe = priv->hw->rx_csum;
4766 struct sk_buff *skb;
4769 skb = stmmac_construct_skb_zc(ch, xdp);
4771 priv->dev->stats.rx_dropped++;
4775 stmmac_get_rx_hwtstamp(priv, p, np, skb);
4776 stmmac_rx_vlan(priv->dev, skb);
4777 skb->protocol = eth_type_trans(skb, priv->dev);
4780 skb_checksum_none_assert(skb);
4782 skb->ip_summed = CHECKSUM_UNNECESSARY;
4784 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4785 skb_set_hash(skb, hash, hash_type);
4787 skb_record_rx_queue(skb, queue);
4788 napi_gro_receive(&ch->rxtx_napi, skb);
4790 priv->dev->stats.rx_packets++;
4791 priv->dev->stats.rx_bytes += len;
4794 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4796 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4797 unsigned int entry = rx_q->dirty_rx;
4798 struct dma_desc *rx_desc = NULL;
4801 budget = min(budget, stmmac_rx_dirty(priv, queue));
4803 while (budget-- > 0 && entry != rx_q->cur_rx) {
4804 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4805 dma_addr_t dma_addr;
4809 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4816 if (priv->extend_desc)
4817 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4819 rx_desc = rx_q->dma_rx + entry;
4821 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4822 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4823 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4824 stmmac_refill_desc3(priv, rx_q, rx_desc);
4826 rx_q->rx_count_frames++;
4827 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4828 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4829 rx_q->rx_count_frames = 0;
4831 use_rx_wd = !priv->rx_coal_frames[queue];
4832 use_rx_wd |= rx_q->rx_count_frames > 0;
4833 if (!priv->use_riwt)
4837 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4839 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4843 rx_q->dirty_rx = entry;
4844 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4845 (rx_q->dirty_rx * sizeof(struct dma_desc));
4846 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4852 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
4854 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4855 unsigned int count = 0, error = 0, len = 0;
4856 int dirty = stmmac_rx_dirty(priv, queue);
4857 unsigned int next_entry = rx_q->cur_rx;
4858 unsigned int desc_size;
4859 struct bpf_prog *prog;
4860 bool failure = false;
4864 if (netif_msg_rx_status(priv)) {
4867 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
4868 if (priv->extend_desc) {
4869 rx_head = (void *)rx_q->dma_erx;
4870 desc_size = sizeof(struct dma_extended_desc);
4872 rx_head = (void *)rx_q->dma_rx;
4873 desc_size = sizeof(struct dma_desc);
4876 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
4877 rx_q->dma_rx_phy, desc_size);
4879 while (count < limit) {
4880 struct stmmac_rx_buffer *buf;
4881 unsigned int buf1_len = 0;
4882 struct dma_desc *np, *p;
4886 if (!count && rx_q->state_saved) {
4887 error = rx_q->state.error;
4888 len = rx_q->state.len;
4890 rx_q->state_saved = false;
4901 buf = &rx_q->buf_pool[entry];
4903 if (dirty >= STMMAC_RX_FILL_BATCH) {
4904 failure = failure ||
4905 !stmmac_rx_refill_zc(priv, queue, dirty);
4909 if (priv->extend_desc)
4910 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4912 p = rx_q->dma_rx + entry;
4914 /* read the status of the incoming frame */
4915 status = stmmac_rx_status(priv, &priv->dev->stats,
4917 /* check if managed by the DMA otherwise go ahead */
4918 if (unlikely(status & dma_own))
4921 /* Prefetch the next RX descriptor */
4922 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
4924 next_entry = rx_q->cur_rx;
4926 if (priv->extend_desc)
4927 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
4929 np = rx_q->dma_rx + next_entry;
4933 /* Ensure a valid XSK buffer before proceed */
4937 if (priv->extend_desc)
4938 stmmac_rx_extended_status(priv, &priv->dev->stats,
4940 rx_q->dma_erx + entry);
4941 if (unlikely(status == discard_frame)) {
4942 xsk_buff_free(buf->xdp);
4946 if (!priv->hwts_rx_en)
4947 priv->dev->stats.rx_errors++;
4950 if (unlikely(error && (status & rx_not_ls)))
4952 if (unlikely(error)) {
4957 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
4958 if (likely(status & rx_not_ls)) {
4959 xsk_buff_free(buf->xdp);
4966 /* XDP ZC Frame only support primary buffers for now */
4967 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
4970 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
4971 * Type frames (LLC/LLC-SNAP)
4973 * llc_snap is never checked in GMAC >= 4, so this ACS
4974 * feature is always disabled and packets need to be
4975 * stripped manually.
4977 if (likely(!(status & rx_not_ls)) &&
4978 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
4979 unlikely(status != llc_snap))) {
4980 buf1_len -= ETH_FCS_LEN;
4984 /* RX buffer is good and fit into a XSK pool buffer */
4985 buf->xdp->data_end = buf->xdp->data + buf1_len;
4986 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
4988 prog = READ_ONCE(priv->xdp_prog);
4989 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
4992 case STMMAC_XDP_PASS:
4993 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
4994 xsk_buff_free(buf->xdp);
4996 case STMMAC_XDP_CONSUMED:
4997 xsk_buff_free(buf->xdp);
4998 priv->dev->stats.rx_dropped++;
5001 case STMMAC_XDP_REDIRECT:
5011 if (status & rx_not_ls) {
5012 rx_q->state_saved = true;
5013 rx_q->state.error = error;
5014 rx_q->state.len = len;
5017 stmmac_finalize_xdp_rx(priv, xdp_status);
5019 priv->xstats.rx_pkt_n += count;
5020 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5022 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5023 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5024 xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5026 xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5031 return failure ? limit : (int)count;
5035 * stmmac_rx - manage the receive process
5036 * @priv: driver private structure
5037 * @limit: napi bugget
5038 * @queue: RX queue index.
5039 * Description : this the function called by the napi poll method.
5040 * It gets all the frames inside the ring.
5042 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5044 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5045 struct stmmac_channel *ch = &priv->channel[queue];
5046 unsigned int count = 0, error = 0, len = 0;
5047 int status = 0, coe = priv->hw->rx_csum;
5048 unsigned int next_entry = rx_q->cur_rx;
5049 enum dma_data_direction dma_dir;
5050 unsigned int desc_size;
5051 struct sk_buff *skb = NULL;
5052 struct xdp_buff xdp;
5056 dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5057 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5059 if (netif_msg_rx_status(priv)) {
5062 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5063 if (priv->extend_desc) {
5064 rx_head = (void *)rx_q->dma_erx;
5065 desc_size = sizeof(struct dma_extended_desc);
5067 rx_head = (void *)rx_q->dma_rx;
5068 desc_size = sizeof(struct dma_desc);
5071 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
5072 rx_q->dma_rx_phy, desc_size);
5074 while (count < limit) {
5075 unsigned int buf1_len = 0, buf2_len = 0;
5076 enum pkt_hash_types hash_type;
5077 struct stmmac_rx_buffer *buf;
5078 struct dma_desc *np, *p;
5082 if (!count && rx_q->state_saved) {
5083 skb = rx_q->state.skb;
5084 error = rx_q->state.error;
5085 len = rx_q->state.len;
5087 rx_q->state_saved = false;
5100 buf = &rx_q->buf_pool[entry];
5102 if (priv->extend_desc)
5103 p = (struct dma_desc *)(rx_q->dma_erx + entry);
5105 p = rx_q->dma_rx + entry;
5107 /* read the status of the incoming frame */
5108 status = stmmac_rx_status(priv, &priv->dev->stats,
5110 /* check if managed by the DMA otherwise go ahead */
5111 if (unlikely(status & dma_own))
5114 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5116 next_entry = rx_q->cur_rx;
5118 if (priv->extend_desc)
5119 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5121 np = rx_q->dma_rx + next_entry;
5125 if (priv->extend_desc)
5126 stmmac_rx_extended_status(priv, &priv->dev->stats,
5127 &priv->xstats, rx_q->dma_erx + entry);
5128 if (unlikely(status == discard_frame)) {
5129 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5132 if (!priv->hwts_rx_en)
5133 priv->dev->stats.rx_errors++;
5136 if (unlikely(error && (status & rx_not_ls)))
5138 if (unlikely(error)) {
5145 /* Buffer is good. Go on. */
5147 prefetch(page_address(buf->page) + buf->page_offset);
5149 prefetch(page_address(buf->sec_page));
5151 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5153 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5156 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5157 * Type frames (LLC/LLC-SNAP)
5159 * llc_snap is never checked in GMAC >= 4, so this ACS
5160 * feature is always disabled and packets need to be
5161 * stripped manually.
5163 if (likely(!(status & rx_not_ls)) &&
5164 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5165 unlikely(status != llc_snap))) {
5167 buf2_len -= ETH_FCS_LEN;
5169 } else if (buf1_len) {
5170 buf1_len -= ETH_FCS_LEN;
5176 unsigned int pre_len, sync_len;
5178 dma_sync_single_for_cpu(priv->device, buf->addr,
5181 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq);
5182 xdp_prepare_buff(&xdp, page_address(buf->page),
5183 buf->page_offset, buf1_len, false);
5185 pre_len = xdp.data_end - xdp.data_hard_start -
5187 skb = stmmac_xdp_run_prog(priv, &xdp);
5188 /* Due xdp_adjust_tail: DMA sync for_device
5189 * cover max len CPU touch
5191 sync_len = xdp.data_end - xdp.data_hard_start -
5193 sync_len = max(sync_len, pre_len);
5195 /* For Not XDP_PASS verdict */
5197 unsigned int xdp_res = -PTR_ERR(skb);
5199 if (xdp_res & STMMAC_XDP_CONSUMED) {
5200 page_pool_put_page(rx_q->page_pool,
5201 virt_to_head_page(xdp.data),
5204 priv->dev->stats.rx_dropped++;
5206 /* Clear skb as it was set as
5207 * status by XDP program.
5211 if (unlikely((status & rx_not_ls)))
5216 } else if (xdp_res & (STMMAC_XDP_TX |
5217 STMMAC_XDP_REDIRECT)) {
5218 xdp_status |= xdp_res;
5228 /* XDP program may expand or reduce tail */
5229 buf1_len = xdp.data_end - xdp.data;
5231 skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5233 priv->dev->stats.rx_dropped++;
5238 /* XDP program may adjust header */
5239 skb_copy_to_linear_data(skb, xdp.data, buf1_len);
5240 skb_put(skb, buf1_len);
5242 /* Data payload copied into SKB, page ready for recycle */
5243 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5245 } else if (buf1_len) {
5246 dma_sync_single_for_cpu(priv->device, buf->addr,
5248 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5249 buf->page, buf->page_offset, buf1_len,
5252 /* Data payload appended into SKB */
5253 page_pool_release_page(rx_q->page_pool, buf->page);
5258 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5260 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5261 buf->sec_page, 0, buf2_len,
5264 /* Data payload appended into SKB */
5265 page_pool_release_page(rx_q->page_pool, buf->sec_page);
5266 buf->sec_page = NULL;
5270 if (likely(status & rx_not_ls))
5275 /* Got entire packet into SKB. Finish it. */
5277 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5278 stmmac_rx_vlan(priv->dev, skb);
5279 skb->protocol = eth_type_trans(skb, priv->dev);
5282 skb_checksum_none_assert(skb);
5284 skb->ip_summed = CHECKSUM_UNNECESSARY;
5286 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5287 skb_set_hash(skb, hash, hash_type);
5289 skb_record_rx_queue(skb, queue);
5290 napi_gro_receive(&ch->rx_napi, skb);
5293 priv->dev->stats.rx_packets++;
5294 priv->dev->stats.rx_bytes += len;
5298 if (status & rx_not_ls || skb) {
5299 rx_q->state_saved = true;
5300 rx_q->state.skb = skb;
5301 rx_q->state.error = error;
5302 rx_q->state.len = len;
5305 stmmac_finalize_xdp_rx(priv, xdp_status);
5307 stmmac_rx_refill(priv, queue);
5309 priv->xstats.rx_pkt_n += count;
5310 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5315 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5317 struct stmmac_channel *ch =
5318 container_of(napi, struct stmmac_channel, rx_napi);
5319 struct stmmac_priv *priv = ch->priv_data;
5320 u32 chan = ch->index;
5323 priv->xstats.napi_poll++;
5325 work_done = stmmac_rx(priv, budget, chan);
5326 if (work_done < budget && napi_complete_done(napi, work_done)) {
5327 unsigned long flags;
5329 spin_lock_irqsave(&ch->lock, flags);
5330 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5331 spin_unlock_irqrestore(&ch->lock, flags);
5337 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5339 struct stmmac_channel *ch =
5340 container_of(napi, struct stmmac_channel, tx_napi);
5341 struct stmmac_priv *priv = ch->priv_data;
5342 u32 chan = ch->index;
5345 priv->xstats.napi_poll++;
5347 work_done = stmmac_tx_clean(priv, budget, chan);
5348 work_done = min(work_done, budget);
5350 if (work_done < budget && napi_complete_done(napi, work_done)) {
5351 unsigned long flags;
5353 spin_lock_irqsave(&ch->lock, flags);
5354 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5355 spin_unlock_irqrestore(&ch->lock, flags);
5361 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5363 struct stmmac_channel *ch =
5364 container_of(napi, struct stmmac_channel, rxtx_napi);
5365 struct stmmac_priv *priv = ch->priv_data;
5366 int rx_done, tx_done, rxtx_done;
5367 u32 chan = ch->index;
5369 priv->xstats.napi_poll++;
5371 tx_done = stmmac_tx_clean(priv, budget, chan);
5372 tx_done = min(tx_done, budget);
5374 rx_done = stmmac_rx_zc(priv, budget, chan);
5376 rxtx_done = max(tx_done, rx_done);
5378 /* If either TX or RX work is not complete, return budget
5381 if (rxtx_done >= budget)
5384 /* all work done, exit the polling mode */
5385 if (napi_complete_done(napi, rxtx_done)) {
5386 unsigned long flags;
5388 spin_lock_irqsave(&ch->lock, flags);
5389 /* Both RX and TX work done are compelte,
5390 * so enable both RX & TX IRQs.
5392 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5393 spin_unlock_irqrestore(&ch->lock, flags);
5396 return min(rxtx_done, budget - 1);
5401 * @dev : Pointer to net device structure
5402 * @txqueue: the index of the hanging transmit queue
5403 * Description: this function is called when a packet transmission fails to
5404 * complete within a reasonable time. The driver will mark the error in the
5405 * netdev structure and arrange for the device to be reset to a sane state
5406 * in order to transmit a new packet.
5408 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5410 struct stmmac_priv *priv = netdev_priv(dev);
5412 stmmac_global_err(priv);
5416 * stmmac_set_rx_mode - entry point for multicast addressing
5417 * @dev : pointer to the device structure
5419 * This function is a driver entry point which gets called by the kernel
5420 * whenever multicast addresses must be enabled/disabled.
5424 static void stmmac_set_rx_mode(struct net_device *dev)
5426 struct stmmac_priv *priv = netdev_priv(dev);
5428 stmmac_set_filter(priv, priv->hw, dev);
5432 * stmmac_change_mtu - entry point to change MTU size for the device.
5433 * @dev : device pointer.
5434 * @new_mtu : the new MTU size for the device.
5435 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
5436 * to drive packet transmission. Ethernet has an MTU of 1500 octets
5437 * (ETH_DATA_LEN). This value can be changed with ifconfig.
5439 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5442 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5444 struct stmmac_priv *priv = netdev_priv(dev);
5445 int txfifosz = priv->plat->tx_fifo_size;
5446 const int mtu = new_mtu;
5449 txfifosz = priv->dma_cap.tx_fifo_size;
5451 txfifosz /= priv->plat->tx_queues_to_use;
5453 if (netif_running(dev)) {
5454 netdev_err(priv->dev, "must be stopped to change its MTU\n");
5458 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5459 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5463 new_mtu = STMMAC_ALIGN(new_mtu);
5465 /* If condition true, FIFO is too small or MTU too large */
5466 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5471 netdev_update_features(dev);
5476 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5477 netdev_features_t features)
5479 struct stmmac_priv *priv = netdev_priv(dev);
5481 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5482 features &= ~NETIF_F_RXCSUM;
5484 if (!priv->plat->tx_coe)
5485 features &= ~NETIF_F_CSUM_MASK;
5487 /* Some GMAC devices have a bugged Jumbo frame support that
5488 * needs to have the Tx COE disabled for oversized frames
5489 * (due to limited buffer sizes). In this case we disable
5490 * the TX csum insertion in the TDES and not use SF.
5492 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5493 features &= ~NETIF_F_CSUM_MASK;
5495 /* Disable tso if asked by ethtool */
5496 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
5497 if (features & NETIF_F_TSO)
5506 static int stmmac_set_features(struct net_device *netdev,
5507 netdev_features_t features)
5509 struct stmmac_priv *priv = netdev_priv(netdev);
5511 /* Keep the COE Type in case of csum is supporting */
5512 if (features & NETIF_F_RXCSUM)
5513 priv->hw->rx_csum = priv->plat->rx_coe;
5515 priv->hw->rx_csum = 0;
5516 /* No check needed because rx_coe has been set before and it will be
5517 * fixed in case of issue.
5519 stmmac_rx_ipc(priv, priv->hw);
5521 if (priv->sph_cap) {
5522 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5525 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5526 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5532 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5534 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5535 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5536 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5537 bool *hs_enable = &fpe_cfg->hs_enable;
5539 if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5542 /* If LP has sent verify mPacket, LP is FPE capable */
5543 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5544 if (*lp_state < FPE_STATE_CAPABLE)
5545 *lp_state = FPE_STATE_CAPABLE;
5547 /* If user has requested FPE enable, quickly response */
5549 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5553 /* If Local has sent verify mPacket, Local is FPE capable */
5554 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5555 if (*lo_state < FPE_STATE_CAPABLE)
5556 *lo_state = FPE_STATE_CAPABLE;
5559 /* If LP has sent response mPacket, LP is entering FPE ON */
5560 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5561 *lp_state = FPE_STATE_ENTERING_ON;
5563 /* If Local has sent response mPacket, Local is entering FPE ON */
5564 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5565 *lo_state = FPE_STATE_ENTERING_ON;
5567 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5568 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5570 queue_work(priv->fpe_wq, &priv->fpe_task);
5574 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5576 u32 rx_cnt = priv->plat->rx_queues_to_use;
5577 u32 tx_cnt = priv->plat->tx_queues_to_use;
5582 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5583 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5586 pm_wakeup_event(priv->device, 0);
5588 if (priv->dma_cap.estsel)
5589 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5590 &priv->xstats, tx_cnt);
5592 if (priv->dma_cap.fpesel) {
5593 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5596 stmmac_fpe_event_status(priv, status);
5599 /* To handle GMAC own interrupts */
5600 if ((priv->plat->has_gmac) || xmac) {
5601 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5603 if (unlikely(status)) {
5604 /* For LPI we need to save the tx status */
5605 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5606 priv->tx_path_in_lpi_mode = true;
5607 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5608 priv->tx_path_in_lpi_mode = false;
5611 for (queue = 0; queue < queues_count; queue++) {
5612 status = stmmac_host_mtl_irq_status(priv, priv->hw,
5616 /* PCS link status */
5617 if (priv->hw->pcs) {
5618 if (priv->xstats.pcs_link)
5619 netif_carrier_on(priv->dev);
5621 netif_carrier_off(priv->dev);
5624 stmmac_timestamp_interrupt(priv, priv);
5629 * stmmac_interrupt - main ISR
5630 * @irq: interrupt number.
5631 * @dev_id: to pass the net device pointer.
5632 * Description: this is the main driver interrupt service routine.
5634 * o DMA service routine (to manage incoming frame reception and transmission
5636 * o Core interrupts to manage: remote wake-up, management counter, LPI
5639 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5641 struct net_device *dev = (struct net_device *)dev_id;
5642 struct stmmac_priv *priv = netdev_priv(dev);
5644 /* Check if adapter is up */
5645 if (test_bit(STMMAC_DOWN, &priv->state))
5648 /* Check if a fatal error happened */
5649 if (stmmac_safety_feat_interrupt(priv))
5652 /* To handle Common interrupts */
5653 stmmac_common_interrupt(priv);
5655 /* To handle DMA interrupts */
5656 stmmac_dma_interrupt(priv);
5661 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5663 struct net_device *dev = (struct net_device *)dev_id;
5664 struct stmmac_priv *priv = netdev_priv(dev);
5666 if (unlikely(!dev)) {
5667 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5671 /* Check if adapter is up */
5672 if (test_bit(STMMAC_DOWN, &priv->state))
5675 /* To handle Common interrupts */
5676 stmmac_common_interrupt(priv);
5681 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5683 struct net_device *dev = (struct net_device *)dev_id;
5684 struct stmmac_priv *priv = netdev_priv(dev);
5686 if (unlikely(!dev)) {
5687 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5691 /* Check if adapter is up */
5692 if (test_bit(STMMAC_DOWN, &priv->state))
5695 /* Check if a fatal error happened */
5696 stmmac_safety_feat_interrupt(priv);
5701 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5703 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5704 int chan = tx_q->queue_index;
5705 struct stmmac_priv *priv;
5708 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]);
5710 if (unlikely(!data)) {
5711 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5715 /* Check if adapter is up */
5716 if (test_bit(STMMAC_DOWN, &priv->state))
5719 status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5721 if (unlikely(status & tx_hard_error_bump_tc)) {
5722 /* Try to bump up the dma threshold on this failure */
5723 stmmac_bump_dma_threshold(priv, chan);
5724 } else if (unlikely(status == tx_hard_error)) {
5725 stmmac_tx_err(priv, chan);
5731 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5733 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5734 int chan = rx_q->queue_index;
5735 struct stmmac_priv *priv;
5737 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]);
5739 if (unlikely(!data)) {
5740 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5744 /* Check if adapter is up */
5745 if (test_bit(STMMAC_DOWN, &priv->state))
5748 stmmac_napi_check(priv, chan, DMA_DIR_RX);
5753 #ifdef CONFIG_NET_POLL_CONTROLLER
5754 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5755 * to allow network I/O with interrupts disabled.
5757 static void stmmac_poll_controller(struct net_device *dev)
5759 struct stmmac_priv *priv = netdev_priv(dev);
5762 /* If adapter is down, do nothing */
5763 if (test_bit(STMMAC_DOWN, &priv->state))
5766 if (priv->plat->multi_msi_en) {
5767 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5768 stmmac_msi_intr_rx(0, &priv->rx_queue[i]);
5770 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5771 stmmac_msi_intr_tx(0, &priv->tx_queue[i]);
5773 disable_irq(dev->irq);
5774 stmmac_interrupt(dev->irq, dev);
5775 enable_irq(dev->irq);
5781 * stmmac_ioctl - Entry point for the Ioctl
5782 * @dev: Device pointer.
5783 * @rq: An IOCTL specefic structure, that can contain a pointer to
5784 * a proprietary structure used to pass information to the driver.
5785 * @cmd: IOCTL command
5787 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5789 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5791 struct stmmac_priv *priv = netdev_priv (dev);
5792 int ret = -EOPNOTSUPP;
5794 if (!netif_running(dev))
5801 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5804 ret = stmmac_hwtstamp_set(dev, rq);
5807 ret = stmmac_hwtstamp_get(dev, rq);
5816 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5819 struct stmmac_priv *priv = cb_priv;
5820 int ret = -EOPNOTSUPP;
5822 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
5825 __stmmac_disable_all_queues(priv);
5828 case TC_SETUP_CLSU32:
5829 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
5831 case TC_SETUP_CLSFLOWER:
5832 ret = stmmac_tc_setup_cls(priv, priv, type_data);
5838 stmmac_enable_all_queues(priv);
5842 static LIST_HEAD(stmmac_block_cb_list);
5844 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
5847 struct stmmac_priv *priv = netdev_priv(ndev);
5850 case TC_SETUP_BLOCK:
5851 return flow_block_cb_setup_simple(type_data,
5852 &stmmac_block_cb_list,
5853 stmmac_setup_tc_block_cb,
5855 case TC_SETUP_QDISC_CBS:
5856 return stmmac_tc_setup_cbs(priv, priv, type_data);
5857 case TC_SETUP_QDISC_TAPRIO:
5858 return stmmac_tc_setup_taprio(priv, priv, type_data);
5859 case TC_SETUP_QDISC_ETF:
5860 return stmmac_tc_setup_etf(priv, priv, type_data);
5866 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
5867 struct net_device *sb_dev)
5869 int gso = skb_shinfo(skb)->gso_type;
5871 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
5873 * There is no way to determine the number of TSO/USO
5874 * capable Queues. Let's use always the Queue 0
5875 * because if TSO/USO is supported then at least this
5876 * one will be capable.
5881 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
5884 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
5886 struct stmmac_priv *priv = netdev_priv(ndev);
5889 ret = pm_runtime_get_sync(priv->device);
5891 pm_runtime_put_noidle(priv->device);
5895 ret = eth_mac_addr(ndev, addr);
5899 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
5902 pm_runtime_put(priv->device);
5907 #ifdef CONFIG_DEBUG_FS
5908 static struct dentry *stmmac_fs_dir;
5910 static void sysfs_display_ring(void *head, int size, int extend_desc,
5911 struct seq_file *seq, dma_addr_t dma_phy_addr)
5914 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
5915 struct dma_desc *p = (struct dma_desc *)head;
5916 dma_addr_t dma_addr;
5918 for (i = 0; i < size; i++) {
5920 dma_addr = dma_phy_addr + i * sizeof(*ep);
5921 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5923 le32_to_cpu(ep->basic.des0),
5924 le32_to_cpu(ep->basic.des1),
5925 le32_to_cpu(ep->basic.des2),
5926 le32_to_cpu(ep->basic.des3));
5929 dma_addr = dma_phy_addr + i * sizeof(*p);
5930 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5932 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
5933 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
5936 seq_printf(seq, "\n");
5940 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
5942 struct net_device *dev = seq->private;
5943 struct stmmac_priv *priv = netdev_priv(dev);
5944 u32 rx_count = priv->plat->rx_queues_to_use;
5945 u32 tx_count = priv->plat->tx_queues_to_use;
5948 if ((dev->flags & IFF_UP) == 0)
5951 for (queue = 0; queue < rx_count; queue++) {
5952 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5954 seq_printf(seq, "RX Queue %d:\n", queue);
5956 if (priv->extend_desc) {
5957 seq_printf(seq, "Extended descriptor ring:\n");
5958 sysfs_display_ring((void *)rx_q->dma_erx,
5959 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy);
5961 seq_printf(seq, "Descriptor ring:\n");
5962 sysfs_display_ring((void *)rx_q->dma_rx,
5963 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy);
5967 for (queue = 0; queue < tx_count; queue++) {
5968 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5970 seq_printf(seq, "TX Queue %d:\n", queue);
5972 if (priv->extend_desc) {
5973 seq_printf(seq, "Extended descriptor ring:\n");
5974 sysfs_display_ring((void *)tx_q->dma_etx,
5975 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy);
5976 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
5977 seq_printf(seq, "Descriptor ring:\n");
5978 sysfs_display_ring((void *)tx_q->dma_tx,
5979 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy);
5985 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
5987 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
5989 struct net_device *dev = seq->private;
5990 struct stmmac_priv *priv = netdev_priv(dev);
5992 if (!priv->hw_cap_support) {
5993 seq_printf(seq, "DMA HW features not supported\n");
5997 seq_printf(seq, "==============================\n");
5998 seq_printf(seq, "\tDMA HW features\n");
5999 seq_printf(seq, "==============================\n");
6001 seq_printf(seq, "\t10/100 Mbps: %s\n",
6002 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6003 seq_printf(seq, "\t1000 Mbps: %s\n",
6004 (priv->dma_cap.mbps_1000) ? "Y" : "N");
6005 seq_printf(seq, "\tHalf duplex: %s\n",
6006 (priv->dma_cap.half_duplex) ? "Y" : "N");
6007 seq_printf(seq, "\tHash Filter: %s\n",
6008 (priv->dma_cap.hash_filter) ? "Y" : "N");
6009 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6010 (priv->dma_cap.multi_addr) ? "Y" : "N");
6011 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6012 (priv->dma_cap.pcs) ? "Y" : "N");
6013 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6014 (priv->dma_cap.sma_mdio) ? "Y" : "N");
6015 seq_printf(seq, "\tPMT Remote wake up: %s\n",
6016 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6017 seq_printf(seq, "\tPMT Magic Frame: %s\n",
6018 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6019 seq_printf(seq, "\tRMON module: %s\n",
6020 (priv->dma_cap.rmon) ? "Y" : "N");
6021 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6022 (priv->dma_cap.time_stamp) ? "Y" : "N");
6023 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6024 (priv->dma_cap.atime_stamp) ? "Y" : "N");
6025 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6026 (priv->dma_cap.eee) ? "Y" : "N");
6027 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6028 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6029 (priv->dma_cap.tx_coe) ? "Y" : "N");
6030 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6031 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6032 (priv->dma_cap.rx_coe) ? "Y" : "N");
6034 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6035 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6036 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6037 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6039 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6040 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6041 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6042 priv->dma_cap.number_rx_channel);
6043 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6044 priv->dma_cap.number_tx_channel);
6045 seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6046 priv->dma_cap.number_rx_queues);
6047 seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6048 priv->dma_cap.number_tx_queues);
6049 seq_printf(seq, "\tEnhanced descriptors: %s\n",
6050 (priv->dma_cap.enh_desc) ? "Y" : "N");
6051 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6052 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6053 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6054 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6055 seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6056 priv->dma_cap.pps_out_num);
6057 seq_printf(seq, "\tSafety Features: %s\n",
6058 priv->dma_cap.asp ? "Y" : "N");
6059 seq_printf(seq, "\tFlexible RX Parser: %s\n",
6060 priv->dma_cap.frpsel ? "Y" : "N");
6061 seq_printf(seq, "\tEnhanced Addressing: %d\n",
6062 priv->dma_cap.addr64);
6063 seq_printf(seq, "\tReceive Side Scaling: %s\n",
6064 priv->dma_cap.rssen ? "Y" : "N");
6065 seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6066 priv->dma_cap.vlhash ? "Y" : "N");
6067 seq_printf(seq, "\tSplit Header: %s\n",
6068 priv->dma_cap.sphen ? "Y" : "N");
6069 seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6070 priv->dma_cap.vlins ? "Y" : "N");
6071 seq_printf(seq, "\tDouble VLAN: %s\n",
6072 priv->dma_cap.dvlan ? "Y" : "N");
6073 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6074 priv->dma_cap.l3l4fnum);
6075 seq_printf(seq, "\tARP Offloading: %s\n",
6076 priv->dma_cap.arpoffsel ? "Y" : "N");
6077 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6078 priv->dma_cap.estsel ? "Y" : "N");
6079 seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6080 priv->dma_cap.fpesel ? "Y" : "N");
6081 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6082 priv->dma_cap.tbssel ? "Y" : "N");
6085 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6087 /* Use network device events to rename debugfs file entries.
6089 static int stmmac_device_event(struct notifier_block *unused,
6090 unsigned long event, void *ptr)
6092 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6093 struct stmmac_priv *priv = netdev_priv(dev);
6095 if (dev->netdev_ops != &stmmac_netdev_ops)
6099 case NETDEV_CHANGENAME:
6100 if (priv->dbgfs_dir)
6101 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6111 static struct notifier_block stmmac_notifier = {
6112 .notifier_call = stmmac_device_event,
6115 static void stmmac_init_fs(struct net_device *dev)
6117 struct stmmac_priv *priv = netdev_priv(dev);
6121 /* Create per netdev entries */
6122 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6124 /* Entry to report DMA RX/TX rings */
6125 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6126 &stmmac_rings_status_fops);
6128 /* Entry to report the DMA HW features */
6129 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6130 &stmmac_dma_cap_fops);
6135 static void stmmac_exit_fs(struct net_device *dev)
6137 struct stmmac_priv *priv = netdev_priv(dev);
6139 debugfs_remove_recursive(priv->dbgfs_dir);
6141 #endif /* CONFIG_DEBUG_FS */
6143 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6145 unsigned char *data = (unsigned char *)&vid_le;
6146 unsigned char data_byte = 0;
6151 bits = get_bitmask_order(VLAN_VID_MASK);
6152 for (i = 0; i < bits; i++) {
6154 data_byte = data[i / 8];
6156 temp = ((crc & 1) ^ data_byte) & 1;
6167 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6174 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6175 __le16 vid_le = cpu_to_le16(vid);
6176 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6181 if (!priv->dma_cap.vlhash) {
6182 if (count > 2) /* VID = 0 always passes filter */
6185 pmatch = cpu_to_le16(vid);
6189 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6192 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6194 struct stmmac_priv *priv = netdev_priv(ndev);
6195 bool is_double = false;
6198 if (be16_to_cpu(proto) == ETH_P_8021AD)
6201 set_bit(vid, priv->active_vlans);
6202 ret = stmmac_vlan_update(priv, is_double);
6204 clear_bit(vid, priv->active_vlans);
6208 if (priv->hw->num_vlan) {
6209 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6217 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6219 struct stmmac_priv *priv = netdev_priv(ndev);
6220 bool is_double = false;
6223 ret = pm_runtime_get_sync(priv->device);
6225 pm_runtime_put_noidle(priv->device);
6229 if (be16_to_cpu(proto) == ETH_P_8021AD)
6232 clear_bit(vid, priv->active_vlans);
6234 if (priv->hw->num_vlan) {
6235 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6237 goto del_vlan_error;
6240 ret = stmmac_vlan_update(priv, is_double);
6243 pm_runtime_put(priv->device);
6248 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6250 struct stmmac_priv *priv = netdev_priv(dev);
6252 switch (bpf->command) {
6253 case XDP_SETUP_PROG:
6254 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6255 case XDP_SETUP_XSK_POOL:
6256 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6263 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6264 struct xdp_frame **frames, u32 flags)
6266 struct stmmac_priv *priv = netdev_priv(dev);
6267 int cpu = smp_processor_id();
6268 struct netdev_queue *nq;
6272 if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6275 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6278 queue = stmmac_xdp_get_tx_queue(priv, cpu);
6279 nq = netdev_get_tx_queue(priv->dev, queue);
6281 __netif_tx_lock(nq, cpu);
6282 /* Avoids TX time-out as we are sharing with slow path */
6283 txq_trans_cond_update(nq);
6285 for (i = 0; i < num_frames; i++) {
6288 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6289 if (res == STMMAC_XDP_CONSUMED)
6295 if (flags & XDP_XMIT_FLUSH) {
6296 stmmac_flush_tx_descriptors(priv, queue);
6297 stmmac_tx_timer_arm(priv, queue);
6300 __netif_tx_unlock(nq);
6305 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6307 struct stmmac_channel *ch = &priv->channel[queue];
6308 unsigned long flags;
6310 spin_lock_irqsave(&ch->lock, flags);
6311 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6312 spin_unlock_irqrestore(&ch->lock, flags);
6314 stmmac_stop_rx_dma(priv, queue);
6315 __free_dma_rx_desc_resources(priv, queue);
6318 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6320 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
6321 struct stmmac_channel *ch = &priv->channel[queue];
6322 unsigned long flags;
6326 ret = __alloc_dma_rx_desc_resources(priv, queue);
6328 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6332 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL);
6334 __free_dma_rx_desc_resources(priv, queue);
6335 netdev_err(priv->dev, "Failed to init RX desc.\n");
6339 stmmac_clear_rx_descriptors(priv, queue);
6341 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6342 rx_q->dma_rx_phy, rx_q->queue_index);
6344 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6345 sizeof(struct dma_desc));
6346 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6347 rx_q->rx_tail_addr, rx_q->queue_index);
6349 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6350 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6351 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6355 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6360 stmmac_start_rx_dma(priv, queue);
6362 spin_lock_irqsave(&ch->lock, flags);
6363 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6364 spin_unlock_irqrestore(&ch->lock, flags);
6367 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6369 struct stmmac_channel *ch = &priv->channel[queue];
6370 unsigned long flags;
6372 spin_lock_irqsave(&ch->lock, flags);
6373 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6374 spin_unlock_irqrestore(&ch->lock, flags);
6376 stmmac_stop_tx_dma(priv, queue);
6377 __free_dma_tx_desc_resources(priv, queue);
6380 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6382 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6383 struct stmmac_channel *ch = &priv->channel[queue];
6384 unsigned long flags;
6387 ret = __alloc_dma_tx_desc_resources(priv, queue);
6389 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6393 ret = __init_dma_tx_desc_rings(priv, queue);
6395 __free_dma_tx_desc_resources(priv, queue);
6396 netdev_err(priv->dev, "Failed to init TX desc.\n");
6400 stmmac_clear_tx_descriptors(priv, queue);
6402 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6403 tx_q->dma_tx_phy, tx_q->queue_index);
6405 if (tx_q->tbs & STMMAC_TBS_AVAIL)
6406 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6408 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6409 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6410 tx_q->tx_tail_addr, tx_q->queue_index);
6412 stmmac_start_tx_dma(priv, queue);
6414 spin_lock_irqsave(&ch->lock, flags);
6415 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6416 spin_unlock_irqrestore(&ch->lock, flags);
6419 void stmmac_xdp_release(struct net_device *dev)
6421 struct stmmac_priv *priv = netdev_priv(dev);
6424 /* Disable NAPI process */
6425 stmmac_disable_all_queues(priv);
6427 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6428 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
6430 /* Free the IRQ lines */
6431 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
6433 /* Stop TX/RX DMA channels */
6434 stmmac_stop_all_dma(priv);
6436 /* Release and free the Rx/Tx resources */
6437 free_dma_desc_resources(priv);
6439 /* Disable the MAC Rx/Tx */
6440 stmmac_mac_set(priv, priv->ioaddr, false);
6442 /* set trans_start so we don't get spurious
6443 * watchdogs during reset
6445 netif_trans_update(dev);
6446 netif_carrier_off(dev);
6449 int stmmac_xdp_open(struct net_device *dev)
6451 struct stmmac_priv *priv = netdev_priv(dev);
6452 u32 rx_cnt = priv->plat->rx_queues_to_use;
6453 u32 tx_cnt = priv->plat->tx_queues_to_use;
6454 u32 dma_csr_ch = max(rx_cnt, tx_cnt);
6455 struct stmmac_rx_queue *rx_q;
6456 struct stmmac_tx_queue *tx_q;
6462 ret = alloc_dma_desc_resources(priv);
6464 netdev_err(dev, "%s: DMA descriptors allocation failed\n",
6466 goto dma_desc_error;
6469 ret = init_dma_desc_rings(dev, GFP_KERNEL);
6471 netdev_err(dev, "%s: DMA descriptors initialization failed\n",
6476 /* DMA CSR Channel configuration */
6477 for (chan = 0; chan < dma_csr_ch; chan++) {
6478 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
6479 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
6482 /* Adjust Split header */
6483 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
6485 /* DMA RX Channel Configuration */
6486 for (chan = 0; chan < rx_cnt; chan++) {
6487 rx_q = &priv->rx_queue[chan];
6489 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6490 rx_q->dma_rx_phy, chan);
6492 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
6493 (rx_q->buf_alloc_num *
6494 sizeof(struct dma_desc));
6495 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6496 rx_q->rx_tail_addr, chan);
6498 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6499 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6500 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6504 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6509 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
6512 /* DMA TX Channel Configuration */
6513 for (chan = 0; chan < tx_cnt; chan++) {
6514 tx_q = &priv->tx_queue[chan];
6516 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6517 tx_q->dma_tx_phy, chan);
6519 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6520 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6521 tx_q->tx_tail_addr, chan);
6523 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
6524 tx_q->txtimer.function = stmmac_tx_timer;
6527 /* Enable the MAC Rx/Tx */
6528 stmmac_mac_set(priv, priv->ioaddr, true);
6530 /* Start Rx & Tx DMA Channels */
6531 stmmac_start_all_dma(priv);
6533 ret = stmmac_request_irq(dev);
6537 /* Enable NAPI process*/
6538 stmmac_enable_all_queues(priv);
6539 netif_carrier_on(dev);
6540 netif_tx_start_all_queues(dev);
6541 stmmac_enable_all_dma_irq(priv);
6546 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6547 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
6549 stmmac_hw_teardown(dev);
6551 free_dma_desc_resources(priv);
6556 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6558 struct stmmac_priv *priv = netdev_priv(dev);
6559 struct stmmac_rx_queue *rx_q;
6560 struct stmmac_tx_queue *tx_q;
6561 struct stmmac_channel *ch;
6563 if (test_bit(STMMAC_DOWN, &priv->state) ||
6564 !netif_carrier_ok(priv->dev))
6567 if (!stmmac_xdp_is_enabled(priv))
6570 if (queue >= priv->plat->rx_queues_to_use ||
6571 queue >= priv->plat->tx_queues_to_use)
6574 rx_q = &priv->rx_queue[queue];
6575 tx_q = &priv->tx_queue[queue];
6576 ch = &priv->channel[queue];
6578 if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6581 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6582 /* EQoS does not have per-DMA channel SW interrupt,
6583 * so we schedule RX Napi straight-away.
6585 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6586 __napi_schedule(&ch->rxtx_napi);
6592 static const struct net_device_ops stmmac_netdev_ops = {
6593 .ndo_open = stmmac_open,
6594 .ndo_start_xmit = stmmac_xmit,
6595 .ndo_stop = stmmac_release,
6596 .ndo_change_mtu = stmmac_change_mtu,
6597 .ndo_fix_features = stmmac_fix_features,
6598 .ndo_set_features = stmmac_set_features,
6599 .ndo_set_rx_mode = stmmac_set_rx_mode,
6600 .ndo_tx_timeout = stmmac_tx_timeout,
6601 .ndo_eth_ioctl = stmmac_ioctl,
6602 .ndo_setup_tc = stmmac_setup_tc,
6603 .ndo_select_queue = stmmac_select_queue,
6604 #ifdef CONFIG_NET_POLL_CONTROLLER
6605 .ndo_poll_controller = stmmac_poll_controller,
6607 .ndo_set_mac_address = stmmac_set_mac_address,
6608 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6609 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6610 .ndo_bpf = stmmac_bpf,
6611 .ndo_xdp_xmit = stmmac_xdp_xmit,
6612 .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6615 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6617 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6619 if (test_bit(STMMAC_DOWN, &priv->state))
6622 netdev_err(priv->dev, "Reset adapter.\n");
6625 netif_trans_update(priv->dev);
6626 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6627 usleep_range(1000, 2000);
6629 set_bit(STMMAC_DOWN, &priv->state);
6630 dev_close(priv->dev);
6631 dev_open(priv->dev, NULL);
6632 clear_bit(STMMAC_DOWN, &priv->state);
6633 clear_bit(STMMAC_RESETING, &priv->state);
6637 static void stmmac_service_task(struct work_struct *work)
6639 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6642 stmmac_reset_subtask(priv);
6643 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6647 * stmmac_hw_init - Init the MAC device
6648 * @priv: driver private structure
6649 * Description: this function is to configure the MAC device according to
6650 * some platform parameters or the HW capability register. It prepares the
6651 * driver to use either ring or chain modes and to setup either enhanced or
6652 * normal descriptors.
6654 static int stmmac_hw_init(struct stmmac_priv *priv)
6658 /* dwmac-sun8i only work in chain mode */
6659 if (priv->plat->has_sun8i)
6661 priv->chain_mode = chain_mode;
6663 /* Initialize HW Interface */
6664 ret = stmmac_hwif_init(priv);
6668 /* Get the HW capability (new GMAC newer than 3.50a) */
6669 priv->hw_cap_support = stmmac_get_hw_features(priv);
6670 if (priv->hw_cap_support) {
6671 dev_info(priv->device, "DMA HW capability register supported\n");
6673 /* We can override some gmac/dma configuration fields: e.g.
6674 * enh_desc, tx_coe (e.g. that are passed through the
6675 * platform) with the values from the HW capability
6676 * register (if supported).
6678 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6679 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6680 !priv->plat->use_phy_wol;
6681 priv->hw->pmt = priv->plat->pmt;
6682 if (priv->dma_cap.hash_tb_sz) {
6683 priv->hw->multicast_filter_bins =
6684 (BIT(priv->dma_cap.hash_tb_sz) << 5);
6685 priv->hw->mcast_bits_log2 =
6686 ilog2(priv->hw->multicast_filter_bins);
6689 /* TXCOE doesn't work in thresh DMA mode */
6690 if (priv->plat->force_thresh_dma_mode)
6691 priv->plat->tx_coe = 0;
6693 priv->plat->tx_coe = priv->dma_cap.tx_coe;
6695 /* In case of GMAC4 rx_coe is from HW cap register. */
6696 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6698 if (priv->dma_cap.rx_coe_type2)
6699 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6700 else if (priv->dma_cap.rx_coe_type1)
6701 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6704 dev_info(priv->device, "No HW DMA feature register supported\n");
6707 if (priv->plat->rx_coe) {
6708 priv->hw->rx_csum = priv->plat->rx_coe;
6709 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6710 if (priv->synopsys_id < DWMAC_CORE_4_00)
6711 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6713 if (priv->plat->tx_coe)
6714 dev_info(priv->device, "TX Checksum insertion supported\n");
6716 if (priv->plat->pmt) {
6717 dev_info(priv->device, "Wake-Up On Lan supported\n");
6718 device_set_wakeup_capable(priv->device, 1);
6721 if (priv->dma_cap.tsoen)
6722 dev_info(priv->device, "TSO supported\n");
6724 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6725 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6727 /* Run HW quirks, if any */
6728 if (priv->hwif_quirks) {
6729 ret = priv->hwif_quirks(priv);
6734 /* Rx Watchdog is available in the COREs newer than the 3.40.
6735 * In some case, for example on bugged HW this feature
6736 * has to be disable and this can be done by passing the
6737 * riwt_off field from the platform.
6739 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6740 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6742 dev_info(priv->device,
6743 "Enable RX Mitigation via HW Watchdog Timer\n");
6749 static void stmmac_napi_add(struct net_device *dev)
6751 struct stmmac_priv *priv = netdev_priv(dev);
6754 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6756 for (queue = 0; queue < maxq; queue++) {
6757 struct stmmac_channel *ch = &priv->channel[queue];
6759 ch->priv_data = priv;
6761 spin_lock_init(&ch->lock);
6763 if (queue < priv->plat->rx_queues_to_use) {
6764 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
6767 if (queue < priv->plat->tx_queues_to_use) {
6768 netif_tx_napi_add(dev, &ch->tx_napi,
6769 stmmac_napi_poll_tx,
6772 if (queue < priv->plat->rx_queues_to_use &&
6773 queue < priv->plat->tx_queues_to_use) {
6774 netif_napi_add(dev, &ch->rxtx_napi,
6775 stmmac_napi_poll_rxtx,
6781 static void stmmac_napi_del(struct net_device *dev)
6783 struct stmmac_priv *priv = netdev_priv(dev);
6786 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6788 for (queue = 0; queue < maxq; queue++) {
6789 struct stmmac_channel *ch = &priv->channel[queue];
6791 if (queue < priv->plat->rx_queues_to_use)
6792 netif_napi_del(&ch->rx_napi);
6793 if (queue < priv->plat->tx_queues_to_use)
6794 netif_napi_del(&ch->tx_napi);
6795 if (queue < priv->plat->rx_queues_to_use &&
6796 queue < priv->plat->tx_queues_to_use) {
6797 netif_napi_del(&ch->rxtx_napi);
6802 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
6804 struct stmmac_priv *priv = netdev_priv(dev);
6807 if (netif_running(dev))
6808 stmmac_release(dev);
6810 stmmac_napi_del(dev);
6812 priv->plat->rx_queues_to_use = rx_cnt;
6813 priv->plat->tx_queues_to_use = tx_cnt;
6815 stmmac_napi_add(dev);
6817 if (netif_running(dev))
6818 ret = stmmac_open(dev);
6823 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
6825 struct stmmac_priv *priv = netdev_priv(dev);
6828 if (netif_running(dev))
6829 stmmac_release(dev);
6831 priv->dma_rx_size = rx_size;
6832 priv->dma_tx_size = tx_size;
6834 if (netif_running(dev))
6835 ret = stmmac_open(dev);
6840 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
6841 static void stmmac_fpe_lp_task(struct work_struct *work)
6843 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6845 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
6846 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
6847 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
6848 bool *hs_enable = &fpe_cfg->hs_enable;
6849 bool *enable = &fpe_cfg->enable;
6852 while (retries-- > 0) {
6853 /* Bail out immediately if FPE handshake is OFF */
6854 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
6857 if (*lo_state == FPE_STATE_ENTERING_ON &&
6858 *lp_state == FPE_STATE_ENTERING_ON) {
6859 stmmac_fpe_configure(priv, priv->ioaddr,
6860 priv->plat->tx_queues_to_use,
6861 priv->plat->rx_queues_to_use,
6864 netdev_info(priv->dev, "configured FPE\n");
6866 *lo_state = FPE_STATE_ON;
6867 *lp_state = FPE_STATE_ON;
6868 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
6872 if ((*lo_state == FPE_STATE_CAPABLE ||
6873 *lo_state == FPE_STATE_ENTERING_ON) &&
6874 *lp_state != FPE_STATE_ON) {
6875 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
6876 *lo_state, *lp_state);
6877 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6880 /* Sleep then retry */
6884 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
6887 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
6889 if (priv->plat->fpe_cfg->hs_enable != enable) {
6891 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6894 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
6895 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
6898 priv->plat->fpe_cfg->hs_enable = enable;
6904 * @device: device pointer
6905 * @plat_dat: platform data pointer
6906 * @res: stmmac resource pointer
6907 * Description: this is the main probe function used to
6908 * call the alloc_etherdev, allocate the priv structure.
6910 * returns 0 on success, otherwise errno.
6912 int stmmac_dvr_probe(struct device *device,
6913 struct plat_stmmacenet_data *plat_dat,
6914 struct stmmac_resources *res)
6916 struct net_device *ndev = NULL;
6917 struct stmmac_priv *priv;
6921 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
6922 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
6926 SET_NETDEV_DEV(ndev, device);
6928 priv = netdev_priv(ndev);
6929 priv->device = device;
6932 stmmac_set_ethtool_ops(ndev);
6933 priv->pause = pause;
6934 priv->plat = plat_dat;
6935 priv->ioaddr = res->addr;
6936 priv->dev->base_addr = (unsigned long)res->addr;
6937 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
6939 priv->dev->irq = res->irq;
6940 priv->wol_irq = res->wol_irq;
6941 priv->lpi_irq = res->lpi_irq;
6942 priv->sfty_ce_irq = res->sfty_ce_irq;
6943 priv->sfty_ue_irq = res->sfty_ue_irq;
6944 for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
6945 priv->rx_irq[i] = res->rx_irq[i];
6946 for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
6947 priv->tx_irq[i] = res->tx_irq[i];
6949 if (!is_zero_ether_addr(res->mac))
6950 eth_hw_addr_set(priv->dev, res->mac);
6952 dev_set_drvdata(device, priv->dev);
6954 /* Verify driver arguments */
6955 stmmac_verify_args();
6957 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
6958 if (!priv->af_xdp_zc_qps)
6961 /* Allocate workqueue */
6962 priv->wq = create_singlethread_workqueue("stmmac_wq");
6964 dev_err(priv->device, "failed to create workqueue\n");
6968 INIT_WORK(&priv->service_task, stmmac_service_task);
6970 /* Initialize Link Partner FPE workqueue */
6971 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
6973 /* Override with kernel parameters if supplied XXX CRS XXX
6974 * this needs to have multiple instances
6976 if ((phyaddr >= 0) && (phyaddr <= 31))
6977 priv->plat->phy_addr = phyaddr;
6979 if (priv->plat->stmmac_rst) {
6980 ret = reset_control_assert(priv->plat->stmmac_rst);
6981 reset_control_deassert(priv->plat->stmmac_rst);
6982 /* Some reset controllers have only reset callback instead of
6983 * assert + deassert callbacks pair.
6985 if (ret == -ENOTSUPP)
6986 reset_control_reset(priv->plat->stmmac_rst);
6989 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
6990 if (ret == -ENOTSUPP)
6991 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
6994 /* Init MAC and get the capabilities */
6995 ret = stmmac_hw_init(priv);
6999 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
7001 if (priv->synopsys_id < DWMAC_CORE_5_20)
7002 priv->plat->dma_cfg->dche = false;
7004 stmmac_check_ether_addr(priv);
7006 ndev->netdev_ops = &stmmac_netdev_ops;
7008 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
7011 ret = stmmac_tc_init(priv, priv);
7013 ndev->hw_features |= NETIF_F_HW_TC;
7016 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
7017 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
7018 if (priv->plat->has_gmac4)
7019 ndev->hw_features |= NETIF_F_GSO_UDP_L4;
7021 dev_info(priv->device, "TSO feature enabled\n");
7024 if (priv->dma_cap.sphen) {
7025 ndev->hw_features |= NETIF_F_GRO;
7026 priv->sph_cap = true;
7027 priv->sph = priv->sph_cap;
7028 dev_info(priv->device, "SPH feature enabled\n");
7031 /* The current IP register MAC_HW_Feature1[ADDR64] only define
7032 * 32/40/64 bit width, but some SOC support others like i.MX8MP
7033 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
7034 * So overwrite dma_cap.addr64 according to HW real design.
7036 if (priv->plat->addr64)
7037 priv->dma_cap.addr64 = priv->plat->addr64;
7039 if (priv->dma_cap.addr64) {
7040 ret = dma_set_mask_and_coherent(device,
7041 DMA_BIT_MASK(priv->dma_cap.addr64));
7043 dev_info(priv->device, "Using %d bits DMA width\n",
7044 priv->dma_cap.addr64);
7047 * If more than 32 bits can be addressed, make sure to
7048 * enable enhanced addressing mode.
7050 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
7051 priv->plat->dma_cfg->eame = true;
7053 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
7055 dev_err(priv->device, "Failed to set DMA Mask\n");
7059 priv->dma_cap.addr64 = 32;
7063 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
7064 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
7065 #ifdef STMMAC_VLAN_TAG_USED
7066 /* Both mac100 and gmac support receive VLAN tag detection */
7067 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
7068 if (priv->dma_cap.vlhash) {
7069 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7070 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
7072 if (priv->dma_cap.vlins) {
7073 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
7074 if (priv->dma_cap.dvlan)
7075 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
7078 priv->msg_enable = netif_msg_init(debug, default_msg_level);
7080 /* Initialize RSS */
7081 rxq = priv->plat->rx_queues_to_use;
7082 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
7083 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7084 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
7086 if (priv->dma_cap.rssen && priv->plat->rss_en)
7087 ndev->features |= NETIF_F_RXHASH;
7089 /* MTU range: 46 - hw-specific max */
7090 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
7091 if (priv->plat->has_xgmac)
7092 ndev->max_mtu = XGMAC_JUMBO_LEN;
7093 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
7094 ndev->max_mtu = JUMBO_LEN;
7096 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
7097 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
7098 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
7100 if ((priv->plat->maxmtu < ndev->max_mtu) &&
7101 (priv->plat->maxmtu >= ndev->min_mtu))
7102 ndev->max_mtu = priv->plat->maxmtu;
7103 else if (priv->plat->maxmtu < ndev->min_mtu)
7104 dev_warn(priv->device,
7105 "%s: warning: maxmtu having invalid value (%d)\n",
7106 __func__, priv->plat->maxmtu);
7109 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
7111 /* Setup channels NAPI */
7112 stmmac_napi_add(ndev);
7114 mutex_init(&priv->lock);
7116 /* If a specific clk_csr value is passed from the platform
7117 * this means that the CSR Clock Range selection cannot be
7118 * changed at run-time and it is fixed. Viceversa the driver'll try to
7119 * set the MDC clock dynamically according to the csr actual
7122 if (priv->plat->clk_csr >= 0)
7123 priv->clk_csr = priv->plat->clk_csr;
7125 stmmac_clk_csr_set(priv);
7127 stmmac_check_pcs_mode(priv);
7129 pm_runtime_get_noresume(device);
7130 pm_runtime_set_active(device);
7131 if (!pm_runtime_enabled(device))
7132 pm_runtime_enable(device);
7134 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7135 priv->hw->pcs != STMMAC_PCS_RTBI) {
7136 /* MDIO bus Registration */
7137 ret = stmmac_mdio_register(ndev);
7139 dev_err(priv->device,
7140 "%s: MDIO bus (id: %d) registration failed",
7141 __func__, priv->plat->bus_id);
7142 goto error_mdio_register;
7146 if (priv->plat->speed_mode_2500)
7147 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7149 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7150 ret = stmmac_xpcs_setup(priv->mii);
7152 goto error_xpcs_setup;
7155 ret = stmmac_phy_setup(priv);
7157 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7158 goto error_phy_setup;
7161 ret = register_netdev(ndev);
7163 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7165 goto error_netdev_register;
7168 if (priv->plat->serdes_powerup) {
7169 ret = priv->plat->serdes_powerup(ndev,
7170 priv->plat->bsp_priv);
7173 goto error_serdes_powerup;
7176 #ifdef CONFIG_DEBUG_FS
7177 stmmac_init_fs(ndev);
7180 if (priv->plat->dump_debug_regs)
7181 priv->plat->dump_debug_regs(priv->plat->bsp_priv);
7183 /* Let pm_runtime_put() disable the clocks.
7184 * If CONFIG_PM is not enabled, the clocks will stay powered.
7186 pm_runtime_put(device);
7190 error_serdes_powerup:
7191 unregister_netdev(ndev);
7192 error_netdev_register:
7193 phylink_destroy(priv->phylink);
7196 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7197 priv->hw->pcs != STMMAC_PCS_RTBI)
7198 stmmac_mdio_unregister(ndev);
7199 error_mdio_register:
7200 stmmac_napi_del(ndev);
7202 destroy_workqueue(priv->wq);
7203 bitmap_free(priv->af_xdp_zc_qps);
7207 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7211 * @dev: device pointer
7212 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7213 * changes the link status, releases the DMA descriptor rings.
7215 int stmmac_dvr_remove(struct device *dev)
7217 struct net_device *ndev = dev_get_drvdata(dev);
7218 struct stmmac_priv *priv = netdev_priv(ndev);
7220 netdev_info(priv->dev, "%s: removing driver", __func__);
7222 pm_runtime_get_sync(dev);
7223 pm_runtime_disable(dev);
7224 pm_runtime_put_noidle(dev);
7226 stmmac_stop_all_dma(priv);
7227 stmmac_mac_set(priv, priv->ioaddr, false);
7228 netif_carrier_off(ndev);
7229 unregister_netdev(ndev);
7231 /* Serdes power down needs to happen after VLAN filter
7232 * is deleted that is triggered by unregister_netdev().
7234 if (priv->plat->serdes_powerdown)
7235 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7237 #ifdef CONFIG_DEBUG_FS
7238 stmmac_exit_fs(ndev);
7240 phylink_destroy(priv->phylink);
7241 if (priv->plat->stmmac_rst)
7242 reset_control_assert(priv->plat->stmmac_rst);
7243 reset_control_assert(priv->plat->stmmac_ahb_rst);
7244 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7245 priv->hw->pcs != STMMAC_PCS_RTBI)
7246 stmmac_mdio_unregister(ndev);
7247 destroy_workqueue(priv->wq);
7248 mutex_destroy(&priv->lock);
7249 bitmap_free(priv->af_xdp_zc_qps);
7253 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7256 * stmmac_suspend - suspend callback
7257 * @dev: device pointer
7258 * Description: this is the function to suspend the device and it is called
7259 * by the platform driver to stop the network queue, release the resources,
7260 * program the PMT register (for WoL), clean and release driver resources.
7262 int stmmac_suspend(struct device *dev)
7264 struct net_device *ndev = dev_get_drvdata(dev);
7265 struct stmmac_priv *priv = netdev_priv(ndev);
7268 if (!ndev || !netif_running(ndev))
7271 mutex_lock(&priv->lock);
7273 netif_device_detach(ndev);
7275 stmmac_disable_all_queues(priv);
7277 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7278 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
7280 if (priv->eee_enabled) {
7281 priv->tx_path_in_lpi_mode = false;
7282 del_timer_sync(&priv->eee_ctrl_timer);
7285 /* Stop TX/RX DMA */
7286 stmmac_stop_all_dma(priv);
7288 if (priv->plat->serdes_powerdown)
7289 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7291 /* Enable Power down mode by programming the PMT regs */
7292 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7293 stmmac_pmt(priv, priv->hw, priv->wolopts);
7296 stmmac_mac_set(priv, priv->ioaddr, false);
7297 pinctrl_pm_select_sleep_state(priv->device);
7300 mutex_unlock(&priv->lock);
7303 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7304 phylink_suspend(priv->phylink, true);
7306 if (device_may_wakeup(priv->device))
7307 phylink_speed_down(priv->phylink, false);
7308 phylink_suspend(priv->phylink, false);
7312 if (priv->dma_cap.fpesel) {
7314 stmmac_fpe_configure(priv, priv->ioaddr,
7315 priv->plat->tx_queues_to_use,
7316 priv->plat->rx_queues_to_use, false);
7318 stmmac_fpe_handshake(priv, false);
7319 stmmac_fpe_stop_wq(priv);
7322 priv->speed = SPEED_UNKNOWN;
7325 EXPORT_SYMBOL_GPL(stmmac_suspend);
7328 * stmmac_reset_queues_param - reset queue parameters
7329 * @priv: device pointer
7331 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7333 u32 rx_cnt = priv->plat->rx_queues_to_use;
7334 u32 tx_cnt = priv->plat->tx_queues_to_use;
7337 for (queue = 0; queue < rx_cnt; queue++) {
7338 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
7344 for (queue = 0; queue < tx_cnt; queue++) {
7345 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
7351 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7356 * stmmac_resume - resume callback
7357 * @dev: device pointer
7358 * Description: when resume this function is invoked to setup the DMA and CORE
7359 * in a usable state.
7361 int stmmac_resume(struct device *dev)
7363 struct net_device *ndev = dev_get_drvdata(dev);
7364 struct stmmac_priv *priv = netdev_priv(ndev);
7367 if (!netif_running(ndev))
7370 /* Power Down bit, into the PM register, is cleared
7371 * automatically as soon as a magic packet or a Wake-up frame
7372 * is received. Anyway, it's better to manually clear
7373 * this bit because it can generate problems while resuming
7374 * from another devices (e.g. serial console).
7376 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7377 mutex_lock(&priv->lock);
7378 stmmac_pmt(priv, priv->hw, 0);
7379 mutex_unlock(&priv->lock);
7382 pinctrl_pm_select_default_state(priv->device);
7383 /* reset the phy so that it's ready */
7385 stmmac_mdio_reset(priv->mii);
7388 if (priv->plat->serdes_powerup) {
7389 ret = priv->plat->serdes_powerup(ndev,
7390 priv->plat->bsp_priv);
7397 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7398 phylink_resume(priv->phylink);
7400 phylink_resume(priv->phylink);
7401 if (device_may_wakeup(priv->device))
7402 phylink_speed_up(priv->phylink);
7407 mutex_lock(&priv->lock);
7409 stmmac_reset_queues_param(priv);
7411 stmmac_free_tx_skbufs(priv);
7412 stmmac_clear_descriptors(priv);
7414 stmmac_hw_setup(ndev, false);
7415 stmmac_init_coalesce(priv);
7416 stmmac_set_rx_mode(ndev);
7418 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7420 stmmac_enable_all_queues(priv);
7421 stmmac_enable_all_dma_irq(priv);
7423 mutex_unlock(&priv->lock);
7426 netif_device_attach(ndev);
7430 EXPORT_SYMBOL_GPL(stmmac_resume);
7433 static int __init stmmac_cmdline_opt(char *str)
7439 while ((opt = strsep(&str, ",")) != NULL) {
7440 if (!strncmp(opt, "debug:", 6)) {
7441 if (kstrtoint(opt + 6, 0, &debug))
7443 } else if (!strncmp(opt, "phyaddr:", 8)) {
7444 if (kstrtoint(opt + 8, 0, &phyaddr))
7446 } else if (!strncmp(opt, "buf_sz:", 7)) {
7447 if (kstrtoint(opt + 7, 0, &buf_sz))
7449 } else if (!strncmp(opt, "tc:", 3)) {
7450 if (kstrtoint(opt + 3, 0, &tc))
7452 } else if (!strncmp(opt, "watchdog:", 9)) {
7453 if (kstrtoint(opt + 9, 0, &watchdog))
7455 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7456 if (kstrtoint(opt + 10, 0, &flow_ctrl))
7458 } else if (!strncmp(opt, "pause:", 6)) {
7459 if (kstrtoint(opt + 6, 0, &pause))
7461 } else if (!strncmp(opt, "eee_timer:", 10)) {
7462 if (kstrtoint(opt + 10, 0, &eee_timer))
7464 } else if (!strncmp(opt, "chain_mode:", 11)) {
7465 if (kstrtoint(opt + 11, 0, &chain_mode))
7472 pr_err("%s: ERROR broken module parameter conversion", __func__);
7476 __setup("stmmaceth=", stmmac_cmdline_opt);
7479 static int __init stmmac_init(void)
7481 #ifdef CONFIG_DEBUG_FS
7482 /* Create debugfs main directory if it doesn't exist yet */
7484 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7485 register_netdevice_notifier(&stmmac_notifier);
7491 static void __exit stmmac_exit(void)
7493 #ifdef CONFIG_DEBUG_FS
7494 unregister_netdevice_notifier(&stmmac_notifier);
7495 debugfs_remove_recursive(stmmac_fs_dir);
7499 module_init(stmmac_init)
7500 module_exit(stmmac_exit)
7502 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7503 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7504 MODULE_LICENSE("GPL");