drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <net/pkt_cls.h>
  40 #include "stmmac_ptp.h"
  41 #include "stmmac.h"
  42 #include <linux/reset.h>
  43 #include <linux/of_mdio.h>
  44 #include "dwmac1000.h"
  45 #include "dwxgmac2.h"
  46 #include "hwif.h"
  47
  48 #define STMMAC_ALIGN(x)         __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
  49 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  50
  51 /* Module parameters */
  52 #define TX_TIMEO        5000
  53 static int watchdog = TX_TIMEO;
  54 module_param(watchdog, int, 0644);
  55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  56
  57 static int debug = -1;
  58 module_param(debug, int, 0644);
  59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  60
  61 static int phyaddr = -1;
  62 module_param(phyaddr, int, 0444);
  63 MODULE_PARM_DESC(phyaddr, "Physical device address");
  64
  65 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  66 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  67
  68 static int flow_ctrl = FLOW_AUTO;
  69 module_param(flow_ctrl, int, 0644);
  70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  71
  72 static int pause = PAUSE_TIME;
  73 module_param(pause, int, 0644);
  74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  75
  76 #define TC_DEFAULT 64
  77 static int tc = TC_DEFAULT;
  78 module_param(tc, int, 0644);
  79 MODULE_PARM_DESC(tc, "DMA threshold control value");
  80
  81 #define DEFAULT_BUFSIZE 1536
  82 static int buf_sz = DEFAULT_BUFSIZE;
  83 module_param(buf_sz, int, 0644);
  84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  85
  86 #define STMMAC_RX_COPYBREAK     256
  87
  88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  89                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  90                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  91
  92 #define STMMAC_DEFAULT_LPI_TIMER        1000
  93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  94 module_param(eee_timer, int, 0644);
  95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  97
  98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
  99  * but allow user to force to use the chain instead of the ring
 100  */
 101 static unsigned int chain_mode;
 102 module_param(chain_mode, int, 0444);
 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 104
 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 106
 107 #ifdef CONFIG_DEBUG_FS
 108 static int stmmac_init_fs(struct net_device *dev);
 109 static void stmmac_exit_fs(struct net_device *dev);
 110 #endif
 111
 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 113
 114 /**
 115  * stmmac_verify_args - verify the driver parameters.
 116  * Description: it checks the driver parameters and set a default in case of
 117  * errors.
 118  */
 119 static void stmmac_verify_args(void)
 120 {
 121         if (unlikely(watchdog < 0))
 122                 watchdog = TX_TIMEO;
 123         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 124                 buf_sz = DEFAULT_BUFSIZE;
 125         if (unlikely(flow_ctrl > 1))
 126                 flow_ctrl = FLOW_AUTO;
 127         else if (likely(flow_ctrl < 0))
 128                 flow_ctrl = FLOW_OFF;
 129         if (unlikely((pause < 0) || (pause > 0xffff)))
 130                 pause = PAUSE_TIME;
 131         if (eee_timer < 0)
 132                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 133 }
 134
 135 /**
 136  * stmmac_disable_all_queues - Disable all queues
 137  * @priv: driver private structure
 138  */
 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 140 {
 141         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 142         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 143         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 144         u32 queue;
 145
 146         for (queue = 0; queue < maxq; queue++) {
 147                 struct stmmac_channel *ch = &priv->channel[queue];
 148
 149                 if (queue < rx_queues_cnt)
 150                         napi_disable(&ch->rx_napi);
 151                 if (queue < tx_queues_cnt)
 152                         napi_disable(&ch->tx_napi);
 153         }
 154 }
 155
 156 /**
 157  * stmmac_enable_all_queues - Enable all queues
 158  * @priv: driver private structure
 159  */
 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 161 {
 162         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 163         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 164         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 165         u32 queue;
 166
 167         for (queue = 0; queue < maxq; queue++) {
 168                 struct stmmac_channel *ch = &priv->channel[queue];
 169
 170                 if (queue < rx_queues_cnt)
 171                         napi_enable(&ch->rx_napi);
 172                 if (queue < tx_queues_cnt)
 173                         napi_enable(&ch->tx_napi);
 174         }
 175 }
 176
 177 /**
 178  * stmmac_stop_all_queues - Stop all queues
 179  * @priv: driver private structure
 180  */
 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 182 {
 183         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 184         u32 queue;
 185
 186         for (queue = 0; queue < tx_queues_cnt; queue++)
 187                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 188 }
 189
 190 /**
 191  * stmmac_start_all_queues - Start all queues
 192  * @priv: driver private structure
 193  */
 194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 195 {
 196         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 197         u32 queue;
 198
 199         for (queue = 0; queue < tx_queues_cnt; queue++)
 200                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 201 }
 202
 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 204 {
 205         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 206             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 207                 queue_work(priv->wq, &priv->service_task);
 208 }
 209
 210 static void stmmac_global_err(struct stmmac_priv *priv)
 211 {
 212         netif_carrier_off(priv->dev);
 213         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 214         stmmac_service_event_schedule(priv);
 215 }
 216
 217 /**
 218  * stmmac_clk_csr_set - dynamically set the MDC clock
 219  * @priv: driver private structure
 220  * Description: this is to dynamically set the MDC clock according to the csr
 221  * clock input.
 222  * Note:
 223  *      If a specific clk_csr value is passed from the platform
 224  *      this means that the CSR Clock Range selection cannot be
 225  *      changed at run-time and it is fixed (as reported in the driver
 226  *      documentation). Viceversa the driver will try to set the MDC
 227  *      clock dynamically according to the actual clock input.
 228  */
 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 230 {
 231         u32 clk_rate;
 232
 233         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 234
 235         /* Platform provided default clk_csr would be assumed valid
 236          * for all other cases except for the below mentioned ones.
 237          * For values higher than the IEEE 802.3 specified frequency
 238          * we can not estimate the proper divider as it is not known
 239          * the frequency of clk_csr_i. So we do not change the default
 240          * divider.
 241          */
 242         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 243                 if (clk_rate < CSR_F_35M)
 244                         priv->clk_csr = STMMAC_CSR_20_35M;
 245                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 246                         priv->clk_csr = STMMAC_CSR_35_60M;
 247                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 248                         priv->clk_csr = STMMAC_CSR_60_100M;
 249                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 250                         priv->clk_csr = STMMAC_CSR_100_150M;
 251                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 252                         priv->clk_csr = STMMAC_CSR_150_250M;
 253                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 254                         priv->clk_csr = STMMAC_CSR_250_300M;
 255         }
 256
 257         if (priv->plat->has_sun8i) {
 258                 if (clk_rate > 160000000)
 259                         priv->clk_csr = 0x03;
 260                 else if (clk_rate > 80000000)
 261                         priv->clk_csr = 0x02;
 262                 else if (clk_rate > 40000000)
 263                         priv->clk_csr = 0x01;
 264                 else
 265                         priv->clk_csr = 0;
 266         }
 267
 268         if (priv->plat->has_xgmac) {
 269                 if (clk_rate > 400000000)
 270                         priv->clk_csr = 0x5;
 271                 else if (clk_rate > 350000000)
 272                         priv->clk_csr = 0x4;
 273                 else if (clk_rate > 300000000)
 274                         priv->clk_csr = 0x3;
 275                 else if (clk_rate > 250000000)
 276                         priv->clk_csr = 0x2;
 277                 else if (clk_rate > 150000000)
 278                         priv->clk_csr = 0x1;
 279                 else
 280                         priv->clk_csr = 0x0;
 281         }
 282 }
 283
 284 static void print_pkt(unsigned char *buf, int len)
 285 {
 286         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 287         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 288 }
 289
 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 291 {
 292         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 293         u32 avail;
 294
 295         if (tx_q->dirty_tx > tx_q->cur_tx)
 296                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 297         else
 298                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 299
 300         return avail;
 301 }
 302
 303 /**
 304  * stmmac_rx_dirty - Get RX queue dirty
 305  * @priv: driver private structure
 306  * @queue: RX queue index
 307  */
 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 309 {
 310         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 311         u32 dirty;
 312
 313         if (rx_q->dirty_rx <= rx_q->cur_rx)
 314                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 315         else
 316                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 317
 318         return dirty;
 319 }
 320
 321 /**
 322  * stmmac_enable_eee_mode - check and enter in LPI mode
 323  * @priv: driver private structure
 324  * Description: this function is to verify and enter in LPI mode in case of
 325  * EEE.
 326  */
 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 328 {
 329         u32 tx_cnt = priv->plat->tx_queues_to_use;
 330         u32 queue;
 331
 332         /* check if all TX queues have the work finished */
 333         for (queue = 0; queue < tx_cnt; queue++) {
 334                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 335
 336                 if (tx_q->dirty_tx != tx_q->cur_tx)
 337                         return; /* still unfinished work */
 338         }
 339
 340         /* Check and enter in LPI mode */
 341         if (!priv->tx_path_in_lpi_mode)
 342                 stmmac_set_eee_mode(priv, priv->hw,
 343                                 priv->plat->en_tx_lpi_clockgating);
 344 }
 345
 346 /**
 347  * stmmac_disable_eee_mode - disable and exit from LPI mode
 348  * @priv: driver private structure
 349  * Description: this function is to exit and disable EEE in case of
 350  * LPI state is true. This is called by the xmit.
 351  */
 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 353 {
 354         stmmac_reset_eee_mode(priv, priv->hw);
 355         del_timer_sync(&priv->eee_ctrl_timer);
 356         priv->tx_path_in_lpi_mode = false;
 357 }
 358
 359 /**
 360  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 361  * @arg : data hook
 362  * Description:
 363  *  if there is no data transfer and if we are not in LPI state,
 364  *  then MAC Transmitter can be moved to LPI state.
 365  */
 366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 367 {
 368         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 369
 370         stmmac_enable_eee_mode(priv);
 371         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 372 }
 373
 374 /**
 375  * stmmac_eee_init - init EEE
 376  * @priv: driver private structure
 377  * Description:
 378  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 379  *  can also manage EEE, this function enable the LPI state and start related
 380  *  timer.
 381  */
 382 bool stmmac_eee_init(struct stmmac_priv *priv)
 383 {
 384         int tx_lpi_timer = priv->tx_lpi_timer;
 385
 386         /* Using PCS we cannot dial with the phy registers at this stage
 387          * so we do not support extra feature like EEE.
 388          */
 389         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 390             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 391             (priv->hw->pcs == STMMAC_PCS_RTBI))
 392                 return false;
 393
 394         /* Check if MAC core supports the EEE feature. */
 395         if (!priv->dma_cap.eee)
 396                 return false;
 397
 398         mutex_lock(&priv->lock);
 399
 400         /* Check if it needs to be deactivated */
 401         if (!priv->eee_active) {
 402                 if (priv->eee_enabled) {
 403                         netdev_dbg(priv->dev, "disable EEE\n");
 404                         del_timer_sync(&priv->eee_ctrl_timer);
 405                         stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 406                 }
 407                 mutex_unlock(&priv->lock);
 408                 return false;
 409         }
 410
 411         if (priv->eee_active && !priv->eee_enabled) {
 412                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 413                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 414                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 415                                      tx_lpi_timer);
 416         }
 417
 418         mutex_unlock(&priv->lock);
 419         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 420         return true;
 421 }
 422
 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 424  * @priv: driver private structure
 425  * @p : descriptor pointer
 426  * @skb : the socket buffer
 427  * Description :
 428  * This function will read timestamp from the descriptor & pass it to stack.
 429  * and also perform some sanity checks.
 430  */
 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 432                                    struct dma_desc *p, struct sk_buff *skb)
 433 {
 434         struct skb_shared_hwtstamps shhwtstamp;
 435         u64 ns = 0;
 436
 437         if (!priv->hwts_tx_en)
 438                 return;
 439
 440         /* exit if skb doesn't support hw tstamp */
 441         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 442                 return;
 443
 444         /* check tx tstamp status */
 445         if (stmmac_get_tx_timestamp_status(priv, p)) {
 446                 /* get the valid tstamp */
 447                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 448
 449                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 450                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 451
 452                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 453                 /* pass tstamp to stack */
 454                 skb_tstamp_tx(skb, &shhwtstamp);
 455         }
 456
 457         return;
 458 }
 459
 460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 461  * @priv: driver private structure
 462  * @p : descriptor pointer
 463  * @np : next descriptor pointer
 464  * @skb : the socket buffer
 465  * Description :
 466  * This function will read received packet's timestamp from the descriptor
 467  * and pass it to stack. It also perform some sanity checks.
 468  */
 469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 470                                    struct dma_desc *np, struct sk_buff *skb)
 471 {
 472         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 473         struct dma_desc *desc = p;
 474         u64 ns = 0;
 475
 476         if (!priv->hwts_rx_en)
 477                 return;
 478         /* For GMAC4, the valid timestamp is from CTX next desc. */
 479         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 480                 desc = np;
 481
 482         /* Check if timestamp is available */
 483         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 484                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 485                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 486                 shhwtstamp = skb_hwtstamps(skb);
 487                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 488                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 489         } else  {
 490                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 491         }
 492 }
 493
 494 /**
 495  *  stmmac_hwtstamp_set - control hardware timestamping.
 496  *  @dev: device pointer.
 497  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 498  *  a proprietary structure used to pass information to the driver.
 499  *  Description:
 500  *  This function configures the MAC to enable/disable both outgoing(TX)
 501  *  and incoming(RX) packets time stamping based on user input.
 502  *  Return Value:
 503  *  0 on success and an appropriate -ve integer on failure.
 504  */
 505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 506 {
 507         struct stmmac_priv *priv = netdev_priv(dev);
 508         struct hwtstamp_config config;
 509         struct timespec64 now;
 510         u64 temp = 0;
 511         u32 ptp_v2 = 0;
 512         u32 tstamp_all = 0;
 513         u32 ptp_over_ipv4_udp = 0;
 514         u32 ptp_over_ipv6_udp = 0;
 515         u32 ptp_over_ethernet = 0;
 516         u32 snap_type_sel = 0;
 517         u32 ts_master_en = 0;
 518         u32 ts_event_en = 0;
 519         u32 sec_inc = 0;
 520         u32 value = 0;
 521         bool xmac;
 522
 523         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 524
 525         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 526                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 527                 priv->hwts_tx_en = 0;
 528                 priv->hwts_rx_en = 0;
 529
 530                 return -EOPNOTSUPP;
 531         }
 532
 533         if (copy_from_user(&config, ifr->ifr_data,
 534                            sizeof(config)))
 535                 return -EFAULT;
 536
 537         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 538                    __func__, config.flags, config.tx_type, config.rx_filter);
 539
 540         /* reserved for future extensions */
 541         if (config.flags)
 542                 return -EINVAL;
 543
 544         if (config.tx_type != HWTSTAMP_TX_OFF &&
 545             config.tx_type != HWTSTAMP_TX_ON)
 546                 return -ERANGE;
 547
 548         if (priv->adv_ts) {
 549                 switch (config.rx_filter) {
 550                 case HWTSTAMP_FILTER_NONE:
 551                         /* time stamp no incoming packet at all */
 552                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 553                         break;
 554
 555                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 556                         /* PTP v1, UDP, any kind of event packet */
 557                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 558                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 559                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 560                          * This leaves Delay_Req timestamps out.
 561                          * Enable all events *and* general purpose message
 562                          * timestamping
 563                          */
 564                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 565                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 566                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 567                         break;
 568
 569                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 570                         /* PTP v1, UDP, Sync packet */
 571                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 572                         /* take time stamp for SYNC messages only */
 573                         ts_event_en = PTP_TCR_TSEVNTENA;
 574
 575                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 576                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 577                         break;
 578
 579                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 580                         /* PTP v1, UDP, Delay_req packet */
 581                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 582                         /* take time stamp for Delay_Req messages only */
 583                         ts_master_en = PTP_TCR_TSMSTRENA;
 584                         ts_event_en = PTP_TCR_TSEVNTENA;
 585
 586                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 587                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 588                         break;
 589
 590                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 591                         /* PTP v2, UDP, any kind of event packet */
 592                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 593                         ptp_v2 = PTP_TCR_TSVER2ENA;
 594                         /* take time stamp for all event messages */
 595                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 596
 597                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 598                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 599                         break;
 600
 601                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 602                         /* PTP v2, UDP, Sync packet */
 603                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 604                         ptp_v2 = PTP_TCR_TSVER2ENA;
 605                         /* take time stamp for SYNC messages only */
 606                         ts_event_en = PTP_TCR_TSEVNTENA;
 607
 608                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 609                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 610                         break;
 611
 612                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 613                         /* PTP v2, UDP, Delay_req packet */
 614                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 615                         ptp_v2 = PTP_TCR_TSVER2ENA;
 616                         /* take time stamp for Delay_Req messages only */
 617                         ts_master_en = PTP_TCR_TSMSTRENA;
 618                         ts_event_en = PTP_TCR_TSEVNTENA;
 619
 620                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 621                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 622                         break;
 623
 624                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 625                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 626                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 627                         ptp_v2 = PTP_TCR_TSVER2ENA;
 628                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 629                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 630                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 631                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 632                         break;
 633
 634                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 635                         /* PTP v2/802.AS1, any layer, Sync packet */
 636                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 637                         ptp_v2 = PTP_TCR_TSVER2ENA;
 638                         /* take time stamp for SYNC messages only */
 639                         ts_event_en = PTP_TCR_TSEVNTENA;
 640
 641                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 642                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 643                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 644                         break;
 645
 646                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 647                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 648                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 649                         ptp_v2 = PTP_TCR_TSVER2ENA;
 650                         /* take time stamp for Delay_Req messages only */
 651                         ts_master_en = PTP_TCR_TSMSTRENA;
 652                         ts_event_en = PTP_TCR_TSEVNTENA;
 653
 654                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 655                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 656                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 657                         break;
 658
 659                 case HWTSTAMP_FILTER_NTP_ALL:
 660                 case HWTSTAMP_FILTER_ALL:
 661                         /* time stamp any incoming packet */
 662                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 663                         tstamp_all = PTP_TCR_TSENALL;
 664                         break;
 665
 666                 default:
 667                         return -ERANGE;
 668                 }
 669         } else {
 670                 switch (config.rx_filter) {
 671                 case HWTSTAMP_FILTER_NONE:
 672                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 673                         break;
 674                 default:
 675                         /* PTP v1, UDP, any kind of event packet */
 676                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 677                         break;
 678                 }
 679         }
 680         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 681         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 682
 683         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 684                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 685         else {
 686                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 687                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 688                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 689                          ts_master_en | snap_type_sel);
 690                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 691
 692                 /* program Sub Second Increment reg */
 693                 stmmac_config_sub_second_increment(priv,
 694                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 695                                 xmac, &sec_inc);
 696                 temp = div_u64(1000000000ULL, sec_inc);
 697
 698                 /* Store sub second increment and flags for later use */
 699                 priv->sub_second_inc = sec_inc;
 700                 priv->systime_flags = value;
 701
 702                 /* calculate default added value:
 703                  * formula is :
 704                  * addend = (2^32)/freq_div_ratio;
 705                  * where, freq_div_ratio = 1e9ns/sec_inc
 706                  */
 707                 temp = (u64)(temp << 32);
 708                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 709                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 710
 711                 /* initialize system time */
 712                 ktime_get_real_ts64(&now);
 713
 714                 /* lower 32 bits of tv_sec are safe until y2106 */
 715                 stmmac_init_systime(priv, priv->ptpaddr,
 716                                 (u32)now.tv_sec, now.tv_nsec);
 717         }
 718
 719         memcpy(&priv->tstamp_config, &config, sizeof(config));
 720
 721         return copy_to_user(ifr->ifr_data, &config,
 722                             sizeof(config)) ? -EFAULT : 0;
 723 }
 724
 725 /**
 726  *  stmmac_hwtstamp_get - read hardware timestamping.
 727  *  @dev: device pointer.
 728  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 729  *  a proprietary structure used to pass information to the driver.
 730  *  Description:
 731  *  This function obtain the current hardware timestamping settings
 732     as requested.
 733  */
 734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 735 {
 736         struct stmmac_priv *priv = netdev_priv(dev);
 737         struct hwtstamp_config *config = &priv->tstamp_config;
 738
 739         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 740                 return -EOPNOTSUPP;
 741
 742         return copy_to_user(ifr->ifr_data, config,
 743                             sizeof(*config)) ? -EFAULT : 0;
 744 }
 745
 746 /**
 747  * stmmac_init_ptp - init PTP
 748  * @priv: driver private structure
 749  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 750  * This is done by looking at the HW cap. register.
 751  * This function also registers the ptp driver.
 752  */
 753 static int stmmac_init_ptp(struct stmmac_priv *priv)
 754 {
 755         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 756
 757         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 758                 return -EOPNOTSUPP;
 759
 760         priv->adv_ts = 0;
 761         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 762         if (xmac && priv->dma_cap.atime_stamp)
 763                 priv->adv_ts = 1;
 764         /* Dwmac 3.x core with extend_desc can support adv_ts */
 765         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 766                 priv->adv_ts = 1;
 767
 768         if (priv->dma_cap.time_stamp)
 769                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 770
 771         if (priv->adv_ts)
 772                 netdev_info(priv->dev,
 773                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 774
 775         priv->hwts_tx_en = 0;
 776         priv->hwts_rx_en = 0;
 777
 778         stmmac_ptp_register(priv);
 779
 780         return 0;
 781 }
 782
 783 static void stmmac_release_ptp(struct stmmac_priv *priv)
 784 {
 785         if (priv->plat->clk_ptp_ref)
 786                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 787         stmmac_ptp_unregister(priv);
 788 }
 789
 790 /**
 791  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 792  *  @priv: driver private structure
 793  *  Description: It is used for configuring the flow control in all queues
 794  */
 795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 796 {
 797         u32 tx_cnt = priv->plat->tx_queues_to_use;
 798
 799         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 800                         priv->pause, tx_cnt);
 801 }
 802
 803 static void stmmac_validate(struct phylink_config *config,
 804                             unsigned long *supported,
 805                             struct phylink_link_state *state)
 806 {
 807         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 808         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 809         int tx_cnt = priv->plat->tx_queues_to_use;
 810         int max_speed = priv->plat->max_speed;
 811
 812         /* Cut down 1G if asked to */
 813         if ((max_speed > 0) && (max_speed < 1000)) {
 814                 phylink_set(mask, 1000baseT_Full);
 815                 phylink_set(mask, 1000baseX_Full);
 816         }
 817
 818         /* Half-Duplex can only work with single queue */
 819         if (tx_cnt > 1) {
 820                 phylink_set(mask, 10baseT_Half);
 821                 phylink_set(mask, 100baseT_Half);
 822                 phylink_set(mask, 1000baseT_Half);
 823         }
 824
 825         bitmap_andnot(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 826         bitmap_andnot(state->advertising, state->advertising, mask,
 827                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 828 }
 829
 830 static int stmmac_mac_link_state(struct phylink_config *config,
 831                                  struct phylink_link_state *state)
 832 {
 833         return -EOPNOTSUPP;
 834 }
 835
 836 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 837                               const struct phylink_link_state *state)
 838 {
 839         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 840         u32 ctrl;
 841
 842         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 843         ctrl &= ~priv->hw->link.speed_mask;
 844
 845         switch (state->speed) {
 846         case SPEED_1000:
 847                 ctrl |= priv->hw->link.speed1000;
 848                 break;
 849         case SPEED_100:
 850                 ctrl |= priv->hw->link.speed100;
 851                 break;
 852         case SPEED_10:
 853                 ctrl |= priv->hw->link.speed10;
 854                 break;
 855         default:
 856                 return;
 857         }
 858
 859         priv->speed = state->speed;
 860
 861         if (priv->plat->fix_mac_speed)
 862                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
 863
 864         if (!state->duplex)
 865                 ctrl &= ~priv->hw->link.duplex;
 866         else
 867                 ctrl |= priv->hw->link.duplex;
 868
 869         /* Flow Control operation */
 870         if (state->pause)
 871                 stmmac_mac_flow_ctrl(priv, state->duplex);
 872
 873         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 874 }
 875
 876 static void stmmac_mac_an_restart(struct phylink_config *config)
 877 {
 878         /* Not Supported */
 879 }
 880
 881 static void stmmac_mac_link_down(struct phylink_config *config,
 882                                  unsigned int mode, phy_interface_t interface)
 883 {
 884         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 885
 886         stmmac_mac_set(priv, priv->ioaddr, false);
 887         priv->eee_active = false;
 888         stmmac_eee_init(priv);
 889         stmmac_set_eee_pls(priv, priv->hw, false);
 890 }
 891
 892 static void stmmac_mac_link_up(struct phylink_config *config,
 893                                unsigned int mode, phy_interface_t interface,
 894                                struct phy_device *phy)
 895 {
 896         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 897
 898         stmmac_mac_set(priv, priv->ioaddr, true);
 899         if (phy && priv->dma_cap.eee) {
 900                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
 901                 priv->eee_enabled = stmmac_eee_init(priv);
 902                 stmmac_set_eee_pls(priv, priv->hw, true);
 903         }
 904 }
 905
 906 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
 907         .validate = stmmac_validate,
 908         .mac_link_state = stmmac_mac_link_state,
 909         .mac_config = stmmac_mac_config,
 910         .mac_an_restart = stmmac_mac_an_restart,
 911         .mac_link_down = stmmac_mac_link_down,
 912         .mac_link_up = stmmac_mac_link_up,
 913 };
 914
 915 /**
 916  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 917  * @priv: driver private structure
 918  * Description: this is to verify if the HW supports the PCS.
 919  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 920  * configured for the TBI, RTBI, or SGMII PHY interface.
 921  */
 922 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 923 {
 924         int interface = priv->plat->interface;
 925
 926         if (priv->dma_cap.pcs) {
 927                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 928                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 929                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 930                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 931                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 932                         priv->hw->pcs = STMMAC_PCS_RGMII;
 933                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 934                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 935                         priv->hw->pcs = STMMAC_PCS_SGMII;
 936                 }
 937         }
 938 }
 939
 940 /**
 941  * stmmac_init_phy - PHY initialization
 942  * @dev: net device structure
 943  * Description: it initializes the driver's PHY state, and attaches the PHY
 944  * to the mac driver.
 945  *  Return value:
 946  *  0 on success
 947  */
 948 static int stmmac_init_phy(struct net_device *dev)
 949 {
 950         struct stmmac_priv *priv = netdev_priv(dev);
 951         struct device_node *node;
 952         int ret;
 953
 954         node = priv->plat->phylink_node;
 955
 956         if (node)
 957                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
 958
 959         /* Some DT bindings do not set-up the PHY handle. Let's try to
 960          * manually parse it
 961          */
 962         if (!node || ret) {
 963                 int addr = priv->plat->phy_addr;
 964                 struct phy_device *phydev;
 965
 966                 phydev = mdiobus_get_phy(priv->mii, addr);
 967                 if (!phydev) {
 968                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
 969                         return -ENODEV;
 970                 }
 971
 972                 ret = phylink_connect_phy(priv->phylink, phydev);
 973         }
 974
 975         return ret;
 976 }
 977
 978 static int stmmac_phy_setup(struct stmmac_priv *priv)
 979 {
 980         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
 981         int mode = priv->plat->interface;
 982         struct phylink *phylink;
 983
 984         priv->phylink_config.dev = &priv->dev->dev;
 985         priv->phylink_config.type = PHYLINK_NETDEV;
 986
 987         phylink = phylink_create(&priv->phylink_config, fwnode,
 988                                  mode, &stmmac_phylink_mac_ops);
 989         if (IS_ERR(phylink))
 990                 return PTR_ERR(phylink);
 991
 992         priv->phylink = phylink;
 993         return 0;
 994 }
 995
 996 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
 997 {
 998         u32 rx_cnt = priv->plat->rx_queues_to_use;
 999         void *head_rx;
1000         u32 queue;
1001
1002         /* Display RX rings */
1003         for (queue = 0; queue < rx_cnt; queue++) {
1004                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1005
1006                 pr_info("\tRX Queue %u rings\n", queue);
1007
1008                 if (priv->extend_desc)
1009                         head_rx = (void *)rx_q->dma_erx;
1010                 else
1011                         head_rx = (void *)rx_q->dma_rx;
1012
1013                 /* Display RX ring */
1014                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1015         }
1016 }
1017
1018 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1019 {
1020         u32 tx_cnt = priv->plat->tx_queues_to_use;
1021         void *head_tx;
1022         u32 queue;
1023
1024         /* Display TX rings */
1025         for (queue = 0; queue < tx_cnt; queue++) {
1026                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1027
1028                 pr_info("\tTX Queue %d rings\n", queue);
1029
1030                 if (priv->extend_desc)
1031                         head_tx = (void *)tx_q->dma_etx;
1032                 else
1033                         head_tx = (void *)tx_q->dma_tx;
1034
1035                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1036         }
1037 }
1038
1039 static void stmmac_display_rings(struct stmmac_priv *priv)
1040 {
1041         /* Display RX ring */
1042         stmmac_display_rx_rings(priv);
1043
1044         /* Display TX ring */
1045         stmmac_display_tx_rings(priv);
1046 }
1047
1048 static int stmmac_set_bfsize(int mtu, int bufsize)
1049 {
1050         int ret = bufsize;
1051
1052         if (mtu >= BUF_SIZE_4KiB)
1053                 ret = BUF_SIZE_8KiB;
1054         else if (mtu >= BUF_SIZE_2KiB)
1055                 ret = BUF_SIZE_4KiB;
1056         else if (mtu > DEFAULT_BUFSIZE)
1057                 ret = BUF_SIZE_2KiB;
1058         else
1059                 ret = DEFAULT_BUFSIZE;
1060
1061         return ret;
1062 }
1063
1064 /**
1065  * stmmac_clear_rx_descriptors - clear RX descriptors
1066  * @priv: driver private structure
1067  * @queue: RX queue index
1068  * Description: this function is called to clear the RX descriptors
1069  * in case of both basic and extended descriptors are used.
1070  */
1071 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1072 {
1073         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1074         int i;
1075
1076         /* Clear the RX descriptors */
1077         for (i = 0; i < DMA_RX_SIZE; i++)
1078                 if (priv->extend_desc)
1079                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1080                                         priv->use_riwt, priv->mode,
1081                                         (i == DMA_RX_SIZE - 1),
1082                                         priv->dma_buf_sz);
1083                 else
1084                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1085                                         priv->use_riwt, priv->mode,
1086                                         (i == DMA_RX_SIZE - 1),
1087                                         priv->dma_buf_sz);
1088 }
1089
1090 /**
1091  * stmmac_clear_tx_descriptors - clear tx descriptors
1092  * @priv: driver private structure
1093  * @queue: TX queue index.
1094  * Description: this function is called to clear the TX descriptors
1095  * in case of both basic and extended descriptors are used.
1096  */
1097 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1098 {
1099         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1100         int i;
1101
1102         /* Clear the TX descriptors */
1103         for (i = 0; i < DMA_TX_SIZE; i++)
1104                 if (priv->extend_desc)
1105                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1106                                         priv->mode, (i == DMA_TX_SIZE - 1));
1107                 else
1108                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1109                                         priv->mode, (i == DMA_TX_SIZE - 1));
1110 }
1111
1112 /**
1113  * stmmac_clear_descriptors - clear descriptors
1114  * @priv: driver private structure
1115  * Description: this function is called to clear the TX and RX descriptors
1116  * in case of both basic and extended descriptors are used.
1117  */
1118 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1119 {
1120         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1121         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1122         u32 queue;
1123
1124         /* Clear the RX descriptors */
1125         for (queue = 0; queue < rx_queue_cnt; queue++)
1126                 stmmac_clear_rx_descriptors(priv, queue);
1127
1128         /* Clear the TX descriptors */
1129         for (queue = 0; queue < tx_queue_cnt; queue++)
1130                 stmmac_clear_tx_descriptors(priv, queue);
1131 }
1132
1133 /**
1134  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1135  * @priv: driver private structure
1136  * @p: descriptor pointer
1137  * @i: descriptor index
1138  * @flags: gfp flag
1139  * @queue: RX queue index
1140  * Description: this function is called to allocate a receive buffer, perform
1141  * the DMA mapping and init the descriptor.
1142  */
1143 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1144                                   int i, gfp_t flags, u32 queue)
1145 {
1146         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1147         struct sk_buff *skb;
1148
1149         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1150         if (!skb) {
1151                 netdev_err(priv->dev,
1152                            "%s: Rx init fails; skb is NULL\n", __func__);
1153                 return -ENOMEM;
1154         }
1155         rx_q->rx_skbuff[i] = skb;
1156         rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1157                                                 priv->dma_buf_sz,
1158                                                 DMA_FROM_DEVICE);
1159         if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1160                 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1161                 dev_kfree_skb_any(skb);
1162                 return -EINVAL;
1163         }
1164
1165         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1166
1167         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1168                 stmmac_init_desc3(priv, p);
1169
1170         return 0;
1171 }
1172
1173 /**
1174  * stmmac_free_rx_buffer - free RX dma buffers
1175  * @priv: private structure
1176  * @queue: RX queue index
1177  * @i: buffer index.
1178  */
1179 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1180 {
1181         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1182
1183         if (rx_q->rx_skbuff[i]) {
1184                 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1185                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1186                 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1187         }
1188         rx_q->rx_skbuff[i] = NULL;
1189 }
1190
1191 /**
1192  * stmmac_free_tx_buffer - free RX dma buffers
1193  * @priv: private structure
1194  * @queue: RX queue index
1195  * @i: buffer index.
1196  */
1197 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1198 {
1199         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1200
1201         if (tx_q->tx_skbuff_dma[i].buf) {
1202                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1203                         dma_unmap_page(priv->device,
1204                                        tx_q->tx_skbuff_dma[i].buf,
1205                                        tx_q->tx_skbuff_dma[i].len,
1206                                        DMA_TO_DEVICE);
1207                 else
1208                         dma_unmap_single(priv->device,
1209                                          tx_q->tx_skbuff_dma[i].buf,
1210                                          tx_q->tx_skbuff_dma[i].len,
1211                                          DMA_TO_DEVICE);
1212         }
1213
1214         if (tx_q->tx_skbuff[i]) {
1215                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1216                 tx_q->tx_skbuff[i] = NULL;
1217                 tx_q->tx_skbuff_dma[i].buf = 0;
1218                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1219         }
1220 }
1221
1222 /**
1223  * init_dma_rx_desc_rings - init the RX descriptor rings
1224  * @dev: net device structure
1225  * @flags: gfp flag.
1226  * Description: this function initializes the DMA RX descriptors
1227  * and allocates the socket buffers. It supports the chained and ring
1228  * modes.
1229  */
1230 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1231 {
1232         struct stmmac_priv *priv = netdev_priv(dev);
1233         u32 rx_count = priv->plat->rx_queues_to_use;
1234         int ret = -ENOMEM;
1235         int bfsize = 0;
1236         int queue;
1237         int i;
1238
1239         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1240         if (bfsize < 0)
1241                 bfsize = 0;
1242
1243         if (bfsize < BUF_SIZE_16KiB)
1244                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1245
1246         priv->dma_buf_sz = bfsize;
1247
1248         /* RX INITIALIZATION */
1249         netif_dbg(priv, probe, priv->dev,
1250                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1251
1252         for (queue = 0; queue < rx_count; queue++) {
1253                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1254
1255                 netif_dbg(priv, probe, priv->dev,
1256                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1257                           (u32)rx_q->dma_rx_phy);
1258
1259                 for (i = 0; i < DMA_RX_SIZE; i++) {
1260                         struct dma_desc *p;
1261
1262                         if (priv->extend_desc)
1263                                 p = &((rx_q->dma_erx + i)->basic);
1264                         else
1265                                 p = rx_q->dma_rx + i;
1266
1267                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1268                                                      queue);
1269                         if (ret)
1270                                 goto err_init_rx_buffers;
1271
1272                         netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1273                                   rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1274                                   (unsigned int)rx_q->rx_skbuff_dma[i]);
1275                 }
1276
1277                 rx_q->cur_rx = 0;
1278                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1279
1280                 stmmac_clear_rx_descriptors(priv, queue);
1281
1282                 /* Setup the chained descriptor addresses */
1283                 if (priv->mode == STMMAC_CHAIN_MODE) {
1284                         if (priv->extend_desc)
1285                                 stmmac_mode_init(priv, rx_q->dma_erx,
1286                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1287                         else
1288                                 stmmac_mode_init(priv, rx_q->dma_rx,
1289                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1290                 }
1291         }
1292
1293         buf_sz = bfsize;
1294
1295         return 0;
1296
1297 err_init_rx_buffers:
1298         while (queue >= 0) {
1299                 while (--i >= 0)
1300                         stmmac_free_rx_buffer(priv, queue, i);
1301
1302                 if (queue == 0)
1303                         break;
1304
1305                 i = DMA_RX_SIZE;
1306                 queue--;
1307         }
1308
1309         return ret;
1310 }
1311
1312 /**
1313  * init_dma_tx_desc_rings - init the TX descriptor rings
1314  * @dev: net device structure.
1315  * Description: this function initializes the DMA TX descriptors
1316  * and allocates the socket buffers. It supports the chained and ring
1317  * modes.
1318  */
1319 static int init_dma_tx_desc_rings(struct net_device *dev)
1320 {
1321         struct stmmac_priv *priv = netdev_priv(dev);
1322         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1323         u32 queue;
1324         int i;
1325
1326         for (queue = 0; queue < tx_queue_cnt; queue++) {
1327                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1328
1329                 netif_dbg(priv, probe, priv->dev,
1330                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1331                          (u32)tx_q->dma_tx_phy);
1332
1333                 /* Setup the chained descriptor addresses */
1334                 if (priv->mode == STMMAC_CHAIN_MODE) {
1335                         if (priv->extend_desc)
1336                                 stmmac_mode_init(priv, tx_q->dma_etx,
1337                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1338                         else
1339                                 stmmac_mode_init(priv, tx_q->dma_tx,
1340                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1341                 }
1342
1343                 for (i = 0; i < DMA_TX_SIZE; i++) {
1344                         struct dma_desc *p;
1345                         if (priv->extend_desc)
1346                                 p = &((tx_q->dma_etx + i)->basic);
1347                         else
1348                                 p = tx_q->dma_tx + i;
1349
1350                         stmmac_clear_desc(priv, p);
1351
1352                         tx_q->tx_skbuff_dma[i].buf = 0;
1353                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1354                         tx_q->tx_skbuff_dma[i].len = 0;
1355                         tx_q->tx_skbuff_dma[i].last_segment = false;
1356                         tx_q->tx_skbuff[i] = NULL;
1357                 }
1358
1359                 tx_q->dirty_tx = 0;
1360                 tx_q->cur_tx = 0;
1361                 tx_q->mss = 0;
1362
1363                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1364         }
1365
1366         return 0;
1367 }
1368
1369 /**
1370  * init_dma_desc_rings - init the RX/TX descriptor rings
1371  * @dev: net device structure
1372  * @flags: gfp flag.
1373  * Description: this function initializes the DMA RX/TX descriptors
1374  * and allocates the socket buffers. It supports the chained and ring
1375  * modes.
1376  */
1377 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1378 {
1379         struct stmmac_priv *priv = netdev_priv(dev);
1380         int ret;
1381
1382         ret = init_dma_rx_desc_rings(dev, flags);
1383         if (ret)
1384                 return ret;
1385
1386         ret = init_dma_tx_desc_rings(dev);
1387
1388         stmmac_clear_descriptors(priv);
1389
1390         if (netif_msg_hw(priv))
1391                 stmmac_display_rings(priv);
1392
1393         return ret;
1394 }
1395
1396 /**
1397  * dma_free_rx_skbufs - free RX dma buffers
1398  * @priv: private structure
1399  * @queue: RX queue index
1400  */
1401 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1402 {
1403         int i;
1404
1405         for (i = 0; i < DMA_RX_SIZE; i++)
1406                 stmmac_free_rx_buffer(priv, queue, i);
1407 }
1408
1409 /**
1410  * dma_free_tx_skbufs - free TX dma buffers
1411  * @priv: private structure
1412  * @queue: TX queue index
1413  */
1414 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1415 {
1416         int i;
1417
1418         for (i = 0; i < DMA_TX_SIZE; i++)
1419                 stmmac_free_tx_buffer(priv, queue, i);
1420 }
1421
1422 /**
1423  * free_dma_rx_desc_resources - free RX dma desc resources
1424  * @priv: private structure
1425  */
1426 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1427 {
1428         u32 rx_count = priv->plat->rx_queues_to_use;
1429         u32 queue;
1430
1431         /* Free RX queue resources */
1432         for (queue = 0; queue < rx_count; queue++) {
1433                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1434
1435                 /* Release the DMA RX socket buffers */
1436                 dma_free_rx_skbufs(priv, queue);
1437
1438                 /* Free DMA regions of consistent memory previously allocated */
1439                 if (!priv->extend_desc)
1440                         dma_free_coherent(priv->device,
1441                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1442                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1443                 else
1444                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1445                                           sizeof(struct dma_extended_desc),
1446                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1447
1448                 kfree(rx_q->rx_skbuff_dma);
1449                 kfree(rx_q->rx_skbuff);
1450         }
1451 }
1452
1453 /**
1454  * free_dma_tx_desc_resources - free TX dma desc resources
1455  * @priv: private structure
1456  */
1457 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1458 {
1459         u32 tx_count = priv->plat->tx_queues_to_use;
1460         u32 queue;
1461
1462         /* Free TX queue resources */
1463         for (queue = 0; queue < tx_count; queue++) {
1464                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1465
1466                 /* Release the DMA TX socket buffers */
1467                 dma_free_tx_skbufs(priv, queue);
1468
1469                 /* Free DMA regions of consistent memory previously allocated */
1470                 if (!priv->extend_desc)
1471                         dma_free_coherent(priv->device,
1472                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1473                                           tx_q->dma_tx, tx_q->dma_tx_phy);
1474                 else
1475                         dma_free_coherent(priv->device, DMA_TX_SIZE *
1476                                           sizeof(struct dma_extended_desc),
1477                                           tx_q->dma_etx, tx_q->dma_tx_phy);
1478
1479                 kfree(tx_q->tx_skbuff_dma);
1480                 kfree(tx_q->tx_skbuff);
1481         }
1482 }
1483
1484 /**
1485  * alloc_dma_rx_desc_resources - alloc RX resources.
1486  * @priv: private structure
1487  * Description: according to which descriptor can be used (extend or basic)
1488  * this function allocates the resources for TX and RX paths. In case of
1489  * reception, for example, it pre-allocated the RX socket buffer in order to
1490  * allow zero-copy mechanism.
1491  */
1492 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1493 {
1494         u32 rx_count = priv->plat->rx_queues_to_use;
1495         int ret = -ENOMEM;
1496         u32 queue;
1497
1498         /* RX queues buffers and DMA */
1499         for (queue = 0; queue < rx_count; queue++) {
1500                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1501
1502                 rx_q->queue_index = queue;
1503                 rx_q->priv_data = priv;
1504
1505                 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1506                                                     sizeof(dma_addr_t),
1507                                                     GFP_KERNEL);
1508                 if (!rx_q->rx_skbuff_dma)
1509                         goto err_dma;
1510
1511                 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1512                                                 sizeof(struct sk_buff *),
1513                                                 GFP_KERNEL);
1514                 if (!rx_q->rx_skbuff)
1515                         goto err_dma;
1516
1517                 if (priv->extend_desc) {
1518                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1519                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1520                                                            &rx_q->dma_rx_phy,
1521                                                            GFP_KERNEL);
1522                         if (!rx_q->dma_erx)
1523                                 goto err_dma;
1524
1525                 } else {
1526                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1527                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1528                                                           &rx_q->dma_rx_phy,
1529                                                           GFP_KERNEL);
1530                         if (!rx_q->dma_rx)
1531                                 goto err_dma;
1532                 }
1533         }
1534
1535         return 0;
1536
1537 err_dma:
1538         free_dma_rx_desc_resources(priv);
1539
1540         return ret;
1541 }
1542
1543 /**
1544  * alloc_dma_tx_desc_resources - alloc TX resources.
1545  * @priv: private structure
1546  * Description: according to which descriptor can be used (extend or basic)
1547  * this function allocates the resources for TX and RX paths. In case of
1548  * reception, for example, it pre-allocated the RX socket buffer in order to
1549  * allow zero-copy mechanism.
1550  */
1551 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1552 {
1553         u32 tx_count = priv->plat->tx_queues_to_use;
1554         int ret = -ENOMEM;
1555         u32 queue;
1556
1557         /* TX queues buffers and DMA */
1558         for (queue = 0; queue < tx_count; queue++) {
1559                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1560
1561                 tx_q->queue_index = queue;
1562                 tx_q->priv_data = priv;
1563
1564                 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1565                                                     sizeof(*tx_q->tx_skbuff_dma),
1566                                                     GFP_KERNEL);
1567                 if (!tx_q->tx_skbuff_dma)
1568                         goto err_dma;
1569
1570                 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1571                                                 sizeof(struct sk_buff *),
1572                                                 GFP_KERNEL);
1573                 if (!tx_q->tx_skbuff)
1574                         goto err_dma;
1575
1576                 if (priv->extend_desc) {
1577                         tx_q->dma_etx = dma_alloc_coherent(priv->device,
1578                                                            DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1579                                                            &tx_q->dma_tx_phy,
1580                                                            GFP_KERNEL);
1581                         if (!tx_q->dma_etx)
1582                                 goto err_dma;
1583                 } else {
1584                         tx_q->dma_tx = dma_alloc_coherent(priv->device,
1585                                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1586                                                           &tx_q->dma_tx_phy,
1587                                                           GFP_KERNEL);
1588                         if (!tx_q->dma_tx)
1589                                 goto err_dma;
1590                 }
1591         }
1592
1593         return 0;
1594
1595 err_dma:
1596         free_dma_tx_desc_resources(priv);
1597
1598         return ret;
1599 }
1600
1601 /**
1602  * alloc_dma_desc_resources - alloc TX/RX resources.
1603  * @priv: private structure
1604  * Description: according to which descriptor can be used (extend or basic)
1605  * this function allocates the resources for TX and RX paths. In case of
1606  * reception, for example, it pre-allocated the RX socket buffer in order to
1607  * allow zero-copy mechanism.
1608  */
1609 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1610 {
1611         /* RX Allocation */
1612         int ret = alloc_dma_rx_desc_resources(priv);
1613
1614         if (ret)
1615                 return ret;
1616
1617         ret = alloc_dma_tx_desc_resources(priv);
1618
1619         return ret;
1620 }
1621
1622 /**
1623  * free_dma_desc_resources - free dma desc resources
1624  * @priv: private structure
1625  */
1626 static void free_dma_desc_resources(struct stmmac_priv *priv)
1627 {
1628         /* Release the DMA RX socket buffers */
1629         free_dma_rx_desc_resources(priv);
1630
1631         /* Release the DMA TX socket buffers */
1632         free_dma_tx_desc_resources(priv);
1633 }
1634
1635 /**
1636  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1637  *  @priv: driver private structure
1638  *  Description: It is used for enabling the rx queues in the MAC
1639  */
1640 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1641 {
1642         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1643         int queue;
1644         u8 mode;
1645
1646         for (queue = 0; queue < rx_queues_count; queue++) {
1647                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1648                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1649         }
1650 }
1651
1652 /**
1653  * stmmac_start_rx_dma - start RX DMA channel
1654  * @priv: driver private structure
1655  * @chan: RX channel index
1656  * Description:
1657  * This starts a RX DMA channel
1658  */
1659 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1660 {
1661         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1662         stmmac_start_rx(priv, priv->ioaddr, chan);
1663 }
1664
1665 /**
1666  * stmmac_start_tx_dma - start TX DMA channel
1667  * @priv: driver private structure
1668  * @chan: TX channel index
1669  * Description:
1670  * This starts a TX DMA channel
1671  */
1672 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1673 {
1674         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1675         stmmac_start_tx(priv, priv->ioaddr, chan);
1676 }
1677
1678 /**
1679  * stmmac_stop_rx_dma - stop RX DMA channel
1680  * @priv: driver private structure
1681  * @chan: RX channel index
1682  * Description:
1683  * This stops a RX DMA channel
1684  */
1685 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1686 {
1687         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1688         stmmac_stop_rx(priv, priv->ioaddr, chan);
1689 }
1690
1691 /**
1692  * stmmac_stop_tx_dma - stop TX DMA channel
1693  * @priv: driver private structure
1694  * @chan: TX channel index
1695  * Description:
1696  * This stops a TX DMA channel
1697  */
1698 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1699 {
1700         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1701         stmmac_stop_tx(priv, priv->ioaddr, chan);
1702 }
1703
1704 /**
1705  * stmmac_start_all_dma - start all RX and TX DMA channels
1706  * @priv: driver private structure
1707  * Description:
1708  * This starts all the RX and TX DMA channels
1709  */
1710 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1711 {
1712         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1713         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1714         u32 chan = 0;
1715
1716         for (chan = 0; chan < rx_channels_count; chan++)
1717                 stmmac_start_rx_dma(priv, chan);
1718
1719         for (chan = 0; chan < tx_channels_count; chan++)
1720                 stmmac_start_tx_dma(priv, chan);
1721 }
1722
1723 /**
1724  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1725  * @priv: driver private structure
1726  * Description:
1727  * This stops the RX and TX DMA channels
1728  */
1729 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1730 {
1731         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1732         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1733         u32 chan = 0;
1734
1735         for (chan = 0; chan < rx_channels_count; chan++)
1736                 stmmac_stop_rx_dma(priv, chan);
1737
1738         for (chan = 0; chan < tx_channels_count; chan++)
1739                 stmmac_stop_tx_dma(priv, chan);
1740 }
1741
1742 /**
1743  *  stmmac_dma_operation_mode - HW DMA operation mode
1744  *  @priv: driver private structure
1745  *  Description: it is used for configuring the DMA operation mode register in
1746  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1747  */
1748 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1749 {
1750         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1751         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1752         int rxfifosz = priv->plat->rx_fifo_size;
1753         int txfifosz = priv->plat->tx_fifo_size;
1754         u32 txmode = 0;
1755         u32 rxmode = 0;
1756         u32 chan = 0;
1757         u8 qmode = 0;
1758
1759         if (rxfifosz == 0)
1760                 rxfifosz = priv->dma_cap.rx_fifo_size;
1761         if (txfifosz == 0)
1762                 txfifosz = priv->dma_cap.tx_fifo_size;
1763
1764         /* Adjust for real per queue fifo size */
1765         rxfifosz /= rx_channels_count;
1766         txfifosz /= tx_channels_count;
1767
1768         if (priv->plat->force_thresh_dma_mode) {
1769                 txmode = tc;
1770                 rxmode = tc;
1771         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1772                 /*
1773                  * In case of GMAC, SF mode can be enabled
1774                  * to perform the TX COE in HW. This depends on:
1775                  * 1) TX COE if actually supported
1776                  * 2) There is no bugged Jumbo frame support
1777                  *    that needs to not insert csum in the TDES.
1778                  */
1779                 txmode = SF_DMA_MODE;
1780                 rxmode = SF_DMA_MODE;
1781                 priv->xstats.threshold = SF_DMA_MODE;
1782         } else {
1783                 txmode = tc;
1784                 rxmode = SF_DMA_MODE;
1785         }
1786
1787         /* configure all channels */
1788         for (chan = 0; chan < rx_channels_count; chan++) {
1789                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1790
1791                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1792                                 rxfifosz, qmode);
1793                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1794                                 chan);
1795         }
1796
1797         for (chan = 0; chan < tx_channels_count; chan++) {
1798                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1799
1800                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1801                                 txfifosz, qmode);
1802         }
1803 }
1804
1805 /**
1806  * stmmac_tx_clean - to manage the transmission completion
1807  * @priv: driver private structure
1808  * @queue: TX queue index
1809  * Description: it reclaims the transmit resources after transmission completes.
1810  */
1811 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1812 {
1813         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1814         unsigned int bytes_compl = 0, pkts_compl = 0;
1815         unsigned int entry, count = 0;
1816
1817         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1818
1819         priv->xstats.tx_clean++;
1820
1821         entry = tx_q->dirty_tx;
1822         while ((entry != tx_q->cur_tx) && (count < budget)) {
1823                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1824                 struct dma_desc *p;
1825                 int status;
1826
1827                 if (priv->extend_desc)
1828                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1829                 else
1830                         p = tx_q->dma_tx + entry;
1831
1832                 status = stmmac_tx_status(priv, &priv->dev->stats,
1833                                 &priv->xstats, p, priv->ioaddr);
1834                 /* Check if the descriptor is owned by the DMA */
1835                 if (unlikely(status & tx_dma_own))
1836                         break;
1837
1838                 count++;
1839
1840                 /* Make sure descriptor fields are read after reading
1841                  * the own bit.
1842                  */
1843                 dma_rmb();
1844
1845                 /* Just consider the last segment and ...*/
1846                 if (likely(!(status & tx_not_ls))) {
1847                         /* ... verify the status error condition */
1848                         if (unlikely(status & tx_err)) {
1849                                 priv->dev->stats.tx_errors++;
1850                         } else {
1851                                 priv->dev->stats.tx_packets++;
1852                                 priv->xstats.tx_pkt_n++;
1853                         }
1854                         stmmac_get_tx_hwtstamp(priv, p, skb);
1855                 }
1856
1857                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1858                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
1859                                 dma_unmap_page(priv->device,
1860                                                tx_q->tx_skbuff_dma[entry].buf,
1861                                                tx_q->tx_skbuff_dma[entry].len,
1862                                                DMA_TO_DEVICE);
1863                         else
1864                                 dma_unmap_single(priv->device,
1865                                                  tx_q->tx_skbuff_dma[entry].buf,
1866                                                  tx_q->tx_skbuff_dma[entry].len,
1867                                                  DMA_TO_DEVICE);
1868                         tx_q->tx_skbuff_dma[entry].buf = 0;
1869                         tx_q->tx_skbuff_dma[entry].len = 0;
1870                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
1871                 }
1872
1873                 stmmac_clean_desc3(priv, tx_q, p);
1874
1875                 tx_q->tx_skbuff_dma[entry].last_segment = false;
1876                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1877
1878                 if (likely(skb != NULL)) {
1879                         pkts_compl++;
1880                         bytes_compl += skb->len;
1881                         dev_consume_skb_any(skb);
1882                         tx_q->tx_skbuff[entry] = NULL;
1883                 }
1884
1885                 stmmac_release_tx_desc(priv, p, priv->mode);
1886
1887                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1888         }
1889         tx_q->dirty_tx = entry;
1890
1891         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1892                                   pkts_compl, bytes_compl);
1893
1894         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1895                                                                 queue))) &&
1896             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1897
1898                 netif_dbg(priv, tx_done, priv->dev,
1899                           "%s: restart transmit\n", __func__);
1900                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1901         }
1902
1903         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1904                 stmmac_enable_eee_mode(priv);
1905                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1906         }
1907
1908         /* We still have pending packets, let's call for a new scheduling */
1909         if (tx_q->dirty_tx != tx_q->cur_tx)
1910                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1911
1912         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1913
1914         return count;
1915 }
1916
1917 /**
1918  * stmmac_tx_err - to manage the tx error
1919  * @priv: driver private structure
1920  * @chan: channel index
1921  * Description: it cleans the descriptors and restarts the transmission
1922  * in case of transmission errors.
1923  */
1924 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1925 {
1926         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1927         int i;
1928
1929         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1930
1931         stmmac_stop_tx_dma(priv, chan);
1932         dma_free_tx_skbufs(priv, chan);
1933         for (i = 0; i < DMA_TX_SIZE; i++)
1934                 if (priv->extend_desc)
1935                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1936                                         priv->mode, (i == DMA_TX_SIZE - 1));
1937                 else
1938                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1939                                         priv->mode, (i == DMA_TX_SIZE - 1));
1940         tx_q->dirty_tx = 0;
1941         tx_q->cur_tx = 0;
1942         tx_q->mss = 0;
1943         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1944         stmmac_start_tx_dma(priv, chan);
1945
1946         priv->dev->stats.tx_errors++;
1947         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1948 }
1949
1950 /**
1951  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1952  *  @priv: driver private structure
1953  *  @txmode: TX operating mode
1954  *  @rxmode: RX operating mode
1955  *  @chan: channel index
1956  *  Description: it is used for configuring of the DMA operation mode in
1957  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1958  *  mode.
1959  */
1960 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
1961                                           u32 rxmode, u32 chan)
1962 {
1963         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1964         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1965         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1966         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1967         int rxfifosz = priv->plat->rx_fifo_size;
1968         int txfifosz = priv->plat->tx_fifo_size;
1969
1970         if (rxfifosz == 0)
1971                 rxfifosz = priv->dma_cap.rx_fifo_size;
1972         if (txfifosz == 0)
1973                 txfifosz = priv->dma_cap.tx_fifo_size;
1974
1975         /* Adjust for real per queue fifo size */
1976         rxfifosz /= rx_channels_count;
1977         txfifosz /= tx_channels_count;
1978
1979         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
1980         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
1981 }
1982
1983 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
1984 {
1985         int ret;
1986
1987         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
1988                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
1989         if (ret && (ret != -EINVAL)) {
1990                 stmmac_global_err(priv);
1991                 return true;
1992         }
1993
1994         return false;
1995 }
1996
1997 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
1998 {
1999         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2000                                                  &priv->xstats, chan);
2001         struct stmmac_channel *ch = &priv->channel[chan];
2002
2003         if (status)
2004                 status |= handle_rx | handle_tx;
2005
2006         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2007                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2008                 napi_schedule_irqoff(&ch->rx_napi);
2009         }
2010
2011         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2012                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2013                 napi_schedule_irqoff(&ch->tx_napi);
2014         }
2015
2016         return status;
2017 }
2018
2019 /**
2020  * stmmac_dma_interrupt - DMA ISR
2021  * @priv: driver private structure
2022  * Description: this is the DMA ISR. It is called by the main ISR.
2023  * It calls the dwmac dma routine and schedule poll method in case of some
2024  * work can be done.
2025  */
2026 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2027 {
2028         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2029         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2030         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2031                                 tx_channel_count : rx_channel_count;
2032         u32 chan;
2033         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2034
2035         /* Make sure we never check beyond our status buffer. */
2036         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2037                 channels_to_check = ARRAY_SIZE(status);
2038
2039         for (chan = 0; chan < channels_to_check; chan++)
2040                 status[chan] = stmmac_napi_check(priv, chan);
2041
2042         for (chan = 0; chan < tx_channel_count; chan++) {
2043                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2044                         /* Try to bump up the dma threshold on this failure */
2045                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2046                             (tc <= 256)) {
2047                                 tc += 64;
2048                                 if (priv->plat->force_thresh_dma_mode)
2049                                         stmmac_set_dma_operation_mode(priv,
2050                                                                       tc,
2051                                                                       tc,
2052                                                                       chan);
2053                                 else
2054                                         stmmac_set_dma_operation_mode(priv,
2055                                                                     tc,
2056                                                                     SF_DMA_MODE,
2057                                                                     chan);
2058                                 priv->xstats.threshold = tc;
2059                         }
2060                 } else if (unlikely(status[chan] == tx_hard_error)) {
2061                         stmmac_tx_err(priv, chan);
2062                 }
2063         }
2064 }
2065
2066 /**
2067  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2068  * @priv: driver private structure
2069  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2070  */
2071 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2072 {
2073         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2074                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2075
2076         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2077
2078         if (priv->dma_cap.rmon) {
2079                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2080                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2081         } else
2082                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2083 }
2084
2085 /**
2086  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2087  * @priv: driver private structure
2088  * Description:
2089  *  new GMAC chip generations have a new register to indicate the
2090  *  presence of the optional feature/functions.
2091  *  This can be also used to override the value passed through the
2092  *  platform and necessary for old MAC10/100 and GMAC chips.
2093  */
2094 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2095 {
2096         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2097 }
2098
2099 /**
2100  * stmmac_check_ether_addr - check if the MAC addr is valid
2101  * @priv: driver private structure
2102  * Description:
2103  * it is to verify if the MAC address is valid, in case of failures it
2104  * generates a random MAC address
2105  */
2106 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2107 {
2108         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2109                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2110                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2111                         eth_hw_addr_random(priv->dev);
2112                 dev_info(priv->device, "device MAC address %pM\n",
2113                          priv->dev->dev_addr);
2114         }
2115 }
2116
2117 /**
2118  * stmmac_init_dma_engine - DMA init.
2119  * @priv: driver private structure
2120  * Description:
2121  * It inits the DMA invoking the specific MAC/GMAC callback.
2122  * Some DMA parameters can be passed from the platform;
2123  * in case of these are not passed a default is kept for the MAC or GMAC.
2124  */
2125 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2126 {
2127         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2128         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2129         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2130         struct stmmac_rx_queue *rx_q;
2131         struct stmmac_tx_queue *tx_q;
2132         u32 chan = 0;
2133         int atds = 0;
2134         int ret = 0;
2135
2136         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2137                 dev_err(priv->device, "Invalid DMA configuration\n");
2138                 return -EINVAL;
2139         }
2140
2141         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2142                 atds = 1;
2143
2144         ret = stmmac_reset(priv, priv->ioaddr);
2145         if (ret) {
2146                 dev_err(priv->device, "Failed to reset the dma\n");
2147                 return ret;
2148         }
2149
2150         /* DMA Configuration */
2151         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2152
2153         if (priv->plat->axi)
2154                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2155
2156         /* DMA CSR Channel configuration */
2157         for (chan = 0; chan < dma_csr_ch; chan++)
2158                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2159
2160         /* DMA RX Channel Configuration */
2161         for (chan = 0; chan < rx_channels_count; chan++) {
2162                 rx_q = &priv->rx_queue[chan];
2163
2164                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2165                                     rx_q->dma_rx_phy, chan);
2166
2167                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2168                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2169                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2170                                        rx_q->rx_tail_addr, chan);
2171         }
2172
2173         /* DMA TX Channel Configuration */
2174         for (chan = 0; chan < tx_channels_count; chan++) {
2175                 tx_q = &priv->tx_queue[chan];
2176
2177                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2178                                     tx_q->dma_tx_phy, chan);
2179
2180                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2181                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2182                                        tx_q->tx_tail_addr, chan);
2183         }
2184
2185         return ret;
2186 }
2187
2188 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2189 {
2190         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2191
2192         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2193 }
2194
2195 /**
2196  * stmmac_tx_timer - mitigation sw timer for tx.
2197  * @data: data pointer
2198  * Description:
2199  * This is the timer handler to directly invoke the stmmac_tx_clean.
2200  */
2201 static void stmmac_tx_timer(struct timer_list *t)
2202 {
2203         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2204         struct stmmac_priv *priv = tx_q->priv_data;
2205         struct stmmac_channel *ch;
2206
2207         ch = &priv->channel[tx_q->queue_index];
2208
2209         /*
2210          * If NAPI is already running we can miss some events. Let's rearm
2211          * the timer and try again.
2212          */
2213         if (likely(napi_schedule_prep(&ch->tx_napi)))
2214                 __napi_schedule(&ch->tx_napi);
2215         else
2216                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2217 }
2218
2219 /**
2220  * stmmac_init_tx_coalesce - init tx mitigation options.
2221  * @priv: driver private structure
2222  * Description:
2223  * This inits the transmit coalesce parameters: i.e. timer rate,
2224  * timer handler and default threshold used for enabling the
2225  * interrupt on completion bit.
2226  */
2227 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2228 {
2229         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2230         u32 chan;
2231
2232         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2233         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2234
2235         for (chan = 0; chan < tx_channel_count; chan++) {
2236                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2237
2238                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2239         }
2240 }
2241
2242 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2243 {
2244         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2245         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2246         u32 chan;
2247
2248         /* set TX ring length */
2249         for (chan = 0; chan < tx_channels_count; chan++)
2250                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2251                                 (DMA_TX_SIZE - 1), chan);
2252
2253         /* set RX ring length */
2254         for (chan = 0; chan < rx_channels_count; chan++)
2255                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2256                                 (DMA_RX_SIZE - 1), chan);
2257 }
2258
2259 /**
2260  *  stmmac_set_tx_queue_weight - Set TX queue weight
2261  *  @priv: driver private structure
2262  *  Description: It is used for setting TX queues weight
2263  */
2264 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2265 {
2266         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2267         u32 weight;
2268         u32 queue;
2269
2270         for (queue = 0; queue < tx_queues_count; queue++) {
2271                 weight = priv->plat->tx_queues_cfg[queue].weight;
2272                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2273         }
2274 }
2275
2276 /**
2277  *  stmmac_configure_cbs - Configure CBS in TX queue
2278  *  @priv: driver private structure
2279  *  Description: It is used for configuring CBS in AVB TX queues
2280  */
2281 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2282 {
2283         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2284         u32 mode_to_use;
2285         u32 queue;
2286
2287         /* queue 0 is reserved for legacy traffic */
2288         for (queue = 1; queue < tx_queues_count; queue++) {
2289                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2290                 if (mode_to_use == MTL_QUEUE_DCB)
2291                         continue;
2292
2293                 stmmac_config_cbs(priv, priv->hw,
2294                                 priv->plat->tx_queues_cfg[queue].send_slope,
2295                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2296                                 priv->plat->tx_queues_cfg[queue].high_credit,
2297                                 priv->plat->tx_queues_cfg[queue].low_credit,
2298                                 queue);
2299         }
2300 }
2301
2302 /**
2303  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2304  *  @priv: driver private structure
2305  *  Description: It is used for mapping RX queues to RX dma channels
2306  */
2307 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2308 {
2309         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2310         u32 queue;
2311         u32 chan;
2312
2313         for (queue = 0; queue < rx_queues_count; queue++) {
2314                 chan = priv->plat->rx_queues_cfg[queue].chan;
2315                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2316         }
2317 }
2318
2319 /**
2320  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2321  *  @priv: driver private structure
2322  *  Description: It is used for configuring the RX Queue Priority
2323  */
2324 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2325 {
2326         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2327         u32 queue;
2328         u32 prio;
2329
2330         for (queue = 0; queue < rx_queues_count; queue++) {
2331                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2332                         continue;
2333
2334                 prio = priv->plat->rx_queues_cfg[queue].prio;
2335                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2336         }
2337 }
2338
2339 /**
2340  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2341  *  @priv: driver private structure
2342  *  Description: It is used for configuring the TX Queue Priority
2343  */
2344 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2345 {
2346         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2347         u32 queue;
2348         u32 prio;
2349
2350         for (queue = 0; queue < tx_queues_count; queue++) {
2351                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2352                         continue;
2353
2354                 prio = priv->plat->tx_queues_cfg[queue].prio;
2355                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2356         }
2357 }
2358
2359 /**
2360  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2361  *  @priv: driver private structure
2362  *  Description: It is used for configuring the RX queue routing
2363  */
2364 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2365 {
2366         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2367         u32 queue;
2368         u8 packet;
2369
2370         for (queue = 0; queue < rx_queues_count; queue++) {
2371                 /* no specific packet type routing specified for the queue */
2372                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2373                         continue;
2374
2375                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2376                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2377         }
2378 }
2379
2380 /**
2381  *  stmmac_mtl_configuration - Configure MTL
2382  *  @priv: driver private structure
2383  *  Description: It is used for configurring MTL
2384  */
2385 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2386 {
2387         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2388         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2389
2390         if (tx_queues_count > 1)
2391                 stmmac_set_tx_queue_weight(priv);
2392
2393         /* Configure MTL RX algorithms */
2394         if (rx_queues_count > 1)
2395                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2396                                 priv->plat->rx_sched_algorithm);
2397
2398         /* Configure MTL TX algorithms */
2399         if (tx_queues_count > 1)
2400                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2401                                 priv->plat->tx_sched_algorithm);
2402
2403         /* Configure CBS in AVB TX queues */
2404         if (tx_queues_count > 1)
2405                 stmmac_configure_cbs(priv);
2406
2407         /* Map RX MTL to DMA channels */
2408         stmmac_rx_queue_dma_chan_map(priv);
2409
2410         /* Enable MAC RX Queues */
2411         stmmac_mac_enable_rx_queues(priv);
2412
2413         /* Set RX priorities */
2414         if (rx_queues_count > 1)
2415                 stmmac_mac_config_rx_queues_prio(priv);
2416
2417         /* Set TX priorities */
2418         if (tx_queues_count > 1)
2419                 stmmac_mac_config_tx_queues_prio(priv);
2420
2421         /* Set RX routing */
2422         if (rx_queues_count > 1)
2423                 stmmac_mac_config_rx_queues_routing(priv);
2424 }
2425
2426 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2427 {
2428         if (priv->dma_cap.asp) {
2429                 netdev_info(priv->dev, "Enabling Safety Features\n");
2430                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2431         } else {
2432                 netdev_info(priv->dev, "No Safety Features support found\n");
2433         }
2434 }
2435
2436 /**
2437  * stmmac_hw_setup - setup mac in a usable state.
2438  *  @dev : pointer to the device structure.
2439  *  Description:
2440  *  this is the main function to setup the HW in a usable state because the
2441  *  dma engine is reset, the core registers are configured (e.g. AXI,
2442  *  Checksum features, timers). The DMA is ready to start receiving and
2443  *  transmitting.
2444  *  Return value:
2445  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2446  *  file on failure.
2447  */
2448 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2449 {
2450         struct stmmac_priv *priv = netdev_priv(dev);
2451         u32 rx_cnt = priv->plat->rx_queues_to_use;
2452         u32 tx_cnt = priv->plat->tx_queues_to_use;
2453         u32 chan;
2454         int ret;
2455
2456         /* DMA initialization and SW reset */
2457         ret = stmmac_init_dma_engine(priv);
2458         if (ret < 0) {
2459                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2460                            __func__);
2461                 return ret;
2462         }
2463
2464         /* Copy the MAC addr into the HW  */
2465         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2466
2467         /* PS and related bits will be programmed according to the speed */
2468         if (priv->hw->pcs) {
2469                 int speed = priv->plat->mac_port_sel_speed;
2470
2471                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2472                     (speed == SPEED_1000)) {
2473                         priv->hw->ps = speed;
2474                 } else {
2475                         dev_warn(priv->device, "invalid port speed\n");
2476                         priv->hw->ps = 0;
2477                 }
2478         }
2479
2480         /* Initialize the MAC Core */
2481         stmmac_core_init(priv, priv->hw, dev);
2482
2483         /* Initialize MTL*/
2484         stmmac_mtl_configuration(priv);
2485
2486         /* Initialize Safety Features */
2487         stmmac_safety_feat_configuration(priv);
2488
2489         ret = stmmac_rx_ipc(priv, priv->hw);
2490         if (!ret) {
2491                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2492                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2493                 priv->hw->rx_csum = 0;
2494         }
2495
2496         /* Enable the MAC Rx/Tx */
2497         stmmac_mac_set(priv, priv->ioaddr, true);
2498
2499         /* Set the HW DMA mode and the COE */
2500         stmmac_dma_operation_mode(priv);
2501
2502         stmmac_mmc_setup(priv);
2503
2504         if (init_ptp) {
2505                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2506                 if (ret < 0)
2507                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2508
2509                 ret = stmmac_init_ptp(priv);
2510                 if (ret == -EOPNOTSUPP)
2511                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2512                 else if (ret)
2513                         netdev_warn(priv->dev, "PTP init failed\n");
2514         }
2515
2516         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2517
2518         if (priv->use_riwt) {
2519                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2520                 if (!ret)
2521                         priv->rx_riwt = MAX_DMA_RIWT;
2522         }
2523
2524         if (priv->hw->pcs)
2525                 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2526
2527         /* set TX and RX rings length */
2528         stmmac_set_rings_length(priv);
2529
2530         /* Enable TSO */
2531         if (priv->tso) {
2532                 for (chan = 0; chan < tx_cnt; chan++)
2533                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2534         }
2535
2536         /* Start the ball rolling... */
2537         stmmac_start_all_dma(priv);
2538
2539         return 0;
2540 }
2541
2542 static void stmmac_hw_teardown(struct net_device *dev)
2543 {
2544         struct stmmac_priv *priv = netdev_priv(dev);
2545
2546         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2547 }
2548
2549 /**
2550  *  stmmac_open - open entry point of the driver
2551  *  @dev : pointer to the device structure.
2552  *  Description:
2553  *  This function is the open entry point of the driver.
2554  *  Return value:
2555  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2556  *  file on failure.
2557  */
2558 static int stmmac_open(struct net_device *dev)
2559 {
2560         struct stmmac_priv *priv = netdev_priv(dev);
2561         u32 chan;
2562         int ret;
2563
2564         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2565             priv->hw->pcs != STMMAC_PCS_TBI &&
2566             priv->hw->pcs != STMMAC_PCS_RTBI) {
2567                 ret = stmmac_init_phy(dev);
2568                 if (ret) {
2569                         netdev_err(priv->dev,
2570                                    "%s: Cannot attach to PHY (error: %d)\n",
2571                                    __func__, ret);
2572                         return ret;
2573                 }
2574         }
2575
2576         /* Extra statistics */
2577         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2578         priv->xstats.threshold = tc;
2579
2580         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2581         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2582
2583         ret = alloc_dma_desc_resources(priv);
2584         if (ret < 0) {
2585                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2586                            __func__);
2587                 goto dma_desc_error;
2588         }
2589
2590         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2591         if (ret < 0) {
2592                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2593                            __func__);
2594                 goto init_error;
2595         }
2596
2597         ret = stmmac_hw_setup(dev, true);
2598         if (ret < 0) {
2599                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2600                 goto init_error;
2601         }
2602
2603         stmmac_init_tx_coalesce(priv);
2604
2605         phylink_start(priv->phylink);
2606
2607         /* Request the IRQ lines */
2608         ret = request_irq(dev->irq, stmmac_interrupt,
2609                           IRQF_SHARED, dev->name, dev);
2610         if (unlikely(ret < 0)) {
2611                 netdev_err(priv->dev,
2612                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2613                            __func__, dev->irq, ret);
2614                 goto irq_error;
2615         }
2616
2617         /* Request the Wake IRQ in case of another line is used for WoL */
2618         if (priv->wol_irq != dev->irq) {
2619                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2620                                   IRQF_SHARED, dev->name, dev);
2621                 if (unlikely(ret < 0)) {
2622                         netdev_err(priv->dev,
2623                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2624                                    __func__, priv->wol_irq, ret);
2625                         goto wolirq_error;
2626                 }
2627         }
2628
2629         /* Request the IRQ lines */
2630         if (priv->lpi_irq > 0) {
2631                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2632                                   dev->name, dev);
2633                 if (unlikely(ret < 0)) {
2634                         netdev_err(priv->dev,
2635                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2636                                    __func__, priv->lpi_irq, ret);
2637                         goto lpiirq_error;
2638                 }
2639         }
2640
2641         stmmac_enable_all_queues(priv);
2642         stmmac_start_all_queues(priv);
2643
2644         return 0;
2645
2646 lpiirq_error:
2647         if (priv->wol_irq != dev->irq)
2648                 free_irq(priv->wol_irq, dev);
2649 wolirq_error:
2650         free_irq(dev->irq, dev);
2651 irq_error:
2652         phylink_stop(priv->phylink);
2653
2654         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2655                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2656
2657         stmmac_hw_teardown(dev);
2658 init_error:
2659         free_dma_desc_resources(priv);
2660 dma_desc_error:
2661         phylink_disconnect_phy(priv->phylink);
2662         return ret;
2663 }
2664
2665 /**
2666  *  stmmac_release - close entry point of the driver
2667  *  @dev : device pointer.
2668  *  Description:
2669  *  This is the stop entry point of the driver.
2670  */
2671 static int stmmac_release(struct net_device *dev)
2672 {
2673         struct stmmac_priv *priv = netdev_priv(dev);
2674         u32 chan;
2675
2676         if (priv->eee_enabled)
2677                 del_timer_sync(&priv->eee_ctrl_timer);
2678
2679         /* Stop and disconnect the PHY */
2680         phylink_stop(priv->phylink);
2681         phylink_disconnect_phy(priv->phylink);
2682
2683         stmmac_stop_all_queues(priv);
2684
2685         stmmac_disable_all_queues(priv);
2686
2687         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2688                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2689
2690         /* Free the IRQ lines */
2691         free_irq(dev->irq, dev);
2692         if (priv->wol_irq != dev->irq)
2693                 free_irq(priv->wol_irq, dev);
2694         if (priv->lpi_irq > 0)
2695                 free_irq(priv->lpi_irq, dev);
2696
2697         /* Stop TX/RX DMA and clear the descriptors */
2698         stmmac_stop_all_dma(priv);
2699
2700         /* Release and free the Rx/Tx resources */
2701         free_dma_desc_resources(priv);
2702
2703         /* Disable the MAC Rx/Tx */
2704         stmmac_mac_set(priv, priv->ioaddr, false);
2705
2706         netif_carrier_off(dev);
2707
2708         stmmac_release_ptp(priv);
2709
2710         return 0;
2711 }
2712
2713 /**
2714  *  stmmac_tso_allocator - close entry point of the driver
2715  *  @priv: driver private structure
2716  *  @des: buffer start address
2717  *  @total_len: total length to fill in descriptors
2718  *  @last_segmant: condition for the last descriptor
2719  *  @queue: TX queue index
2720  *  Description:
2721  *  This function fills descriptor and request new descriptors according to
2722  *  buffer length to fill
2723  */
2724 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2725                                  int total_len, bool last_segment, u32 queue)
2726 {
2727         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2728         struct dma_desc *desc;
2729         u32 buff_size;
2730         int tmp_len;
2731
2732         tmp_len = total_len;
2733
2734         while (tmp_len > 0) {
2735                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2736                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2737                 desc = tx_q->dma_tx + tx_q->cur_tx;
2738
2739                 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2740                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2741                             TSO_MAX_BUFF_SIZE : tmp_len;
2742
2743                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2744                                 0, 1,
2745                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2746                                 0, 0);
2747
2748                 tmp_len -= TSO_MAX_BUFF_SIZE;
2749         }
2750 }
2751
2752 /**
2753  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2754  *  @skb : the socket buffer
2755  *  @dev : device pointer
2756  *  Description: this is the transmit function that is called on TSO frames
2757  *  (support available on GMAC4 and newer chips).
2758  *  Diagram below show the ring programming in case of TSO frames:
2759  *
2760  *  First Descriptor
2761  *   --------
2762  *   | DES0 |---> buffer1 = L2/L3/L4 header
2763  *   | DES1 |---> TCP Payload (can continue on next descr...)
2764  *   | DES2 |---> buffer 1 and 2 len
2765  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2766  *   --------
2767  *      |
2768  *     ...
2769  *      |
2770  *   --------
2771  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2772  *   | DES1 | --|
2773  *   | DES2 | --> buffer 1 and 2 len
2774  *   | DES3 |
2775  *   --------
2776  *
2777  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2778  */
2779 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2780 {
2781         struct dma_desc *desc, *first, *mss_desc = NULL;
2782         struct stmmac_priv *priv = netdev_priv(dev);
2783         int nfrags = skb_shinfo(skb)->nr_frags;
2784         u32 queue = skb_get_queue_mapping(skb);
2785         unsigned int first_entry, des;
2786         struct stmmac_tx_queue *tx_q;
2787         int tmp_pay_len = 0;
2788         u32 pay_len, mss;
2789         u8 proto_hdr_len;
2790         int i;
2791
2792         tx_q = &priv->tx_queue[queue];
2793
2794         /* Compute header lengths */
2795         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2796
2797         /* Desc availability based on threshold should be enough safe */
2798         if (unlikely(stmmac_tx_avail(priv, queue) <
2799                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2800                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2801                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2802                                                                 queue));
2803                         /* This is a hard error, log it. */
2804                         netdev_err(priv->dev,
2805                                    "%s: Tx Ring full when queue awake\n",
2806                                    __func__);
2807                 }
2808                 return NETDEV_TX_BUSY;
2809         }
2810
2811         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2812
2813         mss = skb_shinfo(skb)->gso_size;
2814
2815         /* set new MSS value if needed */
2816         if (mss != tx_q->mss) {
2817                 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2818                 stmmac_set_mss(priv, mss_desc, mss);
2819                 tx_q->mss = mss;
2820                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2821                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2822         }
2823
2824         if (netif_msg_tx_queued(priv)) {
2825                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2826                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2827                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2828                         skb->data_len);
2829         }
2830
2831         first_entry = tx_q->cur_tx;
2832         WARN_ON(tx_q->tx_skbuff[first_entry]);
2833
2834         desc = tx_q->dma_tx + first_entry;
2835         first = desc;
2836
2837         /* first descriptor: fill Headers on Buf1 */
2838         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2839                              DMA_TO_DEVICE);
2840         if (dma_mapping_error(priv->device, des))
2841                 goto dma_map_err;
2842
2843         tx_q->tx_skbuff_dma[first_entry].buf = des;
2844         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2845
2846         first->des0 = cpu_to_le32(des);
2847
2848         /* Fill start of payload in buff2 of first descriptor */
2849         if (pay_len)
2850                 first->des1 = cpu_to_le32(des + proto_hdr_len);
2851
2852         /* If needed take extra descriptors to fill the remaining payload */
2853         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2854
2855         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2856
2857         /* Prepare fragments */
2858         for (i = 0; i < nfrags; i++) {
2859                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2860
2861                 des = skb_frag_dma_map(priv->device, frag, 0,
2862                                        skb_frag_size(frag),
2863                                        DMA_TO_DEVICE);
2864                 if (dma_mapping_error(priv->device, des))
2865                         goto dma_map_err;
2866
2867                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2868                                      (i == nfrags - 1), queue);
2869
2870                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2871                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2872                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2873         }
2874
2875         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2876
2877         /* Only the last descriptor gets to point to the skb. */
2878         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2879
2880         /* We've used all descriptors we need for this skb, however,
2881          * advance cur_tx so that it references a fresh descriptor.
2882          * ndo_start_xmit will fill this descriptor the next time it's
2883          * called and stmmac_tx_clean may clean up to this descriptor.
2884          */
2885         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2886
2887         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2888                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2889                           __func__);
2890                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2891         }
2892
2893         dev->stats.tx_bytes += skb->len;
2894         priv->xstats.tx_tso_frames++;
2895         priv->xstats.tx_tso_nfrags += nfrags;
2896
2897         /* Manage tx mitigation */
2898         tx_q->tx_count_frames += nfrags + 1;
2899         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
2900             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
2901             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2902             priv->hwts_tx_en)) {
2903                 stmmac_tx_timer_arm(priv, queue);
2904         } else {
2905                 tx_q->tx_count_frames = 0;
2906                 stmmac_set_tx_ic(priv, desc);
2907                 priv->xstats.tx_set_ic_bit++;
2908         }
2909
2910         skb_tx_timestamp(skb);
2911
2912         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2913                      priv->hwts_tx_en)) {
2914                 /* declare that device is doing timestamping */
2915                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2916                 stmmac_enable_tx_timestamp(priv, first);
2917         }
2918
2919         /* Complete the first descriptor before granting the DMA */
2920         stmmac_prepare_tso_tx_desc(priv, first, 1,
2921                         proto_hdr_len,
2922                         pay_len,
2923                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2924                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2925
2926         /* If context desc is used to change MSS */
2927         if (mss_desc) {
2928                 /* Make sure that first descriptor has been completely
2929                  * written, including its own bit. This is because MSS is
2930                  * actually before first descriptor, so we need to make
2931                  * sure that MSS's own bit is the last thing written.
2932                  */
2933                 dma_wmb();
2934                 stmmac_set_tx_owner(priv, mss_desc);
2935         }
2936
2937         /* The own bit must be the latest setting done when prepare the
2938          * descriptor and then barrier is needed to make sure that
2939          * all is coherent before granting the DMA engine.
2940          */
2941         wmb();
2942
2943         if (netif_msg_pktdata(priv)) {
2944                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2945                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2946                         tx_q->cur_tx, first, nfrags);
2947
2948                 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
2949
2950                 pr_info(">>> frame to be transmitted: ");
2951                 print_pkt(skb->data, skb_headlen(skb));
2952         }
2953
2954         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
2955
2956         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
2957         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
2958
2959         return NETDEV_TX_OK;
2960
2961 dma_map_err:
2962         dev_err(priv->device, "Tx dma map failed\n");
2963         dev_kfree_skb(skb);
2964         priv->dev->stats.tx_dropped++;
2965         return NETDEV_TX_OK;
2966 }
2967
2968 /**
2969  *  stmmac_xmit - Tx entry point of the driver
2970  *  @skb : the socket buffer
2971  *  @dev : device pointer
2972  *  Description : this is the tx entry point of the driver.
2973  *  It programs the chain or the ring and supports oversized frames
2974  *  and SG feature.
2975  */
2976 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2977 {
2978         struct stmmac_priv *priv = netdev_priv(dev);
2979         unsigned int nopaged_len = skb_headlen(skb);
2980         int i, csum_insertion = 0, is_jumbo = 0;
2981         u32 queue = skb_get_queue_mapping(skb);
2982         int nfrags = skb_shinfo(skb)->nr_frags;
2983         int entry;
2984         unsigned int first_entry;
2985         struct dma_desc *desc, *first;
2986         struct stmmac_tx_queue *tx_q;
2987         unsigned int enh_desc;
2988         unsigned int des;
2989
2990         tx_q = &priv->tx_queue[queue];
2991
2992         if (priv->tx_path_in_lpi_mode)
2993                 stmmac_disable_eee_mode(priv);
2994
2995         /* Manage oversized TCP frames for GMAC4 device */
2996         if (skb_is_gso(skb) && priv->tso) {
2997                 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
2998                         /*
2999                          * There is no way to determine the number of TSO
3000                          * capable Queues. Let's use always the Queue 0
3001                          * because if TSO is supported then at least this
3002                          * one will be capable.
3003                          */
3004                         skb_set_queue_mapping(skb, 0);
3005
3006                         return stmmac_tso_xmit(skb, dev);
3007                 }
3008         }
3009
3010         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3011                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3012                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3013                                                                 queue));
3014                         /* This is a hard error, log it. */
3015                         netdev_err(priv->dev,
3016                                    "%s: Tx Ring full when queue awake\n",
3017                                    __func__);
3018                 }
3019                 return NETDEV_TX_BUSY;
3020         }
3021
3022         entry = tx_q->cur_tx;
3023         first_entry = entry;
3024         WARN_ON(tx_q->tx_skbuff[first_entry]);
3025
3026         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3027
3028         if (likely(priv->extend_desc))
3029                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3030         else
3031                 desc = tx_q->dma_tx + entry;
3032
3033         first = desc;
3034
3035         enh_desc = priv->plat->enh_desc;
3036         /* To program the descriptors according to the size of the frame */
3037         if (enh_desc)
3038                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3039
3040         if (unlikely(is_jumbo)) {
3041                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3042                 if (unlikely(entry < 0) && (entry != -EINVAL))
3043                         goto dma_map_err;
3044         }
3045
3046         for (i = 0; i < nfrags; i++) {
3047                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3048                 int len = skb_frag_size(frag);
3049                 bool last_segment = (i == (nfrags - 1));
3050
3051                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3052                 WARN_ON(tx_q->tx_skbuff[entry]);
3053
3054                 if (likely(priv->extend_desc))
3055                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3056                 else
3057                         desc = tx_q->dma_tx + entry;
3058
3059                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3060                                        DMA_TO_DEVICE);
3061                 if (dma_mapping_error(priv->device, des))
3062                         goto dma_map_err; /* should reuse desc w/o issues */
3063
3064                 tx_q->tx_skbuff_dma[entry].buf = des;
3065
3066                 stmmac_set_desc_addr(priv, desc, des);
3067
3068                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3069                 tx_q->tx_skbuff_dma[entry].len = len;
3070                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3071
3072                 /* Prepare the descriptor and set the own bit too */
3073                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3074                                 priv->mode, 1, last_segment, skb->len);
3075         }
3076
3077         /* Only the last descriptor gets to point to the skb. */
3078         tx_q->tx_skbuff[entry] = skb;
3079
3080         /* We've used all descriptors we need for this skb, however,
3081          * advance cur_tx so that it references a fresh descriptor.
3082          * ndo_start_xmit will fill this descriptor the next time it's
3083          * called and stmmac_tx_clean may clean up to this descriptor.
3084          */
3085         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3086         tx_q->cur_tx = entry;
3087
3088         if (netif_msg_pktdata(priv)) {
3089                 void *tx_head;
3090
3091                 netdev_dbg(priv->dev,
3092                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3093                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3094                            entry, first, nfrags);
3095
3096                 if (priv->extend_desc)
3097                         tx_head = (void *)tx_q->dma_etx;
3098                 else
3099                         tx_head = (void *)tx_q->dma_tx;
3100
3101                 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3102
3103                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3104                 print_pkt(skb->data, skb->len);
3105         }
3106
3107         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3108                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3109                           __func__);
3110                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3111         }
3112
3113         dev->stats.tx_bytes += skb->len;
3114
3115         /* According to the coalesce parameter the IC bit for the latest
3116          * segment is reset and the timer re-started to clean the tx status.
3117          * This approach takes care about the fragments: desc is the first
3118          * element in case of no SG.
3119          */
3120         tx_q->tx_count_frames += nfrags + 1;
3121         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3122             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3123             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3124             priv->hwts_tx_en)) {
3125                 stmmac_tx_timer_arm(priv, queue);
3126         } else {
3127                 tx_q->tx_count_frames = 0;
3128                 stmmac_set_tx_ic(priv, desc);
3129                 priv->xstats.tx_set_ic_bit++;
3130         }
3131
3132         skb_tx_timestamp(skb);
3133
3134         /* Ready to fill the first descriptor and set the OWN bit w/o any
3135          * problems because all the descriptors are actually ready to be
3136          * passed to the DMA engine.
3137          */
3138         if (likely(!is_jumbo)) {
3139                 bool last_segment = (nfrags == 0);
3140
3141                 des = dma_map_single(priv->device, skb->data,
3142                                      nopaged_len, DMA_TO_DEVICE);
3143                 if (dma_mapping_error(priv->device, des))
3144                         goto dma_map_err;
3145
3146                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3147
3148                 stmmac_set_desc_addr(priv, first, des);
3149
3150                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3151                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3152
3153                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3154                              priv->hwts_tx_en)) {
3155                         /* declare that device is doing timestamping */
3156                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3157                         stmmac_enable_tx_timestamp(priv, first);
3158                 }
3159
3160                 /* Prepare the first descriptor setting the OWN bit too */
3161                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3162                                 csum_insertion, priv->mode, 1, last_segment,
3163                                 skb->len);
3164         } else {
3165                 stmmac_set_tx_owner(priv, first);
3166         }
3167
3168         /* The own bit must be the latest setting done when prepare the
3169          * descriptor and then barrier is needed to make sure that
3170          * all is coherent before granting the DMA engine.
3171          */
3172         wmb();
3173
3174         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3175
3176         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3177
3178         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3179         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3180
3181         return NETDEV_TX_OK;
3182
3183 dma_map_err:
3184         netdev_err(priv->dev, "Tx DMA map failed\n");
3185         dev_kfree_skb(skb);
3186         priv->dev->stats.tx_dropped++;
3187         return NETDEV_TX_OK;
3188 }
3189
3190 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3191 {
3192         struct vlan_ethhdr *veth;
3193         __be16 vlan_proto;
3194         u16 vlanid;
3195
3196         veth = (struct vlan_ethhdr *)skb->data;
3197         vlan_proto = veth->h_vlan_proto;
3198
3199         if ((vlan_proto == htons(ETH_P_8021Q) &&
3200              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3201             (vlan_proto == htons(ETH_P_8021AD) &&
3202              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3203                 /* pop the vlan tag */
3204                 vlanid = ntohs(veth->h_vlan_TCI);
3205                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3206                 skb_pull(skb, VLAN_HLEN);
3207                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3208         }
3209 }
3210
3211
3212 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3213 {
3214         if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3215                 return 0;
3216
3217         return 1;
3218 }
3219
3220 /**
3221  * stmmac_rx_refill - refill used skb preallocated buffers
3222  * @priv: driver private structure
3223  * @queue: RX queue index
3224  * Description : this is to reallocate the skb for the reception process
3225  * that is based on zero-copy.
3226  */
3227 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3228 {
3229         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3230         int dirty = stmmac_rx_dirty(priv, queue);
3231         unsigned int entry = rx_q->dirty_rx;
3232
3233         int bfsize = priv->dma_buf_sz;
3234
3235         while (dirty-- > 0) {
3236                 struct dma_desc *p;
3237
3238                 if (priv->extend_desc)
3239                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3240                 else
3241                         p = rx_q->dma_rx + entry;
3242
3243                 if (likely(!rx_q->rx_skbuff[entry])) {
3244                         struct sk_buff *skb;
3245
3246                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3247                         if (unlikely(!skb)) {
3248                                 /* so for a while no zero-copy! */
3249                                 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3250                                 if (unlikely(net_ratelimit()))
3251                                         dev_err(priv->device,
3252                                                 "fail to alloc skb entry %d\n",
3253                                                 entry);
3254                                 break;
3255                         }
3256
3257                         rx_q->rx_skbuff[entry] = skb;
3258                         rx_q->rx_skbuff_dma[entry] =
3259                             dma_map_single(priv->device, skb->data, bfsize,
3260                                            DMA_FROM_DEVICE);
3261                         if (dma_mapping_error(priv->device,
3262                                               rx_q->rx_skbuff_dma[entry])) {
3263                                 netdev_err(priv->dev, "Rx DMA map failed\n");
3264                                 dev_kfree_skb(skb);
3265                                 break;
3266                         }
3267
3268                         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3269                         stmmac_refill_desc3(priv, rx_q, p);
3270
3271                         if (rx_q->rx_zeroc_thresh > 0)
3272                                 rx_q->rx_zeroc_thresh--;
3273
3274                         netif_dbg(priv, rx_status, priv->dev,
3275                                   "refill entry #%d\n", entry);
3276                 }
3277                 dma_wmb();
3278
3279                 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3280
3281                 dma_wmb();
3282
3283                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3284         }
3285         rx_q->dirty_rx = entry;
3286         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3287 }
3288
3289 /**
3290  * stmmac_rx - manage the receive process
3291  * @priv: driver private structure
3292  * @limit: napi bugget
3293  * @queue: RX queue index.
3294  * Description :  this the function called by the napi poll method.
3295  * It gets all the frames inside the ring.
3296  */
3297 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3298 {
3299         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3300         struct stmmac_channel *ch = &priv->channel[queue];
3301         unsigned int next_entry = rx_q->cur_rx;
3302         int coe = priv->hw->rx_csum;
3303         unsigned int count = 0;
3304         bool xmac;
3305
3306         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3307
3308         if (netif_msg_rx_status(priv)) {
3309                 void *rx_head;
3310
3311                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3312                 if (priv->extend_desc)
3313                         rx_head = (void *)rx_q->dma_erx;
3314                 else
3315                         rx_head = (void *)rx_q->dma_rx;
3316
3317                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3318         }
3319         while (count < limit) {
3320                 int entry, status;
3321                 struct dma_desc *p;
3322                 struct dma_desc *np;
3323
3324                 entry = next_entry;
3325
3326                 if (priv->extend_desc)
3327                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3328                 else
3329                         p = rx_q->dma_rx + entry;
3330
3331                 /* read the status of the incoming frame */
3332                 status = stmmac_rx_status(priv, &priv->dev->stats,
3333                                 &priv->xstats, p);
3334                 /* check if managed by the DMA otherwise go ahead */
3335                 if (unlikely(status & dma_own))
3336                         break;
3337
3338                 count++;
3339
3340                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3341                 next_entry = rx_q->cur_rx;
3342
3343                 if (priv->extend_desc)
3344                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3345                 else
3346                         np = rx_q->dma_rx + next_entry;
3347
3348                 prefetch(np);
3349
3350                 if (priv->extend_desc)
3351                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3352                                         &priv->xstats, rx_q->dma_erx + entry);
3353                 if (unlikely(status == discard_frame)) {
3354                         priv->dev->stats.rx_errors++;
3355                         if (priv->hwts_rx_en && !priv->extend_desc) {
3356                                 /* DESC2 & DESC3 will be overwritten by device
3357                                  * with timestamp value, hence reinitialize
3358                                  * them in stmmac_rx_refill() function so that
3359                                  * device can reuse it.
3360                                  */
3361                                 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3362                                 rx_q->rx_skbuff[entry] = NULL;
3363                                 dma_unmap_single(priv->device,
3364                                                  rx_q->rx_skbuff_dma[entry],
3365                                                  priv->dma_buf_sz,
3366                                                  DMA_FROM_DEVICE);
3367                         }
3368                 } else {
3369                         struct sk_buff *skb;
3370                         int frame_len;
3371                         unsigned int des;
3372
3373                         stmmac_get_desc_addr(priv, p, &des);
3374                         frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3375
3376                         /*  If frame length is greater than skb buffer size
3377                          *  (preallocated during init) then the packet is
3378                          *  ignored
3379                          */
3380                         if (frame_len > priv->dma_buf_sz) {
3381                                 if (net_ratelimit())
3382                                         netdev_err(priv->dev,
3383                                                    "len %d larger than size (%d)\n",
3384                                                    frame_len, priv->dma_buf_sz);
3385                                 priv->dev->stats.rx_length_errors++;
3386                                 continue;
3387                         }
3388
3389                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3390                          * Type frames (LLC/LLC-SNAP)
3391                          *
3392                          * llc_snap is never checked in GMAC >= 4, so this ACS
3393                          * feature is always disabled and packets need to be
3394                          * stripped manually.
3395                          */
3396                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3397                             unlikely(status != llc_snap))
3398                                 frame_len -= ETH_FCS_LEN;
3399
3400                         if (netif_msg_rx_status(priv)) {
3401                                 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3402                                            p, entry, des);
3403                                 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3404                                            frame_len, status);
3405                         }
3406
3407                         /* The zero-copy is always used for all the sizes
3408                          * in case of GMAC4 because it needs
3409                          * to refill the used descriptors, always.
3410                          */
3411                         if (unlikely(!xmac &&
3412                                      ((frame_len < priv->rx_copybreak) ||
3413                                      stmmac_rx_threshold_count(rx_q)))) {
3414                                 skb = netdev_alloc_skb_ip_align(priv->dev,
3415                                                                 frame_len);
3416                                 if (unlikely(!skb)) {
3417                                         if (net_ratelimit())
3418                                                 dev_warn(priv->device,
3419                                                          "packet dropped\n");
3420                                         priv->dev->stats.rx_dropped++;
3421                                         continue;
3422                                 }
3423
3424                                 dma_sync_single_for_cpu(priv->device,
3425                                                         rx_q->rx_skbuff_dma
3426                                                         [entry], frame_len,
3427                                                         DMA_FROM_DEVICE);
3428                                 skb_copy_to_linear_data(skb,
3429                                                         rx_q->
3430                                                         rx_skbuff[entry]->data,
3431                                                         frame_len);
3432
3433                                 skb_put(skb, frame_len);
3434                                 dma_sync_single_for_device(priv->device,
3435                                                            rx_q->rx_skbuff_dma
3436                                                            [entry], frame_len,
3437                                                            DMA_FROM_DEVICE);
3438                         } else {
3439                                 skb = rx_q->rx_skbuff[entry];
3440                                 if (unlikely(!skb)) {
3441                                         if (net_ratelimit())
3442                                                 netdev_err(priv->dev,
3443                                                            "%s: Inconsistent Rx chain\n",
3444                                                            priv->dev->name);
3445                                         priv->dev->stats.rx_dropped++;
3446                                         continue;
3447                                 }
3448                                 prefetch(skb->data - NET_IP_ALIGN);
3449                                 rx_q->rx_skbuff[entry] = NULL;
3450                                 rx_q->rx_zeroc_thresh++;
3451
3452                                 skb_put(skb, frame_len);
3453                                 dma_unmap_single(priv->device,
3454                                                  rx_q->rx_skbuff_dma[entry],
3455                                                  priv->dma_buf_sz,
3456                                                  DMA_FROM_DEVICE);
3457                         }
3458
3459                         if (netif_msg_pktdata(priv)) {
3460                                 netdev_dbg(priv->dev, "frame received (%dbytes)",
3461                                            frame_len);
3462                                 print_pkt(skb->data, frame_len);
3463                         }
3464
3465                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
3466
3467                         stmmac_rx_vlan(priv->dev, skb);
3468
3469                         skb->protocol = eth_type_trans(skb, priv->dev);
3470
3471                         if (unlikely(!coe))
3472                                 skb_checksum_none_assert(skb);
3473                         else
3474                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3475
3476                         napi_gro_receive(&ch->rx_napi, skb);
3477
3478                         priv->dev->stats.rx_packets++;
3479                         priv->dev->stats.rx_bytes += frame_len;
3480                 }
3481         }
3482
3483         stmmac_rx_refill(priv, queue);
3484
3485         priv->xstats.rx_pkt_n += count;
3486
3487         return count;
3488 }
3489
3490 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3491 {
3492         struct stmmac_channel *ch =
3493                 container_of(napi, struct stmmac_channel, rx_napi);
3494         struct stmmac_priv *priv = ch->priv_data;
3495         u32 chan = ch->index;
3496         int work_done;
3497
3498         priv->xstats.napi_poll++;
3499
3500         work_done = stmmac_rx(priv, budget, chan);
3501         if (work_done < budget && napi_complete_done(napi, work_done))
3502                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3503         return work_done;
3504 }
3505
3506 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3507 {
3508         struct stmmac_channel *ch =
3509                 container_of(napi, struct stmmac_channel, tx_napi);
3510         struct stmmac_priv *priv = ch->priv_data;
3511         struct stmmac_tx_queue *tx_q;
3512         u32 chan = ch->index;
3513         int work_done;
3514
3515         priv->xstats.napi_poll++;
3516
3517         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3518         work_done = min(work_done, budget);
3519
3520         if (work_done < budget && napi_complete_done(napi, work_done))
3521                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3522
3523         /* Force transmission restart */
3524         tx_q = &priv->tx_queue[chan];
3525         if (tx_q->cur_tx != tx_q->dirty_tx) {
3526                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3527                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3528                                        chan);
3529         }
3530
3531         return work_done;
3532 }
3533
3534 /**
3535  *  stmmac_tx_timeout
3536  *  @dev : Pointer to net device structure
3537  *  Description: this function is called when a packet transmission fails to
3538  *   complete within a reasonable time. The driver will mark the error in the
3539  *   netdev structure and arrange for the device to be reset to a sane state
3540  *   in order to transmit a new packet.
3541  */
3542 static void stmmac_tx_timeout(struct net_device *dev)
3543 {
3544         struct stmmac_priv *priv = netdev_priv(dev);
3545
3546         stmmac_global_err(priv);
3547 }
3548
3549 /**
3550  *  stmmac_set_rx_mode - entry point for multicast addressing
3551  *  @dev : pointer to the device structure
3552  *  Description:
3553  *  This function is a driver entry point which gets called by the kernel
3554  *  whenever multicast addresses must be enabled/disabled.
3555  *  Return value:
3556  *  void.
3557  */
3558 static void stmmac_set_rx_mode(struct net_device *dev)
3559 {
3560         struct stmmac_priv *priv = netdev_priv(dev);
3561
3562         stmmac_set_filter(priv, priv->hw, dev);
3563 }
3564
3565 /**
3566  *  stmmac_change_mtu - entry point to change MTU size for the device.
3567  *  @dev : device pointer.
3568  *  @new_mtu : the new MTU size for the device.
3569  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3570  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3571  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3572  *  Return value:
3573  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3574  *  file on failure.
3575  */
3576 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3577 {
3578         struct stmmac_priv *priv = netdev_priv(dev);
3579
3580         if (netif_running(dev)) {
3581                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3582                 return -EBUSY;
3583         }
3584
3585         dev->mtu = new_mtu;
3586
3587         netdev_update_features(dev);
3588
3589         return 0;
3590 }
3591
3592 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3593                                              netdev_features_t features)
3594 {
3595         struct stmmac_priv *priv = netdev_priv(dev);
3596
3597         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3598                 features &= ~NETIF_F_RXCSUM;
3599
3600         if (!priv->plat->tx_coe)
3601                 features &= ~NETIF_F_CSUM_MASK;
3602
3603         /* Some GMAC devices have a bugged Jumbo frame support that
3604          * needs to have the Tx COE disabled for oversized frames
3605          * (due to limited buffer sizes). In this case we disable
3606          * the TX csum insertion in the TDES and not use SF.
3607          */
3608         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3609                 features &= ~NETIF_F_CSUM_MASK;
3610
3611         /* Disable tso if asked by ethtool */
3612         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3613                 if (features & NETIF_F_TSO)
3614                         priv->tso = true;
3615                 else
3616                         priv->tso = false;
3617         }
3618
3619         return features;
3620 }
3621
3622 static int stmmac_set_features(struct net_device *netdev,
3623                                netdev_features_t features)
3624 {
3625         struct stmmac_priv *priv = netdev_priv(netdev);
3626
3627         /* Keep the COE Type in case of csum is supporting */
3628         if (features & NETIF_F_RXCSUM)
3629                 priv->hw->rx_csum = priv->plat->rx_coe;
3630         else
3631                 priv->hw->rx_csum = 0;
3632         /* No check needed because rx_coe has been set before and it will be
3633          * fixed in case of issue.
3634          */
3635         stmmac_rx_ipc(priv, priv->hw);
3636
3637         return 0;
3638 }
3639
3640 /**
3641  *  stmmac_interrupt - main ISR
3642  *  @irq: interrupt number.
3643  *  @dev_id: to pass the net device pointer.
3644  *  Description: this is the main driver interrupt service routine.
3645  *  It can call:
3646  *  o DMA service routine (to manage incoming frame reception and transmission
3647  *    status)
3648  *  o Core interrupts to manage: remote wake-up, management counter, LPI
3649  *    interrupts.
3650  */
3651 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3652 {
3653         struct net_device *dev = (struct net_device *)dev_id;
3654         struct stmmac_priv *priv = netdev_priv(dev);
3655         u32 rx_cnt = priv->plat->rx_queues_to_use;
3656         u32 tx_cnt = priv->plat->tx_queues_to_use;
3657         u32 queues_count;
3658         u32 queue;
3659         bool xmac;
3660
3661         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3662         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3663
3664         if (priv->irq_wake)
3665                 pm_wakeup_event(priv->device, 0);
3666
3667         if (unlikely(!dev)) {
3668                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3669                 return IRQ_NONE;
3670         }
3671
3672         /* Check if adapter is up */
3673         if (test_bit(STMMAC_DOWN, &priv->state))
3674                 return IRQ_HANDLED;
3675         /* Check if a fatal error happened */
3676         if (stmmac_safety_feat_interrupt(priv))
3677                 return IRQ_HANDLED;
3678
3679         /* To handle GMAC own interrupts */
3680         if ((priv->plat->has_gmac) || xmac) {
3681                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3682                 int mtl_status;
3683
3684                 if (unlikely(status)) {
3685                         /* For LPI we need to save the tx status */
3686                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3687                                 priv->tx_path_in_lpi_mode = true;
3688                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3689                                 priv->tx_path_in_lpi_mode = false;
3690                 }
3691
3692                 for (queue = 0; queue < queues_count; queue++) {
3693                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3694
3695                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3696                                                                 queue);
3697                         if (mtl_status != -EINVAL)
3698                                 status |= mtl_status;
3699
3700                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3701                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3702                                                        rx_q->rx_tail_addr,
3703                                                        queue);
3704                 }
3705
3706                 /* PCS link status */
3707                 if (priv->hw->pcs) {
3708                         if (priv->xstats.pcs_link)
3709                                 netif_carrier_on(dev);
3710                         else
3711                                 netif_carrier_off(dev);
3712                 }
3713         }
3714
3715         /* To handle DMA interrupts */
3716         stmmac_dma_interrupt(priv);
3717
3718         return IRQ_HANDLED;
3719 }
3720
3721 #ifdef CONFIG_NET_POLL_CONTROLLER
3722 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3723  * to allow network I/O with interrupts disabled.
3724  */
3725 static void stmmac_poll_controller(struct net_device *dev)
3726 {
3727         disable_irq(dev->irq);
3728         stmmac_interrupt(dev->irq, dev);
3729         enable_irq(dev->irq);
3730 }
3731 #endif
3732
3733 /**
3734  *  stmmac_ioctl - Entry point for the Ioctl
3735  *  @dev: Device pointer.
3736  *  @rq: An IOCTL specefic structure, that can contain a pointer to
3737  *  a proprietary structure used to pass information to the driver.
3738  *  @cmd: IOCTL command
3739  *  Description:
3740  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3741  */
3742 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3743 {
3744         struct stmmac_priv *priv = netdev_priv (dev);
3745         int ret = -EOPNOTSUPP;
3746
3747         if (!netif_running(dev))
3748                 return -EINVAL;
3749
3750         switch (cmd) {
3751         case SIOCGMIIPHY:
3752         case SIOCGMIIREG:
3753         case SIOCSMIIREG:
3754                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3755                 break;
3756         case SIOCSHWTSTAMP:
3757                 ret = stmmac_hwtstamp_set(dev, rq);
3758                 break;
3759         case SIOCGHWTSTAMP:
3760                 ret = stmmac_hwtstamp_get(dev, rq);
3761                 break;
3762         default:
3763                 break;
3764         }
3765
3766         return ret;
3767 }
3768
3769 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3770                                     void *cb_priv)
3771 {
3772         struct stmmac_priv *priv = cb_priv;
3773         int ret = -EOPNOTSUPP;
3774
3775         stmmac_disable_all_queues(priv);
3776
3777         switch (type) {
3778         case TC_SETUP_CLSU32:
3779                 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3780                         ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3781                 break;
3782         default:
3783                 break;
3784         }
3785
3786         stmmac_enable_all_queues(priv);
3787         return ret;
3788 }
3789
3790 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3791                                  struct tc_block_offload *f)
3792 {
3793         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3794                 return -EOPNOTSUPP;
3795
3796         switch (f->command) {
3797         case TC_BLOCK_BIND:
3798                 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3799                                 priv, priv, f->extack);
3800         case TC_BLOCK_UNBIND:
3801                 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3802                 return 0;
3803         default:
3804                 return -EOPNOTSUPP;
3805         }
3806 }
3807
3808 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3809                            void *type_data)
3810 {
3811         struct stmmac_priv *priv = netdev_priv(ndev);
3812
3813         switch (type) {
3814         case TC_SETUP_BLOCK:
3815                 return stmmac_setup_tc_block(priv, type_data);
3816         case TC_SETUP_QDISC_CBS:
3817                 return stmmac_tc_setup_cbs(priv, priv, type_data);
3818         default:
3819                 return -EOPNOTSUPP;
3820         }
3821 }
3822
3823 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3824 {
3825         struct stmmac_priv *priv = netdev_priv(ndev);
3826         int ret = 0;
3827
3828         ret = eth_mac_addr(ndev, addr);
3829         if (ret)
3830                 return ret;
3831
3832         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3833
3834         return ret;
3835 }
3836
3837 #ifdef CONFIG_DEBUG_FS
3838 static struct dentry *stmmac_fs_dir;
3839
3840 static void sysfs_display_ring(void *head, int size, int extend_desc,
3841                                struct seq_file *seq)
3842 {
3843         int i;
3844         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3845         struct dma_desc *p = (struct dma_desc *)head;
3846
3847         for (i = 0; i < size; i++) {
3848                 if (extend_desc) {
3849                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3850                                    i, (unsigned int)virt_to_phys(ep),
3851                                    le32_to_cpu(ep->basic.des0),
3852                                    le32_to_cpu(ep->basic.des1),
3853                                    le32_to_cpu(ep->basic.des2),
3854                                    le32_to_cpu(ep->basic.des3));
3855                         ep++;
3856                 } else {
3857                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3858                                    i, (unsigned int)virt_to_phys(p),
3859                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3860                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3861                         p++;
3862                 }
3863                 seq_printf(seq, "\n");
3864         }
3865 }
3866
3867 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3868 {
3869         struct net_device *dev = seq->private;
3870         struct stmmac_priv *priv = netdev_priv(dev);
3871         u32 rx_count = priv->plat->rx_queues_to_use;
3872         u32 tx_count = priv->plat->tx_queues_to_use;
3873         u32 queue;
3874
3875         if ((dev->flags & IFF_UP) == 0)
3876                 return 0;
3877
3878         for (queue = 0; queue < rx_count; queue++) {
3879                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3880
3881                 seq_printf(seq, "RX Queue %d:\n", queue);
3882
3883                 if (priv->extend_desc) {
3884                         seq_printf(seq, "Extended descriptor ring:\n");
3885                         sysfs_display_ring((void *)rx_q->dma_erx,
3886                                            DMA_RX_SIZE, 1, seq);
3887                 } else {
3888                         seq_printf(seq, "Descriptor ring:\n");
3889                         sysfs_display_ring((void *)rx_q->dma_rx,
3890                                            DMA_RX_SIZE, 0, seq);
3891                 }
3892         }
3893
3894         for (queue = 0; queue < tx_count; queue++) {
3895                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3896
3897                 seq_printf(seq, "TX Queue %d:\n", queue);
3898
3899                 if (priv->extend_desc) {
3900                         seq_printf(seq, "Extended descriptor ring:\n");
3901                         sysfs_display_ring((void *)tx_q->dma_etx,
3902                                            DMA_TX_SIZE, 1, seq);
3903                 } else {
3904                         seq_printf(seq, "Descriptor ring:\n");
3905                         sysfs_display_ring((void *)tx_q->dma_tx,
3906                                            DMA_TX_SIZE, 0, seq);
3907                 }
3908         }
3909
3910         return 0;
3911 }
3912 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3913
3914 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3915 {
3916         struct net_device *dev = seq->private;
3917         struct stmmac_priv *priv = netdev_priv(dev);
3918
3919         if (!priv->hw_cap_support) {
3920                 seq_printf(seq, "DMA HW features not supported\n");
3921                 return 0;
3922         }
3923
3924         seq_printf(seq, "==============================\n");
3925         seq_printf(seq, "\tDMA HW features\n");
3926         seq_printf(seq, "==============================\n");
3927
3928         seq_printf(seq, "\t10/100 Mbps: %s\n",
3929                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3930         seq_printf(seq, "\t1000 Mbps: %s\n",
3931                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
3932         seq_printf(seq, "\tHalf duplex: %s\n",
3933                    (priv->dma_cap.half_duplex) ? "Y" : "N");
3934         seq_printf(seq, "\tHash Filter: %s\n",
3935                    (priv->dma_cap.hash_filter) ? "Y" : "N");
3936         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3937                    (priv->dma_cap.multi_addr) ? "Y" : "N");
3938         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3939                    (priv->dma_cap.pcs) ? "Y" : "N");
3940         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3941                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
3942         seq_printf(seq, "\tPMT Remote wake up: %s\n",
3943                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3944         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3945                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3946         seq_printf(seq, "\tRMON module: %s\n",
3947                    (priv->dma_cap.rmon) ? "Y" : "N");
3948         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3949                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3950         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3951                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3952         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3953                    (priv->dma_cap.eee) ? "Y" : "N");
3954         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3955         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3956                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3957         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3958                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3959                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3960         } else {
3961                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3962                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3963                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3964                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3965         }
3966         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3967                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3968         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3969                    priv->dma_cap.number_rx_channel);
3970         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3971                    priv->dma_cap.number_tx_channel);
3972         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3973                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3974
3975         return 0;
3976 }
3977 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
3978
3979 static int stmmac_init_fs(struct net_device *dev)
3980 {
3981         struct stmmac_priv *priv = netdev_priv(dev);
3982
3983         /* Create per netdev entries */
3984         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3985
3986         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3987                 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3988
3989                 return -ENOMEM;
3990         }
3991
3992         /* Entry to report DMA RX/TX rings */
3993         priv->dbgfs_rings_status =
3994                 debugfs_create_file("descriptors_status", 0444,
3995                                     priv->dbgfs_dir, dev,
3996                                     &stmmac_rings_status_fops);
3997
3998         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3999                 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4000                 debugfs_remove_recursive(priv->dbgfs_dir);
4001
4002                 return -ENOMEM;
4003         }
4004
4005         /* Entry to report the DMA HW features */
4006         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4007                                                   priv->dbgfs_dir,
4008                                                   dev, &stmmac_dma_cap_fops);
4009
4010         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4011                 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4012                 debugfs_remove_recursive(priv->dbgfs_dir);
4013
4014                 return -ENOMEM;
4015         }
4016
4017         return 0;
4018 }
4019
4020 static void stmmac_exit_fs(struct net_device *dev)
4021 {
4022         struct stmmac_priv *priv = netdev_priv(dev);
4023
4024         debugfs_remove_recursive(priv->dbgfs_dir);
4025 }
4026 #endif /* CONFIG_DEBUG_FS */
4027
4028 static const struct net_device_ops stmmac_netdev_ops = {
4029         .ndo_open = stmmac_open,
4030         .ndo_start_xmit = stmmac_xmit,
4031         .ndo_stop = stmmac_release,
4032         .ndo_change_mtu = stmmac_change_mtu,
4033         .ndo_fix_features = stmmac_fix_features,
4034         .ndo_set_features = stmmac_set_features,
4035         .ndo_set_rx_mode = stmmac_set_rx_mode,
4036         .ndo_tx_timeout = stmmac_tx_timeout,
4037         .ndo_do_ioctl = stmmac_ioctl,
4038         .ndo_setup_tc = stmmac_setup_tc,
4039 #ifdef CONFIG_NET_POLL_CONTROLLER
4040         .ndo_poll_controller = stmmac_poll_controller,
4041 #endif
4042         .ndo_set_mac_address = stmmac_set_mac_address,
4043 };
4044
4045 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4046 {
4047         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4048                 return;
4049         if (test_bit(STMMAC_DOWN, &priv->state))
4050                 return;
4051
4052         netdev_err(priv->dev, "Reset adapter.\n");
4053
4054         rtnl_lock();
4055         netif_trans_update(priv->dev);
4056         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4057                 usleep_range(1000, 2000);
4058
4059         set_bit(STMMAC_DOWN, &priv->state);
4060         dev_close(priv->dev);
4061         dev_open(priv->dev, NULL);
4062         clear_bit(STMMAC_DOWN, &priv->state);
4063         clear_bit(STMMAC_RESETING, &priv->state);
4064         rtnl_unlock();
4065 }
4066
4067 static void stmmac_service_task(struct work_struct *work)
4068 {
4069         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4070                         service_task);
4071
4072         stmmac_reset_subtask(priv);
4073         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4074 }
4075
4076 /**
4077  *  stmmac_hw_init - Init the MAC device
4078  *  @priv: driver private structure
4079  *  Description: this function is to configure the MAC device according to
4080  *  some platform parameters or the HW capability register. It prepares the
4081  *  driver to use either ring or chain modes and to setup either enhanced or
4082  *  normal descriptors.
4083  */
4084 static int stmmac_hw_init(struct stmmac_priv *priv)
4085 {
4086         int ret;
4087
4088         /* dwmac-sun8i only work in chain mode */
4089         if (priv->plat->has_sun8i)
4090                 chain_mode = 1;
4091         priv->chain_mode = chain_mode;
4092
4093         /* Initialize HW Interface */
4094         ret = stmmac_hwif_init(priv);
4095         if (ret)
4096                 return ret;
4097
4098         /* Get the HW capability (new GMAC newer than 3.50a) */
4099         priv->hw_cap_support = stmmac_get_hw_features(priv);
4100         if (priv->hw_cap_support) {
4101                 dev_info(priv->device, "DMA HW capability register supported\n");
4102
4103                 /* We can override some gmac/dma configuration fields: e.g.
4104                  * enh_desc, tx_coe (e.g. that are passed through the
4105                  * platform) with the values from the HW capability
4106                  * register (if supported).
4107                  */
4108                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4109                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4110                 priv->hw->pmt = priv->plat->pmt;
4111
4112                 /* TXCOE doesn't work in thresh DMA mode */
4113                 if (priv->plat->force_thresh_dma_mode)
4114                         priv->plat->tx_coe = 0;
4115                 else
4116                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4117
4118                 /* In case of GMAC4 rx_coe is from HW cap register. */
4119                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4120
4121                 if (priv->dma_cap.rx_coe_type2)
4122                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4123                 else if (priv->dma_cap.rx_coe_type1)
4124                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4125
4126         } else {
4127                 dev_info(priv->device, "No HW DMA feature register supported\n");
4128         }
4129
4130         if (priv->plat->rx_coe) {
4131                 priv->hw->rx_csum = priv->plat->rx_coe;
4132                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4133                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4134                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4135         }
4136         if (priv->plat->tx_coe)
4137                 dev_info(priv->device, "TX Checksum insertion supported\n");
4138
4139         if (priv->plat->pmt) {
4140                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4141                 device_set_wakeup_capable(priv->device, 1);
4142         }
4143
4144         if (priv->dma_cap.tsoen)
4145                 dev_info(priv->device, "TSO supported\n");
4146
4147         /* Run HW quirks, if any */
4148         if (priv->hwif_quirks) {
4149                 ret = priv->hwif_quirks(priv);
4150                 if (ret)
4151                         return ret;
4152         }
4153
4154         /* Rx Watchdog is available in the COREs newer than the 3.40.
4155          * In some case, for example on bugged HW this feature
4156          * has to be disable and this can be done by passing the
4157          * riwt_off field from the platform.
4158          */
4159         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4160             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4161                 priv->use_riwt = 1;
4162                 dev_info(priv->device,
4163                          "Enable RX Mitigation via HW Watchdog Timer\n");
4164         }
4165
4166         return 0;
4167 }
4168
4169 /**
4170  * stmmac_dvr_probe
4171  * @device: device pointer
4172  * @plat_dat: platform data pointer
4173  * @res: stmmac resource pointer
4174  * Description: this is the main probe function used to
4175  * call the alloc_etherdev, allocate the priv structure.
4176  * Return:
4177  * returns 0 on success, otherwise errno.
4178  */
4179 int stmmac_dvr_probe(struct device *device,
4180                      struct plat_stmmacenet_data *plat_dat,
4181                      struct stmmac_resources *res)
4182 {
4183         struct net_device *ndev = NULL;
4184         struct stmmac_priv *priv;
4185         u32 queue, maxq;
4186         int ret = 0;
4187
4188         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4189                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4190         if (!ndev)
4191                 return -ENOMEM;
4192
4193         SET_NETDEV_DEV(ndev, device);
4194
4195         priv = netdev_priv(ndev);
4196         priv->device = device;
4197         priv->dev = ndev;
4198
4199         stmmac_set_ethtool_ops(ndev);
4200         priv->pause = pause;
4201         priv->plat = plat_dat;
4202         priv->ioaddr = res->addr;
4203         priv->dev->base_addr = (unsigned long)res->addr;
4204
4205         priv->dev->irq = res->irq;
4206         priv->wol_irq = res->wol_irq;
4207         priv->lpi_irq = res->lpi_irq;
4208
4209         if (!IS_ERR_OR_NULL(res->mac))
4210                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4211
4212         dev_set_drvdata(device, priv->dev);
4213
4214         /* Verify driver arguments */
4215         stmmac_verify_args();
4216
4217         /* Allocate workqueue */
4218         priv->wq = create_singlethread_workqueue("stmmac_wq");
4219         if (!priv->wq) {
4220                 dev_err(priv->device, "failed to create workqueue\n");
4221                 return -ENOMEM;
4222         }
4223
4224         INIT_WORK(&priv->service_task, stmmac_service_task);
4225
4226         /* Override with kernel parameters if supplied XXX CRS XXX
4227          * this needs to have multiple instances
4228          */
4229         if ((phyaddr >= 0) && (phyaddr <= 31))
4230                 priv->plat->phy_addr = phyaddr;
4231
4232         if (priv->plat->stmmac_rst) {
4233                 ret = reset_control_assert(priv->plat->stmmac_rst);
4234                 reset_control_deassert(priv->plat->stmmac_rst);
4235                 /* Some reset controllers have only reset callback instead of
4236                  * assert + deassert callbacks pair.
4237                  */
4238                 if (ret == -ENOTSUPP)
4239                         reset_control_reset(priv->plat->stmmac_rst);
4240         }
4241
4242         /* Init MAC and get the capabilities */
4243         ret = stmmac_hw_init(priv);
4244         if (ret)
4245                 goto error_hw_init;
4246
4247         stmmac_check_ether_addr(priv);
4248
4249         /* Configure real RX and TX queues */
4250         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4251         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4252
4253         ndev->netdev_ops = &stmmac_netdev_ops;
4254
4255         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4256                             NETIF_F_RXCSUM;
4257
4258         ret = stmmac_tc_init(priv, priv);
4259         if (!ret) {
4260                 ndev->hw_features |= NETIF_F_HW_TC;
4261         }
4262
4263         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4264                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4265                 priv->tso = true;
4266                 dev_info(priv->device, "TSO feature enabled\n");
4267         }
4268         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4269         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4270 #ifdef STMMAC_VLAN_TAG_USED
4271         /* Both mac100 and gmac support receive VLAN tag detection */
4272         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4273 #endif
4274         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4275
4276         /* MTU range: 46 - hw-specific max */
4277         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4278         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4279                 ndev->max_mtu = JUMBO_LEN;
4280         else if (priv->plat->has_xgmac)
4281                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4282         else
4283                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4284         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4285          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4286          */
4287         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4288             (priv->plat->maxmtu >= ndev->min_mtu))
4289                 ndev->max_mtu = priv->plat->maxmtu;
4290         else if (priv->plat->maxmtu < ndev->min_mtu)
4291                 dev_warn(priv->device,
4292                          "%s: warning: maxmtu having invalid value (%d)\n",
4293                          __func__, priv->plat->maxmtu);
4294
4295         if (flow_ctrl)
4296                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4297
4298         /* Setup channels NAPI */
4299         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4300
4301         for (queue = 0; queue < maxq; queue++) {
4302                 struct stmmac_channel *ch = &priv->channel[queue];
4303
4304                 ch->priv_data = priv;
4305                 ch->index = queue;
4306
4307                 if (queue < priv->plat->rx_queues_to_use) {
4308                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4309                                        NAPI_POLL_WEIGHT);
4310                 }
4311                 if (queue < priv->plat->tx_queues_to_use) {
4312                         netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4313                                        NAPI_POLL_WEIGHT);
4314                 }
4315         }
4316
4317         mutex_init(&priv->lock);
4318
4319         /* If a specific clk_csr value is passed from the platform
4320          * this means that the CSR Clock Range selection cannot be
4321          * changed at run-time and it is fixed. Viceversa the driver'll try to
4322          * set the MDC clock dynamically according to the csr actual
4323          * clock input.
4324          */
4325         if (priv->plat->clk_csr >= 0)
4326                 priv->clk_csr = priv->plat->clk_csr;
4327         else
4328                 stmmac_clk_csr_set(priv);
4329
4330         stmmac_check_pcs_mode(priv);
4331
4332         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
4333             priv->hw->pcs != STMMAC_PCS_TBI &&
4334             priv->hw->pcs != STMMAC_PCS_RTBI) {
4335                 /* MDIO bus Registration */
4336                 ret = stmmac_mdio_register(ndev);
4337                 if (ret < 0) {
4338                         dev_err(priv->device,
4339                                 "%s: MDIO bus (id: %d) registration failed",
4340                                 __func__, priv->plat->bus_id);
4341                         goto error_mdio_register;
4342                 }
4343         }
4344
4345         ret = stmmac_phy_setup(priv);
4346         if (ret) {
4347                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4348                 goto error_phy_setup;
4349         }
4350
4351         ret = register_netdev(ndev);
4352         if (ret) {
4353                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4354                         __func__, ret);
4355                 goto error_netdev_register;
4356         }
4357
4358 #ifdef CONFIG_DEBUG_FS
4359         ret = stmmac_init_fs(ndev);
4360         if (ret < 0)
4361                 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4362                             __func__);
4363 #endif
4364
4365         return ret;
4366
4367 error_netdev_register:
4368         phylink_destroy(priv->phylink);
4369 error_phy_setup:
4370         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4371             priv->hw->pcs != STMMAC_PCS_TBI &&
4372             priv->hw->pcs != STMMAC_PCS_RTBI)
4373                 stmmac_mdio_unregister(ndev);
4374 error_mdio_register:
4375         for (queue = 0; queue < maxq; queue++) {
4376                 struct stmmac_channel *ch = &priv->channel[queue];
4377
4378                 if (queue < priv->plat->rx_queues_to_use)
4379                         netif_napi_del(&ch->rx_napi);
4380                 if (queue < priv->plat->tx_queues_to_use)
4381                         netif_napi_del(&ch->tx_napi);
4382         }
4383 error_hw_init:
4384         destroy_workqueue(priv->wq);
4385
4386         return ret;
4387 }
4388 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4389
4390 /**
4391  * stmmac_dvr_remove
4392  * @dev: device pointer
4393  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4394  * changes the link status, releases the DMA descriptor rings.
4395  */
4396 int stmmac_dvr_remove(struct device *dev)
4397 {
4398         struct net_device *ndev = dev_get_drvdata(dev);
4399         struct stmmac_priv *priv = netdev_priv(ndev);
4400
4401         netdev_info(priv->dev, "%s: removing driver", __func__);
4402
4403 #ifdef CONFIG_DEBUG_FS
4404         stmmac_exit_fs(ndev);
4405 #endif
4406         stmmac_stop_all_dma(priv);
4407
4408         stmmac_mac_set(priv, priv->ioaddr, false);
4409         netif_carrier_off(ndev);
4410         unregister_netdev(ndev);
4411         phylink_destroy(priv->phylink);
4412         if (priv->plat->stmmac_rst)
4413                 reset_control_assert(priv->plat->stmmac_rst);
4414         clk_disable_unprepare(priv->plat->pclk);
4415         clk_disable_unprepare(priv->plat->stmmac_clk);
4416         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4417             priv->hw->pcs != STMMAC_PCS_TBI &&
4418             priv->hw->pcs != STMMAC_PCS_RTBI)
4419                 stmmac_mdio_unregister(ndev);
4420         destroy_workqueue(priv->wq);
4421         mutex_destroy(&priv->lock);
4422
4423         return 0;
4424 }
4425 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4426
4427 /**
4428  * stmmac_suspend - suspend callback
4429  * @dev: device pointer
4430  * Description: this is the function to suspend the device and it is called
4431  * by the platform driver to stop the network queue, release the resources,
4432  * program the PMT register (for WoL), clean and release driver resources.
4433  */
4434 int stmmac_suspend(struct device *dev)
4435 {
4436         struct net_device *ndev = dev_get_drvdata(dev);
4437         struct stmmac_priv *priv = netdev_priv(ndev);
4438
4439         if (!ndev || !netif_running(ndev))
4440                 return 0;
4441
4442         phylink_stop(priv->phylink);
4443
4444         mutex_lock(&priv->lock);
4445
4446         netif_device_detach(ndev);
4447         stmmac_stop_all_queues(priv);
4448
4449         stmmac_disable_all_queues(priv);
4450
4451         /* Stop TX/RX DMA */
4452         stmmac_stop_all_dma(priv);
4453
4454         /* Enable Power down mode by programming the PMT regs */
4455         if (device_may_wakeup(priv->device)) {
4456                 stmmac_pmt(priv, priv->hw, priv->wolopts);
4457                 priv->irq_wake = 1;
4458         } else {
4459                 stmmac_mac_set(priv, priv->ioaddr, false);
4460                 pinctrl_pm_select_sleep_state(priv->device);
4461                 /* Disable clock in case of PWM is off */
4462                 clk_disable(priv->plat->pclk);
4463                 clk_disable(priv->plat->stmmac_clk);
4464         }
4465         mutex_unlock(&priv->lock);
4466
4467         priv->speed = SPEED_UNKNOWN;
4468         return 0;
4469 }
4470 EXPORT_SYMBOL_GPL(stmmac_suspend);
4471
4472 /**
4473  * stmmac_reset_queues_param - reset queue parameters
4474  * @dev: device pointer
4475  */
4476 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4477 {
4478         u32 rx_cnt = priv->plat->rx_queues_to_use;
4479         u32 tx_cnt = priv->plat->tx_queues_to_use;
4480         u32 queue;
4481
4482         for (queue = 0; queue < rx_cnt; queue++) {
4483                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4484
4485                 rx_q->cur_rx = 0;
4486                 rx_q->dirty_rx = 0;
4487         }
4488
4489         for (queue = 0; queue < tx_cnt; queue++) {
4490                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4491
4492                 tx_q->cur_tx = 0;
4493                 tx_q->dirty_tx = 0;
4494                 tx_q->mss = 0;
4495         }
4496 }
4497
4498 /**
4499  * stmmac_resume - resume callback
4500  * @dev: device pointer
4501  * Description: when resume this function is invoked to setup the DMA and CORE
4502  * in a usable state.
4503  */
4504 int stmmac_resume(struct device *dev)
4505 {
4506         struct net_device *ndev = dev_get_drvdata(dev);
4507         struct stmmac_priv *priv = netdev_priv(ndev);
4508
4509         if (!netif_running(ndev))
4510                 return 0;
4511
4512         /* Power Down bit, into the PM register, is cleared
4513          * automatically as soon as a magic packet or a Wake-up frame
4514          * is received. Anyway, it's better to manually clear
4515          * this bit because it can generate problems while resuming
4516          * from another devices (e.g. serial console).
4517          */
4518         if (device_may_wakeup(priv->device)) {
4519                 mutex_lock(&priv->lock);
4520                 stmmac_pmt(priv, priv->hw, 0);
4521                 mutex_unlock(&priv->lock);
4522                 priv->irq_wake = 0;
4523         } else {
4524                 pinctrl_pm_select_default_state(priv->device);
4525                 /* enable the clk previously disabled */
4526                 clk_enable(priv->plat->stmmac_clk);
4527                 clk_enable(priv->plat->pclk);
4528                 /* reset the phy so that it's ready */
4529                 if (priv->mii)
4530                         stmmac_mdio_reset(priv->mii);
4531         }
4532
4533         netif_device_attach(ndev);
4534
4535         mutex_lock(&priv->lock);
4536
4537         stmmac_reset_queues_param(priv);
4538
4539         stmmac_clear_descriptors(priv);
4540
4541         stmmac_hw_setup(ndev, false);
4542         stmmac_init_tx_coalesce(priv);
4543         stmmac_set_rx_mode(ndev);
4544
4545         stmmac_enable_all_queues(priv);
4546
4547         stmmac_start_all_queues(priv);
4548
4549         mutex_unlock(&priv->lock);
4550
4551         phylink_start(priv->phylink);
4552
4553         return 0;
4554 }
4555 EXPORT_SYMBOL_GPL(stmmac_resume);
4556
4557 #ifndef MODULE
4558 static int __init stmmac_cmdline_opt(char *str)
4559 {
4560         char *opt;
4561
4562         if (!str || !*str)
4563                 return -EINVAL;
4564         while ((opt = strsep(&str, ",")) != NULL) {
4565                 if (!strncmp(opt, "debug:", 6)) {
4566                         if (kstrtoint(opt + 6, 0, &debug))
4567                                 goto err;
4568                 } else if (!strncmp(opt, "phyaddr:", 8)) {
4569                         if (kstrtoint(opt + 8, 0, &phyaddr))
4570                                 goto err;
4571                 } else if (!strncmp(opt, "buf_sz:", 7)) {
4572                         if (kstrtoint(opt + 7, 0, &buf_sz))
4573                                 goto err;
4574                 } else if (!strncmp(opt, "tc:", 3)) {
4575                         if (kstrtoint(opt + 3, 0, &tc))
4576                                 goto err;
4577                 } else if (!strncmp(opt, "watchdog:", 9)) {
4578                         if (kstrtoint(opt + 9, 0, &watchdog))
4579                                 goto err;
4580                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4581                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
4582                                 goto err;
4583                 } else if (!strncmp(opt, "pause:", 6)) {
4584                         if (kstrtoint(opt + 6, 0, &pause))
4585                                 goto err;
4586                 } else if (!strncmp(opt, "eee_timer:", 10)) {
4587                         if (kstrtoint(opt + 10, 0, &eee_timer))
4588                                 goto err;
4589                 } else if (!strncmp(opt, "chain_mode:", 11)) {
4590                         if (kstrtoint(opt + 11, 0, &chain_mode))
4591                                 goto err;
4592                 }
4593         }
4594         return 0;
4595
4596 err:
4597         pr_err("%s: ERROR broken module parameter conversion", __func__);
4598         return -EINVAL;
4599 }
4600
4601 __setup("stmmaceth=", stmmac_cmdline_opt);
4602 #endif /* MODULE */
4603
4604 static int __init stmmac_init(void)
4605 {
4606 #ifdef CONFIG_DEBUG_FS
4607         /* Create debugfs main directory if it doesn't exist yet */
4608         if (!stmmac_fs_dir) {
4609                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4610
4611                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4612                         pr_err("ERROR %s, debugfs create directory failed\n",
4613                                STMMAC_RESOURCE_NAME);
4614
4615                         return -ENOMEM;
4616                 }
4617         }
4618 #endif
4619
4620         return 0;
4621 }
4622
4623 static void __exit stmmac_exit(void)
4624 {
4625 #ifdef CONFIG_DEBUG_FS
4626         debugfs_remove_recursive(stmmac_fs_dir);
4627 #endif
4628 }
4629
4630 module_init(stmmac_init)
4631 module_exit(stmmac_exit)
4632
4633 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4634 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4635 MODULE_LICENSE("GPL");