1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/prefetch.h>
32 #include <linux/pinctrl/consumer.h>
33 #ifdef CONFIG_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/seq_file.h>
36 #endif /* CONFIG_DEBUG_FS */
37 #include <linux/net_tstamp.h>
38 #include <net/pkt_cls.h>
39 #include "stmmac_ptp.h"
41 #include <linux/reset.h>
42 #include <linux/of_mdio.h>
43 #include "dwmac1000.h"
47 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
48 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
50 /* Module parameters */
52 static int watchdog = TX_TIMEO;
53 module_param(watchdog, int, 0644);
54 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
56 static int debug = -1;
57 module_param(debug, int, 0644);
58 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
60 static int phyaddr = -1;
61 module_param(phyaddr, int, 0444);
62 MODULE_PARM_DESC(phyaddr, "Physical device address");
64 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
65 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
67 static int flow_ctrl = FLOW_AUTO;
68 module_param(flow_ctrl, int, 0644);
69 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
71 static int pause = PAUSE_TIME;
72 module_param(pause, int, 0644);
73 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
76 static int tc = TC_DEFAULT;
77 module_param(tc, int, 0644);
78 MODULE_PARM_DESC(tc, "DMA threshold control value");
80 #define DEFAULT_BUFSIZE 1536
81 static int buf_sz = DEFAULT_BUFSIZE;
82 module_param(buf_sz, int, 0644);
83 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
85 #define STMMAC_RX_COPYBREAK 256
87 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
88 NETIF_MSG_LINK | NETIF_MSG_IFUP |
89 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
91 #define STMMAC_DEFAULT_LPI_TIMER 1000
92 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
93 module_param(eee_timer, int, 0644);
94 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
95 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
97 /* By default the driver will use the ring mode to manage tx and rx descriptors,
98 * but allow user to force to use the chain instead of the ring
100 static unsigned int chain_mode;
101 module_param(chain_mode, int, 0444);
102 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
104 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
106 #ifdef CONFIG_DEBUG_FS
107 static int stmmac_init_fs(struct net_device *dev);
108 static void stmmac_exit_fs(struct net_device *dev);
111 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
114 * stmmac_verify_args - verify the driver parameters.
115 * Description: it checks the driver parameters and set a default in case of
118 static void stmmac_verify_args(void)
120 if (unlikely(watchdog < 0))
122 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
123 buf_sz = DEFAULT_BUFSIZE;
124 if (unlikely(flow_ctrl > 1))
125 flow_ctrl = FLOW_AUTO;
126 else if (likely(flow_ctrl < 0))
127 flow_ctrl = FLOW_OFF;
128 if (unlikely((pause < 0) || (pause > 0xffff)))
131 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
135 * stmmac_disable_all_queues - Disable all queues
136 * @priv: driver private structure
138 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
140 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
141 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
142 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
145 for (queue = 0; queue < maxq; queue++) {
146 struct stmmac_channel *ch = &priv->channel[queue];
148 if (queue < rx_queues_cnt)
149 napi_disable(&ch->rx_napi);
150 if (queue < tx_queues_cnt)
151 napi_disable(&ch->tx_napi);
156 * stmmac_enable_all_queues - Enable all queues
157 * @priv: driver private structure
159 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
161 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
162 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
163 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
166 for (queue = 0; queue < maxq; queue++) {
167 struct stmmac_channel *ch = &priv->channel[queue];
169 if (queue < rx_queues_cnt)
170 napi_enable(&ch->rx_napi);
171 if (queue < tx_queues_cnt)
172 napi_enable(&ch->tx_napi);
177 * stmmac_stop_all_queues - Stop all queues
178 * @priv: driver private structure
180 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
182 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
185 for (queue = 0; queue < tx_queues_cnt; queue++)
186 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
190 * stmmac_start_all_queues - Start all queues
191 * @priv: driver private structure
193 static void stmmac_start_all_queues(struct stmmac_priv *priv)
195 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
198 for (queue = 0; queue < tx_queues_cnt; queue++)
199 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
202 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
204 if (!test_bit(STMMAC_DOWN, &priv->state) &&
205 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
206 queue_work(priv->wq, &priv->service_task);
209 static void stmmac_global_err(struct stmmac_priv *priv)
211 netif_carrier_off(priv->dev);
212 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
213 stmmac_service_event_schedule(priv);
217 * stmmac_clk_csr_set - dynamically set the MDC clock
218 * @priv: driver private structure
219 * Description: this is to dynamically set the MDC clock according to the csr
222 * If a specific clk_csr value is passed from the platform
223 * this means that the CSR Clock Range selection cannot be
224 * changed at run-time and it is fixed (as reported in the driver
225 * documentation). Viceversa the driver will try to set the MDC
226 * clock dynamically according to the actual clock input.
228 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
232 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
234 /* Platform provided default clk_csr would be assumed valid
235 * for all other cases except for the below mentioned ones.
236 * For values higher than the IEEE 802.3 specified frequency
237 * we can not estimate the proper divider as it is not known
238 * the frequency of clk_csr_i. So we do not change the default
241 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
242 if (clk_rate < CSR_F_35M)
243 priv->clk_csr = STMMAC_CSR_20_35M;
244 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
245 priv->clk_csr = STMMAC_CSR_35_60M;
246 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
247 priv->clk_csr = STMMAC_CSR_60_100M;
248 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
249 priv->clk_csr = STMMAC_CSR_100_150M;
250 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
251 priv->clk_csr = STMMAC_CSR_150_250M;
252 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
253 priv->clk_csr = STMMAC_CSR_250_300M;
256 if (priv->plat->has_sun8i) {
257 if (clk_rate > 160000000)
258 priv->clk_csr = 0x03;
259 else if (clk_rate > 80000000)
260 priv->clk_csr = 0x02;
261 else if (clk_rate > 40000000)
262 priv->clk_csr = 0x01;
267 if (priv->plat->has_xgmac) {
268 if (clk_rate > 400000000)
270 else if (clk_rate > 350000000)
272 else if (clk_rate > 300000000)
274 else if (clk_rate > 250000000)
276 else if (clk_rate > 150000000)
283 static void print_pkt(unsigned char *buf, int len)
285 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
286 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
289 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
291 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
294 if (tx_q->dirty_tx > tx_q->cur_tx)
295 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
297 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
303 * stmmac_rx_dirty - Get RX queue dirty
304 * @priv: driver private structure
305 * @queue: RX queue index
307 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
309 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
312 if (rx_q->dirty_rx <= rx_q->cur_rx)
313 dirty = rx_q->cur_rx - rx_q->dirty_rx;
315 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
321 * stmmac_hw_fix_mac_speed - callback for speed selection
322 * @priv: driver private structure
323 * Description: on some platforms (e.g. ST), some HW system configuration
324 * registers have to be set according to the link speed negotiated.
326 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
328 struct net_device *ndev = priv->dev;
329 struct phy_device *phydev = ndev->phydev;
331 if (likely(priv->plat->fix_mac_speed))
332 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
336 * stmmac_enable_eee_mode - check and enter in LPI mode
337 * @priv: driver private structure
338 * Description: this function is to verify and enter in LPI mode in case of
341 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
343 u32 tx_cnt = priv->plat->tx_queues_to_use;
346 /* check if all TX queues have the work finished */
347 for (queue = 0; queue < tx_cnt; queue++) {
348 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
350 if (tx_q->dirty_tx != tx_q->cur_tx)
351 return; /* still unfinished work */
354 /* Check and enter in LPI mode */
355 if (!priv->tx_path_in_lpi_mode)
356 stmmac_set_eee_mode(priv, priv->hw,
357 priv->plat->en_tx_lpi_clockgating);
361 * stmmac_disable_eee_mode - disable and exit from LPI mode
362 * @priv: driver private structure
363 * Description: this function is to exit and disable EEE in case of
364 * LPI state is true. This is called by the xmit.
366 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
368 stmmac_reset_eee_mode(priv, priv->hw);
369 del_timer_sync(&priv->eee_ctrl_timer);
370 priv->tx_path_in_lpi_mode = false;
374 * stmmac_eee_ctrl_timer - EEE TX SW timer.
377 * if there is no data transfer and if we are not in LPI state,
378 * then MAC Transmitter can be moved to LPI state.
380 static void stmmac_eee_ctrl_timer(struct timer_list *t)
382 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
384 stmmac_enable_eee_mode(priv);
385 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
389 * stmmac_eee_init - init EEE
390 * @priv: driver private structure
392 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
393 * can also manage EEE, this function enable the LPI state and start related
396 bool stmmac_eee_init(struct stmmac_priv *priv)
398 struct net_device *ndev = priv->dev;
399 int interface = priv->plat->interface;
402 if ((interface != PHY_INTERFACE_MODE_MII) &&
403 (interface != PHY_INTERFACE_MODE_GMII) &&
404 !phy_interface_mode_is_rgmii(interface))
407 /* Using PCS we cannot dial with the phy registers at this stage
408 * so we do not support extra feature like EEE.
410 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
411 (priv->hw->pcs == STMMAC_PCS_TBI) ||
412 (priv->hw->pcs == STMMAC_PCS_RTBI))
415 /* MAC core supports the EEE feature. */
416 if (priv->dma_cap.eee) {
417 int tx_lpi_timer = priv->tx_lpi_timer;
419 /* Check if the PHY supports EEE */
420 if (phy_init_eee(ndev->phydev, 1)) {
421 /* To manage at run-time if the EEE cannot be supported
422 * anymore (for example because the lp caps have been
424 * In that case the driver disable own timers.
426 mutex_lock(&priv->lock);
427 if (priv->eee_active) {
428 netdev_dbg(priv->dev, "disable EEE\n");
429 del_timer_sync(&priv->eee_ctrl_timer);
430 stmmac_set_eee_timer(priv, priv->hw, 0,
433 priv->eee_active = 0;
434 mutex_unlock(&priv->lock);
437 /* Activate the EEE and start timers */
438 mutex_lock(&priv->lock);
439 if (!priv->eee_active) {
440 priv->eee_active = 1;
441 timer_setup(&priv->eee_ctrl_timer,
442 stmmac_eee_ctrl_timer, 0);
443 mod_timer(&priv->eee_ctrl_timer,
444 STMMAC_LPI_T(eee_timer));
446 stmmac_set_eee_timer(priv, priv->hw,
447 STMMAC_DEFAULT_LIT_LS, tx_lpi_timer);
449 /* Set HW EEE according to the speed */
450 stmmac_set_eee_pls(priv, priv->hw, ndev->phydev->link);
453 mutex_unlock(&priv->lock);
455 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
461 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
462 * @priv: driver private structure
463 * @p : descriptor pointer
464 * @skb : the socket buffer
466 * This function will read timestamp from the descriptor & pass it to stack.
467 * and also perform some sanity checks.
469 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
470 struct dma_desc *p, struct sk_buff *skb)
472 struct skb_shared_hwtstamps shhwtstamp;
475 if (!priv->hwts_tx_en)
478 /* exit if skb doesn't support hw tstamp */
479 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
482 /* check tx tstamp status */
483 if (stmmac_get_tx_timestamp_status(priv, p)) {
484 /* get the valid tstamp */
485 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
487 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
488 shhwtstamp.hwtstamp = ns_to_ktime(ns);
490 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
491 /* pass tstamp to stack */
492 skb_tstamp_tx(skb, &shhwtstamp);
498 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
499 * @priv: driver private structure
500 * @p : descriptor pointer
501 * @np : next descriptor pointer
502 * @skb : the socket buffer
504 * This function will read received packet's timestamp from the descriptor
505 * and pass it to stack. It also perform some sanity checks.
507 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
508 struct dma_desc *np, struct sk_buff *skb)
510 struct skb_shared_hwtstamps *shhwtstamp = NULL;
511 struct dma_desc *desc = p;
514 if (!priv->hwts_rx_en)
516 /* For GMAC4, the valid timestamp is from CTX next desc. */
517 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
520 /* Check if timestamp is available */
521 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
522 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
523 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
524 shhwtstamp = skb_hwtstamps(skb);
525 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
526 shhwtstamp->hwtstamp = ns_to_ktime(ns);
528 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
533 * stmmac_hwtstamp_set - control hardware timestamping.
534 * @dev: device pointer.
535 * @ifr: An IOCTL specific structure, that can contain a pointer to
536 * a proprietary structure used to pass information to the driver.
538 * This function configures the MAC to enable/disable both outgoing(TX)
539 * and incoming(RX) packets time stamping based on user input.
541 * 0 on success and an appropriate -ve integer on failure.
543 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
545 struct stmmac_priv *priv = netdev_priv(dev);
546 struct hwtstamp_config config;
547 struct timespec64 now;
551 u32 ptp_over_ipv4_udp = 0;
552 u32 ptp_over_ipv6_udp = 0;
553 u32 ptp_over_ethernet = 0;
554 u32 snap_type_sel = 0;
555 u32 ts_master_en = 0;
561 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
563 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
564 netdev_alert(priv->dev, "No support for HW time stamping\n");
565 priv->hwts_tx_en = 0;
566 priv->hwts_rx_en = 0;
571 if (copy_from_user(&config, ifr->ifr_data,
575 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
576 __func__, config.flags, config.tx_type, config.rx_filter);
578 /* reserved for future extensions */
582 if (config.tx_type != HWTSTAMP_TX_OFF &&
583 config.tx_type != HWTSTAMP_TX_ON)
587 switch (config.rx_filter) {
588 case HWTSTAMP_FILTER_NONE:
589 /* time stamp no incoming packet at all */
590 config.rx_filter = HWTSTAMP_FILTER_NONE;
593 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
594 /* PTP v1, UDP, any kind of event packet */
595 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
596 /* 'xmac' hardware can support Sync, Pdelay_Req and
597 * Pdelay_resp by setting bit14 and bits17/16 to 01
598 * This leaves Delay_Req timestamps out.
599 * Enable all events *and* general purpose message
602 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
603 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
604 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
607 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
608 /* PTP v1, UDP, Sync packet */
609 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
610 /* take time stamp for SYNC messages only */
611 ts_event_en = PTP_TCR_TSEVNTENA;
613 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
614 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
617 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
618 /* PTP v1, UDP, Delay_req packet */
619 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
620 /* take time stamp for Delay_Req messages only */
621 ts_master_en = PTP_TCR_TSMSTRENA;
622 ts_event_en = PTP_TCR_TSEVNTENA;
624 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
625 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
628 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
629 /* PTP v2, UDP, any kind of event packet */
630 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
631 ptp_v2 = PTP_TCR_TSVER2ENA;
632 /* take time stamp for all event messages */
633 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
635 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
636 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
639 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
640 /* PTP v2, UDP, Sync packet */
641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
642 ptp_v2 = PTP_TCR_TSVER2ENA;
643 /* take time stamp for SYNC messages only */
644 ts_event_en = PTP_TCR_TSEVNTENA;
646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
650 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
651 /* PTP v2, UDP, Delay_req packet */
652 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
653 ptp_v2 = PTP_TCR_TSVER2ENA;
654 /* take time stamp for Delay_Req messages only */
655 ts_master_en = PTP_TCR_TSMSTRENA;
656 ts_event_en = PTP_TCR_TSEVNTENA;
658 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
659 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
662 case HWTSTAMP_FILTER_PTP_V2_EVENT:
663 /* PTP v2/802.AS1 any layer, any kind of event packet */
664 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
665 ptp_v2 = PTP_TCR_TSVER2ENA;
666 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
667 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
668 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
669 ptp_over_ethernet = PTP_TCR_TSIPENA;
672 case HWTSTAMP_FILTER_PTP_V2_SYNC:
673 /* PTP v2/802.AS1, any layer, Sync packet */
674 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
675 ptp_v2 = PTP_TCR_TSVER2ENA;
676 /* take time stamp for SYNC messages only */
677 ts_event_en = PTP_TCR_TSEVNTENA;
679 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
680 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
681 ptp_over_ethernet = PTP_TCR_TSIPENA;
684 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
685 /* PTP v2/802.AS1, any layer, Delay_req packet */
686 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
687 ptp_v2 = PTP_TCR_TSVER2ENA;
688 /* take time stamp for Delay_Req messages only */
689 ts_master_en = PTP_TCR_TSMSTRENA;
690 ts_event_en = PTP_TCR_TSEVNTENA;
692 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
693 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
694 ptp_over_ethernet = PTP_TCR_TSIPENA;
697 case HWTSTAMP_FILTER_NTP_ALL:
698 case HWTSTAMP_FILTER_ALL:
699 /* time stamp any incoming packet */
700 config.rx_filter = HWTSTAMP_FILTER_ALL;
701 tstamp_all = PTP_TCR_TSENALL;
708 switch (config.rx_filter) {
709 case HWTSTAMP_FILTER_NONE:
710 config.rx_filter = HWTSTAMP_FILTER_NONE;
713 /* PTP v1, UDP, any kind of event packet */
714 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
718 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
719 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
721 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
722 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
724 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
725 tstamp_all | ptp_v2 | ptp_over_ethernet |
726 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
727 ts_master_en | snap_type_sel);
728 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
730 /* program Sub Second Increment reg */
731 stmmac_config_sub_second_increment(priv,
732 priv->ptpaddr, priv->plat->clk_ptp_rate,
734 temp = div_u64(1000000000ULL, sec_inc);
736 /* Store sub second increment and flags for later use */
737 priv->sub_second_inc = sec_inc;
738 priv->systime_flags = value;
740 /* calculate default added value:
742 * addend = (2^32)/freq_div_ratio;
743 * where, freq_div_ratio = 1e9ns/sec_inc
745 temp = (u64)(temp << 32);
746 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
747 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
749 /* initialize system time */
750 ktime_get_real_ts64(&now);
752 /* lower 32 bits of tv_sec are safe until y2106 */
753 stmmac_init_systime(priv, priv->ptpaddr,
754 (u32)now.tv_sec, now.tv_nsec);
757 memcpy(&priv->tstamp_config, &config, sizeof(config));
759 return copy_to_user(ifr->ifr_data, &config,
760 sizeof(config)) ? -EFAULT : 0;
764 * stmmac_hwtstamp_get - read hardware timestamping.
765 * @dev: device pointer.
766 * @ifr: An IOCTL specific structure, that can contain a pointer to
767 * a proprietary structure used to pass information to the driver.
769 * This function obtain the current hardware timestamping settings
772 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
774 struct stmmac_priv *priv = netdev_priv(dev);
775 struct hwtstamp_config *config = &priv->tstamp_config;
777 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
780 return copy_to_user(ifr->ifr_data, config,
781 sizeof(*config)) ? -EFAULT : 0;
785 * stmmac_init_ptp - init PTP
786 * @priv: driver private structure
787 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
788 * This is done by looking at the HW cap. register.
789 * This function also registers the ptp driver.
791 static int stmmac_init_ptp(struct stmmac_priv *priv)
793 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
795 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
799 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
800 if (xmac && priv->dma_cap.atime_stamp)
802 /* Dwmac 3.x core with extend_desc can support adv_ts */
803 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
806 if (priv->dma_cap.time_stamp)
807 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
810 netdev_info(priv->dev,
811 "IEEE 1588-2008 Advanced Timestamp supported\n");
813 priv->hwts_tx_en = 0;
814 priv->hwts_rx_en = 0;
816 stmmac_ptp_register(priv);
821 static void stmmac_release_ptp(struct stmmac_priv *priv)
823 if (priv->plat->clk_ptp_ref)
824 clk_disable_unprepare(priv->plat->clk_ptp_ref);
825 stmmac_ptp_unregister(priv);
829 * stmmac_mac_flow_ctrl - Configure flow control in all queues
830 * @priv: driver private structure
831 * Description: It is used for configuring the flow control in all queues
833 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
835 u32 tx_cnt = priv->plat->tx_queues_to_use;
837 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
838 priv->pause, tx_cnt);
842 * stmmac_adjust_link - adjusts the link parameters
843 * @dev: net device structure
844 * Description: this is the helper called by the physical abstraction layer
845 * drivers to communicate the phy link status. According the speed and duplex
846 * this driver can invoke registered glue-logic as well.
847 * It also invoke the eee initialization because it could happen when switch
848 * on different networks (that are eee capable).
850 static void stmmac_adjust_link(struct net_device *dev)
852 struct stmmac_priv *priv = netdev_priv(dev);
853 struct phy_device *phydev = dev->phydev;
854 bool new_state = false;
859 mutex_lock(&priv->lock);
862 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
864 /* Now we make sure that we can be in full duplex mode.
865 * If not, we operate in half-duplex mode. */
866 if (phydev->duplex != priv->oldduplex) {
869 ctrl &= ~priv->hw->link.duplex;
871 ctrl |= priv->hw->link.duplex;
872 priv->oldduplex = phydev->duplex;
874 /* Flow Control operation */
876 stmmac_mac_flow_ctrl(priv, phydev->duplex);
878 if (phydev->speed != priv->speed) {
880 ctrl &= ~priv->hw->link.speed_mask;
881 switch (phydev->speed) {
883 ctrl |= priv->hw->link.speed1000;
886 ctrl |= priv->hw->link.speed100;
889 ctrl |= priv->hw->link.speed10;
892 netif_warn(priv, link, priv->dev,
893 "broken speed: %d\n", phydev->speed);
894 phydev->speed = SPEED_UNKNOWN;
897 if (phydev->speed != SPEED_UNKNOWN)
898 stmmac_hw_fix_mac_speed(priv);
899 priv->speed = phydev->speed;
902 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
904 if (!priv->oldlink) {
906 priv->oldlink = true;
908 } else if (priv->oldlink) {
910 priv->oldlink = false;
911 priv->speed = SPEED_UNKNOWN;
912 priv->oldduplex = DUPLEX_UNKNOWN;
915 if (new_state && netif_msg_link(priv))
916 phy_print_status(phydev);
918 mutex_unlock(&priv->lock);
920 if (phydev->is_pseudo_fixed_link)
921 /* Stop PHY layer to call the hook to adjust the link in case
922 * of a switch is attached to the stmmac driver.
924 phydev->irq = PHY_IGNORE_INTERRUPT;
926 /* At this stage, init the EEE if supported.
927 * Never called in case of fixed_link.
929 priv->eee_enabled = stmmac_eee_init(priv);
933 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
934 * @priv: driver private structure
935 * Description: this is to verify if the HW supports the PCS.
936 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
937 * configured for the TBI, RTBI, or SGMII PHY interface.
939 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
941 int interface = priv->plat->interface;
943 if (priv->dma_cap.pcs) {
944 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
945 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
946 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
947 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
948 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
949 priv->hw->pcs = STMMAC_PCS_RGMII;
950 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
951 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
952 priv->hw->pcs = STMMAC_PCS_SGMII;
958 * stmmac_init_phy - PHY initialization
959 * @dev: net device structure
960 * Description: it initializes the driver's PHY state, and attaches the PHY
965 static int stmmac_init_phy(struct net_device *dev)
967 struct stmmac_priv *priv = netdev_priv(dev);
968 u32 tx_cnt = priv->plat->tx_queues_to_use;
969 struct phy_device *phydev;
970 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
971 char bus_id[MII_BUS_ID_SIZE];
972 int interface = priv->plat->interface;
973 int max_speed = priv->plat->max_speed;
974 priv->oldlink = false;
975 priv->speed = SPEED_UNKNOWN;
976 priv->oldduplex = DUPLEX_UNKNOWN;
978 if (priv->plat->phy_node) {
979 phydev = of_phy_connect(dev, priv->plat->phy_node,
980 &stmmac_adjust_link, 0, interface);
982 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
985 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
986 priv->plat->phy_addr);
987 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
990 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
994 if (IS_ERR_OR_NULL(phydev)) {
995 netdev_err(priv->dev, "Could not attach to PHY\n");
999 return PTR_ERR(phydev);
1002 /* Stop Advertising 1000BASE Capability if interface is not GMII */
1003 if ((interface == PHY_INTERFACE_MODE_MII) ||
1004 (interface == PHY_INTERFACE_MODE_RMII) ||
1005 (max_speed < 1000 && max_speed > 0))
1006 phy_set_max_speed(phydev, SPEED_100);
1009 * Half-duplex mode not supported with multiqueue
1010 * half-duplex can only works with single queue
1013 phy_remove_link_mode(phydev,
1014 ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1015 phy_remove_link_mode(phydev,
1016 ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1017 phy_remove_link_mode(phydev,
1018 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1022 * Broken HW is sometimes missing the pull-up resistor on the
1023 * MDIO line, which results in reads to non-existent devices returning
1024 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
1026 * Note: phydev->phy_id is the result of reading the UID PHY registers.
1028 if (!priv->plat->phy_node && phydev->phy_id == 0) {
1029 phy_disconnect(phydev);
1033 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
1034 * subsequent PHY polling, make sure we force a link transition if
1035 * we have a UP/DOWN/UP transition
1037 if (phydev->is_pseudo_fixed_link)
1038 phydev->irq = PHY_POLL;
1040 phy_attached_info(phydev);
1044 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1046 u32 rx_cnt = priv->plat->rx_queues_to_use;
1050 /* Display RX rings */
1051 for (queue = 0; queue < rx_cnt; queue++) {
1052 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1054 pr_info("\tRX Queue %u rings\n", queue);
1056 if (priv->extend_desc)
1057 head_rx = (void *)rx_q->dma_erx;
1059 head_rx = (void *)rx_q->dma_rx;
1061 /* Display RX ring */
1062 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1066 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1068 u32 tx_cnt = priv->plat->tx_queues_to_use;
1072 /* Display TX rings */
1073 for (queue = 0; queue < tx_cnt; queue++) {
1074 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1076 pr_info("\tTX Queue %d rings\n", queue);
1078 if (priv->extend_desc)
1079 head_tx = (void *)tx_q->dma_etx;
1081 head_tx = (void *)tx_q->dma_tx;
1083 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1087 static void stmmac_display_rings(struct stmmac_priv *priv)
1089 /* Display RX ring */
1090 stmmac_display_rx_rings(priv);
1092 /* Display TX ring */
1093 stmmac_display_tx_rings(priv);
1096 static int stmmac_set_bfsize(int mtu, int bufsize)
1100 if (mtu >= BUF_SIZE_4KiB)
1101 ret = BUF_SIZE_8KiB;
1102 else if (mtu >= BUF_SIZE_2KiB)
1103 ret = BUF_SIZE_4KiB;
1104 else if (mtu > DEFAULT_BUFSIZE)
1105 ret = BUF_SIZE_2KiB;
1107 ret = DEFAULT_BUFSIZE;
1113 * stmmac_clear_rx_descriptors - clear RX descriptors
1114 * @priv: driver private structure
1115 * @queue: RX queue index
1116 * Description: this function is called to clear the RX descriptors
1117 * in case of both basic and extended descriptors are used.
1119 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1121 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1124 /* Clear the RX descriptors */
1125 for (i = 0; i < DMA_RX_SIZE; i++)
1126 if (priv->extend_desc)
1127 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1128 priv->use_riwt, priv->mode,
1129 (i == DMA_RX_SIZE - 1),
1132 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1133 priv->use_riwt, priv->mode,
1134 (i == DMA_RX_SIZE - 1),
1139 * stmmac_clear_tx_descriptors - clear tx descriptors
1140 * @priv: driver private structure
1141 * @queue: TX queue index.
1142 * Description: this function is called to clear the TX descriptors
1143 * in case of both basic and extended descriptors are used.
1145 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1147 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1150 /* Clear the TX descriptors */
1151 for (i = 0; i < DMA_TX_SIZE; i++)
1152 if (priv->extend_desc)
1153 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1154 priv->mode, (i == DMA_TX_SIZE - 1));
1156 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1157 priv->mode, (i == DMA_TX_SIZE - 1));
1161 * stmmac_clear_descriptors - clear descriptors
1162 * @priv: driver private structure
1163 * Description: this function is called to clear the TX and RX descriptors
1164 * in case of both basic and extended descriptors are used.
1166 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1168 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1169 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1172 /* Clear the RX descriptors */
1173 for (queue = 0; queue < rx_queue_cnt; queue++)
1174 stmmac_clear_rx_descriptors(priv, queue);
1176 /* Clear the TX descriptors */
1177 for (queue = 0; queue < tx_queue_cnt; queue++)
1178 stmmac_clear_tx_descriptors(priv, queue);
1182 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1183 * @priv: driver private structure
1184 * @p: descriptor pointer
1185 * @i: descriptor index
1187 * @queue: RX queue index
1188 * Description: this function is called to allocate a receive buffer, perform
1189 * the DMA mapping and init the descriptor.
1191 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1192 int i, gfp_t flags, u32 queue)
1194 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1195 struct sk_buff *skb;
1197 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1199 netdev_err(priv->dev,
1200 "%s: Rx init fails; skb is NULL\n", __func__);
1203 rx_q->rx_skbuff[i] = skb;
1204 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1207 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1208 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1209 dev_kfree_skb_any(skb);
1213 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1215 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1216 stmmac_init_desc3(priv, p);
1222 * stmmac_free_rx_buffer - free RX dma buffers
1223 * @priv: private structure
1224 * @queue: RX queue index
1227 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1229 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1231 if (rx_q->rx_skbuff[i]) {
1232 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1233 priv->dma_buf_sz, DMA_FROM_DEVICE);
1234 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1236 rx_q->rx_skbuff[i] = NULL;
1240 * stmmac_free_tx_buffer - free RX dma buffers
1241 * @priv: private structure
1242 * @queue: RX queue index
1245 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1247 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1249 if (tx_q->tx_skbuff_dma[i].buf) {
1250 if (tx_q->tx_skbuff_dma[i].map_as_page)
1251 dma_unmap_page(priv->device,
1252 tx_q->tx_skbuff_dma[i].buf,
1253 tx_q->tx_skbuff_dma[i].len,
1256 dma_unmap_single(priv->device,
1257 tx_q->tx_skbuff_dma[i].buf,
1258 tx_q->tx_skbuff_dma[i].len,
1262 if (tx_q->tx_skbuff[i]) {
1263 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1264 tx_q->tx_skbuff[i] = NULL;
1265 tx_q->tx_skbuff_dma[i].buf = 0;
1266 tx_q->tx_skbuff_dma[i].map_as_page = false;
1271 * init_dma_rx_desc_rings - init the RX descriptor rings
1272 * @dev: net device structure
1274 * Description: this function initializes the DMA RX descriptors
1275 * and allocates the socket buffers. It supports the chained and ring
1278 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1280 struct stmmac_priv *priv = netdev_priv(dev);
1281 u32 rx_count = priv->plat->rx_queues_to_use;
1287 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1291 if (bfsize < BUF_SIZE_16KiB)
1292 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1294 priv->dma_buf_sz = bfsize;
1296 /* RX INITIALIZATION */
1297 netif_dbg(priv, probe, priv->dev,
1298 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1300 for (queue = 0; queue < rx_count; queue++) {
1301 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1303 netif_dbg(priv, probe, priv->dev,
1304 "(%s) dma_rx_phy=0x%08x\n", __func__,
1305 (u32)rx_q->dma_rx_phy);
1307 for (i = 0; i < DMA_RX_SIZE; i++) {
1310 if (priv->extend_desc)
1311 p = &((rx_q->dma_erx + i)->basic);
1313 p = rx_q->dma_rx + i;
1315 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1318 goto err_init_rx_buffers;
1320 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1321 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1322 (unsigned int)rx_q->rx_skbuff_dma[i]);
1326 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1328 stmmac_clear_rx_descriptors(priv, queue);
1330 /* Setup the chained descriptor addresses */
1331 if (priv->mode == STMMAC_CHAIN_MODE) {
1332 if (priv->extend_desc)
1333 stmmac_mode_init(priv, rx_q->dma_erx,
1334 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1336 stmmac_mode_init(priv, rx_q->dma_rx,
1337 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1345 err_init_rx_buffers:
1346 while (queue >= 0) {
1348 stmmac_free_rx_buffer(priv, queue, i);
1361 * init_dma_tx_desc_rings - init the TX descriptor rings
1362 * @dev: net device structure.
1363 * Description: this function initializes the DMA TX descriptors
1364 * and allocates the socket buffers. It supports the chained and ring
1367 static int init_dma_tx_desc_rings(struct net_device *dev)
1369 struct stmmac_priv *priv = netdev_priv(dev);
1370 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1374 for (queue = 0; queue < tx_queue_cnt; queue++) {
1375 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1377 netif_dbg(priv, probe, priv->dev,
1378 "(%s) dma_tx_phy=0x%08x\n", __func__,
1379 (u32)tx_q->dma_tx_phy);
1381 /* Setup the chained descriptor addresses */
1382 if (priv->mode == STMMAC_CHAIN_MODE) {
1383 if (priv->extend_desc)
1384 stmmac_mode_init(priv, tx_q->dma_etx,
1385 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1387 stmmac_mode_init(priv, tx_q->dma_tx,
1388 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1391 for (i = 0; i < DMA_TX_SIZE; i++) {
1393 if (priv->extend_desc)
1394 p = &((tx_q->dma_etx + i)->basic);
1396 p = tx_q->dma_tx + i;
1398 stmmac_clear_desc(priv, p);
1400 tx_q->tx_skbuff_dma[i].buf = 0;
1401 tx_q->tx_skbuff_dma[i].map_as_page = false;
1402 tx_q->tx_skbuff_dma[i].len = 0;
1403 tx_q->tx_skbuff_dma[i].last_segment = false;
1404 tx_q->tx_skbuff[i] = NULL;
1411 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1418 * init_dma_desc_rings - init the RX/TX descriptor rings
1419 * @dev: net device structure
1421 * Description: this function initializes the DMA RX/TX descriptors
1422 * and allocates the socket buffers. It supports the chained and ring
1425 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1427 struct stmmac_priv *priv = netdev_priv(dev);
1430 ret = init_dma_rx_desc_rings(dev, flags);
1434 ret = init_dma_tx_desc_rings(dev);
1436 stmmac_clear_descriptors(priv);
1438 if (netif_msg_hw(priv))
1439 stmmac_display_rings(priv);
1445 * dma_free_rx_skbufs - free RX dma buffers
1446 * @priv: private structure
1447 * @queue: RX queue index
1449 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1453 for (i = 0; i < DMA_RX_SIZE; i++)
1454 stmmac_free_rx_buffer(priv, queue, i);
1458 * dma_free_tx_skbufs - free TX dma buffers
1459 * @priv: private structure
1460 * @queue: TX queue index
1462 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1466 for (i = 0; i < DMA_TX_SIZE; i++)
1467 stmmac_free_tx_buffer(priv, queue, i);
1471 * free_dma_rx_desc_resources - free RX dma desc resources
1472 * @priv: private structure
1474 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1476 u32 rx_count = priv->plat->rx_queues_to_use;
1479 /* Free RX queue resources */
1480 for (queue = 0; queue < rx_count; queue++) {
1481 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1483 /* Release the DMA RX socket buffers */
1484 dma_free_rx_skbufs(priv, queue);
1486 /* Free DMA regions of consistent memory previously allocated */
1487 if (!priv->extend_desc)
1488 dma_free_coherent(priv->device,
1489 DMA_RX_SIZE * sizeof(struct dma_desc),
1490 rx_q->dma_rx, rx_q->dma_rx_phy);
1492 dma_free_coherent(priv->device, DMA_RX_SIZE *
1493 sizeof(struct dma_extended_desc),
1494 rx_q->dma_erx, rx_q->dma_rx_phy);
1496 kfree(rx_q->rx_skbuff_dma);
1497 kfree(rx_q->rx_skbuff);
1502 * free_dma_tx_desc_resources - free TX dma desc resources
1503 * @priv: private structure
1505 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1507 u32 tx_count = priv->plat->tx_queues_to_use;
1510 /* Free TX queue resources */
1511 for (queue = 0; queue < tx_count; queue++) {
1512 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1514 /* Release the DMA TX socket buffers */
1515 dma_free_tx_skbufs(priv, queue);
1517 /* Free DMA regions of consistent memory previously allocated */
1518 if (!priv->extend_desc)
1519 dma_free_coherent(priv->device,
1520 DMA_TX_SIZE * sizeof(struct dma_desc),
1521 tx_q->dma_tx, tx_q->dma_tx_phy);
1523 dma_free_coherent(priv->device, DMA_TX_SIZE *
1524 sizeof(struct dma_extended_desc),
1525 tx_q->dma_etx, tx_q->dma_tx_phy);
1527 kfree(tx_q->tx_skbuff_dma);
1528 kfree(tx_q->tx_skbuff);
1533 * alloc_dma_rx_desc_resources - alloc RX resources.
1534 * @priv: private structure
1535 * Description: according to which descriptor can be used (extend or basic)
1536 * this function allocates the resources for TX and RX paths. In case of
1537 * reception, for example, it pre-allocated the RX socket buffer in order to
1538 * allow zero-copy mechanism.
1540 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1542 u32 rx_count = priv->plat->rx_queues_to_use;
1546 /* RX queues buffers and DMA */
1547 for (queue = 0; queue < rx_count; queue++) {
1548 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1550 rx_q->queue_index = queue;
1551 rx_q->priv_data = priv;
1553 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1556 if (!rx_q->rx_skbuff_dma)
1559 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1560 sizeof(struct sk_buff *),
1562 if (!rx_q->rx_skbuff)
1565 if (priv->extend_desc) {
1566 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1567 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1574 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1575 DMA_RX_SIZE * sizeof(struct dma_desc),
1586 free_dma_rx_desc_resources(priv);
1592 * alloc_dma_tx_desc_resources - alloc TX resources.
1593 * @priv: private structure
1594 * Description: according to which descriptor can be used (extend or basic)
1595 * this function allocates the resources for TX and RX paths. In case of
1596 * reception, for example, it pre-allocated the RX socket buffer in order to
1597 * allow zero-copy mechanism.
1599 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1601 u32 tx_count = priv->plat->tx_queues_to_use;
1605 /* TX queues buffers and DMA */
1606 for (queue = 0; queue < tx_count; queue++) {
1607 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1609 tx_q->queue_index = queue;
1610 tx_q->priv_data = priv;
1612 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1613 sizeof(*tx_q->tx_skbuff_dma),
1615 if (!tx_q->tx_skbuff_dma)
1618 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1619 sizeof(struct sk_buff *),
1621 if (!tx_q->tx_skbuff)
1624 if (priv->extend_desc) {
1625 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1626 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1632 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1633 DMA_TX_SIZE * sizeof(struct dma_desc),
1644 free_dma_tx_desc_resources(priv);
1650 * alloc_dma_desc_resources - alloc TX/RX resources.
1651 * @priv: private structure
1652 * Description: according to which descriptor can be used (extend or basic)
1653 * this function allocates the resources for TX and RX paths. In case of
1654 * reception, for example, it pre-allocated the RX socket buffer in order to
1655 * allow zero-copy mechanism.
1657 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1660 int ret = alloc_dma_rx_desc_resources(priv);
1665 ret = alloc_dma_tx_desc_resources(priv);
1671 * free_dma_desc_resources - free dma desc resources
1672 * @priv: private structure
1674 static void free_dma_desc_resources(struct stmmac_priv *priv)
1676 /* Release the DMA RX socket buffers */
1677 free_dma_rx_desc_resources(priv);
1679 /* Release the DMA TX socket buffers */
1680 free_dma_tx_desc_resources(priv);
1684 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1685 * @priv: driver private structure
1686 * Description: It is used for enabling the rx queues in the MAC
1688 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1690 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1694 for (queue = 0; queue < rx_queues_count; queue++) {
1695 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1696 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1701 * stmmac_start_rx_dma - start RX DMA channel
1702 * @priv: driver private structure
1703 * @chan: RX channel index
1705 * This starts a RX DMA channel
1707 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1709 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1710 stmmac_start_rx(priv, priv->ioaddr, chan);
1714 * stmmac_start_tx_dma - start TX DMA channel
1715 * @priv: driver private structure
1716 * @chan: TX channel index
1718 * This starts a TX DMA channel
1720 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1722 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1723 stmmac_start_tx(priv, priv->ioaddr, chan);
1727 * stmmac_stop_rx_dma - stop RX DMA channel
1728 * @priv: driver private structure
1729 * @chan: RX channel index
1731 * This stops a RX DMA channel
1733 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1735 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1736 stmmac_stop_rx(priv, priv->ioaddr, chan);
1740 * stmmac_stop_tx_dma - stop TX DMA channel
1741 * @priv: driver private structure
1742 * @chan: TX channel index
1744 * This stops a TX DMA channel
1746 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1748 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1749 stmmac_stop_tx(priv, priv->ioaddr, chan);
1753 * stmmac_start_all_dma - start all RX and TX DMA channels
1754 * @priv: driver private structure
1756 * This starts all the RX and TX DMA channels
1758 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1760 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1761 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1764 for (chan = 0; chan < rx_channels_count; chan++)
1765 stmmac_start_rx_dma(priv, chan);
1767 for (chan = 0; chan < tx_channels_count; chan++)
1768 stmmac_start_tx_dma(priv, chan);
1772 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1773 * @priv: driver private structure
1775 * This stops the RX and TX DMA channels
1777 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1779 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1780 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1783 for (chan = 0; chan < rx_channels_count; chan++)
1784 stmmac_stop_rx_dma(priv, chan);
1786 for (chan = 0; chan < tx_channels_count; chan++)
1787 stmmac_stop_tx_dma(priv, chan);
1791 * stmmac_dma_operation_mode - HW DMA operation mode
1792 * @priv: driver private structure
1793 * Description: it is used for configuring the DMA operation mode register in
1794 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1796 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1798 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1799 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1800 int rxfifosz = priv->plat->rx_fifo_size;
1801 int txfifosz = priv->plat->tx_fifo_size;
1808 rxfifosz = priv->dma_cap.rx_fifo_size;
1810 txfifosz = priv->dma_cap.tx_fifo_size;
1812 /* Adjust for real per queue fifo size */
1813 rxfifosz /= rx_channels_count;
1814 txfifosz /= tx_channels_count;
1816 if (priv->plat->force_thresh_dma_mode) {
1819 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1821 * In case of GMAC, SF mode can be enabled
1822 * to perform the TX COE in HW. This depends on:
1823 * 1) TX COE if actually supported
1824 * 2) There is no bugged Jumbo frame support
1825 * that needs to not insert csum in the TDES.
1827 txmode = SF_DMA_MODE;
1828 rxmode = SF_DMA_MODE;
1829 priv->xstats.threshold = SF_DMA_MODE;
1832 rxmode = SF_DMA_MODE;
1835 /* configure all channels */
1836 for (chan = 0; chan < rx_channels_count; chan++) {
1837 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1839 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1841 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1845 for (chan = 0; chan < tx_channels_count; chan++) {
1846 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1848 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1854 * stmmac_tx_clean - to manage the transmission completion
1855 * @priv: driver private structure
1856 * @queue: TX queue index
1857 * Description: it reclaims the transmit resources after transmission completes.
1859 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1861 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1862 unsigned int bytes_compl = 0, pkts_compl = 0;
1863 unsigned int entry, count = 0;
1865 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1867 priv->xstats.tx_clean++;
1869 entry = tx_q->dirty_tx;
1870 while ((entry != tx_q->cur_tx) && (count < budget)) {
1871 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1875 if (priv->extend_desc)
1876 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1878 p = tx_q->dma_tx + entry;
1880 status = stmmac_tx_status(priv, &priv->dev->stats,
1881 &priv->xstats, p, priv->ioaddr);
1882 /* Check if the descriptor is owned by the DMA */
1883 if (unlikely(status & tx_dma_own))
1888 /* Make sure descriptor fields are read after reading
1893 /* Just consider the last segment and ...*/
1894 if (likely(!(status & tx_not_ls))) {
1895 /* ... verify the status error condition */
1896 if (unlikely(status & tx_err)) {
1897 priv->dev->stats.tx_errors++;
1899 priv->dev->stats.tx_packets++;
1900 priv->xstats.tx_pkt_n++;
1902 stmmac_get_tx_hwtstamp(priv, p, skb);
1905 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1906 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1907 dma_unmap_page(priv->device,
1908 tx_q->tx_skbuff_dma[entry].buf,
1909 tx_q->tx_skbuff_dma[entry].len,
1912 dma_unmap_single(priv->device,
1913 tx_q->tx_skbuff_dma[entry].buf,
1914 tx_q->tx_skbuff_dma[entry].len,
1916 tx_q->tx_skbuff_dma[entry].buf = 0;
1917 tx_q->tx_skbuff_dma[entry].len = 0;
1918 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1921 stmmac_clean_desc3(priv, tx_q, p);
1923 tx_q->tx_skbuff_dma[entry].last_segment = false;
1924 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1926 if (likely(skb != NULL)) {
1928 bytes_compl += skb->len;
1929 dev_consume_skb_any(skb);
1930 tx_q->tx_skbuff[entry] = NULL;
1933 stmmac_release_tx_desc(priv, p, priv->mode);
1935 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1937 tx_q->dirty_tx = entry;
1939 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1940 pkts_compl, bytes_compl);
1942 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1944 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1946 netif_dbg(priv, tx_done, priv->dev,
1947 "%s: restart transmit\n", __func__);
1948 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1951 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1952 stmmac_enable_eee_mode(priv);
1953 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1956 /* We still have pending packets, let's call for a new scheduling */
1957 if (tx_q->dirty_tx != tx_q->cur_tx)
1958 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1960 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1966 * stmmac_tx_err - to manage the tx error
1967 * @priv: driver private structure
1968 * @chan: channel index
1969 * Description: it cleans the descriptors and restarts the transmission
1970 * in case of transmission errors.
1972 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1974 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1977 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1979 stmmac_stop_tx_dma(priv, chan);
1980 dma_free_tx_skbufs(priv, chan);
1981 for (i = 0; i < DMA_TX_SIZE; i++)
1982 if (priv->extend_desc)
1983 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1984 priv->mode, (i == DMA_TX_SIZE - 1));
1986 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1987 priv->mode, (i == DMA_TX_SIZE - 1));
1991 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1992 stmmac_start_tx_dma(priv, chan);
1994 priv->dev->stats.tx_errors++;
1995 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1999 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2000 * @priv: driver private structure
2001 * @txmode: TX operating mode
2002 * @rxmode: RX operating mode
2003 * @chan: channel index
2004 * Description: it is used for configuring of the DMA operation mode in
2005 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2008 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2009 u32 rxmode, u32 chan)
2011 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2012 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2013 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2014 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2015 int rxfifosz = priv->plat->rx_fifo_size;
2016 int txfifosz = priv->plat->tx_fifo_size;
2019 rxfifosz = priv->dma_cap.rx_fifo_size;
2021 txfifosz = priv->dma_cap.tx_fifo_size;
2023 /* Adjust for real per queue fifo size */
2024 rxfifosz /= rx_channels_count;
2025 txfifosz /= tx_channels_count;
2027 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2028 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2031 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2035 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2036 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2037 if (ret && (ret != -EINVAL)) {
2038 stmmac_global_err(priv);
2045 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2047 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2048 &priv->xstats, chan);
2049 struct stmmac_channel *ch = &priv->channel[chan];
2051 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2052 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2053 napi_schedule_irqoff(&ch->rx_napi);
2056 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2057 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2058 napi_schedule_irqoff(&ch->tx_napi);
2065 * stmmac_dma_interrupt - DMA ISR
2066 * @priv: driver private structure
2067 * Description: this is the DMA ISR. It is called by the main ISR.
2068 * It calls the dwmac dma routine and schedule poll method in case of some
2071 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2073 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2074 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2075 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2076 tx_channel_count : rx_channel_count;
2078 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2080 /* Make sure we never check beyond our status buffer. */
2081 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2082 channels_to_check = ARRAY_SIZE(status);
2084 for (chan = 0; chan < channels_to_check; chan++)
2085 status[chan] = stmmac_napi_check(priv, chan);
2087 for (chan = 0; chan < tx_channel_count; chan++) {
2088 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2089 /* Try to bump up the dma threshold on this failure */
2090 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2093 if (priv->plat->force_thresh_dma_mode)
2094 stmmac_set_dma_operation_mode(priv,
2099 stmmac_set_dma_operation_mode(priv,
2103 priv->xstats.threshold = tc;
2105 } else if (unlikely(status[chan] == tx_hard_error)) {
2106 stmmac_tx_err(priv, chan);
2112 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2113 * @priv: driver private structure
2114 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2116 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2118 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2119 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2121 dwmac_mmc_intr_all_mask(priv->mmcaddr);
2123 if (priv->dma_cap.rmon) {
2124 dwmac_mmc_ctrl(priv->mmcaddr, mode);
2125 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2127 netdev_info(priv->dev, "No MAC Management Counters available\n");
2131 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2132 * @priv: driver private structure
2134 * new GMAC chip generations have a new register to indicate the
2135 * presence of the optional feature/functions.
2136 * This can be also used to override the value passed through the
2137 * platform and necessary for old MAC10/100 and GMAC chips.
2139 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2141 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2145 * stmmac_check_ether_addr - check if the MAC addr is valid
2146 * @priv: driver private structure
2148 * it is to verify if the MAC address is valid, in case of failures it
2149 * generates a random MAC address
2151 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2153 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2154 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2155 if (!is_valid_ether_addr(priv->dev->dev_addr))
2156 eth_hw_addr_random(priv->dev);
2157 netdev_info(priv->dev, "device MAC address %pM\n",
2158 priv->dev->dev_addr);
2163 * stmmac_init_dma_engine - DMA init.
2164 * @priv: driver private structure
2166 * It inits the DMA invoking the specific MAC/GMAC callback.
2167 * Some DMA parameters can be passed from the platform;
2168 * in case of these are not passed a default is kept for the MAC or GMAC.
2170 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2172 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2173 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2174 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2175 struct stmmac_rx_queue *rx_q;
2176 struct stmmac_tx_queue *tx_q;
2181 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2182 dev_err(priv->device, "Invalid DMA configuration\n");
2186 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2189 ret = stmmac_reset(priv, priv->ioaddr);
2191 dev_err(priv->device, "Failed to reset the dma\n");
2195 /* DMA Configuration */
2196 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2198 if (priv->plat->axi)
2199 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2201 /* DMA CSR Channel configuration */
2202 for (chan = 0; chan < dma_csr_ch; chan++)
2203 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2205 /* DMA RX Channel Configuration */
2206 for (chan = 0; chan < rx_channels_count; chan++) {
2207 rx_q = &priv->rx_queue[chan];
2209 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2210 rx_q->dma_rx_phy, chan);
2212 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2213 (DMA_RX_SIZE * sizeof(struct dma_desc));
2214 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2215 rx_q->rx_tail_addr, chan);
2218 /* DMA TX Channel Configuration */
2219 for (chan = 0; chan < tx_channels_count; chan++) {
2220 tx_q = &priv->tx_queue[chan];
2222 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2223 tx_q->dma_tx_phy, chan);
2225 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2226 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2227 tx_q->tx_tail_addr, chan);
2233 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2235 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2237 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2241 * stmmac_tx_timer - mitigation sw timer for tx.
2242 * @data: data pointer
2244 * This is the timer handler to directly invoke the stmmac_tx_clean.
2246 static void stmmac_tx_timer(struct timer_list *t)
2248 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2249 struct stmmac_priv *priv = tx_q->priv_data;
2250 struct stmmac_channel *ch;
2252 ch = &priv->channel[tx_q->queue_index];
2255 * If NAPI is already running we can miss some events. Let's rearm
2256 * the timer and try again.
2258 if (likely(napi_schedule_prep(&ch->tx_napi)))
2259 __napi_schedule(&ch->tx_napi);
2261 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2265 * stmmac_init_tx_coalesce - init tx mitigation options.
2266 * @priv: driver private structure
2268 * This inits the transmit coalesce parameters: i.e. timer rate,
2269 * timer handler and default threshold used for enabling the
2270 * interrupt on completion bit.
2272 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2274 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2277 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2278 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2280 for (chan = 0; chan < tx_channel_count; chan++) {
2281 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2283 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2287 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2289 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2290 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2293 /* set TX ring length */
2294 for (chan = 0; chan < tx_channels_count; chan++)
2295 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2296 (DMA_TX_SIZE - 1), chan);
2298 /* set RX ring length */
2299 for (chan = 0; chan < rx_channels_count; chan++)
2300 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2301 (DMA_RX_SIZE - 1), chan);
2305 * stmmac_set_tx_queue_weight - Set TX queue weight
2306 * @priv: driver private structure
2307 * Description: It is used for setting TX queues weight
2309 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2311 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2315 for (queue = 0; queue < tx_queues_count; queue++) {
2316 weight = priv->plat->tx_queues_cfg[queue].weight;
2317 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2322 * stmmac_configure_cbs - Configure CBS in TX queue
2323 * @priv: driver private structure
2324 * Description: It is used for configuring CBS in AVB TX queues
2326 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2328 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2332 /* queue 0 is reserved for legacy traffic */
2333 for (queue = 1; queue < tx_queues_count; queue++) {
2334 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2335 if (mode_to_use == MTL_QUEUE_DCB)
2338 stmmac_config_cbs(priv, priv->hw,
2339 priv->plat->tx_queues_cfg[queue].send_slope,
2340 priv->plat->tx_queues_cfg[queue].idle_slope,
2341 priv->plat->tx_queues_cfg[queue].high_credit,
2342 priv->plat->tx_queues_cfg[queue].low_credit,
2348 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2349 * @priv: driver private structure
2350 * Description: It is used for mapping RX queues to RX dma channels
2352 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2354 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2358 for (queue = 0; queue < rx_queues_count; queue++) {
2359 chan = priv->plat->rx_queues_cfg[queue].chan;
2360 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2365 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2366 * @priv: driver private structure
2367 * Description: It is used for configuring the RX Queue Priority
2369 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2371 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2375 for (queue = 0; queue < rx_queues_count; queue++) {
2376 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2379 prio = priv->plat->rx_queues_cfg[queue].prio;
2380 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2385 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2386 * @priv: driver private structure
2387 * Description: It is used for configuring the TX Queue Priority
2389 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2391 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2395 for (queue = 0; queue < tx_queues_count; queue++) {
2396 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2399 prio = priv->plat->tx_queues_cfg[queue].prio;
2400 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2405 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2406 * @priv: driver private structure
2407 * Description: It is used for configuring the RX queue routing
2409 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2411 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2415 for (queue = 0; queue < rx_queues_count; queue++) {
2416 /* no specific packet type routing specified for the queue */
2417 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2420 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2421 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2426 * stmmac_mtl_configuration - Configure MTL
2427 * @priv: driver private structure
2428 * Description: It is used for configurring MTL
2430 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2432 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2433 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2435 if (tx_queues_count > 1)
2436 stmmac_set_tx_queue_weight(priv);
2438 /* Configure MTL RX algorithms */
2439 if (rx_queues_count > 1)
2440 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2441 priv->plat->rx_sched_algorithm);
2443 /* Configure MTL TX algorithms */
2444 if (tx_queues_count > 1)
2445 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2446 priv->plat->tx_sched_algorithm);
2448 /* Configure CBS in AVB TX queues */
2449 if (tx_queues_count > 1)
2450 stmmac_configure_cbs(priv);
2452 /* Map RX MTL to DMA channels */
2453 stmmac_rx_queue_dma_chan_map(priv);
2455 /* Enable MAC RX Queues */
2456 stmmac_mac_enable_rx_queues(priv);
2458 /* Set RX priorities */
2459 if (rx_queues_count > 1)
2460 stmmac_mac_config_rx_queues_prio(priv);
2462 /* Set TX priorities */
2463 if (tx_queues_count > 1)
2464 stmmac_mac_config_tx_queues_prio(priv);
2466 /* Set RX routing */
2467 if (rx_queues_count > 1)
2468 stmmac_mac_config_rx_queues_routing(priv);
2471 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2473 if (priv->dma_cap.asp) {
2474 netdev_info(priv->dev, "Enabling Safety Features\n");
2475 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2477 netdev_info(priv->dev, "No Safety Features support found\n");
2482 * stmmac_hw_setup - setup mac in a usable state.
2483 * @dev : pointer to the device structure.
2485 * this is the main function to setup the HW in a usable state because the
2486 * dma engine is reset, the core registers are configured (e.g. AXI,
2487 * Checksum features, timers). The DMA is ready to start receiving and
2490 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2493 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2495 struct stmmac_priv *priv = netdev_priv(dev);
2496 u32 rx_cnt = priv->plat->rx_queues_to_use;
2497 u32 tx_cnt = priv->plat->tx_queues_to_use;
2501 /* DMA initialization and SW reset */
2502 ret = stmmac_init_dma_engine(priv);
2504 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2509 /* Copy the MAC addr into the HW */
2510 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2512 /* PS and related bits will be programmed according to the speed */
2513 if (priv->hw->pcs) {
2514 int speed = priv->plat->mac_port_sel_speed;
2516 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2517 (speed == SPEED_1000)) {
2518 priv->hw->ps = speed;
2520 dev_warn(priv->device, "invalid port speed\n");
2525 /* Initialize the MAC Core */
2526 stmmac_core_init(priv, priv->hw, dev);
2529 stmmac_mtl_configuration(priv);
2531 /* Initialize Safety Features */
2532 stmmac_safety_feat_configuration(priv);
2534 ret = stmmac_rx_ipc(priv, priv->hw);
2536 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2537 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2538 priv->hw->rx_csum = 0;
2541 /* Enable the MAC Rx/Tx */
2542 stmmac_mac_set(priv, priv->ioaddr, true);
2544 /* Set the HW DMA mode and the COE */
2545 stmmac_dma_operation_mode(priv);
2547 stmmac_mmc_setup(priv);
2550 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2552 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2554 ret = stmmac_init_ptp(priv);
2555 if (ret == -EOPNOTSUPP)
2556 netdev_warn(priv->dev, "PTP not supported by HW\n");
2558 netdev_warn(priv->dev, "PTP init failed\n");
2561 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2563 if (priv->use_riwt) {
2564 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2566 priv->rx_riwt = MAX_DMA_RIWT;
2570 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2572 /* set TX and RX rings length */
2573 stmmac_set_rings_length(priv);
2577 for (chan = 0; chan < tx_cnt; chan++)
2578 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2581 /* Start the ball rolling... */
2582 stmmac_start_all_dma(priv);
2587 static void stmmac_hw_teardown(struct net_device *dev)
2589 struct stmmac_priv *priv = netdev_priv(dev);
2591 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2595 * stmmac_open - open entry point of the driver
2596 * @dev : pointer to the device structure.
2598 * This function is the open entry point of the driver.
2600 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2603 static int stmmac_open(struct net_device *dev)
2605 struct stmmac_priv *priv = netdev_priv(dev);
2609 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2610 priv->hw->pcs != STMMAC_PCS_TBI &&
2611 priv->hw->pcs != STMMAC_PCS_RTBI) {
2612 ret = stmmac_init_phy(dev);
2614 netdev_err(priv->dev,
2615 "%s: Cannot attach to PHY (error: %d)\n",
2621 /* Extra statistics */
2622 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2623 priv->xstats.threshold = tc;
2625 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2626 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2628 ret = alloc_dma_desc_resources(priv);
2630 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2632 goto dma_desc_error;
2635 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2637 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2642 ret = stmmac_hw_setup(dev, true);
2644 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2648 stmmac_init_tx_coalesce(priv);
2651 phy_start(dev->phydev);
2653 /* Request the IRQ lines */
2654 ret = request_irq(dev->irq, stmmac_interrupt,
2655 IRQF_SHARED, dev->name, dev);
2656 if (unlikely(ret < 0)) {
2657 netdev_err(priv->dev,
2658 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2659 __func__, dev->irq, ret);
2663 /* Request the Wake IRQ in case of another line is used for WoL */
2664 if (priv->wol_irq != dev->irq) {
2665 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2666 IRQF_SHARED, dev->name, dev);
2667 if (unlikely(ret < 0)) {
2668 netdev_err(priv->dev,
2669 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2670 __func__, priv->wol_irq, ret);
2675 /* Request the IRQ lines */
2676 if (priv->lpi_irq > 0) {
2677 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2679 if (unlikely(ret < 0)) {
2680 netdev_err(priv->dev,
2681 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2682 __func__, priv->lpi_irq, ret);
2687 stmmac_enable_all_queues(priv);
2688 stmmac_start_all_queues(priv);
2693 if (priv->wol_irq != dev->irq)
2694 free_irq(priv->wol_irq, dev);
2696 free_irq(dev->irq, dev);
2699 phy_stop(dev->phydev);
2701 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2702 del_timer_sync(&priv->tx_queue[chan].txtimer);
2704 stmmac_hw_teardown(dev);
2706 free_dma_desc_resources(priv);
2709 phy_disconnect(dev->phydev);
2715 * stmmac_release - close entry point of the driver
2716 * @dev : device pointer.
2718 * This is the stop entry point of the driver.
2720 static int stmmac_release(struct net_device *dev)
2722 struct stmmac_priv *priv = netdev_priv(dev);
2725 if (priv->eee_enabled)
2726 del_timer_sync(&priv->eee_ctrl_timer);
2728 /* Stop and disconnect the PHY */
2730 phy_stop(dev->phydev);
2731 phy_disconnect(dev->phydev);
2734 stmmac_stop_all_queues(priv);
2736 stmmac_disable_all_queues(priv);
2738 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2739 del_timer_sync(&priv->tx_queue[chan].txtimer);
2741 /* Free the IRQ lines */
2742 free_irq(dev->irq, dev);
2743 if (priv->wol_irq != dev->irq)
2744 free_irq(priv->wol_irq, dev);
2745 if (priv->lpi_irq > 0)
2746 free_irq(priv->lpi_irq, dev);
2748 /* Stop TX/RX DMA and clear the descriptors */
2749 stmmac_stop_all_dma(priv);
2751 /* Release and free the Rx/Tx resources */
2752 free_dma_desc_resources(priv);
2754 /* Disable the MAC Rx/Tx */
2755 stmmac_mac_set(priv, priv->ioaddr, false);
2757 netif_carrier_off(dev);
2759 stmmac_release_ptp(priv);
2765 * stmmac_tso_allocator - close entry point of the driver
2766 * @priv: driver private structure
2767 * @des: buffer start address
2768 * @total_len: total length to fill in descriptors
2769 * @last_segmant: condition for the last descriptor
2770 * @queue: TX queue index
2772 * This function fills descriptor and request new descriptors according to
2773 * buffer length to fill
2775 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2776 int total_len, bool last_segment, u32 queue)
2778 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2779 struct dma_desc *desc;
2783 tmp_len = total_len;
2785 while (tmp_len > 0) {
2786 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2787 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2788 desc = tx_q->dma_tx + tx_q->cur_tx;
2790 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2791 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2792 TSO_MAX_BUFF_SIZE : tmp_len;
2794 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2796 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2799 tmp_len -= TSO_MAX_BUFF_SIZE;
2804 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2805 * @skb : the socket buffer
2806 * @dev : device pointer
2807 * Description: this is the transmit function that is called on TSO frames
2808 * (support available on GMAC4 and newer chips).
2809 * Diagram below show the ring programming in case of TSO frames:
2813 * | DES0 |---> buffer1 = L2/L3/L4 header
2814 * | DES1 |---> TCP Payload (can continue on next descr...)
2815 * | DES2 |---> buffer 1 and 2 len
2816 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2822 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2824 * | DES2 | --> buffer 1 and 2 len
2828 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2830 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2832 struct dma_desc *desc, *first, *mss_desc = NULL;
2833 struct stmmac_priv *priv = netdev_priv(dev);
2834 int nfrags = skb_shinfo(skb)->nr_frags;
2835 u32 queue = skb_get_queue_mapping(skb);
2836 unsigned int first_entry, des;
2837 struct stmmac_tx_queue *tx_q;
2838 int tmp_pay_len = 0;
2843 tx_q = &priv->tx_queue[queue];
2845 /* Compute header lengths */
2846 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2848 /* Desc availability based on threshold should be enough safe */
2849 if (unlikely(stmmac_tx_avail(priv, queue) <
2850 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2851 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2852 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2854 /* This is a hard error, log it. */
2855 netdev_err(priv->dev,
2856 "%s: Tx Ring full when queue awake\n",
2859 return NETDEV_TX_BUSY;
2862 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2864 mss = skb_shinfo(skb)->gso_size;
2866 /* set new MSS value if needed */
2867 if (mss != tx_q->mss) {
2868 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2869 stmmac_set_mss(priv, mss_desc, mss);
2871 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2872 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2875 if (netif_msg_tx_queued(priv)) {
2876 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2877 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2878 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2882 first_entry = tx_q->cur_tx;
2883 WARN_ON(tx_q->tx_skbuff[first_entry]);
2885 desc = tx_q->dma_tx + first_entry;
2888 /* first descriptor: fill Headers on Buf1 */
2889 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2891 if (dma_mapping_error(priv->device, des))
2894 tx_q->tx_skbuff_dma[first_entry].buf = des;
2895 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2897 first->des0 = cpu_to_le32(des);
2899 /* Fill start of payload in buff2 of first descriptor */
2901 first->des1 = cpu_to_le32(des + proto_hdr_len);
2903 /* If needed take extra descriptors to fill the remaining payload */
2904 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2906 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2908 /* Prepare fragments */
2909 for (i = 0; i < nfrags; i++) {
2910 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2912 des = skb_frag_dma_map(priv->device, frag, 0,
2913 skb_frag_size(frag),
2915 if (dma_mapping_error(priv->device, des))
2918 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2919 (i == nfrags - 1), queue);
2921 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2922 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2923 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2926 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2928 /* Only the last descriptor gets to point to the skb. */
2929 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2931 /* We've used all descriptors we need for this skb, however,
2932 * advance cur_tx so that it references a fresh descriptor.
2933 * ndo_start_xmit will fill this descriptor the next time it's
2934 * called and stmmac_tx_clean may clean up to this descriptor.
2936 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2938 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2939 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2941 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2944 dev->stats.tx_bytes += skb->len;
2945 priv->xstats.tx_tso_frames++;
2946 priv->xstats.tx_tso_nfrags += nfrags;
2948 /* Manage tx mitigation */
2949 tx_q->tx_count_frames += nfrags + 1;
2950 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
2951 stmmac_set_tx_ic(priv, desc);
2952 priv->xstats.tx_set_ic_bit++;
2953 tx_q->tx_count_frames = 0;
2955 stmmac_tx_timer_arm(priv, queue);
2958 skb_tx_timestamp(skb);
2960 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2961 priv->hwts_tx_en)) {
2962 /* declare that device is doing timestamping */
2963 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2964 stmmac_enable_tx_timestamp(priv, first);
2967 /* Complete the first descriptor before granting the DMA */
2968 stmmac_prepare_tso_tx_desc(priv, first, 1,
2971 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2972 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2974 /* If context desc is used to change MSS */
2976 /* Make sure that first descriptor has been completely
2977 * written, including its own bit. This is because MSS is
2978 * actually before first descriptor, so we need to make
2979 * sure that MSS's own bit is the last thing written.
2982 stmmac_set_tx_owner(priv, mss_desc);
2985 /* The own bit must be the latest setting done when prepare the
2986 * descriptor and then barrier is needed to make sure that
2987 * all is coherent before granting the DMA engine.
2991 if (netif_msg_pktdata(priv)) {
2992 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2993 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2994 tx_q->cur_tx, first, nfrags);
2996 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
2998 pr_info(">>> frame to be transmitted: ");
2999 print_pkt(skb->data, skb_headlen(skb));
3002 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3004 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3005 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3007 return NETDEV_TX_OK;
3010 dev_err(priv->device, "Tx dma map failed\n");
3012 priv->dev->stats.tx_dropped++;
3013 return NETDEV_TX_OK;
3017 * stmmac_xmit - Tx entry point of the driver
3018 * @skb : the socket buffer
3019 * @dev : device pointer
3020 * Description : this is the tx entry point of the driver.
3021 * It programs the chain or the ring and supports oversized frames
3024 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3026 struct stmmac_priv *priv = netdev_priv(dev);
3027 unsigned int nopaged_len = skb_headlen(skb);
3028 int i, csum_insertion = 0, is_jumbo = 0;
3029 u32 queue = skb_get_queue_mapping(skb);
3030 int nfrags = skb_shinfo(skb)->nr_frags;
3032 unsigned int first_entry;
3033 struct dma_desc *desc, *first;
3034 struct stmmac_tx_queue *tx_q;
3035 unsigned int enh_desc;
3038 tx_q = &priv->tx_queue[queue];
3040 if (priv->tx_path_in_lpi_mode)
3041 stmmac_disable_eee_mode(priv);
3043 /* Manage oversized TCP frames for GMAC4 device */
3044 if (skb_is_gso(skb) && priv->tso) {
3045 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3047 * There is no way to determine the number of TSO
3048 * capable Queues. Let's use always the Queue 0
3049 * because if TSO is supported then at least this
3050 * one will be capable.
3052 skb_set_queue_mapping(skb, 0);
3054 return stmmac_tso_xmit(skb, dev);
3058 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3059 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3060 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3062 /* This is a hard error, log it. */
3063 netdev_err(priv->dev,
3064 "%s: Tx Ring full when queue awake\n",
3067 return NETDEV_TX_BUSY;
3070 entry = tx_q->cur_tx;
3071 first_entry = entry;
3072 WARN_ON(tx_q->tx_skbuff[first_entry]);
3074 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3076 if (likely(priv->extend_desc))
3077 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3079 desc = tx_q->dma_tx + entry;
3083 enh_desc = priv->plat->enh_desc;
3084 /* To program the descriptors according to the size of the frame */
3086 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3088 if (unlikely(is_jumbo)) {
3089 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3090 if (unlikely(entry < 0) && (entry != -EINVAL))
3094 for (i = 0; i < nfrags; i++) {
3095 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3096 int len = skb_frag_size(frag);
3097 bool last_segment = (i == (nfrags - 1));
3099 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3100 WARN_ON(tx_q->tx_skbuff[entry]);
3102 if (likely(priv->extend_desc))
3103 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3105 desc = tx_q->dma_tx + entry;
3107 des = skb_frag_dma_map(priv->device, frag, 0, len,
3109 if (dma_mapping_error(priv->device, des))
3110 goto dma_map_err; /* should reuse desc w/o issues */
3112 tx_q->tx_skbuff_dma[entry].buf = des;
3114 stmmac_set_desc_addr(priv, desc, des);
3116 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3117 tx_q->tx_skbuff_dma[entry].len = len;
3118 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3120 /* Prepare the descriptor and set the own bit too */
3121 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3122 priv->mode, 1, last_segment, skb->len);
3125 /* Only the last descriptor gets to point to the skb. */
3126 tx_q->tx_skbuff[entry] = skb;
3128 /* We've used all descriptors we need for this skb, however,
3129 * advance cur_tx so that it references a fresh descriptor.
3130 * ndo_start_xmit will fill this descriptor the next time it's
3131 * called and stmmac_tx_clean may clean up to this descriptor.
3133 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3134 tx_q->cur_tx = entry;
3136 if (netif_msg_pktdata(priv)) {
3139 netdev_dbg(priv->dev,
3140 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3141 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3142 entry, first, nfrags);
3144 if (priv->extend_desc)
3145 tx_head = (void *)tx_q->dma_etx;
3147 tx_head = (void *)tx_q->dma_tx;
3149 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3151 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3152 print_pkt(skb->data, skb->len);
3155 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3156 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3158 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3161 dev->stats.tx_bytes += skb->len;
3163 /* According to the coalesce parameter the IC bit for the latest
3164 * segment is reset and the timer re-started to clean the tx status.
3165 * This approach takes care about the fragments: desc is the first
3166 * element in case of no SG.
3168 tx_q->tx_count_frames += nfrags + 1;
3169 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
3170 stmmac_set_tx_ic(priv, desc);
3171 priv->xstats.tx_set_ic_bit++;
3172 tx_q->tx_count_frames = 0;
3174 stmmac_tx_timer_arm(priv, queue);
3177 skb_tx_timestamp(skb);
3179 /* Ready to fill the first descriptor and set the OWN bit w/o any
3180 * problems because all the descriptors are actually ready to be
3181 * passed to the DMA engine.
3183 if (likely(!is_jumbo)) {
3184 bool last_segment = (nfrags == 0);
3186 des = dma_map_single(priv->device, skb->data,
3187 nopaged_len, DMA_TO_DEVICE);
3188 if (dma_mapping_error(priv->device, des))
3191 tx_q->tx_skbuff_dma[first_entry].buf = des;
3193 stmmac_set_desc_addr(priv, first, des);
3195 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3196 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3198 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3199 priv->hwts_tx_en)) {
3200 /* declare that device is doing timestamping */
3201 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3202 stmmac_enable_tx_timestamp(priv, first);
3205 /* Prepare the first descriptor setting the OWN bit too */
3206 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3207 csum_insertion, priv->mode, 1, last_segment,
3210 stmmac_set_tx_owner(priv, first);
3213 /* The own bit must be the latest setting done when prepare the
3214 * descriptor and then barrier is needed to make sure that
3215 * all is coherent before granting the DMA engine.
3219 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3221 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3223 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3224 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3226 return NETDEV_TX_OK;
3229 netdev_err(priv->dev, "Tx DMA map failed\n");
3231 priv->dev->stats.tx_dropped++;
3232 return NETDEV_TX_OK;
3235 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3237 struct vlan_ethhdr *veth;
3241 veth = (struct vlan_ethhdr *)skb->data;
3242 vlan_proto = veth->h_vlan_proto;
3244 if ((vlan_proto == htons(ETH_P_8021Q) &&
3245 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3246 (vlan_proto == htons(ETH_P_8021AD) &&
3247 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3248 /* pop the vlan tag */
3249 vlanid = ntohs(veth->h_vlan_TCI);
3250 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3251 skb_pull(skb, VLAN_HLEN);
3252 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3257 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3259 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3266 * stmmac_rx_refill - refill used skb preallocated buffers
3267 * @priv: driver private structure
3268 * @queue: RX queue index
3269 * Description : this is to reallocate the skb for the reception process
3270 * that is based on zero-copy.
3272 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3274 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3275 int dirty = stmmac_rx_dirty(priv, queue);
3276 unsigned int entry = rx_q->dirty_rx;
3278 int bfsize = priv->dma_buf_sz;
3280 while (dirty-- > 0) {
3283 if (priv->extend_desc)
3284 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3286 p = rx_q->dma_rx + entry;
3288 if (likely(!rx_q->rx_skbuff[entry])) {
3289 struct sk_buff *skb;
3291 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3292 if (unlikely(!skb)) {
3293 /* so for a while no zero-copy! */
3294 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3295 if (unlikely(net_ratelimit()))
3296 dev_err(priv->device,
3297 "fail to alloc skb entry %d\n",
3302 rx_q->rx_skbuff[entry] = skb;
3303 rx_q->rx_skbuff_dma[entry] =
3304 dma_map_single(priv->device, skb->data, bfsize,
3306 if (dma_mapping_error(priv->device,
3307 rx_q->rx_skbuff_dma[entry])) {
3308 netdev_err(priv->dev, "Rx DMA map failed\n");
3313 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3314 stmmac_refill_desc3(priv, rx_q, p);
3316 if (rx_q->rx_zeroc_thresh > 0)
3317 rx_q->rx_zeroc_thresh--;
3319 netif_dbg(priv, rx_status, priv->dev,
3320 "refill entry #%d\n", entry);
3324 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3328 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3330 rx_q->dirty_rx = entry;
3331 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3335 * stmmac_rx - manage the receive process
3336 * @priv: driver private structure
3337 * @limit: napi bugget
3338 * @queue: RX queue index.
3339 * Description : this the function called by the napi poll method.
3340 * It gets all the frames inside the ring.
3342 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3344 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3345 struct stmmac_channel *ch = &priv->channel[queue];
3346 unsigned int next_entry = rx_q->cur_rx;
3347 int coe = priv->hw->rx_csum;
3348 unsigned int count = 0;
3351 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3353 if (netif_msg_rx_status(priv)) {
3356 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3357 if (priv->extend_desc)
3358 rx_head = (void *)rx_q->dma_erx;
3360 rx_head = (void *)rx_q->dma_rx;
3362 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3364 while (count < limit) {
3367 struct dma_desc *np;
3371 if (priv->extend_desc)
3372 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3374 p = rx_q->dma_rx + entry;
3376 /* read the status of the incoming frame */
3377 status = stmmac_rx_status(priv, &priv->dev->stats,
3379 /* check if managed by the DMA otherwise go ahead */
3380 if (unlikely(status & dma_own))
3385 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3386 next_entry = rx_q->cur_rx;
3388 if (priv->extend_desc)
3389 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3391 np = rx_q->dma_rx + next_entry;
3395 if (priv->extend_desc)
3396 stmmac_rx_extended_status(priv, &priv->dev->stats,
3397 &priv->xstats, rx_q->dma_erx + entry);
3398 if (unlikely(status == discard_frame)) {
3399 priv->dev->stats.rx_errors++;
3400 if (priv->hwts_rx_en && !priv->extend_desc) {
3401 /* DESC2 & DESC3 will be overwritten by device
3402 * with timestamp value, hence reinitialize
3403 * them in stmmac_rx_refill() function so that
3404 * device can reuse it.
3406 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3407 rx_q->rx_skbuff[entry] = NULL;
3408 dma_unmap_single(priv->device,
3409 rx_q->rx_skbuff_dma[entry],
3414 struct sk_buff *skb;
3418 stmmac_get_desc_addr(priv, p, &des);
3419 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3421 /* If frame length is greater than skb buffer size
3422 * (preallocated during init) then the packet is
3425 if (frame_len > priv->dma_buf_sz) {
3426 if (net_ratelimit())
3427 netdev_err(priv->dev,
3428 "len %d larger than size (%d)\n",
3429 frame_len, priv->dma_buf_sz);
3430 priv->dev->stats.rx_length_errors++;
3434 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3435 * Type frames (LLC/LLC-SNAP)
3437 * llc_snap is never checked in GMAC >= 4, so this ACS
3438 * feature is always disabled and packets need to be
3439 * stripped manually.
3441 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3442 unlikely(status != llc_snap))
3443 frame_len -= ETH_FCS_LEN;
3445 if (netif_msg_rx_status(priv)) {
3446 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3448 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3452 /* The zero-copy is always used for all the sizes
3453 * in case of GMAC4 because it needs
3454 * to refill the used descriptors, always.
3456 if (unlikely(!xmac &&
3457 ((frame_len < priv->rx_copybreak) ||
3458 stmmac_rx_threshold_count(rx_q)))) {
3459 skb = netdev_alloc_skb_ip_align(priv->dev,
3461 if (unlikely(!skb)) {
3462 if (net_ratelimit())
3463 dev_warn(priv->device,
3464 "packet dropped\n");
3465 priv->dev->stats.rx_dropped++;
3469 dma_sync_single_for_cpu(priv->device,
3473 skb_copy_to_linear_data(skb,
3475 rx_skbuff[entry]->data,
3478 skb_put(skb, frame_len);
3479 dma_sync_single_for_device(priv->device,
3484 skb = rx_q->rx_skbuff[entry];
3485 if (unlikely(!skb)) {
3486 if (net_ratelimit())
3487 netdev_err(priv->dev,
3488 "%s: Inconsistent Rx chain\n",
3490 priv->dev->stats.rx_dropped++;
3493 prefetch(skb->data - NET_IP_ALIGN);
3494 rx_q->rx_skbuff[entry] = NULL;
3495 rx_q->rx_zeroc_thresh++;
3497 skb_put(skb, frame_len);
3498 dma_unmap_single(priv->device,
3499 rx_q->rx_skbuff_dma[entry],
3504 if (netif_msg_pktdata(priv)) {
3505 netdev_dbg(priv->dev, "frame received (%dbytes)",
3507 print_pkt(skb->data, frame_len);
3510 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3512 stmmac_rx_vlan(priv->dev, skb);
3514 skb->protocol = eth_type_trans(skb, priv->dev);
3517 skb_checksum_none_assert(skb);
3519 skb->ip_summed = CHECKSUM_UNNECESSARY;
3521 napi_gro_receive(&ch->rx_napi, skb);
3523 priv->dev->stats.rx_packets++;
3524 priv->dev->stats.rx_bytes += frame_len;
3528 stmmac_rx_refill(priv, queue);
3530 priv->xstats.rx_pkt_n += count;
3535 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3537 struct stmmac_channel *ch =
3538 container_of(napi, struct stmmac_channel, rx_napi);
3539 struct stmmac_priv *priv = ch->priv_data;
3540 u32 chan = ch->index;
3543 priv->xstats.napi_poll++;
3545 work_done = stmmac_rx(priv, budget, chan);
3546 if (work_done < budget && napi_complete_done(napi, work_done))
3547 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3551 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3553 struct stmmac_channel *ch =
3554 container_of(napi, struct stmmac_channel, tx_napi);
3555 struct stmmac_priv *priv = ch->priv_data;
3556 struct stmmac_tx_queue *tx_q;
3557 u32 chan = ch->index;
3560 priv->xstats.napi_poll++;
3562 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3563 work_done = min(work_done, budget);
3565 if (work_done < budget && napi_complete_done(napi, work_done))
3566 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3568 /* Force transmission restart */
3569 tx_q = &priv->tx_queue[chan];
3570 if (tx_q->cur_tx != tx_q->dirty_tx) {
3571 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3572 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3581 * @dev : Pointer to net device structure
3582 * Description: this function is called when a packet transmission fails to
3583 * complete within a reasonable time. The driver will mark the error in the
3584 * netdev structure and arrange for the device to be reset to a sane state
3585 * in order to transmit a new packet.
3587 static void stmmac_tx_timeout(struct net_device *dev)
3589 struct stmmac_priv *priv = netdev_priv(dev);
3591 stmmac_global_err(priv);
3595 * stmmac_set_rx_mode - entry point for multicast addressing
3596 * @dev : pointer to the device structure
3598 * This function is a driver entry point which gets called by the kernel
3599 * whenever multicast addresses must be enabled/disabled.
3603 static void stmmac_set_rx_mode(struct net_device *dev)
3605 struct stmmac_priv *priv = netdev_priv(dev);
3607 stmmac_set_filter(priv, priv->hw, dev);
3611 * stmmac_change_mtu - entry point to change MTU size for the device.
3612 * @dev : device pointer.
3613 * @new_mtu : the new MTU size for the device.
3614 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3615 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3616 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3618 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3621 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3623 struct stmmac_priv *priv = netdev_priv(dev);
3625 if (netif_running(dev)) {
3626 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3632 netdev_update_features(dev);
3637 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3638 netdev_features_t features)
3640 struct stmmac_priv *priv = netdev_priv(dev);
3642 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3643 features &= ~NETIF_F_RXCSUM;
3645 if (!priv->plat->tx_coe)
3646 features &= ~NETIF_F_CSUM_MASK;
3648 /* Some GMAC devices have a bugged Jumbo frame support that
3649 * needs to have the Tx COE disabled for oversized frames
3650 * (due to limited buffer sizes). In this case we disable
3651 * the TX csum insertion in the TDES and not use SF.
3653 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3654 features &= ~NETIF_F_CSUM_MASK;
3656 /* Disable tso if asked by ethtool */
3657 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3658 if (features & NETIF_F_TSO)
3667 static int stmmac_set_features(struct net_device *netdev,
3668 netdev_features_t features)
3670 struct stmmac_priv *priv = netdev_priv(netdev);
3672 /* Keep the COE Type in case of csum is supporting */
3673 if (features & NETIF_F_RXCSUM)
3674 priv->hw->rx_csum = priv->plat->rx_coe;
3676 priv->hw->rx_csum = 0;
3677 /* No check needed because rx_coe has been set before and it will be
3678 * fixed in case of issue.
3680 stmmac_rx_ipc(priv, priv->hw);
3686 * stmmac_interrupt - main ISR
3687 * @irq: interrupt number.
3688 * @dev_id: to pass the net device pointer.
3689 * Description: this is the main driver interrupt service routine.
3691 * o DMA service routine (to manage incoming frame reception and transmission
3693 * o Core interrupts to manage: remote wake-up, management counter, LPI
3696 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3698 struct net_device *dev = (struct net_device *)dev_id;
3699 struct stmmac_priv *priv = netdev_priv(dev);
3700 u32 rx_cnt = priv->plat->rx_queues_to_use;
3701 u32 tx_cnt = priv->plat->tx_queues_to_use;
3706 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3707 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3710 pm_wakeup_event(priv->device, 0);
3712 if (unlikely(!dev)) {
3713 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3717 /* Check if adapter is up */
3718 if (test_bit(STMMAC_DOWN, &priv->state))
3720 /* Check if a fatal error happened */
3721 if (stmmac_safety_feat_interrupt(priv))
3724 /* To handle GMAC own interrupts */
3725 if ((priv->plat->has_gmac) || xmac) {
3726 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3729 if (unlikely(status)) {
3730 /* For LPI we need to save the tx status */
3731 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3732 priv->tx_path_in_lpi_mode = true;
3733 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3734 priv->tx_path_in_lpi_mode = false;
3737 for (queue = 0; queue < queues_count; queue++) {
3738 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3740 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3742 if (mtl_status != -EINVAL)
3743 status |= mtl_status;
3745 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3746 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3751 /* PCS link status */
3752 if (priv->hw->pcs) {
3753 if (priv->xstats.pcs_link)
3754 netif_carrier_on(dev);
3756 netif_carrier_off(dev);
3760 /* To handle DMA interrupts */
3761 stmmac_dma_interrupt(priv);
3766 #ifdef CONFIG_NET_POLL_CONTROLLER
3767 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3768 * to allow network I/O with interrupts disabled.
3770 static void stmmac_poll_controller(struct net_device *dev)
3772 disable_irq(dev->irq);
3773 stmmac_interrupt(dev->irq, dev);
3774 enable_irq(dev->irq);
3779 * stmmac_ioctl - Entry point for the Ioctl
3780 * @dev: Device pointer.
3781 * @rq: An IOCTL specefic structure, that can contain a pointer to
3782 * a proprietary structure used to pass information to the driver.
3783 * @cmd: IOCTL command
3785 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3787 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3789 int ret = -EOPNOTSUPP;
3791 if (!netif_running(dev))
3800 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3803 ret = stmmac_hwtstamp_set(dev, rq);
3806 ret = stmmac_hwtstamp_get(dev, rq);
3815 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3818 struct stmmac_priv *priv = cb_priv;
3819 int ret = -EOPNOTSUPP;
3821 stmmac_disable_all_queues(priv);
3824 case TC_SETUP_CLSU32:
3825 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3826 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3832 stmmac_enable_all_queues(priv);
3836 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3837 struct tc_block_offload *f)
3839 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3842 switch (f->command) {
3844 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3845 priv, priv, f->extack);
3846 case TC_BLOCK_UNBIND:
3847 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3854 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3857 struct stmmac_priv *priv = netdev_priv(ndev);
3860 case TC_SETUP_BLOCK:
3861 return stmmac_setup_tc_block(priv, type_data);
3862 case TC_SETUP_QDISC_CBS:
3863 return stmmac_tc_setup_cbs(priv, priv, type_data);
3869 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3871 struct stmmac_priv *priv = netdev_priv(ndev);
3874 ret = eth_mac_addr(ndev, addr);
3878 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3883 #ifdef CONFIG_DEBUG_FS
3884 static struct dentry *stmmac_fs_dir;
3886 static void sysfs_display_ring(void *head, int size, int extend_desc,
3887 struct seq_file *seq)
3890 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3891 struct dma_desc *p = (struct dma_desc *)head;
3893 for (i = 0; i < size; i++) {
3895 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3896 i, (unsigned int)virt_to_phys(ep),
3897 le32_to_cpu(ep->basic.des0),
3898 le32_to_cpu(ep->basic.des1),
3899 le32_to_cpu(ep->basic.des2),
3900 le32_to_cpu(ep->basic.des3));
3903 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3904 i, (unsigned int)virt_to_phys(p),
3905 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3906 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3909 seq_printf(seq, "\n");
3913 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3915 struct net_device *dev = seq->private;
3916 struct stmmac_priv *priv = netdev_priv(dev);
3917 u32 rx_count = priv->plat->rx_queues_to_use;
3918 u32 tx_count = priv->plat->tx_queues_to_use;
3921 if ((dev->flags & IFF_UP) == 0)
3924 for (queue = 0; queue < rx_count; queue++) {
3925 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3927 seq_printf(seq, "RX Queue %d:\n", queue);
3929 if (priv->extend_desc) {
3930 seq_printf(seq, "Extended descriptor ring:\n");
3931 sysfs_display_ring((void *)rx_q->dma_erx,
3932 DMA_RX_SIZE, 1, seq);
3934 seq_printf(seq, "Descriptor ring:\n");
3935 sysfs_display_ring((void *)rx_q->dma_rx,
3936 DMA_RX_SIZE, 0, seq);
3940 for (queue = 0; queue < tx_count; queue++) {
3941 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3943 seq_printf(seq, "TX Queue %d:\n", queue);
3945 if (priv->extend_desc) {
3946 seq_printf(seq, "Extended descriptor ring:\n");
3947 sysfs_display_ring((void *)tx_q->dma_etx,
3948 DMA_TX_SIZE, 1, seq);
3950 seq_printf(seq, "Descriptor ring:\n");
3951 sysfs_display_ring((void *)tx_q->dma_tx,
3952 DMA_TX_SIZE, 0, seq);
3958 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3960 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3962 struct net_device *dev = seq->private;
3963 struct stmmac_priv *priv = netdev_priv(dev);
3965 if (!priv->hw_cap_support) {
3966 seq_printf(seq, "DMA HW features not supported\n");
3970 seq_printf(seq, "==============================\n");
3971 seq_printf(seq, "\tDMA HW features\n");
3972 seq_printf(seq, "==============================\n");
3974 seq_printf(seq, "\t10/100 Mbps: %s\n",
3975 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3976 seq_printf(seq, "\t1000 Mbps: %s\n",
3977 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3978 seq_printf(seq, "\tHalf duplex: %s\n",
3979 (priv->dma_cap.half_duplex) ? "Y" : "N");
3980 seq_printf(seq, "\tHash Filter: %s\n",
3981 (priv->dma_cap.hash_filter) ? "Y" : "N");
3982 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3983 (priv->dma_cap.multi_addr) ? "Y" : "N");
3984 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3985 (priv->dma_cap.pcs) ? "Y" : "N");
3986 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3987 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3988 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3989 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3990 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3991 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3992 seq_printf(seq, "\tRMON module: %s\n",
3993 (priv->dma_cap.rmon) ? "Y" : "N");
3994 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3995 (priv->dma_cap.time_stamp) ? "Y" : "N");
3996 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3997 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3998 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3999 (priv->dma_cap.eee) ? "Y" : "N");
4000 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4001 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4002 (priv->dma_cap.tx_coe) ? "Y" : "N");
4003 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4004 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4005 (priv->dma_cap.rx_coe) ? "Y" : "N");
4007 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4008 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4009 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4010 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4012 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4013 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4014 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4015 priv->dma_cap.number_rx_channel);
4016 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4017 priv->dma_cap.number_tx_channel);
4018 seq_printf(seq, "\tEnhanced descriptors: %s\n",
4019 (priv->dma_cap.enh_desc) ? "Y" : "N");
4023 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4025 static int stmmac_init_fs(struct net_device *dev)
4027 struct stmmac_priv *priv = netdev_priv(dev);
4029 /* Create per netdev entries */
4030 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4032 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
4033 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
4038 /* Entry to report DMA RX/TX rings */
4039 priv->dbgfs_rings_status =
4040 debugfs_create_file("descriptors_status", 0444,
4041 priv->dbgfs_dir, dev,
4042 &stmmac_rings_status_fops);
4044 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
4045 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4046 debugfs_remove_recursive(priv->dbgfs_dir);
4051 /* Entry to report the DMA HW features */
4052 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4054 dev, &stmmac_dma_cap_fops);
4056 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4057 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4058 debugfs_remove_recursive(priv->dbgfs_dir);
4066 static void stmmac_exit_fs(struct net_device *dev)
4068 struct stmmac_priv *priv = netdev_priv(dev);
4070 debugfs_remove_recursive(priv->dbgfs_dir);
4072 #endif /* CONFIG_DEBUG_FS */
4074 static const struct net_device_ops stmmac_netdev_ops = {
4075 .ndo_open = stmmac_open,
4076 .ndo_start_xmit = stmmac_xmit,
4077 .ndo_stop = stmmac_release,
4078 .ndo_change_mtu = stmmac_change_mtu,
4079 .ndo_fix_features = stmmac_fix_features,
4080 .ndo_set_features = stmmac_set_features,
4081 .ndo_set_rx_mode = stmmac_set_rx_mode,
4082 .ndo_tx_timeout = stmmac_tx_timeout,
4083 .ndo_do_ioctl = stmmac_ioctl,
4084 .ndo_setup_tc = stmmac_setup_tc,
4085 #ifdef CONFIG_NET_POLL_CONTROLLER
4086 .ndo_poll_controller = stmmac_poll_controller,
4088 .ndo_set_mac_address = stmmac_set_mac_address,
4091 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4093 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4095 if (test_bit(STMMAC_DOWN, &priv->state))
4098 netdev_err(priv->dev, "Reset adapter.\n");
4101 netif_trans_update(priv->dev);
4102 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4103 usleep_range(1000, 2000);
4105 set_bit(STMMAC_DOWN, &priv->state);
4106 dev_close(priv->dev);
4107 dev_open(priv->dev, NULL);
4108 clear_bit(STMMAC_DOWN, &priv->state);
4109 clear_bit(STMMAC_RESETING, &priv->state);
4113 static void stmmac_service_task(struct work_struct *work)
4115 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4118 stmmac_reset_subtask(priv);
4119 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4123 * stmmac_hw_init - Init the MAC device
4124 * @priv: driver private structure
4125 * Description: this function is to configure the MAC device according to
4126 * some platform parameters or the HW capability register. It prepares the
4127 * driver to use either ring or chain modes and to setup either enhanced or
4128 * normal descriptors.
4130 static int stmmac_hw_init(struct stmmac_priv *priv)
4134 /* dwmac-sun8i only work in chain mode */
4135 if (priv->plat->has_sun8i)
4137 priv->chain_mode = chain_mode;
4139 /* Initialize HW Interface */
4140 ret = stmmac_hwif_init(priv);
4144 /* Get the HW capability (new GMAC newer than 3.50a) */
4145 priv->hw_cap_support = stmmac_get_hw_features(priv);
4146 if (priv->hw_cap_support) {
4147 dev_info(priv->device, "DMA HW capability register supported\n");
4149 /* We can override some gmac/dma configuration fields: e.g.
4150 * enh_desc, tx_coe (e.g. that are passed through the
4151 * platform) with the values from the HW capability
4152 * register (if supported).
4154 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4155 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4156 priv->hw->pmt = priv->plat->pmt;
4158 /* TXCOE doesn't work in thresh DMA mode */
4159 if (priv->plat->force_thresh_dma_mode)
4160 priv->plat->tx_coe = 0;
4162 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4164 /* In case of GMAC4 rx_coe is from HW cap register. */
4165 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4167 if (priv->dma_cap.rx_coe_type2)
4168 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4169 else if (priv->dma_cap.rx_coe_type1)
4170 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4173 dev_info(priv->device, "No HW DMA feature register supported\n");
4176 if (priv->plat->rx_coe) {
4177 priv->hw->rx_csum = priv->plat->rx_coe;
4178 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4179 if (priv->synopsys_id < DWMAC_CORE_4_00)
4180 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4182 if (priv->plat->tx_coe)
4183 dev_info(priv->device, "TX Checksum insertion supported\n");
4185 if (priv->plat->pmt) {
4186 dev_info(priv->device, "Wake-Up On Lan supported\n");
4187 device_set_wakeup_capable(priv->device, 1);
4190 if (priv->dma_cap.tsoen)
4191 dev_info(priv->device, "TSO supported\n");
4193 /* Run HW quirks, if any */
4194 if (priv->hwif_quirks) {
4195 ret = priv->hwif_quirks(priv);
4200 /* Rx Watchdog is available in the COREs newer than the 3.40.
4201 * In some case, for example on bugged HW this feature
4202 * has to be disable and this can be done by passing the
4203 * riwt_off field from the platform.
4205 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4206 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4208 dev_info(priv->device,
4209 "Enable RX Mitigation via HW Watchdog Timer\n");
4217 * @device: device pointer
4218 * @plat_dat: platform data pointer
4219 * @res: stmmac resource pointer
4220 * Description: this is the main probe function used to
4221 * call the alloc_etherdev, allocate the priv structure.
4223 * returns 0 on success, otherwise errno.
4225 int stmmac_dvr_probe(struct device *device,
4226 struct plat_stmmacenet_data *plat_dat,
4227 struct stmmac_resources *res)
4229 struct net_device *ndev = NULL;
4230 struct stmmac_priv *priv;
4234 ndev = alloc_etherdev_mqs(sizeof(struct stmmac_priv),
4240 SET_NETDEV_DEV(ndev, device);
4242 priv = netdev_priv(ndev);
4243 priv->device = device;
4246 stmmac_set_ethtool_ops(ndev);
4247 priv->pause = pause;
4248 priv->plat = plat_dat;
4249 priv->ioaddr = res->addr;
4250 priv->dev->base_addr = (unsigned long)res->addr;
4252 priv->dev->irq = res->irq;
4253 priv->wol_irq = res->wol_irq;
4254 priv->lpi_irq = res->lpi_irq;
4256 if (!IS_ERR_OR_NULL(res->mac))
4257 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4259 dev_set_drvdata(device, priv->dev);
4261 /* Verify driver arguments */
4262 stmmac_verify_args();
4264 /* Allocate workqueue */
4265 priv->wq = create_singlethread_workqueue("stmmac_wq");
4267 dev_err(priv->device, "failed to create workqueue\n");
4272 INIT_WORK(&priv->service_task, stmmac_service_task);
4274 /* Override with kernel parameters if supplied XXX CRS XXX
4275 * this needs to have multiple instances
4277 if ((phyaddr >= 0) && (phyaddr <= 31))
4278 priv->plat->phy_addr = phyaddr;
4280 if (priv->plat->stmmac_rst) {
4281 ret = reset_control_assert(priv->plat->stmmac_rst);
4282 reset_control_deassert(priv->plat->stmmac_rst);
4283 /* Some reset controllers have only reset callback instead of
4284 * assert + deassert callbacks pair.
4286 if (ret == -ENOTSUPP)
4287 reset_control_reset(priv->plat->stmmac_rst);
4290 /* Init MAC and get the capabilities */
4291 ret = stmmac_hw_init(priv);
4295 stmmac_check_ether_addr(priv);
4297 /* Configure real RX and TX queues */
4298 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4299 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4301 ndev->netdev_ops = &stmmac_netdev_ops;
4303 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4306 ret = stmmac_tc_init(priv, priv);
4308 ndev->hw_features |= NETIF_F_HW_TC;
4311 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4312 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4314 dev_info(priv->device, "TSO feature enabled\n");
4316 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4317 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4318 #ifdef STMMAC_VLAN_TAG_USED
4319 /* Both mac100 and gmac support receive VLAN tag detection */
4320 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4322 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4324 /* MTU range: 46 - hw-specific max */
4325 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4326 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4327 ndev->max_mtu = JUMBO_LEN;
4328 else if (priv->plat->has_xgmac)
4329 ndev->max_mtu = XGMAC_JUMBO_LEN;
4331 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4332 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4333 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4335 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4336 (priv->plat->maxmtu >= ndev->min_mtu))
4337 ndev->max_mtu = priv->plat->maxmtu;
4338 else if (priv->plat->maxmtu < ndev->min_mtu)
4339 dev_warn(priv->device,
4340 "%s: warning: maxmtu having invalid value (%d)\n",
4341 __func__, priv->plat->maxmtu);
4344 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4346 /* Setup channels NAPI */
4347 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4349 for (queue = 0; queue < maxq; queue++) {
4350 struct stmmac_channel *ch = &priv->channel[queue];
4352 ch->priv_data = priv;
4355 if (queue < priv->plat->rx_queues_to_use) {
4356 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4359 if (queue < priv->plat->tx_queues_to_use) {
4360 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4365 mutex_init(&priv->lock);
4367 /* If a specific clk_csr value is passed from the platform
4368 * this means that the CSR Clock Range selection cannot be
4369 * changed at run-time and it is fixed. Viceversa the driver'll try to
4370 * set the MDC clock dynamically according to the csr actual
4373 if (priv->plat->clk_csr >= 0)
4374 priv->clk_csr = priv->plat->clk_csr;
4376 stmmac_clk_csr_set(priv);
4378 stmmac_check_pcs_mode(priv);
4380 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4381 priv->hw->pcs != STMMAC_PCS_TBI &&
4382 priv->hw->pcs != STMMAC_PCS_RTBI) {
4383 /* MDIO bus Registration */
4384 ret = stmmac_mdio_register(ndev);
4386 dev_err(priv->device,
4387 "%s: MDIO bus (id: %d) registration failed",
4388 __func__, priv->plat->bus_id);
4389 goto error_mdio_register;
4393 ret = register_netdev(ndev);
4395 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4397 goto error_netdev_register;
4400 #ifdef CONFIG_DEBUG_FS
4401 ret = stmmac_init_fs(ndev);
4403 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4409 error_netdev_register:
4410 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4411 priv->hw->pcs != STMMAC_PCS_TBI &&
4412 priv->hw->pcs != STMMAC_PCS_RTBI)
4413 stmmac_mdio_unregister(ndev);
4414 error_mdio_register:
4415 for (queue = 0; queue < maxq; queue++) {
4416 struct stmmac_channel *ch = &priv->channel[queue];
4418 if (queue < priv->plat->rx_queues_to_use)
4419 netif_napi_del(&ch->rx_napi);
4420 if (queue < priv->plat->tx_queues_to_use)
4421 netif_napi_del(&ch->tx_napi);
4424 destroy_workqueue(priv->wq);
4430 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4434 * @dev: device pointer
4435 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4436 * changes the link status, releases the DMA descriptor rings.
4438 int stmmac_dvr_remove(struct device *dev)
4440 struct net_device *ndev = dev_get_drvdata(dev);
4441 struct stmmac_priv *priv = netdev_priv(ndev);
4443 netdev_info(priv->dev, "%s: removing driver", __func__);
4445 #ifdef CONFIG_DEBUG_FS
4446 stmmac_exit_fs(ndev);
4448 stmmac_stop_all_dma(priv);
4450 stmmac_mac_set(priv, priv->ioaddr, false);
4451 netif_carrier_off(ndev);
4452 unregister_netdev(ndev);
4453 if (priv->plat->stmmac_rst)
4454 reset_control_assert(priv->plat->stmmac_rst);
4455 clk_disable_unprepare(priv->plat->pclk);
4456 clk_disable_unprepare(priv->plat->stmmac_clk);
4457 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4458 priv->hw->pcs != STMMAC_PCS_TBI &&
4459 priv->hw->pcs != STMMAC_PCS_RTBI)
4460 stmmac_mdio_unregister(ndev);
4461 destroy_workqueue(priv->wq);
4462 mutex_destroy(&priv->lock);
4467 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4470 * stmmac_suspend - suspend callback
4471 * @dev: device pointer
4472 * Description: this is the function to suspend the device and it is called
4473 * by the platform driver to stop the network queue, release the resources,
4474 * program the PMT register (for WoL), clean and release driver resources.
4476 int stmmac_suspend(struct device *dev)
4478 struct net_device *ndev = dev_get_drvdata(dev);
4479 struct stmmac_priv *priv = netdev_priv(ndev);
4481 if (!ndev || !netif_running(ndev))
4485 phy_stop(ndev->phydev);
4487 mutex_lock(&priv->lock);
4489 netif_device_detach(ndev);
4490 stmmac_stop_all_queues(priv);
4492 stmmac_disable_all_queues(priv);
4494 /* Stop TX/RX DMA */
4495 stmmac_stop_all_dma(priv);
4497 /* Enable Power down mode by programming the PMT regs */
4498 if (device_may_wakeup(priv->device)) {
4499 stmmac_pmt(priv, priv->hw, priv->wolopts);
4502 stmmac_mac_set(priv, priv->ioaddr, false);
4503 pinctrl_pm_select_sleep_state(priv->device);
4504 /* Disable clock in case of PWM is off */
4505 clk_disable(priv->plat->pclk);
4506 clk_disable(priv->plat->stmmac_clk);
4508 mutex_unlock(&priv->lock);
4510 priv->oldlink = false;
4511 priv->speed = SPEED_UNKNOWN;
4512 priv->oldduplex = DUPLEX_UNKNOWN;
4515 EXPORT_SYMBOL_GPL(stmmac_suspend);
4518 * stmmac_reset_queues_param - reset queue parameters
4519 * @dev: device pointer
4521 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4523 u32 rx_cnt = priv->plat->rx_queues_to_use;
4524 u32 tx_cnt = priv->plat->tx_queues_to_use;
4527 for (queue = 0; queue < rx_cnt; queue++) {
4528 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4534 for (queue = 0; queue < tx_cnt; queue++) {
4535 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4544 * stmmac_resume - resume callback
4545 * @dev: device pointer
4546 * Description: when resume this function is invoked to setup the DMA and CORE
4547 * in a usable state.
4549 int stmmac_resume(struct device *dev)
4551 struct net_device *ndev = dev_get_drvdata(dev);
4552 struct stmmac_priv *priv = netdev_priv(ndev);
4554 if (!netif_running(ndev))
4557 /* Power Down bit, into the PM register, is cleared
4558 * automatically as soon as a magic packet or a Wake-up frame
4559 * is received. Anyway, it's better to manually clear
4560 * this bit because it can generate problems while resuming
4561 * from another devices (e.g. serial console).
4563 if (device_may_wakeup(priv->device)) {
4564 mutex_lock(&priv->lock);
4565 stmmac_pmt(priv, priv->hw, 0);
4566 mutex_unlock(&priv->lock);
4569 pinctrl_pm_select_default_state(priv->device);
4570 /* enable the clk previously disabled */
4571 clk_enable(priv->plat->stmmac_clk);
4572 clk_enable(priv->plat->pclk);
4573 /* reset the phy so that it's ready */
4575 stmmac_mdio_reset(priv->mii);
4578 netif_device_attach(ndev);
4580 mutex_lock(&priv->lock);
4582 stmmac_reset_queues_param(priv);
4584 stmmac_clear_descriptors(priv);
4586 stmmac_hw_setup(ndev, false);
4587 stmmac_init_tx_coalesce(priv);
4588 stmmac_set_rx_mode(ndev);
4590 stmmac_enable_all_queues(priv);
4592 stmmac_start_all_queues(priv);
4594 mutex_unlock(&priv->lock);
4597 phy_start(ndev->phydev);
4601 EXPORT_SYMBOL_GPL(stmmac_resume);
4604 static int __init stmmac_cmdline_opt(char *str)
4610 while ((opt = strsep(&str, ",")) != NULL) {
4611 if (!strncmp(opt, "debug:", 6)) {
4612 if (kstrtoint(opt + 6, 0, &debug))
4614 } else if (!strncmp(opt, "phyaddr:", 8)) {
4615 if (kstrtoint(opt + 8, 0, &phyaddr))
4617 } else if (!strncmp(opt, "buf_sz:", 7)) {
4618 if (kstrtoint(opt + 7, 0, &buf_sz))
4620 } else if (!strncmp(opt, "tc:", 3)) {
4621 if (kstrtoint(opt + 3, 0, &tc))
4623 } else if (!strncmp(opt, "watchdog:", 9)) {
4624 if (kstrtoint(opt + 9, 0, &watchdog))
4626 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4627 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4629 } else if (!strncmp(opt, "pause:", 6)) {
4630 if (kstrtoint(opt + 6, 0, &pause))
4632 } else if (!strncmp(opt, "eee_timer:", 10)) {
4633 if (kstrtoint(opt + 10, 0, &eee_timer))
4635 } else if (!strncmp(opt, "chain_mode:", 11)) {
4636 if (kstrtoint(opt + 11, 0, &chain_mode))
4643 pr_err("%s: ERROR broken module parameter conversion", __func__);
4647 __setup("stmmaceth=", stmmac_cmdline_opt);
4650 static int __init stmmac_init(void)
4652 #ifdef CONFIG_DEBUG_FS
4653 /* Create debugfs main directory if it doesn't exist yet */
4654 if (!stmmac_fs_dir) {
4655 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4657 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4658 pr_err("ERROR %s, debugfs create directory failed\n",
4659 STMMAC_RESOURCE_NAME);
4669 static void __exit stmmac_exit(void)
4671 #ifdef CONFIG_DEBUG_FS
4672 debugfs_remove_recursive(stmmac_fs_dir);
4676 module_init(stmmac_init)
4677 module_exit(stmmac_exit)
4679 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4680 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4681 MODULE_LICENSE("GPL");