drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
   4  * stmmac XGMAC support.
   5  */
   6
   7 #include <linux/bitrev.h>
   8 #include <linux/crc32.h>
   9 #include "stmmac.h"
  10 #include "dwxgmac2.h"
  11
  12 static void dwxgmac2_core_init(struct mac_device_info *hw,
  13                                struct net_device *dev)
  14 {
  15         void __iomem *ioaddr = hw->pcsr;
  16         int mtu = dev->mtu;
  17         u32 tx, rx;
  18
  19         tx = readl(ioaddr + XGMAC_TX_CONFIG);
  20         rx = readl(ioaddr + XGMAC_RX_CONFIG);
  21
  22         tx |= XGMAC_CORE_INIT_TX;
  23         rx |= XGMAC_CORE_INIT_RX;
  24
  25         if (mtu >= 9000) {
  26                 rx |= XGMAC_CONFIG_GPSLCE;
  27                 rx |= XGMAC_JUMBO_LEN << XGMAC_CONFIG_GPSL_SHIFT;
  28                 rx |= XGMAC_CONFIG_WD;
  29         } else if (mtu > 2000) {
  30                 rx |= XGMAC_CONFIG_JE;
  31         } else if (mtu > 1500) {
  32                 rx |= XGMAC_CONFIG_S2KP;
  33         }
  34
  35         if (hw->ps) {
  36                 tx |= XGMAC_CONFIG_TE;
  37                 tx &= ~hw->link.speed_mask;
  38
  39                 switch (hw->ps) {
  40                 case SPEED_10000:
  41                         tx |= hw->link.xgmii.speed10000;
  42                         break;
  43                 case SPEED_2500:
  44                         tx |= hw->link.speed2500;
  45                         break;
  46                 case SPEED_1000:
  47                 default:
  48                         tx |= hw->link.speed1000;
  49                         break;
  50                 }
  51         }
  52
  53         writel(tx, ioaddr + XGMAC_TX_CONFIG);
  54         writel(rx, ioaddr + XGMAC_RX_CONFIG);
  55         writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
  56 }
  57
  58 static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)
  59 {
  60         u32 tx = readl(ioaddr + XGMAC_TX_CONFIG);
  61         u32 rx = readl(ioaddr + XGMAC_RX_CONFIG);
  62
  63         if (enable) {
  64                 tx |= XGMAC_CONFIG_TE;
  65                 rx |= XGMAC_CONFIG_RE;
  66         } else {
  67                 tx &= ~XGMAC_CONFIG_TE;
  68                 rx &= ~XGMAC_CONFIG_RE;
  69         }
  70
  71         writel(tx, ioaddr + XGMAC_TX_CONFIG);
  72         writel(rx, ioaddr + XGMAC_RX_CONFIG);
  73 }
  74
  75 static int dwxgmac2_rx_ipc(struct mac_device_info *hw)
  76 {
  77         void __iomem *ioaddr = hw->pcsr;
  78         u32 value;
  79
  80         value = readl(ioaddr + XGMAC_RX_CONFIG);
  81         if (hw->rx_csum)
  82                 value |= XGMAC_CONFIG_IPC;
  83         else
  84                 value &= ~XGMAC_CONFIG_IPC;
  85         writel(value, ioaddr + XGMAC_RX_CONFIG);
  86
  87         return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC);
  88 }
  89
  90 static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
  91                                      u32 queue)
  92 {
  93         void __iomem *ioaddr = hw->pcsr;
  94         u32 value;
  95
  96         value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue);
  97         if (mode == MTL_QUEUE_AVB)
  98                 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
  99         else if (mode == MTL_QUEUE_DCB)
 100                 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
 101         writel(value, ioaddr + XGMAC_RXQ_CTRL0);
 102 }
 103
 104 static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,
 105                                    u32 queue)
 106 {
 107         void __iomem *ioaddr = hw->pcsr;
 108         u32 value, reg;
 109
 110         reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3;
 111
 112         value = readl(ioaddr + reg);
 113         value &= ~XGMAC_PSRQ(queue);
 114         value |= (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue);
 115
 116         writel(value, ioaddr + reg);
 117 }
 118
 119 static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 120                                             u32 rx_alg)
 121 {
 122         void __iomem *ioaddr = hw->pcsr;
 123         u32 value;
 124
 125         value = readl(ioaddr + XGMAC_MTL_OPMODE);
 126         value &= ~XGMAC_RAA;
 127
 128         switch (rx_alg) {
 129         case MTL_RX_ALGORITHM_SP:
 130                 break;
 131         case MTL_RX_ALGORITHM_WSP:
 132                 value |= XGMAC_RAA;
 133                 break;
 134         default:
 135                 break;
 136         }
 137
 138         writel(value, ioaddr + XGMAC_MTL_OPMODE);
 139 }
 140
 141 static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 142                                             u32 tx_alg)
 143 {
 144         void __iomem *ioaddr = hw->pcsr;
 145         u32 value;
 146
 147         value = readl(ioaddr + XGMAC_MTL_OPMODE);
 148         value &= ~XGMAC_ETSALG;
 149
 150         switch (tx_alg) {
 151         case MTL_TX_ALGORITHM_WRR:
 152                 value |= XGMAC_WRR;
 153                 break;
 154         case MTL_TX_ALGORITHM_WFQ:
 155                 value |= XGMAC_WFQ;
 156                 break;
 157         case MTL_TX_ALGORITHM_DWRR:
 158                 value |= XGMAC_DWRR;
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         writel(value, ioaddr + XGMAC_MTL_OPMODE);
 165 }
 166
 167 static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
 168                                     u32 chan)
 169 {
 170         void __iomem *ioaddr = hw->pcsr;
 171         u32 value, reg;
 172
 173         reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1;
 174
 175         value = readl(ioaddr + reg);
 176         value &= ~XGMAC_QxMDMACH(queue);
 177         value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue);
 178
 179         writel(value, ioaddr + reg);
 180 }
 181
 182 static void dwxgmac2_config_cbs(struct mac_device_info *hw,
 183                                 u32 send_slope, u32 idle_slope,
 184                                 u32 high_credit, u32 low_credit, u32 queue)
 185 {
 186         void __iomem *ioaddr = hw->pcsr;
 187         u32 value;
 188
 189         writel(send_slope, ioaddr + XGMAC_MTL_TCx_SENDSLOPE(queue));
 190         writel(idle_slope, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
 191         writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(queue));
 192         writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(queue));
 193
 194         value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
 195         value |= XGMAC_CC | XGMAC_CBS;
 196         writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
 197 }
 198
 199 static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
 200                                     struct stmmac_extra_stats *x)
 201 {
 202         void __iomem *ioaddr = hw->pcsr;
 203         u32 stat, en;
 204
 205         en = readl(ioaddr + XGMAC_INT_EN);
 206         stat = readl(ioaddr + XGMAC_INT_STATUS);
 207
 208         stat &= en;
 209
 210         if (stat & XGMAC_PMTIS) {
 211                 x->irq_receive_pmt_irq_n++;
 212                 readl(ioaddr + XGMAC_PMT);
 213         }
 214
 215         return 0;
 216 }
 217
 218 static int dwxgmac2_host_mtl_irq_status(struct mac_device_info *hw, u32 chan)
 219 {
 220         void __iomem *ioaddr = hw->pcsr;
 221         int ret = 0;
 222         u32 status;
 223
 224         status = readl(ioaddr + XGMAC_MTL_INT_STATUS);
 225         if (status & BIT(chan)) {
 226                 u32 chan_status = readl(ioaddr + XGMAC_MTL_QINT_STATUS(chan));
 227
 228                 if (chan_status & XGMAC_RXOVFIS)
 229                         ret |= CORE_IRQ_MTL_RX_OVERFLOW;
 230
 231                 writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(chan));
 232         }
 233
 234         return ret;
 235 }
 236
 237 static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 238                                unsigned int fc, unsigned int pause_time,
 239                                u32 tx_cnt)
 240 {
 241         void __iomem *ioaddr = hw->pcsr;
 242         u32 i;
 243
 244         if (fc & FLOW_RX)
 245                 writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);
 246         if (fc & FLOW_TX) {
 247                 for (i = 0; i < tx_cnt; i++) {
 248                         u32 value = XGMAC_TFE;
 249
 250                         if (duplex)
 251                                 value |= pause_time << XGMAC_PT_SHIFT;
 252
 253                         writel(value, ioaddr + XGMAC_Qx_TX_FLOW_CTRL(i));
 254                 }
 255         }
 256 }
 257
 258 static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
 259 {
 260         void __iomem *ioaddr = hw->pcsr;
 261         u32 val = 0x0;
 262
 263         if (mode & WAKE_MAGIC)
 264                 val |= XGMAC_PWRDWN | XGMAC_MGKPKTEN;
 265         if (mode & WAKE_UCAST)
 266                 val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN;
 267         if (val) {
 268                 u32 cfg = readl(ioaddr + XGMAC_RX_CONFIG);
 269                 cfg |= XGMAC_CONFIG_RE;
 270                 writel(cfg, ioaddr + XGMAC_RX_CONFIG);
 271         }
 272
 273         writel(val, ioaddr + XGMAC_PMT);
 274 }
 275
 276 static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
 277                                    unsigned char *addr, unsigned int reg_n)
 278 {
 279         void __iomem *ioaddr = hw->pcsr;
 280         u32 value;
 281
 282         value = (addr[5] << 8) | addr[4];
 283         writel(value | XGMAC_AE, ioaddr + XGMAC_ADDRx_HIGH(reg_n));
 284
 285         value = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
 286         writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
 287 }
 288
 289 static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
 290                                    unsigned char *addr, unsigned int reg_n)
 291 {
 292         void __iomem *ioaddr = hw->pcsr;
 293         u32 hi_addr, lo_addr;
 294
 295         /* Read the MAC address from the hardware */
 296         hi_addr = readl(ioaddr + XGMAC_ADDRx_HIGH(reg_n));
 297         lo_addr = readl(ioaddr + XGMAC_ADDRx_LOW(reg_n));
 298
 299         /* Extract the MAC address from the high and low words */
 300         addr[0] = lo_addr & 0xff;
 301         addr[1] = (lo_addr >> 8) & 0xff;
 302         addr[2] = (lo_addr >> 16) & 0xff;
 303         addr[3] = (lo_addr >> 24) & 0xff;
 304         addr[4] = hi_addr & 0xff;
 305         addr[5] = (hi_addr >> 8) & 0xff;
 306 }
 307
 308 static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
 309                                 int mcbitslog2)
 310 {
 311         int numhashregs, regs;
 312
 313         switch (mcbitslog2) {
 314         case 6:
 315                 numhashregs = 2;
 316                 break;
 317         case 7:
 318                 numhashregs = 4;
 319                 break;
 320         case 8:
 321                 numhashregs = 8;
 322                 break;
 323         default:
 324                 return;
 325         }
 326
 327         for (regs = 0; regs < numhashregs; regs++)
 328                 writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
 329 }
 330
 331 static void dwxgmac2_set_filter(struct mac_device_info *hw,
 332                                 struct net_device *dev)
 333 {
 334         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 335         u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
 336         int mcbitslog2 = hw->mcast_bits_log2;
 337         u32 mc_filter[8];
 338         int i;
 339
 340         value &= ~(XGMAC_FILTER_PR | XGMAC_FILTER_HMC | XGMAC_FILTER_PM);
 341         value |= XGMAC_FILTER_HPF;
 342
 343         memset(mc_filter, 0, sizeof(mc_filter));
 344
 345         if (dev->flags & IFF_PROMISC) {
 346                 value |= XGMAC_FILTER_PR;
 347                 value |= XGMAC_FILTER_PCF;
 348         } else if ((dev->flags & IFF_ALLMULTI) ||
 349                    (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
 350                 value |= XGMAC_FILTER_PM;
 351
 352                 for (i = 0; i < XGMAC_MAX_HASH_TABLE; i++)
 353                         writel(~0x0, ioaddr + XGMAC_HASH_TABLE(i));
 354         } else if (!netdev_mc_empty(dev)) {
 355                 struct netdev_hw_addr *ha;
 356
 357                 value |= XGMAC_FILTER_HMC;
 358
 359                 netdev_for_each_mc_addr(ha, dev) {
 360                         int nr = (bitrev32(~crc32_le(~0, ha->addr, 6)) >>
 361                                         (32 - mcbitslog2));
 362                         mc_filter[nr >> 5] |= (1 << (nr & 0x1F));
 363                 }
 364         }
 365
 366         dwxgmac2_set_mchash(ioaddr, mc_filter, mcbitslog2);
 367
 368         /* Handle multiple unicast addresses */
 369         if (netdev_uc_count(dev) > XGMAC_ADDR_MAX) {
 370                 value |= XGMAC_FILTER_PR;
 371         } else {
 372                 struct netdev_hw_addr *ha;
 373                 int reg = 1;
 374
 375                 netdev_for_each_uc_addr(ha, dev) {
 376                         dwxgmac2_set_umac_addr(hw, ha->addr, reg);
 377                         reg++;
 378                 }
 379
 380                 for ( ; reg < XGMAC_ADDR_MAX; reg++) {
 381                         writel(0, ioaddr + XGMAC_ADDRx_HIGH(reg));
 382                         writel(0, ioaddr + XGMAC_ADDRx_LOW(reg));
 383                 }
 384         }
 385
 386         writel(value, ioaddr + XGMAC_PACKET_FILTER);
 387 }
 388
 389 static void dwxgmac2_set_mac_loopback(void __iomem *ioaddr, bool enable)
 390 {
 391         u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
 392
 393         if (enable)
 394                 value |= XGMAC_CONFIG_LM;
 395         else
 396                 value &= ~XGMAC_CONFIG_LM;
 397
 398         writel(value, ioaddr + XGMAC_RX_CONFIG);
 399 }
 400
 401 const struct stmmac_ops dwxgmac210_ops = {
 402         .core_init = dwxgmac2_core_init,
 403         .set_mac = dwxgmac2_set_mac,
 404         .rx_ipc = dwxgmac2_rx_ipc,
 405         .rx_queue_enable = dwxgmac2_rx_queue_enable,
 406         .rx_queue_prio = dwxgmac2_rx_queue_prio,
 407         .tx_queue_prio = NULL,
 408         .rx_queue_routing = NULL,
 409         .prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
 410         .prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
 411         .set_mtl_tx_queue_weight = NULL,
 412         .map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
 413         .config_cbs = dwxgmac2_config_cbs,
 414         .dump_regs = NULL,
 415         .host_irq_status = dwxgmac2_host_irq_status,
 416         .host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
 417         .flow_ctrl = dwxgmac2_flow_ctrl,
 418         .pmt = dwxgmac2_pmt,
 419         .set_umac_addr = dwxgmac2_set_umac_addr,
 420         .get_umac_addr = dwxgmac2_get_umac_addr,
 421         .set_eee_mode = NULL,
 422         .reset_eee_mode = NULL,
 423         .set_eee_timer = NULL,
 424         .set_eee_pls = NULL,
 425         .pcs_ctrl_ane = NULL,
 426         .pcs_rane = NULL,
 427         .pcs_get_adv_lp = NULL,
 428         .debug = NULL,
 429         .set_filter = dwxgmac2_set_filter,
 430         .set_mac_loopback = dwxgmac2_set_mac_loopback,
 431 };
 432
 433 int dwxgmac2_setup(struct stmmac_priv *priv)
 434 {
 435         struct mac_device_info *mac = priv->hw;
 436
 437         dev_info(priv->device, "\tXGMAC2\n");
 438
 439         priv->dev->priv_flags |= IFF_UNICAST_FLT;
 440         mac->pcsr = priv->ioaddr;
 441         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
 442         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
 443         mac->mcast_bits_log2 = 0;
 444
 445         if (mac->multicast_filter_bins)
 446                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 447
 448         mac->link.duplex = 0;
 449         mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;
 450         mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;
 451         mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
 452         mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
 453         mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
 454         mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
 455         mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
 456         mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
 457
 458         mac->mii.addr = XGMAC_MDIO_ADDR;
 459         mac->mii.data = XGMAC_MDIO_DATA;
 460         mac->mii.addr_shift = 16;
 461         mac->mii.addr_mask = GENMASK(20, 16);
 462         mac->mii.reg_shift = 0;
 463         mac->mii.reg_mask = GENMASK(15, 0);
 464         mac->mii.clk_csr_shift = 19;
 465         mac->mii.clk_csr_mask = GENMASK(21, 19);
 466
 467         return 0;
 468 }