1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.xx has been used for developing this code.
6 * This contains the functions to handle the dma.
8 * Copyright (C) 2015 STMicroelectronics Ltd
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
15 #include "dwmac4_dma.h"
17 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
19 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
22 pr_info("dwmac4: Master AXI performs %s burst length\n",
23 (value & DMA_SYS_BUS_FB) ? "fixed" : "any");
26 value |= DMA_AXI_EN_LPI;
28 value |= DMA_AXI_LPI_XIT_FRM;
30 value &= ~DMA_AXI_WR_OSR_LMT;
31 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
32 DMA_AXI_WR_OSR_LMT_SHIFT;
34 value &= ~DMA_AXI_RD_OSR_LMT;
35 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
36 DMA_AXI_RD_OSR_LMT_SHIFT;
38 /* Depending on the UNDEF bit the Master AXI will perform any burst
39 * length according to the BLEN programmed (by default all BLEN are
42 for (i = 0; i < AXI_BLEN; i++) {
43 switch (axi->axi_blen[i]) {
45 value |= DMA_AXI_BLEN256;
48 value |= DMA_AXI_BLEN128;
51 value |= DMA_AXI_BLEN64;
54 value |= DMA_AXI_BLEN32;
57 value |= DMA_AXI_BLEN16;
60 value |= DMA_AXI_BLEN8;
63 value |= DMA_AXI_BLEN4;
68 writel(value, ioaddr + DMA_SYS_BUS_MODE);
71 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
72 struct stmmac_dma_cfg *dma_cfg,
73 dma_addr_t dma_rx_phy, u32 chan)
76 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
78 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
79 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
80 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
82 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
83 writel(upper_32_bits(dma_rx_phy),
84 ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
86 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
89 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
90 struct stmmac_dma_cfg *dma_cfg,
91 dma_addr_t dma_tx_phy, u32 chan)
94 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
96 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
97 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
99 /* Enable OSP to get best performance */
100 value |= DMA_CONTROL_OSP;
102 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
104 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
105 writel(upper_32_bits(dma_tx_phy),
106 ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
108 writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
111 static void dwmac4_dma_init_channel(void __iomem *ioaddr,
112 struct stmmac_dma_cfg *dma_cfg, u32 chan)
116 /* common channel control register config */
117 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
119 value = value | DMA_BUS_MODE_PBL;
120 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
122 /* Mask interrupts by writing to CSR7 */
123 writel(DMA_CHAN_INTR_DEFAULT_MASK,
124 ioaddr + DMA_CHAN_INTR_ENA(chan));
127 static void dwmac410_dma_init_channel(void __iomem *ioaddr,
128 struct stmmac_dma_cfg *dma_cfg, u32 chan)
132 /* common channel control register config */
133 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
135 value = value | DMA_BUS_MODE_PBL;
137 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
139 /* Mask interrupts by writing to CSR7 */
140 writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
141 ioaddr + DMA_CHAN_INTR_ENA(chan));
144 static void dwmac4_dma_init(void __iomem *ioaddr,
145 struct stmmac_dma_cfg *dma_cfg, int atds)
147 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
149 /* Set the Fixed burst mode */
150 if (dma_cfg->fixed_burst)
151 value |= DMA_SYS_BUS_FB;
153 /* Mixed Burst has no effect when fb is set */
154 if (dma_cfg->mixed_burst)
155 value |= DMA_SYS_BUS_MB;
158 value |= DMA_SYS_BUS_AAL;
161 value |= DMA_SYS_BUS_EAME;
163 writel(value, ioaddr + DMA_SYS_BUS_MODE);
165 if (dma_cfg->multi_msi_en) {
166 value = readl(ioaddr + DMA_BUS_MODE);
167 value &= ~DMA_BUS_MODE_INTM_MASK;
168 value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
169 writel(value, ioaddr + DMA_BUS_MODE);
173 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
176 reg_space[DMA_CHAN_CONTROL(channel) / 4] =
177 readl(ioaddr + DMA_CHAN_CONTROL(channel));
178 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
179 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
180 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
181 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
182 reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
183 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
184 reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
185 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
186 reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
187 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
188 reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
189 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
190 reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
191 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
192 reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
193 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
194 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
195 readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
196 reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
197 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
198 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
199 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
200 reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
201 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
202 reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
203 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
204 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
205 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
206 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
207 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
208 reg_space[DMA_CHAN_STATUS(channel) / 4] =
209 readl(ioaddr + DMA_CHAN_STATUS(channel));
212 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
216 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
217 _dwmac4_dump_dma_regs(ioaddr, i, reg_space);
220 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 queue)
222 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
225 static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
226 u32 channel, int fifosz, u8 qmode)
228 unsigned int rqs = fifosz / 256 - 1;
229 u32 mtl_rx_op, mtl_rx_int;
231 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
233 if (mode == SF_DMA_MODE) {
234 pr_debug("GMAC: enable RX store and forward mode\n");
235 mtl_rx_op |= MTL_OP_MODE_RSF;
237 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
238 mtl_rx_op &= ~MTL_OP_MODE_RSF;
239 mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
241 mtl_rx_op |= MTL_OP_MODE_RTC_32;
243 mtl_rx_op |= MTL_OP_MODE_RTC_64;
245 mtl_rx_op |= MTL_OP_MODE_RTC_96;
247 mtl_rx_op |= MTL_OP_MODE_RTC_128;
250 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
251 mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
253 /* Enable flow control only if each channel gets 4 KiB or more FIFO and
254 * only if channel is not an AVB channel.
256 if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
257 unsigned int rfd, rfa;
259 mtl_rx_op |= MTL_OP_MODE_EHFC;
261 /* Set Threshold for Activating Flow Control to min 2 frames,
262 * i.e. 1500 * 2 = 3000 bytes.
264 * Set Threshold for Deactivating Flow Control to min 1 frame,
269 /* This violates the above formula because of FIFO size
270 * limit therefore overflow may occur in spite of this.
272 rfd = 0x03; /* Full-2.5K */
273 rfa = 0x01; /* Full-1.5K */
277 rfd = 0x07; /* Full-4.5K */
278 rfa = 0x04; /* Full-3K */
282 mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
283 mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
285 mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
286 mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
289 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
291 /* Enable MTL RX overflow */
292 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
293 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
294 ioaddr + MTL_CHAN_INT_CTRL(channel));
297 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
298 u32 channel, int fifosz, u8 qmode)
300 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
301 unsigned int tqs = fifosz / 256 - 1;
303 if (mode == SF_DMA_MODE) {
304 pr_debug("GMAC: enable TX store and forward mode\n");
305 /* Transmit COE type 2 cannot be done in cut-through mode. */
306 mtl_tx_op |= MTL_OP_MODE_TSF;
308 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
309 mtl_tx_op &= ~MTL_OP_MODE_TSF;
310 mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
311 /* Set the transmit threshold */
313 mtl_tx_op |= MTL_OP_MODE_TTC_32;
315 mtl_tx_op |= MTL_OP_MODE_TTC_64;
317 mtl_tx_op |= MTL_OP_MODE_TTC_96;
318 else if (mode <= 128)
319 mtl_tx_op |= MTL_OP_MODE_TTC_128;
320 else if (mode <= 192)
321 mtl_tx_op |= MTL_OP_MODE_TTC_192;
322 else if (mode <= 256)
323 mtl_tx_op |= MTL_OP_MODE_TTC_256;
324 else if (mode <= 384)
325 mtl_tx_op |= MTL_OP_MODE_TTC_384;
327 mtl_tx_op |= MTL_OP_MODE_TTC_512;
329 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
330 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
331 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
332 * with reset values: TXQEN off, TQS 256 bytes.
334 * TXQEN must be written for multi-channel operation and TQS must
335 * reflect the available fifo size per queue (total fifo size / number
336 * of enabled queues).
338 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
339 if (qmode != MTL_QUEUE_AVB)
340 mtl_tx_op |= MTL_OP_MODE_TXQEN;
342 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
343 mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
344 mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
346 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
349 static void dwmac4_get_hw_feature(void __iomem *ioaddr,
350 struct dma_features *dma_cap)
352 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
354 /* MAC HW feature0 */
355 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
356 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
357 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
358 dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
359 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
360 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
361 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
362 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
363 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
365 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
367 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
368 /* 802.3az - Energy-Efficient Ethernet (EEE) */
369 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
371 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
372 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
373 dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
374 dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
376 /* MAC HW feature1 */
377 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
378 dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
379 dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
380 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
381 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
382 dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
384 dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
385 switch (dma_cap->addr64) {
387 dma_cap->addr64 = 32;
390 dma_cap->addr64 = 40;
393 dma_cap->addr64 = 48;
396 dma_cap->addr64 = 32;
400 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
401 * shifting and store the sizes in bytes.
403 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
404 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
405 /* MAC HW feature2 */
406 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
407 /* TX and RX number of channels */
408 dma_cap->number_rx_channel =
409 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
410 dma_cap->number_tx_channel =
411 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
412 /* TX and RX number of queues */
413 dma_cap->number_rx_queues =
414 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
415 dma_cap->number_tx_queues =
416 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
418 dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
421 dma_cap->time_stamp = 0;
422 /* Number of Auxiliary Snapshot Inputs */
423 dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;
425 /* MAC HW feature3 */
426 hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
429 dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
430 dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
431 dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
432 dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
433 dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
434 dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
435 dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
436 dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
437 dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
438 dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
441 /* Enable/disable TSO feature and set MSS */
442 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
448 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
449 writel(value | DMA_CONTROL_TSE,
450 ioaddr + DMA_CHAN_TX_CONTROL(chan));
453 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
454 writel(value & ~DMA_CONTROL_TSE,
455 ioaddr + DMA_CHAN_TX_CONTROL(chan));
459 static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
461 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
463 mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
464 if (qmode != MTL_QUEUE_AVB)
465 mtl_tx_op |= MTL_OP_MODE_TXQEN;
467 mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
469 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
472 static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
474 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
476 value &= ~DMA_RBSZ_MASK;
477 value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
479 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
482 static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
484 u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
486 value &= ~GMAC_CONFIG_HDSMS;
487 value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
488 writel(value, ioaddr + GMAC_EXT_CONFIG);
490 value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
492 value |= DMA_CONTROL_SPH;
494 value &= ~DMA_CONTROL_SPH;
495 writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
498 static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
500 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
503 value |= DMA_CONTROL_EDSE;
505 value &= ~DMA_CONTROL_EDSE;
507 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
509 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;
513 writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
517 const struct stmmac_dma_ops dwmac4_dma_ops = {
518 .reset = dwmac4_dma_reset,
519 .init = dwmac4_dma_init,
520 .init_chan = dwmac4_dma_init_channel,
521 .init_rx_chan = dwmac4_dma_init_rx_chan,
522 .init_tx_chan = dwmac4_dma_init_tx_chan,
523 .axi = dwmac4_dma_axi,
524 .dump_regs = dwmac4_dump_dma_regs,
525 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
526 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
527 .enable_dma_irq = dwmac4_enable_dma_irq,
528 .disable_dma_irq = dwmac4_disable_dma_irq,
529 .start_tx = dwmac4_dma_start_tx,
530 .stop_tx = dwmac4_dma_stop_tx,
531 .start_rx = dwmac4_dma_start_rx,
532 .stop_rx = dwmac4_dma_stop_rx,
533 .dma_interrupt = dwmac4_dma_interrupt,
534 .get_hw_feature = dwmac4_get_hw_feature,
535 .rx_watchdog = dwmac4_rx_watchdog,
536 .set_rx_ring_len = dwmac4_set_rx_ring_len,
537 .set_tx_ring_len = dwmac4_set_tx_ring_len,
538 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
539 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
540 .enable_tso = dwmac4_enable_tso,
541 .qmode = dwmac4_qmode,
542 .set_bfsize = dwmac4_set_bfsize,
543 .enable_sph = dwmac4_enable_sph,
546 const struct stmmac_dma_ops dwmac410_dma_ops = {
547 .reset = dwmac4_dma_reset,
548 .init = dwmac4_dma_init,
549 .init_chan = dwmac410_dma_init_channel,
550 .init_rx_chan = dwmac4_dma_init_rx_chan,
551 .init_tx_chan = dwmac4_dma_init_tx_chan,
552 .axi = dwmac4_dma_axi,
553 .dump_regs = dwmac4_dump_dma_regs,
554 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
555 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
556 .enable_dma_irq = dwmac410_enable_dma_irq,
557 .disable_dma_irq = dwmac4_disable_dma_irq,
558 .start_tx = dwmac4_dma_start_tx,
559 .stop_tx = dwmac4_dma_stop_tx,
560 .start_rx = dwmac4_dma_start_rx,
561 .stop_rx = dwmac4_dma_stop_rx,
562 .dma_interrupt = dwmac4_dma_interrupt,
563 .get_hw_feature = dwmac4_get_hw_feature,
564 .rx_watchdog = dwmac4_rx_watchdog,
565 .set_rx_ring_len = dwmac4_set_rx_ring_len,
566 .set_tx_ring_len = dwmac4_set_tx_ring_len,
567 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
568 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
569 .enable_tso = dwmac4_enable_tso,
570 .qmode = dwmac4_qmode,
571 .set_bfsize = dwmac4_set_bfsize,
572 .enable_sph = dwmac4_enable_sph,
573 .enable_tbs = dwmac4_enable_tbs,