2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
4 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
19 #include <linux/iopoll.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_net.h>
25 #include <linux/phy.h>
26 #include <linux/platform_device.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/regmap.h>
29 #include <linux/stmmac.h>
32 #include "stmmac_platform.h"
34 /* General notes on dwmac-sun8i:
35 * Locking: no locking is necessary in this file because all necessary locking
36 * is done in the "stmmac files"
39 /* struct emac_variant - Descrive dwmac-sun8i hardware variant
40 * @default_syscon_value: The default value of the EMAC register in syscon
41 * This value is used for disabling properly EMAC
42 * and used as a good starting value in case of the
43 * boot process(uboot) leave some stuff.
44 * @internal_phy: Does the MAC embed an internal PHY
45 * @support_mii: Does the MAC handle MII
46 * @support_rmii: Does the MAC handle RMII
47 * @support_rgmii: Does the MAC handle RGMII
50 u32 default_syscon_value;
57 /* struct sunxi_priv_data - hold all sunxi private data
58 * @tx_clk: reference to MAC TX clock
59 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
60 * @regulator: reference to the optional regulator
61 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
62 * @variant: reference to the current board variant
63 * @regmap: regmap for using the syscon
64 * @use_internal_phy: Does the current PHY choice imply using the internal PHY
66 struct sunxi_priv_data {
69 struct regulator *regulator;
70 struct reset_control *rst_ephy;
71 const struct emac_variant *variant;
72 struct regmap *regmap;
73 bool use_internal_phy;
76 static const struct emac_variant emac_variant_h3 = {
77 .default_syscon_value = 0x58000,
78 .internal_phy = PHY_INTERFACE_MODE_MII,
84 static const struct emac_variant emac_variant_v3s = {
85 .default_syscon_value = 0x38000,
86 .internal_phy = PHY_INTERFACE_MODE_MII,
90 static const struct emac_variant emac_variant_a83t = {
91 .default_syscon_value = 0,
97 static const struct emac_variant emac_variant_a64 = {
98 .default_syscon_value = 0,
101 .support_rmii = true,
102 .support_rgmii = true
105 #define EMAC_BASIC_CTL0 0x00
106 #define EMAC_BASIC_CTL1 0x04
107 #define EMAC_INT_STA 0x08
108 #define EMAC_INT_EN 0x0C
109 #define EMAC_TX_CTL0 0x10
110 #define EMAC_TX_CTL1 0x14
111 #define EMAC_TX_FLOW_CTL 0x1C
112 #define EMAC_TX_DESC_LIST 0x20
113 #define EMAC_RX_CTL0 0x24
114 #define EMAC_RX_CTL1 0x28
115 #define EMAC_RX_DESC_LIST 0x34
116 #define EMAC_RX_FRM_FLT 0x38
117 #define EMAC_MDIO_CMD 0x48
118 #define EMAC_MDIO_DATA 0x4C
119 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
120 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
121 #define EMAC_TX_DMA_STA 0xB0
122 #define EMAC_TX_CUR_DESC 0xB4
123 #define EMAC_TX_CUR_BUF 0xB8
124 #define EMAC_RX_DMA_STA 0xC0
125 #define EMAC_RX_CUR_DESC 0xC4
126 #define EMAC_RX_CUR_BUF 0xC8
128 /* Use in EMAC_BASIC_CTL0 */
129 #define EMAC_DUPLEX_FULL BIT(0)
130 #define EMAC_LOOPBACK BIT(1)
131 #define EMAC_SPEED_1000 0
132 #define EMAC_SPEED_100 (0x03 << 2)
133 #define EMAC_SPEED_10 (0x02 << 2)
135 /* Use in EMAC_BASIC_CTL1 */
136 #define EMAC_BURSTLEN_SHIFT 24
138 /* Used in EMAC_RX_FRM_FLT */
139 #define EMAC_FRM_FLT_RXALL BIT(0)
140 #define EMAC_FRM_FLT_CTL BIT(13)
141 #define EMAC_FRM_FLT_MULTICAST BIT(16)
144 #define EMAC_RX_MD BIT(1)
145 #define EMAC_RX_TH_MASK GENMASK(4, 5)
146 #define EMAC_RX_TH_32 0
147 #define EMAC_RX_TH_64 (0x1 << 4)
148 #define EMAC_RX_TH_96 (0x2 << 4)
149 #define EMAC_RX_TH_128 (0x3 << 4)
150 #define EMAC_RX_DMA_EN BIT(30)
151 #define EMAC_RX_DMA_START BIT(31)
154 #define EMAC_TX_MD BIT(1)
155 #define EMAC_TX_NEXT_FRM BIT(2)
156 #define EMAC_TX_TH_MASK GENMASK(8, 10)
157 #define EMAC_TX_TH_64 0
158 #define EMAC_TX_TH_128 (0x1 << 8)
159 #define EMAC_TX_TH_192 (0x2 << 8)
160 #define EMAC_TX_TH_256 (0x3 << 8)
161 #define EMAC_TX_DMA_EN BIT(30)
162 #define EMAC_TX_DMA_START BIT(31)
164 /* Used in RX_CTL0 */
165 #define EMAC_RX_RECEIVER_EN BIT(31)
166 #define EMAC_RX_DO_CRC BIT(27)
167 #define EMAC_RX_FLOW_CTL_EN BIT(16)
169 /* Used in TX_CTL0 */
170 #define EMAC_TX_TRANSMITTER_EN BIT(31)
172 /* Used in EMAC_TX_FLOW_CTL */
173 #define EMAC_TX_FLOW_CTL_EN BIT(0)
175 /* Used in EMAC_INT_STA */
176 #define EMAC_TX_INT BIT(0)
177 #define EMAC_TX_DMA_STOP_INT BIT(1)
178 #define EMAC_TX_BUF_UA_INT BIT(2)
179 #define EMAC_TX_TIMEOUT_INT BIT(3)
180 #define EMAC_TX_UNDERFLOW_INT BIT(4)
181 #define EMAC_TX_EARLY_INT BIT(5)
182 #define EMAC_RX_INT BIT(8)
183 #define EMAC_RX_BUF_UA_INT BIT(9)
184 #define EMAC_RX_DMA_STOP_INT BIT(10)
185 #define EMAC_RX_TIMEOUT_INT BIT(11)
186 #define EMAC_RX_OVERFLOW_INT BIT(12)
187 #define EMAC_RX_EARLY_INT BIT(13)
188 #define EMAC_RGMII_STA_INT BIT(16)
190 #define MAC_ADDR_TYPE_DST BIT(31)
192 /* H3 specific bits for EPHY */
193 #define H3_EPHY_ADDR_SHIFT 20
194 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
195 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
196 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
197 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
199 /* H3/A64 specific bits */
200 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
202 /* Generic system control EMAC_CLK bits */
203 #define SYSCON_ETXDC_MASK GENMASK(2, 0)
204 #define SYSCON_ETXDC_SHIFT 10
205 #define SYSCON_ERXDC_MASK GENMASK(4, 0)
206 #define SYSCON_ERXDC_SHIFT 5
207 /* EMAC PHY Interface Type */
208 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
209 #define SYSCON_ETCS_MASK GENMASK(1, 0)
210 #define SYSCON_ETCS_MII 0x0
211 #define SYSCON_ETCS_EXT_GMII 0x1
212 #define SYSCON_ETCS_INT_GMII 0x2
213 #define SYSCON_EMAC_REG 0x30
215 /* sun8i_dwmac_dma_reset() - reset the EMAC
216 * Called from stmmac via stmmac_dma_ops->reset
218 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
220 writel(0, ioaddr + EMAC_RX_CTL1);
221 writel(0, ioaddr + EMAC_TX_CTL1);
222 writel(0, ioaddr + EMAC_RX_FRM_FLT);
223 writel(0, ioaddr + EMAC_RX_DESC_LIST);
224 writel(0, ioaddr + EMAC_TX_DESC_LIST);
225 writel(0, ioaddr + EMAC_INT_EN);
226 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
230 /* sun8i_dwmac_dma_init() - initialize the EMAC
231 * Called from stmmac via stmmac_dma_ops->init
233 static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
234 struct stmmac_dma_cfg *dma_cfg,
235 u32 dma_tx, u32 dma_rx, int atds)
237 /* Write TX and RX descriptors address */
238 writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);
239 writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);
241 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
242 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
245 /* sun8i_dwmac_dump_regs() - Dump EMAC address space
246 * Called from stmmac_dma_ops->dump_regs
249 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
253 for (i = 0; i < 0xC8; i += 4) {
254 if (i == 0x32 || i == 0x3C)
256 reg_space[i / 4] = readl(ioaddr + i);
260 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
261 * Called from stmmac_ops->dump_regs
264 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
268 void __iomem *ioaddr = hw->pcsr;
270 for (i = 0; i < 0xC8; i += 4) {
271 if (i == 0x32 || i == 0x3C)
273 reg_space[i / 4] = readl(ioaddr + i);
277 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
279 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
282 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
284 writel(0, ioaddr + EMAC_INT_EN);
287 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
291 v = readl(ioaddr + EMAC_TX_CTL1);
292 v |= EMAC_TX_DMA_START;
294 writel(v, ioaddr + EMAC_TX_CTL1);
297 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
301 v = readl(ioaddr + EMAC_TX_CTL1);
302 v |= EMAC_TX_DMA_START;
304 writel(v, ioaddr + EMAC_TX_CTL1);
307 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
311 v = readl(ioaddr + EMAC_TX_CTL1);
312 v &= ~EMAC_TX_DMA_EN;
313 writel(v, ioaddr + EMAC_TX_CTL1);
316 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
320 v = readl(ioaddr + EMAC_RX_CTL1);
321 v |= EMAC_RX_DMA_START;
323 writel(v, ioaddr + EMAC_RX_CTL1);
326 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
330 v = readl(ioaddr + EMAC_RX_CTL1);
331 v &= ~EMAC_RX_DMA_EN;
332 writel(v, ioaddr + EMAC_RX_CTL1);
335 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
336 struct stmmac_extra_stats *x, u32 chan)
341 v = readl(ioaddr + EMAC_INT_STA);
343 if (v & EMAC_TX_INT) {
345 x->tx_normal_irq_n++;
348 if (v & EMAC_TX_DMA_STOP_INT)
349 x->tx_process_stopped_irq++;
351 if (v & EMAC_TX_BUF_UA_INT)
352 x->tx_process_stopped_irq++;
354 if (v & EMAC_TX_TIMEOUT_INT)
355 ret |= tx_hard_error;
357 if (v & EMAC_TX_UNDERFLOW_INT) {
358 ret |= tx_hard_error;
359 x->tx_undeflow_irq++;
362 if (v & EMAC_TX_EARLY_INT)
365 if (v & EMAC_RX_INT) {
367 x->rx_normal_irq_n++;
370 if (v & EMAC_RX_BUF_UA_INT)
371 x->rx_buf_unav_irq++;
373 if (v & EMAC_RX_DMA_STOP_INT)
374 x->rx_process_stopped_irq++;
376 if (v & EMAC_RX_TIMEOUT_INT)
377 ret |= tx_hard_error;
379 if (v & EMAC_RX_OVERFLOW_INT) {
380 ret |= tx_hard_error;
381 x->rx_overflow_irq++;
384 if (v & EMAC_RX_EARLY_INT)
387 if (v & EMAC_RGMII_STA_INT)
390 writel(v, ioaddr + EMAC_INT_STA);
395 static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode,
396 int rxmode, int rxfifosz)
400 v = readl(ioaddr + EMAC_TX_CTL1);
401 if (txmode == SF_DMA_MODE) {
403 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
405 * "Operating on second frame increase the performance
406 * especially when transmit store-and-forward is used."
408 v |= EMAC_TX_NEXT_FRM;
411 v &= ~EMAC_TX_TH_MASK;
414 else if (txmode < 128)
416 else if (txmode < 192)
418 else if (txmode < 256)
421 writel(v, ioaddr + EMAC_TX_CTL1);
423 v = readl(ioaddr + EMAC_RX_CTL1);
424 if (rxmode == SF_DMA_MODE) {
428 v &= ~EMAC_RX_TH_MASK;
431 else if (rxmode < 64)
433 else if (rxmode < 96)
435 else if (rxmode < 128)
438 writel(v, ioaddr + EMAC_RX_CTL1);
441 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
442 .reset = sun8i_dwmac_dma_reset,
443 .init = sun8i_dwmac_dma_init,
444 .dump_regs = sun8i_dwmac_dump_regs,
445 .dma_mode = sun8i_dwmac_dma_operation_mode,
446 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
447 .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
448 .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
449 .start_tx = sun8i_dwmac_dma_start_tx,
450 .stop_tx = sun8i_dwmac_dma_stop_tx,
451 .start_rx = sun8i_dwmac_dma_start_rx,
452 .stop_rx = sun8i_dwmac_dma_stop_rx,
453 .dma_interrupt = sun8i_dwmac_dma_interrupt,
456 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
458 struct sunxi_priv_data *gmac = priv;
461 if (gmac->regulator) {
462 ret = regulator_enable(gmac->regulator);
464 dev_err(&pdev->dev, "Fail to enable regulator\n");
469 ret = clk_prepare_enable(gmac->tx_clk);
472 regulator_disable(gmac->regulator);
473 dev_err(&pdev->dev, "Could not enable AHB clock\n");
480 static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu)
482 void __iomem *ioaddr = hw->pcsr;
485 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
486 writel(v, ioaddr + EMAC_BASIC_CTL1);
489 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
493 t = readl(ioaddr + EMAC_TX_CTL0);
494 r = readl(ioaddr + EMAC_RX_CTL0);
496 t |= EMAC_TX_TRANSMITTER_EN;
497 r |= EMAC_RX_RECEIVER_EN;
499 t &= ~EMAC_TX_TRANSMITTER_EN;
500 r &= ~EMAC_RX_RECEIVER_EN;
502 writel(t, ioaddr + EMAC_TX_CTL0);
503 writel(r, ioaddr + EMAC_RX_CTL0);
506 /* Set MAC address at slot reg_n
507 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
508 * If addr is NULL, clear the slot
510 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
514 void __iomem *ioaddr = hw->pcsr;
518 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
522 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
523 EMAC_MACADDR_LO(reg_n));
525 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
526 v |= MAC_ADDR_TYPE_DST;
527 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
531 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
535 void __iomem *ioaddr = hw->pcsr;
537 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
538 EMAC_MACADDR_LO(reg_n));
541 /* caution this function must return non 0 to work */
542 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
544 void __iomem *ioaddr = hw->pcsr;
547 v = readl(ioaddr + EMAC_RX_CTL0);
549 writel(v, ioaddr + EMAC_RX_CTL0);
554 static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
555 struct net_device *dev)
557 void __iomem *ioaddr = hw->pcsr;
560 struct netdev_hw_addr *ha;
561 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
563 v = EMAC_FRM_FLT_CTL;
565 if (dev->flags & IFF_PROMISC) {
566 v = EMAC_FRM_FLT_RXALL;
567 } else if (dev->flags & IFF_ALLMULTI) {
568 v |= EMAC_FRM_FLT_MULTICAST;
569 } else if (macaddrs <= hw->unicast_filter_entries) {
570 if (!netdev_mc_empty(dev)) {
571 netdev_for_each_mc_addr(ha, dev) {
572 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
576 if (!netdev_uc_empty(dev)) {
577 netdev_for_each_uc_addr(ha, dev) {
578 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
583 netdev_info(dev, "Too many address, switching to promiscuous\n");
584 v = EMAC_FRM_FLT_RXALL;
587 /* Disable unused address filter slots */
588 while (i < hw->unicast_filter_entries)
589 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
591 writel(v, ioaddr + EMAC_RX_FRM_FLT);
594 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
595 unsigned int duplex, unsigned int fc,
596 unsigned int pause_time, u32 tx_cnt)
598 void __iomem *ioaddr = hw->pcsr;
601 v = readl(ioaddr + EMAC_RX_CTL0);
603 v |= EMAC_RX_FLOW_CTL_EN;
605 v &= ~EMAC_RX_FLOW_CTL_EN;
606 writel(v, ioaddr + EMAC_RX_CTL0);
608 v = readl(ioaddr + EMAC_TX_FLOW_CTL);
610 v |= EMAC_TX_FLOW_CTL_EN;
612 v &= ~EMAC_TX_FLOW_CTL_EN;
613 writel(v, ioaddr + EMAC_TX_FLOW_CTL);
616 static int sun8i_dwmac_reset(struct stmmac_priv *priv)
621 v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
622 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
624 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
625 * need more if no cable plugged. 100ms seems OK
627 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
628 !(v & 0x01), 100, 100000);
631 dev_err(priv->device, "EMAC reset timeout\n");
637 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
639 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
640 struct device_node *node = priv->device->of_node;
644 regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val);
645 reg = gmac->variant->default_syscon_value;
647 dev_warn(priv->device,
648 "Current syscon value is not the default %x (expect %x)\n",
651 if (gmac->variant->internal_phy) {
652 if (!gmac->use_internal_phy) {
653 /* switch to external PHY interface */
654 reg &= ~H3_EPHY_SELECT;
656 reg |= H3_EPHY_SELECT;
657 reg &= ~H3_EPHY_SHUTDOWN;
658 dev_dbg(priv->device, "Select internal_phy %x\n", reg);
660 if (of_property_read_bool(priv->plat->phy_node,
661 "allwinner,leds-active-low"))
662 reg |= H3_EPHY_LED_POL;
664 reg &= ~H3_EPHY_LED_POL;
666 /* Force EPHY xtal frequency to 24MHz. */
667 reg |= H3_EPHY_CLK_SEL;
669 ret = of_mdio_parse_addr(priv->device,
670 priv->plat->phy_node);
672 dev_err(priv->device, "Could not parse MDIO addr\n");
675 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
676 * address. No need to mask it again.
678 reg |= ret << H3_EPHY_ADDR_SHIFT;
682 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
684 dev_err(priv->device, "tx-delay must be a multiple of 100\n");
688 dev_dbg(priv->device, "set tx-delay to %x\n", val);
689 if (val <= SYSCON_ETXDC_MASK) {
690 reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
691 reg |= (val << SYSCON_ETXDC_SHIFT);
693 dev_err(priv->device, "Invalid TX clock delay: %d\n",
699 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
701 dev_err(priv->device, "rx-delay must be a multiple of 100\n");
705 dev_dbg(priv->device, "set rx-delay to %x\n", val);
706 if (val <= SYSCON_ERXDC_MASK) {
707 reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT);
708 reg |= (val << SYSCON_ERXDC_SHIFT);
710 dev_err(priv->device, "Invalid RX clock delay: %d\n",
716 /* Clear interface mode bits */
717 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
718 if (gmac->variant->support_rmii)
719 reg &= ~SYSCON_RMII_EN;
721 switch (priv->plat->interface) {
722 case PHY_INTERFACE_MODE_MII:
725 case PHY_INTERFACE_MODE_RGMII:
726 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
728 case PHY_INTERFACE_MODE_RMII:
729 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
732 dev_err(priv->device, "Unsupported interface mode: %s",
733 phy_modes(priv->plat->interface));
737 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
742 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
744 u32 reg = gmac->variant->default_syscon_value;
746 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
749 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
751 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
754 if (!gmac->use_internal_phy)
757 ret = clk_prepare_enable(gmac->ephy_clk);
759 dev_err(priv->device, "Cannot enable ephy\n");
763 /* Make sure the EPHY is properly reseted, as U-Boot may leave
764 * it at deasserted state, and thus it may fail to reset EMAC.
766 reset_control_assert(gmac->rst_ephy);
768 ret = reset_control_deassert(gmac->rst_ephy);
770 dev_err(priv->device, "Cannot deassert ephy\n");
771 clk_disable_unprepare(gmac->ephy_clk);
778 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
780 if (!gmac->use_internal_phy)
783 clk_disable_unprepare(gmac->ephy_clk);
784 reset_control_assert(gmac->rst_ephy);
788 /* sun8i_power_phy() - Activate the PHY:
789 * In case of error, no need to call sun8i_unpower_phy(),
790 * it will be called anyway by sun8i_dwmac_exit()
792 static int sun8i_power_phy(struct stmmac_priv *priv)
796 ret = sun8i_dwmac_power_internal_phy(priv);
800 ret = sun8i_dwmac_set_syscon(priv);
804 /* After changing syscon value, the MAC need reset or it will use
805 * the last value (and so the last PHY set.
807 ret = sun8i_dwmac_reset(priv);
813 static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)
815 sun8i_dwmac_unset_syscon(gmac);
816 sun8i_dwmac_unpower_internal_phy(gmac);
819 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
821 struct sunxi_priv_data *gmac = priv;
823 sun8i_unpower_phy(gmac);
825 clk_disable_unprepare(gmac->tx_clk);
828 regulator_disable(gmac->regulator);
831 static const struct stmmac_ops sun8i_dwmac_ops = {
832 .core_init = sun8i_dwmac_core_init,
833 .set_mac = sun8i_dwmac_set_mac,
834 .dump_regs = sun8i_dwmac_dump_mac_regs,
835 .rx_ipc = sun8i_dwmac_rx_ipc_enable,
836 .set_filter = sun8i_dwmac_set_filter,
837 .flow_ctrl = sun8i_dwmac_flow_ctrl,
838 .set_umac_addr = sun8i_dwmac_set_umac_addr,
839 .get_umac_addr = sun8i_dwmac_get_umac_addr,
842 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
844 struct mac_device_info *mac;
845 struct stmmac_priv *priv = ppriv;
848 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
852 ret = sun8i_power_phy(priv);
856 mac->pcsr = priv->ioaddr;
857 mac->mac = &sun8i_dwmac_ops;
858 mac->dma = &sun8i_dwmac_dma_ops;
860 /* The loopback bit seems to be re-set when link change
861 * Simply mask it each time
862 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
864 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
865 mac->link.speed10 = EMAC_SPEED_10;
866 mac->link.speed100 = EMAC_SPEED_100;
867 mac->link.speed1000 = EMAC_SPEED_1000;
868 mac->link.duplex = EMAC_DUPLEX_FULL;
869 mac->mii.addr = EMAC_MDIO_CMD;
870 mac->mii.data = EMAC_MDIO_DATA;
871 mac->mii.reg_shift = 4;
872 mac->mii.reg_mask = GENMASK(8, 4);
873 mac->mii.addr_shift = 12;
874 mac->mii.addr_mask = GENMASK(16, 12);
875 mac->mii.clk_csr_shift = 20;
876 mac->mii.clk_csr_mask = GENMASK(22, 20);
877 mac->unicast_filter_entries = 8;
879 /* Synopsys Id is not available */
880 priv->synopsys_id = 0;
885 static int sun8i_dwmac_probe(struct platform_device *pdev)
887 struct plat_stmmacenet_data *plat_dat;
888 struct stmmac_resources stmmac_res;
889 struct sunxi_priv_data *gmac;
890 struct device *dev = &pdev->dev;
893 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
897 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
898 if (IS_ERR(plat_dat))
899 return PTR_ERR(plat_dat);
901 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
905 gmac->variant = of_device_get_match_data(&pdev->dev);
906 if (!gmac->variant) {
907 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
911 gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
912 if (IS_ERR(gmac->tx_clk)) {
913 dev_err(dev, "Could not get TX clock\n");
914 return PTR_ERR(gmac->tx_clk);
917 /* Optional regulator for PHY */
918 gmac->regulator = devm_regulator_get_optional(dev, "phy");
919 if (IS_ERR(gmac->regulator)) {
920 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
921 return -EPROBE_DEFER;
922 dev_info(dev, "No regulator found\n");
923 gmac->regulator = NULL;
926 gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
928 if (IS_ERR(gmac->regmap)) {
929 ret = PTR_ERR(gmac->regmap);
930 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
934 plat_dat->interface = of_get_phy_mode(dev->of_node);
935 if (plat_dat->interface == gmac->variant->internal_phy) {
936 dev_info(&pdev->dev, "Will use internal PHY\n");
937 gmac->use_internal_phy = true;
938 gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
939 if (IS_ERR(gmac->ephy_clk)) {
940 ret = PTR_ERR(gmac->ephy_clk);
941 dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret);
945 gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
946 if (IS_ERR(gmac->rst_ephy)) {
947 ret = PTR_ERR(gmac->rst_ephy);
948 if (ret == -EPROBE_DEFER)
950 dev_err(&pdev->dev, "No EPHY reset control found %d\n",
955 dev_info(&pdev->dev, "Will use external PHY\n");
956 gmac->use_internal_phy = false;
959 /* platform data specifying hardware features and callbacks.
960 * hardware features were copied from Allwinner drivers.
962 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
963 plat_dat->tx_coe = 1;
964 plat_dat->has_sun8i = true;
965 plat_dat->bsp_priv = gmac;
966 plat_dat->init = sun8i_dwmac_init;
967 plat_dat->exit = sun8i_dwmac_exit;
968 plat_dat->setup = sun8i_dwmac_setup;
970 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
974 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
976 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
981 static const struct of_device_id sun8i_dwmac_match[] = {
984 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
986 static struct platform_driver sun8i_dwmac_driver = {
987 .probe = sun8i_dwmac_probe,
988 .remove = stmmac_pltfr_remove,
990 .name = "dwmac-sun8i",
991 .pm = &stmmac_pltfr_pm_ops,
992 .of_match_table = sun8i_dwmac_match,
995 module_platform_driver(sun8i_dwmac_driver);
997 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
998 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
999 MODULE_LICENSE("GPL");