drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /**
   3  * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   4  *
   5  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   6  *
   7  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   8  */
   9
  10 #include <linux/stmmac.h>
  11 #include <linux/bitops.h>
  12 #include <linux/clk.h>
  13 #include <linux/phy.h>
  14 #include <linux/of_net.h>
  15 #include <linux/gpio.h>
  16 #include <linux/module.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/delay.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include "stmmac_platform.h"
  27
  28 struct rk_priv_data;
  29 struct rk_gmac_ops {
  30         void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  31                              int tx_delay, int rx_delay);
  32         void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  33         void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  34         void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  35         void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
  36         u32 regs[];
  37 };
  38
  39 struct rk_priv_data {
  40         struct platform_device *pdev;
  41         phy_interface_t phy_iface;
  42         int id;
  43         struct regulator *regulator;
  44         bool suspended;
  45         const struct rk_gmac_ops *ops;
  46
  47         bool clk_enabled;
  48         bool clock_input;
  49         bool integrated_phy;
  50
  51         struct clk *clk_mac;
  52         struct clk *gmac_clkin;
  53         struct clk *mac_clk_rx;
  54         struct clk *mac_clk_tx;
  55         struct clk *clk_mac_ref;
  56         struct clk *clk_mac_refout;
  57         struct clk *clk_mac_speed;
  58         struct clk *aclk_mac;
  59         struct clk *pclk_mac;
  60         struct clk *clk_phy;
  61
  62         struct reset_control *phy_reset;
  63
  64         int tx_delay;
  65         int rx_delay;
  66
  67         struct regmap *grf;
  68 };
  69
  70 #define HIWORD_UPDATE(val, mask, shift) \
  71                 ((val) << (shift) | (mask) << ((shift) + 16))
  72
  73 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  74 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  75
  76 #define DELAY_ENABLE(soc, tx, rx) \
  77         (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
  78          ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
  79
  80 #define PX30_GRF_GMAC_CON1              0x0904
  81
  82 /* PX30_GRF_GMAC_CON1 */
  83 #define PX30_GMAC_PHY_INTF_SEL_RMII     (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
  84                                          GRF_BIT(6))
  85 #define PX30_GMAC_SPEED_10M             GRF_CLR_BIT(2)
  86 #define PX30_GMAC_SPEED_100M            GRF_BIT(2)
  87
  88 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
  89 {
  90         struct device *dev = &bsp_priv->pdev->dev;
  91
  92         if (IS_ERR(bsp_priv->grf)) {
  93                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
  94                 return;
  95         }
  96
  97         regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
  98                      PX30_GMAC_PHY_INTF_SEL_RMII);
  99 }
 100
 101 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 102 {
 103         struct device *dev = &bsp_priv->pdev->dev;
 104         int ret;
 105
 106         if (IS_ERR(bsp_priv->clk_mac_speed)) {
 107                 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
 108                 return;
 109         }
 110
 111         if (speed == 10) {
 112                 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
 113                              PX30_GMAC_SPEED_10M);
 114
 115                 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
 116                 if (ret)
 117                         dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
 118                                 __func__, ret);
 119         } else if (speed == 100) {
 120                 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
 121                              PX30_GMAC_SPEED_100M);
 122
 123                 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
 124                 if (ret)
 125                         dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
 126                                 __func__, ret);
 127
 128         } else {
 129                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 130         }
 131 }
 132
 133 static const struct rk_gmac_ops px30_ops = {
 134         .set_to_rmii = px30_set_to_rmii,
 135         .set_rmii_speed = px30_set_rmii_speed,
 136 };
 137
 138 #define RK3128_GRF_MAC_CON0     0x0168
 139 #define RK3128_GRF_MAC_CON1     0x016c
 140
 141 /* RK3128_GRF_MAC_CON0 */
 142 #define RK3128_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
 143 #define RK3128_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
 144 #define RK3128_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
 145 #define RK3128_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
 146 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
 147 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
 148
 149 /* RK3128_GRF_MAC_CON1 */
 150 #define RK3128_GMAC_PHY_INTF_SEL_RGMII  \
 151                 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
 152 #define RK3128_GMAC_PHY_INTF_SEL_RMII   \
 153                 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
 154 #define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
 155 #define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
 156 #define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
 157 #define RK3128_GMAC_SPEED_100M         GRF_BIT(10)
 158 #define RK3128_GMAC_RMII_CLK_25M       GRF_BIT(11)
 159 #define RK3128_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
 160 #define RK3128_GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 161 #define RK3128_GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
 162 #define RK3128_GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
 163 #define RK3128_GMAC_RMII_MODE          GRF_BIT(14)
 164 #define RK3128_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
 165
 166 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
 167                                 int tx_delay, int rx_delay)
 168 {
 169         struct device *dev = &bsp_priv->pdev->dev;
 170
 171         if (IS_ERR(bsp_priv->grf)) {
 172                 dev_err(dev, "Missing rockchip,grf property\n");
 173                 return;
 174         }
 175
 176         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 177                      RK3128_GMAC_PHY_INTF_SEL_RGMII |
 178                      RK3128_GMAC_RMII_MODE_CLR);
 179         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
 180                      DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
 181                      RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
 182                      RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
 183 }
 184
 185 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
 186 {
 187         struct device *dev = &bsp_priv->pdev->dev;
 188
 189         if (IS_ERR(bsp_priv->grf)) {
 190                 dev_err(dev, "Missing rockchip,grf property\n");
 191                 return;
 192         }
 193
 194         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 195                      RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
 196 }
 197
 198 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 199 {
 200         struct device *dev = &bsp_priv->pdev->dev;
 201
 202         if (IS_ERR(bsp_priv->grf)) {
 203                 dev_err(dev, "Missing rockchip,grf property\n");
 204                 return;
 205         }
 206
 207         if (speed == 10)
 208                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 209                              RK3128_GMAC_CLK_2_5M);
 210         else if (speed == 100)
 211                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 212                              RK3128_GMAC_CLK_25M);
 213         else if (speed == 1000)
 214                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 215                              RK3128_GMAC_CLK_125M);
 216         else
 217                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 218 }
 219
 220 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 221 {
 222         struct device *dev = &bsp_priv->pdev->dev;
 223
 224         if (IS_ERR(bsp_priv->grf)) {
 225                 dev_err(dev, "Missing rockchip,grf property\n");
 226                 return;
 227         }
 228
 229         if (speed == 10) {
 230                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 231                              RK3128_GMAC_RMII_CLK_2_5M |
 232                              RK3128_GMAC_SPEED_10M);
 233         } else if (speed == 100) {
 234                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 235                              RK3128_GMAC_RMII_CLK_25M |
 236                              RK3128_GMAC_SPEED_100M);
 237         } else {
 238                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 239         }
 240 }
 241
 242 static const struct rk_gmac_ops rk3128_ops = {
 243         .set_to_rgmii = rk3128_set_to_rgmii,
 244         .set_to_rmii = rk3128_set_to_rmii,
 245         .set_rgmii_speed = rk3128_set_rgmii_speed,
 246         .set_rmii_speed = rk3128_set_rmii_speed,
 247 };
 248
 249 #define RK3228_GRF_MAC_CON0     0x0900
 250 #define RK3228_GRF_MAC_CON1     0x0904
 251
 252 #define RK3228_GRF_CON_MUX      0x50
 253
 254 /* RK3228_GRF_MAC_CON0 */
 255 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 256 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 257
 258 /* RK3228_GRF_MAC_CON1 */
 259 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
 260                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 261 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
 262                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 263 #define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
 264 #define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 265 #define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 266 #define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
 267 #define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
 268 #define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 269 #define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
 270 #define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
 271 #define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
 272 #define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
 273 #define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
 274 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 275 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 276 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 277 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 278
 279 /* RK3228_GRF_COM_MUX */
 280 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY  GRF_BIT(15)
 281
 282 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 283                                 int tx_delay, int rx_delay)
 284 {
 285         struct device *dev = &bsp_priv->pdev->dev;
 286
 287         if (IS_ERR(bsp_priv->grf)) {
 288                 dev_err(dev, "Missing rockchip,grf property\n");
 289                 return;
 290         }
 291
 292         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 293                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 294                      RK3228_GMAC_RMII_MODE_CLR |
 295                      DELAY_ENABLE(RK3228, tx_delay, rx_delay));
 296
 297         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 298                      RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 299                      RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 300 }
 301
 302 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 303 {
 304         struct device *dev = &bsp_priv->pdev->dev;
 305
 306         if (IS_ERR(bsp_priv->grf)) {
 307                 dev_err(dev, "Missing rockchip,grf property\n");
 308                 return;
 309         }
 310
 311         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 312                      RK3228_GMAC_PHY_INTF_SEL_RMII |
 313                      RK3228_GMAC_RMII_MODE);
 314
 315         /* set MAC to RMII mode */
 316         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 317 }
 318
 319 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 320 {
 321         struct device *dev = &bsp_priv->pdev->dev;
 322
 323         if (IS_ERR(bsp_priv->grf)) {
 324                 dev_err(dev, "Missing rockchip,grf property\n");
 325                 return;
 326         }
 327
 328         if (speed == 10)
 329                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 330                              RK3228_GMAC_CLK_2_5M);
 331         else if (speed == 100)
 332                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 333                              RK3228_GMAC_CLK_25M);
 334         else if (speed == 1000)
 335                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 336                              RK3228_GMAC_CLK_125M);
 337         else
 338                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 339 }
 340
 341 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 342 {
 343         struct device *dev = &bsp_priv->pdev->dev;
 344
 345         if (IS_ERR(bsp_priv->grf)) {
 346                 dev_err(dev, "Missing rockchip,grf property\n");
 347                 return;
 348         }
 349
 350         if (speed == 10)
 351                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 352                              RK3228_GMAC_RMII_CLK_2_5M |
 353                              RK3228_GMAC_SPEED_10M);
 354         else if (speed == 100)
 355                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 356                              RK3228_GMAC_RMII_CLK_25M |
 357                              RK3228_GMAC_SPEED_100M);
 358         else
 359                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 360 }
 361
 362 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
 363 {
 364         regmap_write(priv->grf, RK3228_GRF_CON_MUX,
 365                      RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
 366 }
 367
 368 static const struct rk_gmac_ops rk3228_ops = {
 369         .set_to_rgmii = rk3228_set_to_rgmii,
 370         .set_to_rmii = rk3228_set_to_rmii,
 371         .set_rgmii_speed = rk3228_set_rgmii_speed,
 372         .set_rmii_speed = rk3228_set_rmii_speed,
 373         .integrated_phy_powerup =  rk3228_integrated_phy_powerup,
 374 };
 375
 376 #define RK3288_GRF_SOC_CON1     0x0248
 377 #define RK3288_GRF_SOC_CON3     0x0250
 378
 379 /*RK3288_GRF_SOC_CON1*/
 380 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 381                                          GRF_CLR_BIT(8))
 382 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 383                                          GRF_BIT(8))
 384 #define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 385 #define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 386 #define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 387 #define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 388 #define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 389 #define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 390 #define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 391 #define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 392 #define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 393 #define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 394 #define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 395
 396 /*RK3288_GRF_SOC_CON3*/
 397 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 398 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 399 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 400 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 401 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 402 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 403
 404 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 405                                 int tx_delay, int rx_delay)
 406 {
 407         struct device *dev = &bsp_priv->pdev->dev;
 408
 409         if (IS_ERR(bsp_priv->grf)) {
 410                 dev_err(dev, "Missing rockchip,grf property\n");
 411                 return;
 412         }
 413
 414         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 415                      RK3288_GMAC_PHY_INTF_SEL_RGMII |
 416                      RK3288_GMAC_RMII_MODE_CLR);
 417         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 418                      DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
 419                      RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 420                      RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 421 }
 422
 423 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 424 {
 425         struct device *dev = &bsp_priv->pdev->dev;
 426
 427         if (IS_ERR(bsp_priv->grf)) {
 428                 dev_err(dev, "Missing rockchip,grf property\n");
 429                 return;
 430         }
 431
 432         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 433                      RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 434 }
 435
 436 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 437 {
 438         struct device *dev = &bsp_priv->pdev->dev;
 439
 440         if (IS_ERR(bsp_priv->grf)) {
 441                 dev_err(dev, "Missing rockchip,grf property\n");
 442                 return;
 443         }
 444
 445         if (speed == 10)
 446                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 447                              RK3288_GMAC_CLK_2_5M);
 448         else if (speed == 100)
 449                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 450                              RK3288_GMAC_CLK_25M);
 451         else if (speed == 1000)
 452                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 453                              RK3288_GMAC_CLK_125M);
 454         else
 455                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 456 }
 457
 458 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 459 {
 460         struct device *dev = &bsp_priv->pdev->dev;
 461
 462         if (IS_ERR(bsp_priv->grf)) {
 463                 dev_err(dev, "Missing rockchip,grf property\n");
 464                 return;
 465         }
 466
 467         if (speed == 10) {
 468                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 469                              RK3288_GMAC_RMII_CLK_2_5M |
 470                              RK3288_GMAC_SPEED_10M);
 471         } else if (speed == 100) {
 472                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 473                              RK3288_GMAC_RMII_CLK_25M |
 474                              RK3288_GMAC_SPEED_100M);
 475         } else {
 476                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 477         }
 478 }
 479
 480 static const struct rk_gmac_ops rk3288_ops = {
 481         .set_to_rgmii = rk3288_set_to_rgmii,
 482         .set_to_rmii = rk3288_set_to_rmii,
 483         .set_rgmii_speed = rk3288_set_rgmii_speed,
 484         .set_rmii_speed = rk3288_set_rmii_speed,
 485 };
 486
 487 #define RK3308_GRF_MAC_CON0             0x04a0
 488
 489 /* RK3308_GRF_MAC_CON0 */
 490 #define RK3308_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
 491                                         GRF_BIT(4))
 492 #define RK3308_GMAC_FLOW_CTRL           GRF_BIT(3)
 493 #define RK3308_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 494 #define RK3308_GMAC_SPEED_10M           GRF_CLR_BIT(0)
 495 #define RK3308_GMAC_SPEED_100M          GRF_BIT(0)
 496
 497 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
 498 {
 499         struct device *dev = &bsp_priv->pdev->dev;
 500
 501         if (IS_ERR(bsp_priv->grf)) {
 502                 dev_err(dev, "Missing rockchip,grf property\n");
 503                 return;
 504         }
 505
 506         regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
 507                      RK3308_GMAC_PHY_INTF_SEL_RMII);
 508 }
 509
 510 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 511 {
 512         struct device *dev = &bsp_priv->pdev->dev;
 513
 514         if (IS_ERR(bsp_priv->grf)) {
 515                 dev_err(dev, "Missing rockchip,grf property\n");
 516                 return;
 517         }
 518
 519         if (speed == 10) {
 520                 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
 521                              RK3308_GMAC_SPEED_10M);
 522         } else if (speed == 100) {
 523                 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
 524                              RK3308_GMAC_SPEED_100M);
 525         } else {
 526                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 527         }
 528 }
 529
 530 static const struct rk_gmac_ops rk3308_ops = {
 531         .set_to_rmii = rk3308_set_to_rmii,
 532         .set_rmii_speed = rk3308_set_rmii_speed,
 533 };
 534
 535 #define RK3328_GRF_MAC_CON0     0x0900
 536 #define RK3328_GRF_MAC_CON1     0x0904
 537 #define RK3328_GRF_MAC_CON2     0x0908
 538 #define RK3328_GRF_MACPHY_CON1  0xb04
 539
 540 /* RK3328_GRF_MAC_CON0 */
 541 #define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 542 #define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 543
 544 /* RK3328_GRF_MAC_CON1 */
 545 #define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
 546                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 547 #define RK3328_GMAC_PHY_INTF_SEL_RMII   \
 548                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 549 #define RK3328_GMAC_FLOW_CTRL           GRF_BIT(3)
 550 #define RK3328_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 551 #define RK3328_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 552 #define RK3328_GMAC_SPEED_100M          GRF_BIT(2)
 553 #define RK3328_GMAC_RMII_CLK_25M        GRF_BIT(7)
 554 #define RK3328_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 555 #define RK3328_GMAC_CLK_125M            (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 556 #define RK3328_GMAC_CLK_25M             (GRF_BIT(11) | GRF_BIT(12))
 557 #define RK3328_GMAC_CLK_2_5M            (GRF_CLR_BIT(11) | GRF_BIT(12))
 558 #define RK3328_GMAC_RMII_MODE           GRF_BIT(9)
 559 #define RK3328_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(9)
 560 #define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 561 #define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 562 #define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 563 #define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 564
 565 /* RK3328_GRF_MACPHY_CON1 */
 566 #define RK3328_MACPHY_RMII_MODE         GRF_BIT(9)
 567
 568 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 569                                 int tx_delay, int rx_delay)
 570 {
 571         struct device *dev = &bsp_priv->pdev->dev;
 572
 573         if (IS_ERR(bsp_priv->grf)) {
 574                 dev_err(dev, "Missing rockchip,grf property\n");
 575                 return;
 576         }
 577
 578         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 579                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 580                      RK3328_GMAC_RMII_MODE_CLR |
 581                      RK3328_GMAC_RXCLK_DLY_ENABLE |
 582                      RK3328_GMAC_TXCLK_DLY_ENABLE);
 583
 584         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 585                      RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 586                      RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 587 }
 588
 589 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 590 {
 591         struct device *dev = &bsp_priv->pdev->dev;
 592         unsigned int reg;
 593
 594         if (IS_ERR(bsp_priv->grf)) {
 595                 dev_err(dev, "Missing rockchip,grf property\n");
 596                 return;
 597         }
 598
 599         reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 600                   RK3328_GRF_MAC_CON1;
 601
 602         regmap_write(bsp_priv->grf, reg,
 603                      RK3328_GMAC_PHY_INTF_SEL_RMII |
 604                      RK3328_GMAC_RMII_MODE);
 605 }
 606
 607 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 608 {
 609         struct device *dev = &bsp_priv->pdev->dev;
 610
 611         if (IS_ERR(bsp_priv->grf)) {
 612                 dev_err(dev, "Missing rockchip,grf property\n");
 613                 return;
 614         }
 615
 616         if (speed == 10)
 617                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 618                              RK3328_GMAC_CLK_2_5M);
 619         else if (speed == 100)
 620                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 621                              RK3328_GMAC_CLK_25M);
 622         else if (speed == 1000)
 623                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 624                              RK3328_GMAC_CLK_125M);
 625         else
 626                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 627 }
 628
 629 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 630 {
 631         struct device *dev = &bsp_priv->pdev->dev;
 632         unsigned int reg;
 633
 634         if (IS_ERR(bsp_priv->grf)) {
 635                 dev_err(dev, "Missing rockchip,grf property\n");
 636                 return;
 637         }
 638
 639         reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 640                   RK3328_GRF_MAC_CON1;
 641
 642         if (speed == 10)
 643                 regmap_write(bsp_priv->grf, reg,
 644                              RK3328_GMAC_RMII_CLK_2_5M |
 645                              RK3328_GMAC_SPEED_10M);
 646         else if (speed == 100)
 647                 regmap_write(bsp_priv->grf, reg,
 648                              RK3328_GMAC_RMII_CLK_25M |
 649                              RK3328_GMAC_SPEED_100M);
 650         else
 651                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 652 }
 653
 654 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
 655 {
 656         regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
 657                      RK3328_MACPHY_RMII_MODE);
 658 }
 659
 660 static const struct rk_gmac_ops rk3328_ops = {
 661         .set_to_rgmii = rk3328_set_to_rgmii,
 662         .set_to_rmii = rk3328_set_to_rmii,
 663         .set_rgmii_speed = rk3328_set_rgmii_speed,
 664         .set_rmii_speed = rk3328_set_rmii_speed,
 665         .integrated_phy_powerup =  rk3328_integrated_phy_powerup,
 666 };
 667
 668 #define RK3366_GRF_SOC_CON6     0x0418
 669 #define RK3366_GRF_SOC_CON7     0x041c
 670
 671 /* RK3366_GRF_SOC_CON6 */
 672 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 673                                          GRF_CLR_BIT(11))
 674 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 675                                          GRF_BIT(11))
 676 #define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 677 #define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 678 #define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 679 #define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 680 #define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 681 #define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 682 #define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 683 #define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 684 #define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 685 #define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 686 #define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 687
 688 /* RK3366_GRF_SOC_CON7 */
 689 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 690 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 691 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 692 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 693 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 694 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 695
 696 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 697                                 int tx_delay, int rx_delay)
 698 {
 699         struct device *dev = &bsp_priv->pdev->dev;
 700
 701         if (IS_ERR(bsp_priv->grf)) {
 702                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 703                 return;
 704         }
 705
 706         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 707                      RK3366_GMAC_PHY_INTF_SEL_RGMII |
 708                      RK3366_GMAC_RMII_MODE_CLR);
 709         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 710                      DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
 711                      RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 712                      RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 713 }
 714
 715 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 716 {
 717         struct device *dev = &bsp_priv->pdev->dev;
 718
 719         if (IS_ERR(bsp_priv->grf)) {
 720                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 721                 return;
 722         }
 723
 724         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 725                      RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 726 }
 727
 728 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 729 {
 730         struct device *dev = &bsp_priv->pdev->dev;
 731
 732         if (IS_ERR(bsp_priv->grf)) {
 733                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 734                 return;
 735         }
 736
 737         if (speed == 10)
 738                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 739                              RK3366_GMAC_CLK_2_5M);
 740         else if (speed == 100)
 741                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 742                              RK3366_GMAC_CLK_25M);
 743         else if (speed == 1000)
 744                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 745                              RK3366_GMAC_CLK_125M);
 746         else
 747                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 748 }
 749
 750 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 751 {
 752         struct device *dev = &bsp_priv->pdev->dev;
 753
 754         if (IS_ERR(bsp_priv->grf)) {
 755                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 756                 return;
 757         }
 758
 759         if (speed == 10) {
 760                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 761                              RK3366_GMAC_RMII_CLK_2_5M |
 762                              RK3366_GMAC_SPEED_10M);
 763         } else if (speed == 100) {
 764                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 765                              RK3366_GMAC_RMII_CLK_25M |
 766                              RK3366_GMAC_SPEED_100M);
 767         } else {
 768                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 769         }
 770 }
 771
 772 static const struct rk_gmac_ops rk3366_ops = {
 773         .set_to_rgmii = rk3366_set_to_rgmii,
 774         .set_to_rmii = rk3366_set_to_rmii,
 775         .set_rgmii_speed = rk3366_set_rgmii_speed,
 776         .set_rmii_speed = rk3366_set_rmii_speed,
 777 };
 778
 779 #define RK3368_GRF_SOC_CON15    0x043c
 780 #define RK3368_GRF_SOC_CON16    0x0440
 781
 782 /* RK3368_GRF_SOC_CON15 */
 783 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 784                                          GRF_CLR_BIT(11))
 785 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 786                                          GRF_BIT(11))
 787 #define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 788 #define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 789 #define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 790 #define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 791 #define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 792 #define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 793 #define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 794 #define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 795 #define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 796 #define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 797 #define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 798
 799 /* RK3368_GRF_SOC_CON16 */
 800 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 801 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 802 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 803 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 804 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 805 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 806
 807 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 808                                 int tx_delay, int rx_delay)
 809 {
 810         struct device *dev = &bsp_priv->pdev->dev;
 811
 812         if (IS_ERR(bsp_priv->grf)) {
 813                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 814                 return;
 815         }
 816
 817         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 818                      RK3368_GMAC_PHY_INTF_SEL_RGMII |
 819                      RK3368_GMAC_RMII_MODE_CLR);
 820         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 821                      DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
 822                      RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 823                      RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 824 }
 825
 826 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 827 {
 828         struct device *dev = &bsp_priv->pdev->dev;
 829
 830         if (IS_ERR(bsp_priv->grf)) {
 831                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 832                 return;
 833         }
 834
 835         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 836                      RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 837 }
 838
 839 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 840 {
 841         struct device *dev = &bsp_priv->pdev->dev;
 842
 843         if (IS_ERR(bsp_priv->grf)) {
 844                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 845                 return;
 846         }
 847
 848         if (speed == 10)
 849                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 850                              RK3368_GMAC_CLK_2_5M);
 851         else if (speed == 100)
 852                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 853                              RK3368_GMAC_CLK_25M);
 854         else if (speed == 1000)
 855                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 856                              RK3368_GMAC_CLK_125M);
 857         else
 858                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 859 }
 860
 861 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 862 {
 863         struct device *dev = &bsp_priv->pdev->dev;
 864
 865         if (IS_ERR(bsp_priv->grf)) {
 866                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 867                 return;
 868         }
 869
 870         if (speed == 10) {
 871                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 872                              RK3368_GMAC_RMII_CLK_2_5M |
 873                              RK3368_GMAC_SPEED_10M);
 874         } else if (speed == 100) {
 875                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 876                              RK3368_GMAC_RMII_CLK_25M |
 877                              RK3368_GMAC_SPEED_100M);
 878         } else {
 879                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 880         }
 881 }
 882
 883 static const struct rk_gmac_ops rk3368_ops = {
 884         .set_to_rgmii = rk3368_set_to_rgmii,
 885         .set_to_rmii = rk3368_set_to_rmii,
 886         .set_rgmii_speed = rk3368_set_rgmii_speed,
 887         .set_rmii_speed = rk3368_set_rmii_speed,
 888 };
 889
 890 #define RK3399_GRF_SOC_CON5     0xc214
 891 #define RK3399_GRF_SOC_CON6     0xc218
 892
 893 /* RK3399_GRF_SOC_CON5 */
 894 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 895                                          GRF_CLR_BIT(11))
 896 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 897                                          GRF_BIT(11))
 898 #define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 899 #define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 900 #define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 901 #define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 902 #define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 903 #define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 904 #define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 905 #define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 906 #define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 907 #define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 908 #define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 909
 910 /* RK3399_GRF_SOC_CON6 */
 911 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 912 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 913 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 914 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 915 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 916 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 917
 918 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 919                                 int tx_delay, int rx_delay)
 920 {
 921         struct device *dev = &bsp_priv->pdev->dev;
 922
 923         if (IS_ERR(bsp_priv->grf)) {
 924                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 925                 return;
 926         }
 927
 928         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 929                      RK3399_GMAC_PHY_INTF_SEL_RGMII |
 930                      RK3399_GMAC_RMII_MODE_CLR);
 931         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 932                      DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
 933                      RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 934                      RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 935 }
 936
 937 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 938 {
 939         struct device *dev = &bsp_priv->pdev->dev;
 940
 941         if (IS_ERR(bsp_priv->grf)) {
 942                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 943                 return;
 944         }
 945
 946         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 947                      RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 948 }
 949
 950 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 951 {
 952         struct device *dev = &bsp_priv->pdev->dev;
 953
 954         if (IS_ERR(bsp_priv->grf)) {
 955                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 956                 return;
 957         }
 958
 959         if (speed == 10)
 960                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 961                              RK3399_GMAC_CLK_2_5M);
 962         else if (speed == 100)
 963                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 964                              RK3399_GMAC_CLK_25M);
 965         else if (speed == 1000)
 966                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 967                              RK3399_GMAC_CLK_125M);
 968         else
 969                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 970 }
 971
 972 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 973 {
 974         struct device *dev = &bsp_priv->pdev->dev;
 975
 976         if (IS_ERR(bsp_priv->grf)) {
 977                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 978                 return;
 979         }
 980
 981         if (speed == 10) {
 982                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 983                              RK3399_GMAC_RMII_CLK_2_5M |
 984                              RK3399_GMAC_SPEED_10M);
 985         } else if (speed == 100) {
 986                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 987                              RK3399_GMAC_RMII_CLK_25M |
 988                              RK3399_GMAC_SPEED_100M);
 989         } else {
 990                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 991         }
 992 }
 993
 994 static const struct rk_gmac_ops rk3399_ops = {
 995         .set_to_rgmii = rk3399_set_to_rgmii,
 996         .set_to_rmii = rk3399_set_to_rmii,
 997         .set_rgmii_speed = rk3399_set_rgmii_speed,
 998         .set_rmii_speed = rk3399_set_rmii_speed,
 999 };
1000
1001 #define RK3568_GRF_GMAC0_CON0           0x0380
1002 #define RK3568_GRF_GMAC0_CON1           0x0384
1003 #define RK3568_GRF_GMAC1_CON0           0x0388
1004 #define RK3568_GRF_GMAC1_CON1           0x038c
1005
1006 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1007 #define RK3568_GMAC_PHY_INTF_SEL_RGMII  \
1008                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1009 #define RK3568_GMAC_PHY_INTF_SEL_RMII   \
1010                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1011 #define RK3568_GMAC_FLOW_CTRL                   GRF_BIT(3)
1012 #define RK3568_GMAC_FLOW_CTRL_CLR               GRF_CLR_BIT(3)
1013 #define RK3568_GMAC_RXCLK_DLY_ENABLE            GRF_BIT(1)
1014 #define RK3568_GMAC_RXCLK_DLY_DISABLE           GRF_CLR_BIT(1)
1015 #define RK3568_GMAC_TXCLK_DLY_ENABLE            GRF_BIT(0)
1016 #define RK3568_GMAC_TXCLK_DLY_DISABLE           GRF_CLR_BIT(0)
1017
1018 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1019 #define RK3568_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
1020 #define RK3568_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
1021
1022 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1023                                 int tx_delay, int rx_delay)
1024 {
1025         struct device *dev = &bsp_priv->pdev->dev;
1026         u32 con0, con1;
1027
1028         if (IS_ERR(bsp_priv->grf)) {
1029                 dev_err(dev, "Missing rockchip,grf property\n");
1030                 return;
1031         }
1032
1033         con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1034                                      RK3568_GRF_GMAC0_CON0;
1035         con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1036                                      RK3568_GRF_GMAC0_CON1;
1037
1038         regmap_write(bsp_priv->grf, con0,
1039                      RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1040                      RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1041
1042         regmap_write(bsp_priv->grf, con1,
1043                      RK3568_GMAC_PHY_INTF_SEL_RGMII |
1044                      RK3568_GMAC_RXCLK_DLY_ENABLE |
1045                      RK3568_GMAC_TXCLK_DLY_ENABLE);
1046 }
1047
1048 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1049 {
1050         struct device *dev = &bsp_priv->pdev->dev;
1051         u32 con1;
1052
1053         if (IS_ERR(bsp_priv->grf)) {
1054                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1055                 return;
1056         }
1057
1058         con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1059                                      RK3568_GRF_GMAC0_CON1;
1060         regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1061 }
1062
1063 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1064 {
1065         struct device *dev = &bsp_priv->pdev->dev;
1066         unsigned long rate;
1067         int ret;
1068
1069         switch (speed) {
1070         case 10:
1071                 rate = 2500000;
1072                 break;
1073         case 100:
1074                 rate = 25000000;
1075                 break;
1076         case 1000:
1077                 rate = 125000000;
1078                 break;
1079         default:
1080                 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1081                 return;
1082         }
1083
1084         ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1085         if (ret)
1086                 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1087                         __func__, rate, ret);
1088 }
1089
1090 static const struct rk_gmac_ops rk3568_ops = {
1091         .set_to_rgmii = rk3568_set_to_rgmii,
1092         .set_to_rmii = rk3568_set_to_rmii,
1093         .set_rgmii_speed = rk3568_set_gmac_speed,
1094         .set_rmii_speed = rk3568_set_gmac_speed,
1095         .regs = {
1096                 0xfe2a0000, /* gmac0 */
1097                 0xfe010000, /* gmac1 */
1098                 0x0, /* sentinel */
1099         },
1100 };
1101
1102 #define RV1108_GRF_GMAC_CON0            0X0900
1103
1104 /* RV1108_GRF_GMAC_CON0 */
1105 #define RV1108_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1106                                         GRF_BIT(6))
1107 #define RV1108_GMAC_FLOW_CTRL           GRF_BIT(3)
1108 #define RV1108_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
1109 #define RV1108_GMAC_SPEED_10M           GRF_CLR_BIT(2)
1110 #define RV1108_GMAC_SPEED_100M          GRF_BIT(2)
1111 #define RV1108_GMAC_RMII_CLK_25M        GRF_BIT(7)
1112 #define RV1108_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
1113
1114 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1115 {
1116         struct device *dev = &bsp_priv->pdev->dev;
1117
1118         if (IS_ERR(bsp_priv->grf)) {
1119                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1120                 return;
1121         }
1122
1123         regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1124                      RV1108_GMAC_PHY_INTF_SEL_RMII);
1125 }
1126
1127 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1128 {
1129         struct device *dev = &bsp_priv->pdev->dev;
1130
1131         if (IS_ERR(bsp_priv->grf)) {
1132                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1133                 return;
1134         }
1135
1136         if (speed == 10) {
1137                 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1138                              RV1108_GMAC_RMII_CLK_2_5M |
1139                              RV1108_GMAC_SPEED_10M);
1140         } else if (speed == 100) {
1141                 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1142                              RV1108_GMAC_RMII_CLK_25M |
1143                              RV1108_GMAC_SPEED_100M);
1144         } else {
1145                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1146         }
1147 }
1148
1149 static const struct rk_gmac_ops rv1108_ops = {
1150         .set_to_rmii = rv1108_set_to_rmii,
1151         .set_rmii_speed = rv1108_set_rmii_speed,
1152 };
1153
1154 #define RK_GRF_MACPHY_CON0              0xb00
1155 #define RK_GRF_MACPHY_CON1              0xb04
1156 #define RK_GRF_MACPHY_CON2              0xb08
1157 #define RK_GRF_MACPHY_CON3              0xb0c
1158
1159 #define RK_MACPHY_ENABLE                GRF_BIT(0)
1160 #define RK_MACPHY_DISABLE               GRF_CLR_BIT(0)
1161 #define RK_MACPHY_CFG_CLK_50M           GRF_BIT(14)
1162 #define RK_GMAC2PHY_RMII_MODE           (GRF_BIT(6) | GRF_CLR_BIT(7))
1163 #define RK_GRF_CON2_MACPHY_ID           HIWORD_UPDATE(0x1234, 0xffff, 0)
1164 #define RK_GRF_CON3_MACPHY_ID           HIWORD_UPDATE(0x35, 0x3f, 0)
1165
1166 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1167 {
1168         if (priv->ops->integrated_phy_powerup)
1169                 priv->ops->integrated_phy_powerup(priv);
1170
1171         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1172         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1173
1174         regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1175         regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1176
1177         if (priv->phy_reset) {
1178                 /* PHY needs to be disabled before trying to reset it */
1179                 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1180                 if (priv->phy_reset)
1181                         reset_control_assert(priv->phy_reset);
1182                 usleep_range(10, 20);
1183                 if (priv->phy_reset)
1184                         reset_control_deassert(priv->phy_reset);
1185                 usleep_range(10, 20);
1186                 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1187                 msleep(30);
1188         }
1189 }
1190
1191 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1192 {
1193         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1194         if (priv->phy_reset)
1195                 reset_control_assert(priv->phy_reset);
1196 }
1197
1198 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1199 {
1200         struct rk_priv_data *bsp_priv = plat->bsp_priv;
1201         struct device *dev = &bsp_priv->pdev->dev;
1202         int ret;
1203
1204         bsp_priv->clk_enabled = false;
1205
1206         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
1207         if (IS_ERR(bsp_priv->mac_clk_rx))
1208                 dev_err(dev, "cannot get clock %s\n",
1209                         "mac_clk_rx");
1210
1211         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
1212         if (IS_ERR(bsp_priv->mac_clk_tx))
1213                 dev_err(dev, "cannot get clock %s\n",
1214                         "mac_clk_tx");
1215
1216         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
1217         if (IS_ERR(bsp_priv->aclk_mac))
1218                 dev_err(dev, "cannot get clock %s\n",
1219                         "aclk_mac");
1220
1221         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
1222         if (IS_ERR(bsp_priv->pclk_mac))
1223                 dev_err(dev, "cannot get clock %s\n",
1224                         "pclk_mac");
1225
1226         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1227         if (IS_ERR(bsp_priv->clk_mac))
1228                 dev_err(dev, "cannot get clock %s\n",
1229                         "stmmaceth");
1230
1231         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1232                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
1233                 if (IS_ERR(bsp_priv->clk_mac_ref))
1234                         dev_err(dev, "cannot get clock %s\n",
1235                                 "clk_mac_ref");
1236
1237                 if (!bsp_priv->clock_input) {
1238                         bsp_priv->clk_mac_refout =
1239                                 devm_clk_get(dev, "clk_mac_refout");
1240                         if (IS_ERR(bsp_priv->clk_mac_refout))
1241                                 dev_err(dev, "cannot get clock %s\n",
1242                                         "clk_mac_refout");
1243                 }
1244         }
1245
1246         bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
1247         if (IS_ERR(bsp_priv->clk_mac_speed))
1248                 dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
1249
1250         if (bsp_priv->clock_input) {
1251                 dev_info(dev, "clock input from PHY\n");
1252         } else {
1253                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1254                         clk_set_rate(bsp_priv->clk_mac, 50000000);
1255         }
1256
1257         if (plat->phy_node && bsp_priv->integrated_phy) {
1258                 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1259                 if (IS_ERR(bsp_priv->clk_phy)) {
1260                         ret = PTR_ERR(bsp_priv->clk_phy);
1261                         dev_err(dev, "Cannot get PHY clock: %d\n", ret);
1262                         return -EINVAL;
1263                 }
1264                 clk_set_rate(bsp_priv->clk_phy, 50000000);
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1271 {
1272         int phy_iface = bsp_priv->phy_iface;
1273
1274         if (enable) {
1275                 if (!bsp_priv->clk_enabled) {
1276                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1277                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
1278                                         clk_prepare_enable(
1279                                                 bsp_priv->mac_clk_rx);
1280
1281                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
1282                                         clk_prepare_enable(
1283                                                 bsp_priv->clk_mac_ref);
1284
1285                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
1286                                         clk_prepare_enable(
1287                                                 bsp_priv->clk_mac_refout);
1288                         }
1289
1290                         if (!IS_ERR(bsp_priv->clk_phy))
1291                                 clk_prepare_enable(bsp_priv->clk_phy);
1292
1293                         if (!IS_ERR(bsp_priv->aclk_mac))
1294                                 clk_prepare_enable(bsp_priv->aclk_mac);
1295
1296                         if (!IS_ERR(bsp_priv->pclk_mac))
1297                                 clk_prepare_enable(bsp_priv->pclk_mac);
1298
1299                         if (!IS_ERR(bsp_priv->mac_clk_tx))
1300                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
1301
1302                         if (!IS_ERR(bsp_priv->clk_mac_speed))
1303                                 clk_prepare_enable(bsp_priv->clk_mac_speed);
1304
1305                         /**
1306                          * if (!IS_ERR(bsp_priv->clk_mac))
1307                          *      clk_prepare_enable(bsp_priv->clk_mac);
1308                          */
1309                         mdelay(5);
1310                         bsp_priv->clk_enabled = true;
1311                 }
1312         } else {
1313                 if (bsp_priv->clk_enabled) {
1314                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1315                                 clk_disable_unprepare(bsp_priv->mac_clk_rx);
1316
1317                                 clk_disable_unprepare(bsp_priv->clk_mac_ref);
1318
1319                                 clk_disable_unprepare(bsp_priv->clk_mac_refout);
1320                         }
1321
1322                         clk_disable_unprepare(bsp_priv->clk_phy);
1323
1324                         clk_disable_unprepare(bsp_priv->aclk_mac);
1325
1326                         clk_disable_unprepare(bsp_priv->pclk_mac);
1327
1328                         clk_disable_unprepare(bsp_priv->mac_clk_tx);
1329
1330                         clk_disable_unprepare(bsp_priv->clk_mac_speed);
1331                         /**
1332                          * if (!IS_ERR(bsp_priv->clk_mac))
1333                          *      clk_disable_unprepare(bsp_priv->clk_mac);
1334                          */
1335                         bsp_priv->clk_enabled = false;
1336                 }
1337         }
1338
1339         return 0;
1340 }
1341
1342 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1343 {
1344         struct regulator *ldo = bsp_priv->regulator;
1345         int ret;
1346         struct device *dev = &bsp_priv->pdev->dev;
1347
1348         if (!ldo)
1349                 return 0;
1350
1351         if (enable) {
1352                 ret = regulator_enable(ldo);
1353                 if (ret)
1354                         dev_err(dev, "fail to enable phy-supply\n");
1355         } else {
1356                 ret = regulator_disable(ldo);
1357                 if (ret)
1358                         dev_err(dev, "fail to disable phy-supply\n");
1359         }
1360
1361         return 0;
1362 }
1363
1364 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1365                                           struct plat_stmmacenet_data *plat,
1366                                           const struct rk_gmac_ops *ops)
1367 {
1368         struct rk_priv_data *bsp_priv;
1369         struct device *dev = &pdev->dev;
1370         struct resource *res;
1371         int ret;
1372         const char *strings = NULL;
1373         int value;
1374
1375         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1376         if (!bsp_priv)
1377                 return ERR_PTR(-ENOMEM);
1378
1379         of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
1380         bsp_priv->ops = ops;
1381
1382         /* Some SoCs have multiple MAC controllers, which need
1383          * to be distinguished.
1384          */
1385         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386         if (res) {
1387                 int i = 0;
1388
1389                 while (ops->regs[i]) {
1390                         if (ops->regs[i] == res->start) {
1391                                 bsp_priv->id = i;
1392                                 break;
1393                         }
1394                         i++;
1395                 }
1396         }
1397
1398         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
1399         if (IS_ERR(bsp_priv->regulator)) {
1400                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
1401                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
1402                         return ERR_PTR(-EPROBE_DEFER);
1403                 }
1404                 dev_err(dev, "no regulator found\n");
1405                 bsp_priv->regulator = NULL;
1406         }
1407
1408         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1409         if (ret) {
1410                 dev_err(dev, "Can not read property: clock_in_out.\n");
1411                 bsp_priv->clock_input = true;
1412         } else {
1413                 dev_info(dev, "clock input or output? (%s).\n",
1414                          strings);
1415                 if (!strcmp(strings, "input"))
1416                         bsp_priv->clock_input = true;
1417                 else
1418                         bsp_priv->clock_input = false;
1419         }
1420
1421         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1422         if (ret) {
1423                 bsp_priv->tx_delay = 0x30;
1424                 dev_err(dev, "Can not read property: tx_delay.");
1425                 dev_err(dev, "set tx_delay to 0x%x\n",
1426                         bsp_priv->tx_delay);
1427         } else {
1428                 dev_info(dev, "TX delay(0x%x).\n", value);
1429                 bsp_priv->tx_delay = value;
1430         }
1431
1432         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1433         if (ret) {
1434                 bsp_priv->rx_delay = 0x10;
1435                 dev_err(dev, "Can not read property: rx_delay.");
1436                 dev_err(dev, "set rx_delay to 0x%x\n",
1437                         bsp_priv->rx_delay);
1438         } else {
1439                 dev_info(dev, "RX delay(0x%x).\n", value);
1440                 bsp_priv->rx_delay = value;
1441         }
1442
1443         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1444                                                         "rockchip,grf");
1445
1446         if (plat->phy_node) {
1447                 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1448                                                                  "phy-is-integrated");
1449                 if (bsp_priv->integrated_phy) {
1450                         bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1451                         if (IS_ERR(bsp_priv->phy_reset)) {
1452                                 dev_err(&pdev->dev, "No PHY reset control found.\n");
1453                                 bsp_priv->phy_reset = NULL;
1454                         }
1455                 }
1456         }
1457         dev_info(dev, "integrated PHY? (%s).\n",
1458                  bsp_priv->integrated_phy ? "yes" : "no");
1459
1460         bsp_priv->pdev = pdev;
1461
1462         return bsp_priv;
1463 }
1464
1465 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1466 {
1467         switch (bsp_priv->phy_iface) {
1468         case PHY_INTERFACE_MODE_RGMII:
1469         case PHY_INTERFACE_MODE_RGMII_ID:
1470         case PHY_INTERFACE_MODE_RGMII_RXID:
1471         case PHY_INTERFACE_MODE_RGMII_TXID:
1472                 if (!bsp_priv->ops->set_to_rgmii)
1473                         return -EINVAL;
1474                 break;
1475         case PHY_INTERFACE_MODE_RMII:
1476                 if (!bsp_priv->ops->set_to_rmii)
1477                         return -EINVAL;
1478                 break;
1479         default:
1480                 dev_err(&bsp_priv->pdev->dev,
1481                         "unsupported interface %d", bsp_priv->phy_iface);
1482         }
1483         return 0;
1484 }
1485
1486 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1487 {
1488         int ret;
1489         struct device *dev = &bsp_priv->pdev->dev;
1490
1491         ret = rk_gmac_check_ops(bsp_priv);
1492         if (ret)
1493                 return ret;
1494
1495         ret = gmac_clk_enable(bsp_priv, true);
1496         if (ret)
1497                 return ret;
1498
1499         /*rmii or rgmii*/
1500         switch (bsp_priv->phy_iface) {
1501         case PHY_INTERFACE_MODE_RGMII:
1502                 dev_info(dev, "init for RGMII\n");
1503                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1504                                             bsp_priv->rx_delay);
1505                 break;
1506         case PHY_INTERFACE_MODE_RGMII_ID:
1507                 dev_info(dev, "init for RGMII_ID\n");
1508                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1509                 break;
1510         case PHY_INTERFACE_MODE_RGMII_RXID:
1511                 dev_info(dev, "init for RGMII_RXID\n");
1512                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1513                 break;
1514         case PHY_INTERFACE_MODE_RGMII_TXID:
1515                 dev_info(dev, "init for RGMII_TXID\n");
1516                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1517                 break;
1518         case PHY_INTERFACE_MODE_RMII:
1519                 dev_info(dev, "init for RMII\n");
1520                 bsp_priv->ops->set_to_rmii(bsp_priv);
1521                 break;
1522         default:
1523                 dev_err(dev, "NO interface defined!\n");
1524         }
1525
1526         ret = phy_power_on(bsp_priv, true);
1527         if (ret) {
1528                 gmac_clk_enable(bsp_priv, false);
1529                 return ret;
1530         }
1531
1532         pm_runtime_enable(dev);
1533         pm_runtime_get_sync(dev);
1534
1535         if (bsp_priv->integrated_phy)
1536                 rk_gmac_integrated_phy_powerup(bsp_priv);
1537
1538         return 0;
1539 }
1540
1541 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1542 {
1543         struct device *dev = &gmac->pdev->dev;
1544
1545         if (gmac->integrated_phy)
1546                 rk_gmac_integrated_phy_powerdown(gmac);
1547
1548         pm_runtime_put_sync(dev);
1549         pm_runtime_disable(dev);
1550
1551         phy_power_on(gmac, false);
1552         gmac_clk_enable(gmac, false);
1553 }
1554
1555 static void rk_fix_speed(void *priv, unsigned int speed)
1556 {
1557         struct rk_priv_data *bsp_priv = priv;
1558         struct device *dev = &bsp_priv->pdev->dev;
1559
1560         switch (bsp_priv->phy_iface) {
1561         case PHY_INTERFACE_MODE_RGMII:
1562         case PHY_INTERFACE_MODE_RGMII_ID:
1563         case PHY_INTERFACE_MODE_RGMII_RXID:
1564         case PHY_INTERFACE_MODE_RGMII_TXID:
1565                 if (bsp_priv->ops->set_rgmii_speed)
1566                         bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1567                 break;
1568         case PHY_INTERFACE_MODE_RMII:
1569                 if (bsp_priv->ops->set_rmii_speed)
1570                         bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1571                 break;
1572         default:
1573                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1574         }
1575 }
1576
1577 static int rk_gmac_probe(struct platform_device *pdev)
1578 {
1579         struct plat_stmmacenet_data *plat_dat;
1580         struct stmmac_resources stmmac_res;
1581         const struct rk_gmac_ops *data;
1582         int ret;
1583
1584         data = of_device_get_match_data(&pdev->dev);
1585         if (!data) {
1586                 dev_err(&pdev->dev, "no of match data provided\n");
1587                 return -EINVAL;
1588         }
1589
1590         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1591         if (ret)
1592                 return ret;
1593
1594         plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
1595         if (IS_ERR(plat_dat))
1596                 return PTR_ERR(plat_dat);
1597
1598         /* If the stmmac is not already selected as gmac4,
1599          * then make sure we fallback to gmac.
1600          */
1601         if (!plat_dat->has_gmac4)
1602                 plat_dat->has_gmac = true;
1603         plat_dat->fix_mac_speed = rk_fix_speed;
1604
1605         plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1606         if (IS_ERR(plat_dat->bsp_priv)) {
1607                 ret = PTR_ERR(plat_dat->bsp_priv);
1608                 goto err_remove_config_dt;
1609         }
1610
1611         ret = rk_gmac_clk_init(plat_dat);
1612         if (ret)
1613                 goto err_remove_config_dt;
1614
1615         ret = rk_gmac_powerup(plat_dat->bsp_priv);
1616         if (ret)
1617                 goto err_remove_config_dt;
1618
1619         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1620         if (ret)
1621                 goto err_gmac_powerdown;
1622
1623         return 0;
1624
1625 err_gmac_powerdown:
1626         rk_gmac_powerdown(plat_dat->bsp_priv);
1627 err_remove_config_dt:
1628         stmmac_remove_config_dt(pdev, plat_dat);
1629
1630         return ret;
1631 }
1632
1633 static int rk_gmac_remove(struct platform_device *pdev)
1634 {
1635         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1636         int ret = stmmac_dvr_remove(&pdev->dev);
1637
1638         rk_gmac_powerdown(bsp_priv);
1639
1640         return ret;
1641 }
1642
1643 #ifdef CONFIG_PM_SLEEP
1644 static int rk_gmac_suspend(struct device *dev)
1645 {
1646         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1647         int ret = stmmac_suspend(dev);
1648
1649         /* Keep the PHY up if we use Wake-on-Lan. */
1650         if (!device_may_wakeup(dev)) {
1651                 rk_gmac_powerdown(bsp_priv);
1652                 bsp_priv->suspended = true;
1653         }
1654
1655         return ret;
1656 }
1657
1658 static int rk_gmac_resume(struct device *dev)
1659 {
1660         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1661
1662         /* The PHY was up for Wake-on-Lan. */
1663         if (bsp_priv->suspended) {
1664                 rk_gmac_powerup(bsp_priv);
1665                 bsp_priv->suspended = false;
1666         }
1667
1668         return stmmac_resume(dev);
1669 }
1670 #endif /* CONFIG_PM_SLEEP */
1671
1672 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1673
1674 static const struct of_device_id rk_gmac_dwmac_match[] = {
1675         { .compatible = "rockchip,px30-gmac",   .data = &px30_ops   },
1676         { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1677         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1678         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1679         { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1680         { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1681         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1682         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1683         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1684         { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1685         { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1686         { }
1687 };
1688 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1689
1690 static struct platform_driver rk_gmac_dwmac_driver = {
1691         .probe  = rk_gmac_probe,
1692         .remove = rk_gmac_remove,
1693         .driver = {
1694                 .name           = "rk_gmac-dwmac",
1695                 .pm             = &rk_gmac_pm_ops,
1696                 .of_match_table = rk_gmac_dwmac_match,
1697         },
1698 };
1699 module_platform_driver(rk_gmac_dwmac_driver);
1700
1701 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1702 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1703 MODULE_LICENSE("GPL");