1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
11 struct intel_priv_data {
12 int mdio_adhoc_addr; /* mdio address for serdes & etc */
15 /* This struct is used to associate PCI Function of MAC controller on a board,
16 * discovered via DMI, with the address of PHY connected to the MAC. The
17 * negative value of the address means that MAC controller is not connected
20 struct stmmac_pci_func_data {
25 struct stmmac_pci_dmi_data {
26 const struct stmmac_pci_func_data *func;
30 struct stmmac_pci_info {
31 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
34 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
35 const struct dmi_system_id *dmi_list)
37 const struct stmmac_pci_func_data *func_data;
38 const struct stmmac_pci_dmi_data *dmi_data;
39 const struct dmi_system_id *dmi_id;
40 int func = PCI_FUNC(pdev->devfn);
43 dmi_id = dmi_first_match(dmi_list);
47 dmi_data = dmi_id->driver_data;
48 func_data = dmi_data->func;
50 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
51 if (func_data->func == func)
52 return func_data->phy_addr;
57 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
58 int phyreg, u32 mask, u32 val)
60 unsigned int retries = 10;
64 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
65 if ((val_rd & mask) == (val & mask))
67 udelay(POLL_DELAY_US);
73 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
75 struct intel_priv_data *intel_priv = priv_data;
76 struct stmmac_priv *priv = netdev_priv(ndev);
77 int serdes_phy_addr = 0;
80 if (!intel_priv->mdio_adhoc_addr)
83 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
86 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
87 data |= SERDES_PLL_CLK;
88 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
90 /* check for clk_ack assertion */
91 data = serdes_status_poll(priv, serdes_phy_addr,
97 dev_err(priv->device, "Serdes PLL clk request timeout\n");
101 /* assert lane reset */
102 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
104 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
106 /* check for assert lane reset reflection */
107 data = serdes_status_poll(priv, serdes_phy_addr,
113 dev_err(priv->device, "Serdes assert lane reset timeout\n");
117 /* move power state to P0 */
118 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
120 data &= ~SERDES_PWR_ST_MASK;
121 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
123 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
125 /* Check for P0 state */
126 data = serdes_status_poll(priv, serdes_phy_addr,
129 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
132 dev_err(priv->device, "Serdes power state P0 timeout.\n");
139 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
141 struct intel_priv_data *intel_priv = intel_data;
142 struct stmmac_priv *priv = netdev_priv(ndev);
143 int serdes_phy_addr = 0;
146 if (!intel_priv->mdio_adhoc_addr)
149 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
151 /* move power state to P3 */
152 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
154 data &= ~SERDES_PWR_ST_MASK;
155 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
157 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
159 /* Check for P3 state */
160 data = serdes_status_poll(priv, serdes_phy_addr,
163 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
166 dev_err(priv->device, "Serdes power state P3 timeout\n");
170 /* de-assert clk_req */
171 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
172 data &= ~SERDES_PLL_CLK;
173 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
175 /* check for clk_ack de-assert */
176 data = serdes_status_poll(priv, serdes_phy_addr,
179 (u32)~SERDES_PLL_CLK);
182 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
186 /* de-assert lane reset */
187 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
189 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
191 /* check for de-assert lane reset reflection */
192 data = serdes_status_poll(priv, serdes_phy_addr,
198 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
203 static void common_default_data(struct plat_stmmacenet_data *plat)
205 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
207 plat->force_sf_dma_mode = 1;
209 plat->mdio_bus_data->needs_reset = true;
211 /* Set default value for multicast hash bins */
212 plat->multicast_filter_bins = HASH_TABLE_SIZE;
214 /* Set default value for unicast filter entries */
215 plat->unicast_filter_entries = 1;
217 /* Set the maxmtu to a default of JUMBO_LEN */
218 plat->maxmtu = JUMBO_LEN;
220 /* Set default number of RX and TX queues to use */
221 plat->tx_queues_to_use = 1;
222 plat->rx_queues_to_use = 1;
224 /* Disable Priority config by default */
225 plat->tx_queues_cfg[0].use_prio = false;
226 plat->rx_queues_cfg[0].use_prio = false;
228 /* Disable RX queues routing by default */
229 plat->rx_queues_cfg[0].pkt_route = 0x0;
232 static int intel_mgbe_common_data(struct pci_dev *pdev,
233 struct plat_stmmacenet_data *plat)
241 plat->force_sf_dma_mode = 0;
244 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
246 for (i = 0; i < plat->rx_queues_to_use; i++) {
247 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
248 plat->rx_queues_cfg[i].chan = i;
250 /* Disable Priority config by default */
251 plat->rx_queues_cfg[i].use_prio = false;
253 /* Disable RX queues routing by default */
254 plat->rx_queues_cfg[i].pkt_route = 0x0;
257 for (i = 0; i < plat->tx_queues_to_use; i++) {
258 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
260 /* Disable Priority config by default */
261 plat->tx_queues_cfg[i].use_prio = false;
264 /* FIFO size is 4096 bytes for 1 tx/rx queue */
265 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
266 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
268 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
269 plat->tx_queues_cfg[0].weight = 0x09;
270 plat->tx_queues_cfg[1].weight = 0x0A;
271 plat->tx_queues_cfg[2].weight = 0x0B;
272 plat->tx_queues_cfg[3].weight = 0x0C;
273 plat->tx_queues_cfg[4].weight = 0x0D;
274 plat->tx_queues_cfg[5].weight = 0x0E;
275 plat->tx_queues_cfg[6].weight = 0x0F;
276 plat->tx_queues_cfg[7].weight = 0x10;
278 plat->dma_cfg->pbl = 32;
279 plat->dma_cfg->pblx8 = true;
280 plat->dma_cfg->fixed_burst = 0;
281 plat->dma_cfg->mixed_burst = 0;
282 plat->dma_cfg->aal = 0;
284 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
289 plat->axi->axi_lpi_en = 0;
290 plat->axi->axi_xit_frm = 0;
291 plat->axi->axi_wr_osr_lmt = 1;
292 plat->axi->axi_rd_osr_lmt = 1;
293 plat->axi->axi_blen[0] = 4;
294 plat->axi->axi_blen[1] = 8;
295 plat->axi->axi_blen[2] = 16;
297 plat->ptp_max_adj = plat->clk_ptp_rate;
299 /* Set system clock */
300 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
301 "stmmac-clk", NULL, 0,
304 if (IS_ERR(plat->stmmac_clk)) {
305 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
306 plat->stmmac_clk = NULL;
309 ret = clk_prepare_enable(plat->stmmac_clk);
311 clk_unregister_fixed_rate(plat->stmmac_clk);
315 /* Set default value for multicast hash bins */
316 plat->multicast_filter_bins = HASH_TABLE_SIZE;
318 /* Set default value for unicast filter entries */
319 plat->unicast_filter_entries = 1;
321 /* Set the maxmtu to a default of JUMBO_LEN */
322 plat->maxmtu = JUMBO_LEN;
327 static int ehl_common_data(struct pci_dev *pdev,
328 struct plat_stmmacenet_data *plat)
330 plat->rx_queues_to_use = 8;
331 plat->tx_queues_to_use = 8;
332 plat->clk_ptp_rate = 200000000;
334 return intel_mgbe_common_data(pdev, plat);
337 static int ehl_sgmii_data(struct pci_dev *pdev,
338 struct plat_stmmacenet_data *plat)
342 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
344 plat->serdes_powerup = intel_serdes_powerup;
345 plat->serdes_powerdown = intel_serdes_powerdown;
347 return ehl_common_data(pdev, plat);
350 static struct stmmac_pci_info ehl_sgmii1g_info = {
351 .setup = ehl_sgmii_data,
354 static int ehl_rgmii_data(struct pci_dev *pdev,
355 struct plat_stmmacenet_data *plat)
359 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
361 return ehl_common_data(pdev, plat);
364 static struct stmmac_pci_info ehl_rgmii1g_info = {
365 .setup = ehl_rgmii_data,
368 static int ehl_pse0_common_data(struct pci_dev *pdev,
369 struct plat_stmmacenet_data *plat)
373 return ehl_common_data(pdev, plat);
376 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
377 struct plat_stmmacenet_data *plat)
379 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
380 return ehl_pse0_common_data(pdev, plat);
383 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
384 .setup = ehl_pse0_rgmii1g_data,
387 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
388 struct plat_stmmacenet_data *plat)
390 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
391 plat->serdes_powerup = intel_serdes_powerup;
392 plat->serdes_powerdown = intel_serdes_powerdown;
393 return ehl_pse0_common_data(pdev, plat);
396 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
397 .setup = ehl_pse0_sgmii1g_data,
400 static int ehl_pse1_common_data(struct pci_dev *pdev,
401 struct plat_stmmacenet_data *plat)
405 return ehl_common_data(pdev, plat);
408 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
409 struct plat_stmmacenet_data *plat)
411 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
412 return ehl_pse1_common_data(pdev, plat);
415 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
416 .setup = ehl_pse1_rgmii1g_data,
419 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
420 struct plat_stmmacenet_data *plat)
422 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
423 plat->serdes_powerup = intel_serdes_powerup;
424 plat->serdes_powerdown = intel_serdes_powerdown;
425 return ehl_pse1_common_data(pdev, plat);
428 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
429 .setup = ehl_pse1_sgmii1g_data,
432 static int tgl_common_data(struct pci_dev *pdev,
433 struct plat_stmmacenet_data *plat)
435 plat->rx_queues_to_use = 6;
436 plat->tx_queues_to_use = 4;
437 plat->clk_ptp_rate = 200000000;
439 return intel_mgbe_common_data(pdev, plat);
442 static int tgl_sgmii_data(struct pci_dev *pdev,
443 struct plat_stmmacenet_data *plat)
447 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
448 plat->serdes_powerup = intel_serdes_powerup;
449 plat->serdes_powerdown = intel_serdes_powerdown;
450 return tgl_common_data(pdev, plat);
453 static struct stmmac_pci_info tgl_sgmii1g_info = {
454 .setup = tgl_sgmii_data,
457 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
464 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
465 .func = galileo_stmmac_func_data,
466 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
469 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
480 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
481 .func = iot2040_stmmac_func_data,
482 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
485 static const struct dmi_system_id quark_pci_dmi[] = {
488 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
490 .driver_data = (void *)&galileo_stmmac_dmi_data,
494 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
496 .driver_data = (void *)&galileo_stmmac_dmi_data,
498 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
499 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
500 * has only one pci network device while other asset tags are
501 * for IOT2040 which has two.
505 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
506 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
507 "6ES7647-0AA00-0YA2"),
509 .driver_data = (void *)&galileo_stmmac_dmi_data,
513 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
515 .driver_data = (void *)&iot2040_stmmac_dmi_data,
520 static int quark_default_data(struct pci_dev *pdev,
521 struct plat_stmmacenet_data *plat)
525 /* Set common default data first */
526 common_default_data(plat);
528 /* Refuse to load the driver and register net device if MAC controller
529 * does not connect to any PHY interface.
531 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
533 /* Return error to the caller on DMI enabled boards. */
534 if (dmi_get_system_info(DMI_BOARD_NAME))
537 /* Galileo boards with old firmware don't support DMI. We always
538 * use 1 here as PHY address, so at least the first found MAC
539 * controller would be probed.
544 plat->bus_id = pci_dev_id(pdev);
545 plat->phy_addr = ret;
546 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
548 plat->dma_cfg->pbl = 16;
549 plat->dma_cfg->pblx8 = true;
550 plat->dma_cfg->fixed_burst = 1;
556 static const struct stmmac_pci_info quark_info = {
557 .setup = quark_default_data,
561 * intel_eth_pci_probe
563 * @pdev: pci device pointer
564 * @id: pointer to table of device id/id's.
566 * Description: This probing function gets called for all PCI devices which
567 * match the ID table and are not "owned" by other driver yet. This function
568 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
569 * matches the device. The probe functions returns zero when the driver choose
570 * to take "ownership" of the device or an error code(-ve no) otherwise.
572 static int intel_eth_pci_probe(struct pci_dev *pdev,
573 const struct pci_device_id *id)
575 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
576 struct intel_priv_data *intel_priv;
577 struct plat_stmmacenet_data *plat;
578 struct stmmac_resources res;
581 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
585 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
589 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
590 sizeof(*plat->mdio_bus_data),
592 if (!plat->mdio_bus_data)
595 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
600 /* Enable pci device */
601 ret = pci_enable_device(pdev);
603 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
608 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
612 pci_set_master(pdev);
614 plat->bsp_priv = intel_priv;
615 intel_priv->mdio_adhoc_addr = 0x15;
617 ret = info->setup(pdev, plat);
621 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
625 memset(&res, 0, sizeof(res));
626 res.addr = pcim_iomap_table(pdev)[0];
627 res.wol_irq = pci_irq_vector(pdev, 0);
628 res.irq = pci_irq_vector(pdev, 0);
630 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
632 pci_free_irq_vectors(pdev);
633 clk_disable_unprepare(plat->stmmac_clk);
634 clk_unregister_fixed_rate(plat->stmmac_clk);
641 * intel_eth_pci_remove
643 * @pdev: platform device pointer
644 * Description: this function calls the main to free the net resources
645 * and releases the PCI resources.
647 static void intel_eth_pci_remove(struct pci_dev *pdev)
649 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
650 struct stmmac_priv *priv = netdev_priv(ndev);
652 stmmac_dvr_remove(&pdev->dev);
654 pci_free_irq_vectors(pdev);
656 clk_disable_unprepare(priv->plat->stmmac_clk);
657 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
659 pcim_iounmap_regions(pdev, BIT(0));
661 pci_disable_device(pdev);
664 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
666 struct pci_dev *pdev = to_pci_dev(dev);
669 ret = stmmac_suspend(dev);
673 ret = pci_save_state(pdev);
677 pci_disable_device(pdev);
678 pci_wake_from_d3(pdev, true);
682 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
684 struct pci_dev *pdev = to_pci_dev(dev);
687 pci_restore_state(pdev);
688 pci_set_power_state(pdev, PCI_D0);
690 ret = pci_enable_device(pdev);
694 pci_set_master(pdev);
696 return stmmac_resume(dev);
699 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
700 intel_eth_pci_resume);
702 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
703 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
704 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
705 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32
706 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
707 * which are named PSE0 and PSE1
709 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
710 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
711 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2
712 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
713 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
714 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2
715 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
717 static const struct pci_device_id intel_eth_pci_id_table[] = {
718 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
719 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
720 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
721 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
722 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
723 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
724 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) },
725 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
726 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
727 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
728 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
731 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
733 static struct pci_driver intel_eth_pci_driver = {
734 .name = "intel-eth-pci",
735 .id_table = intel_eth_pci_id_table,
736 .probe = intel_eth_pci_probe,
737 .remove = intel_eth_pci_remove,
739 .pm = &intel_eth_pm_ops,
743 module_pci_driver(intel_eth_pci_driver);
745 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
746 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
747 MODULE_LICENSE("GPL v2");