1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
11 struct intel_priv_data {
12 int mdio_adhoc_addr; /* mdio address for serdes & etc */
15 /* This struct is used to associate PCI Function of MAC controller on a board,
16 * discovered via DMI, with the address of PHY connected to the MAC. The
17 * negative value of the address means that MAC controller is not connected
20 struct stmmac_pci_func_data {
25 struct stmmac_pci_dmi_data {
26 const struct stmmac_pci_func_data *func;
30 struct stmmac_pci_info {
31 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
34 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
35 const struct dmi_system_id *dmi_list)
37 const struct stmmac_pci_func_data *func_data;
38 const struct stmmac_pci_dmi_data *dmi_data;
39 const struct dmi_system_id *dmi_id;
40 int func = PCI_FUNC(pdev->devfn);
43 dmi_id = dmi_first_match(dmi_list);
47 dmi_data = dmi_id->driver_data;
48 func_data = dmi_data->func;
50 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
51 if (func_data->func == func)
52 return func_data->phy_addr;
57 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
58 int phyreg, u32 mask, u32 val)
60 unsigned int retries = 10;
64 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
65 if ((val_rd & mask) == (val & mask))
67 udelay(POLL_DELAY_US);
73 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
75 struct intel_priv_data *intel_priv = priv_data;
76 struct stmmac_priv *priv = netdev_priv(ndev);
77 int serdes_phy_addr = 0;
80 if (!intel_priv->mdio_adhoc_addr)
83 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
86 data = mdiobus_read(priv->mii, serdes_phy_addr,
89 data |= SERDES_PLL_CLK;
91 mdiobus_write(priv->mii, serdes_phy_addr,
94 /* check for clk_ack assertion */
95 data = serdes_status_poll(priv, serdes_phy_addr,
101 dev_err(priv->device, "Serdes PLL clk request timeout\n");
105 /* assert lane reset */
106 data = mdiobus_read(priv->mii, serdes_phy_addr,
111 mdiobus_write(priv->mii, serdes_phy_addr,
114 /* check for assert lane reset reflection */
115 data = serdes_status_poll(priv, serdes_phy_addr,
121 dev_err(priv->device, "Serdes assert lane reset timeout\n");
125 /* move power state to P0 */
126 data = mdiobus_read(priv->mii, serdes_phy_addr,
129 data &= ~SERDES_PWR_ST_MASK;
130 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
132 mdiobus_write(priv->mii, serdes_phy_addr,
135 /* Check for P0 state */
136 data = serdes_status_poll(priv, serdes_phy_addr,
139 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
142 dev_err(priv->device, "Serdes power state P0 timeout.\n");
149 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
151 struct intel_priv_data *intel_priv = intel_data;
152 struct stmmac_priv *priv = netdev_priv(ndev);
153 int serdes_phy_addr = 0;
156 if (!intel_priv->mdio_adhoc_addr)
159 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
161 /* move power state to P3 */
162 data = mdiobus_read(priv->mii, serdes_phy_addr,
165 data &= ~SERDES_PWR_ST_MASK;
166 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
168 mdiobus_write(priv->mii, serdes_phy_addr,
171 /* Check for P3 state */
172 data = serdes_status_poll(priv, serdes_phy_addr,
175 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
178 dev_err(priv->device, "Serdes power state P3 timeout\n");
182 /* de-assert clk_req */
183 data = mdiobus_read(priv->mii, serdes_phy_addr,
186 data &= ~SERDES_PLL_CLK;
188 mdiobus_write(priv->mii, serdes_phy_addr,
191 /* check for clk_ack de-assert */
192 data = serdes_status_poll(priv, serdes_phy_addr,
195 (u32)~SERDES_PLL_CLK);
198 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
202 /* de-assert lane reset */
203 data = mdiobus_read(priv->mii, serdes_phy_addr,
208 mdiobus_write(priv->mii, serdes_phy_addr,
211 /* check for de-assert lane reset reflection */
212 data = serdes_status_poll(priv, serdes_phy_addr,
218 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
223 static void common_default_data(struct plat_stmmacenet_data *plat)
225 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
227 plat->force_sf_dma_mode = 1;
229 plat->mdio_bus_data->needs_reset = true;
231 /* Set default value for multicast hash bins */
232 plat->multicast_filter_bins = HASH_TABLE_SIZE;
234 /* Set default value for unicast filter entries */
235 plat->unicast_filter_entries = 1;
237 /* Set the maxmtu to a default of JUMBO_LEN */
238 plat->maxmtu = JUMBO_LEN;
240 /* Set default number of RX and TX queues to use */
241 plat->tx_queues_to_use = 1;
242 plat->rx_queues_to_use = 1;
244 /* Disable Priority config by default */
245 plat->tx_queues_cfg[0].use_prio = false;
246 plat->rx_queues_cfg[0].use_prio = false;
248 /* Disable RX queues routing by default */
249 plat->rx_queues_cfg[0].pkt_route = 0x0;
252 static int intel_mgbe_common_data(struct pci_dev *pdev,
253 struct plat_stmmacenet_data *plat)
260 plat->force_sf_dma_mode = 0;
263 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
265 for (i = 0; i < plat->rx_queues_to_use; i++) {
266 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
267 plat->rx_queues_cfg[i].chan = i;
269 /* Disable Priority config by default */
270 plat->rx_queues_cfg[i].use_prio = false;
272 /* Disable RX queues routing by default */
273 plat->rx_queues_cfg[i].pkt_route = 0x0;
276 for (i = 0; i < plat->tx_queues_to_use; i++) {
277 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
279 /* Disable Priority config by default */
280 plat->tx_queues_cfg[i].use_prio = false;
283 /* FIFO size is 4096 bytes for 1 tx/rx queue */
284 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
285 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
287 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
288 plat->tx_queues_cfg[0].weight = 0x09;
289 plat->tx_queues_cfg[1].weight = 0x0A;
290 plat->tx_queues_cfg[2].weight = 0x0B;
291 plat->tx_queues_cfg[3].weight = 0x0C;
292 plat->tx_queues_cfg[4].weight = 0x0D;
293 plat->tx_queues_cfg[5].weight = 0x0E;
294 plat->tx_queues_cfg[6].weight = 0x0F;
295 plat->tx_queues_cfg[7].weight = 0x10;
297 plat->dma_cfg->pbl = 32;
298 plat->dma_cfg->pblx8 = true;
299 plat->dma_cfg->fixed_burst = 0;
300 plat->dma_cfg->mixed_burst = 0;
301 plat->dma_cfg->aal = 0;
303 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
308 plat->axi->axi_lpi_en = 0;
309 plat->axi->axi_xit_frm = 0;
310 plat->axi->axi_wr_osr_lmt = 1;
311 plat->axi->axi_rd_osr_lmt = 1;
312 plat->axi->axi_blen[0] = 4;
313 plat->axi->axi_blen[1] = 8;
314 plat->axi->axi_blen[2] = 16;
316 plat->ptp_max_adj = plat->clk_ptp_rate;
318 /* Set system clock */
319 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
320 "stmmac-clk", NULL, 0,
323 if (IS_ERR(plat->stmmac_clk)) {
324 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
325 plat->stmmac_clk = NULL;
327 clk_prepare_enable(plat->stmmac_clk);
329 /* Set default value for multicast hash bins */
330 plat->multicast_filter_bins = HASH_TABLE_SIZE;
332 /* Set default value for unicast filter entries */
333 plat->unicast_filter_entries = 1;
335 /* Set the maxmtu to a default of JUMBO_LEN */
336 plat->maxmtu = JUMBO_LEN;
341 static int ehl_common_data(struct pci_dev *pdev,
342 struct plat_stmmacenet_data *plat)
346 plat->rx_queues_to_use = 8;
347 plat->tx_queues_to_use = 8;
348 plat->clk_ptp_rate = 200000000;
349 ret = intel_mgbe_common_data(pdev, plat);
356 static int ehl_sgmii_data(struct pci_dev *pdev,
357 struct plat_stmmacenet_data *plat)
361 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
363 plat->serdes_powerup = intel_serdes_powerup;
364 plat->serdes_powerdown = intel_serdes_powerdown;
366 return ehl_common_data(pdev, plat);
369 static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
370 .setup = ehl_sgmii_data,
373 static int ehl_rgmii_data(struct pci_dev *pdev,
374 struct plat_stmmacenet_data *plat)
378 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
380 return ehl_common_data(pdev, plat);
383 static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
384 .setup = ehl_rgmii_data,
387 static int ehl_pse0_common_data(struct pci_dev *pdev,
388 struct plat_stmmacenet_data *plat)
392 return ehl_common_data(pdev, plat);
395 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
396 struct plat_stmmacenet_data *plat)
398 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
399 return ehl_pse0_common_data(pdev, plat);
402 static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = {
403 .setup = ehl_pse0_rgmii1g_data,
406 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
407 struct plat_stmmacenet_data *plat)
409 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
410 plat->serdes_powerup = intel_serdes_powerup;
411 plat->serdes_powerdown = intel_serdes_powerdown;
412 return ehl_pse0_common_data(pdev, plat);
415 static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = {
416 .setup = ehl_pse0_sgmii1g_data,
419 static int ehl_pse1_common_data(struct pci_dev *pdev,
420 struct plat_stmmacenet_data *plat)
424 return ehl_common_data(pdev, plat);
427 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
428 struct plat_stmmacenet_data *plat)
430 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
431 return ehl_pse1_common_data(pdev, plat);
434 static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = {
435 .setup = ehl_pse1_rgmii1g_data,
438 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
439 struct plat_stmmacenet_data *plat)
441 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
442 plat->serdes_powerup = intel_serdes_powerup;
443 plat->serdes_powerdown = intel_serdes_powerdown;
444 return ehl_pse1_common_data(pdev, plat);
447 static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = {
448 .setup = ehl_pse1_sgmii1g_data,
451 static int tgl_common_data(struct pci_dev *pdev,
452 struct plat_stmmacenet_data *plat)
456 plat->rx_queues_to_use = 6;
457 plat->tx_queues_to_use = 4;
458 plat->clk_ptp_rate = 200000000;
459 ret = intel_mgbe_common_data(pdev, plat);
466 static int tgl_sgmii_data(struct pci_dev *pdev,
467 struct plat_stmmacenet_data *plat)
471 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
472 plat->serdes_powerup = intel_serdes_powerup;
473 plat->serdes_powerdown = intel_serdes_powerdown;
474 return tgl_common_data(pdev, plat);
477 static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
478 .setup = tgl_sgmii_data,
481 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
488 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
489 .func = galileo_stmmac_func_data,
490 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
493 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
504 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
505 .func = iot2040_stmmac_func_data,
506 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
509 static const struct dmi_system_id quark_pci_dmi[] = {
512 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
514 .driver_data = (void *)&galileo_stmmac_dmi_data,
518 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
520 .driver_data = (void *)&galileo_stmmac_dmi_data,
522 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
523 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
524 * has only one pci network device while other asset tags are
525 * for IOT2040 which has two.
529 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
530 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
531 "6ES7647-0AA00-0YA2"),
533 .driver_data = (void *)&galileo_stmmac_dmi_data,
537 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
539 .driver_data = (void *)&iot2040_stmmac_dmi_data,
544 static int quark_default_data(struct pci_dev *pdev,
545 struct plat_stmmacenet_data *plat)
549 /* Set common default data first */
550 common_default_data(plat);
552 /* Refuse to load the driver and register net device if MAC controller
553 * does not connect to any PHY interface.
555 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
557 /* Return error to the caller on DMI enabled boards. */
558 if (dmi_get_system_info(DMI_BOARD_NAME))
561 /* Galileo boards with old firmware don't support DMI. We always
562 * use 1 here as PHY address, so at least the first found MAC
563 * controller would be probed.
568 plat->bus_id = pci_dev_id(pdev);
569 plat->phy_addr = ret;
570 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
572 plat->dma_cfg->pbl = 16;
573 plat->dma_cfg->pblx8 = true;
574 plat->dma_cfg->fixed_burst = 1;
580 static const struct stmmac_pci_info quark_pci_info = {
581 .setup = quark_default_data,
585 * intel_eth_pci_probe
587 * @pdev: pci device pointer
588 * @id: pointer to table of device id/id's.
590 * Description: This probing function gets called for all PCI devices which
591 * match the ID table and are not "owned" by other driver yet. This function
592 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
593 * matches the device. The probe functions returns zero when the driver choose
594 * to take "ownership" of the device or an error code(-ve no) otherwise.
596 static int intel_eth_pci_probe(struct pci_dev *pdev,
597 const struct pci_device_id *id)
599 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
600 struct intel_priv_data *intel_priv;
601 struct plat_stmmacenet_data *plat;
602 struct stmmac_resources res;
606 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv),
611 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
615 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
616 sizeof(*plat->mdio_bus_data),
618 if (!plat->mdio_bus_data)
621 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
626 /* Enable pci device */
627 ret = pci_enable_device(pdev);
629 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
634 /* Get the base address of device */
635 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
636 if (pci_resource_len(pdev, i) == 0)
638 ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev));
644 pci_set_master(pdev);
646 plat->bsp_priv = intel_priv;
647 intel_priv->mdio_adhoc_addr = 0x15;
649 ret = info->setup(pdev, plat);
653 pci_enable_msi(pdev);
655 memset(&res, 0, sizeof(res));
656 res.addr = pcim_iomap_table(pdev)[i];
657 res.wol_irq = pdev->irq;
660 return stmmac_dvr_probe(&pdev->dev, plat, &res);
664 * intel_eth_pci_remove
666 * @pdev: platform device pointer
667 * Description: this function calls the main to free the net resources
668 * and releases the PCI resources.
670 static void intel_eth_pci_remove(struct pci_dev *pdev)
672 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
673 struct stmmac_priv *priv = netdev_priv(ndev);
676 stmmac_dvr_remove(&pdev->dev);
678 if (priv->plat->stmmac_clk)
679 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
681 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
682 if (pci_resource_len(pdev, i) == 0)
684 pcim_iounmap_regions(pdev, BIT(i));
688 pci_disable_device(pdev);
691 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
693 struct pci_dev *pdev = to_pci_dev(dev);
696 ret = stmmac_suspend(dev);
700 ret = pci_save_state(pdev);
704 pci_disable_device(pdev);
705 pci_wake_from_d3(pdev, true);
709 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
711 struct pci_dev *pdev = to_pci_dev(dev);
714 pci_restore_state(pdev);
715 pci_set_power_state(pdev, PCI_D0);
717 ret = pci_enable_device(pdev);
721 pci_set_master(pdev);
723 return stmmac_resume(dev);
726 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
727 intel_eth_pci_resume);
729 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
730 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
731 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
732 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32
733 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
734 * which are named PSE0 and PSE1
736 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
737 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
738 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2
739 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
740 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
741 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2
742 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
744 static const struct pci_device_id intel_eth_pci_id_table[] = {
745 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) },
746 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) },
747 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) },
748 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) },
749 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID,
750 &ehl_pse0_rgmii1g_pci_info) },
751 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID,
752 &ehl_pse0_sgmii1g_pci_info) },
753 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID,
754 &ehl_pse0_sgmii1g_pci_info) },
755 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID,
756 &ehl_pse1_rgmii1g_pci_info) },
757 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID,
758 &ehl_pse1_sgmii1g_pci_info) },
759 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID,
760 &ehl_pse1_sgmii1g_pci_info) },
761 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) },
765 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
767 static struct pci_driver intel_eth_pci_driver = {
768 .name = "intel-eth-pci",
769 .id_table = intel_eth_pci_id_table,
770 .probe = intel_eth_pci_probe,
771 .remove = intel_eth_pci_remove,
773 .pm = &intel_eth_pm_ops,
777 module_pci_driver(intel_eth_pci_driver);
779 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
780 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
781 MODULE_LICENSE("GPL v2");