1 // SPDX-License-Identifier: GPL-2.0+
3 #include <linux/types.h>
5 #include <linux/platform_device.h>
6 #include <linux/pm_runtime.h>
7 #include <linux/acpi.h>
8 #include <linux/of_mdio.h>
9 #include <linux/of_net.h>
10 #include <linux/etherdevice.h>
11 #include <linux/interrupt.h>
13 #include <linux/netlink.h>
14 #include <linux/bpf.h>
15 #include <linux/bpf_trace.h>
18 #include <net/page_pool.h>
19 #include <net/ip6_checksum.h>
21 #define NETSEC_REG_SOFT_RST 0x104
22 #define NETSEC_REG_COM_INIT 0x120
24 #define NETSEC_REG_TOP_STATUS 0x200
25 #define NETSEC_IRQ_RX BIT(1)
26 #define NETSEC_IRQ_TX BIT(0)
28 #define NETSEC_REG_TOP_INTEN 0x204
29 #define NETSEC_REG_INTEN_SET 0x234
30 #define NETSEC_REG_INTEN_CLR 0x238
32 #define NETSEC_REG_NRM_TX_STATUS 0x400
33 #define NETSEC_REG_NRM_TX_INTEN 0x404
34 #define NETSEC_REG_NRM_TX_INTEN_SET 0x428
35 #define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c
36 #define NRM_TX_ST_NTOWNR BIT(17)
37 #define NRM_TX_ST_TR_ERR BIT(16)
38 #define NRM_TX_ST_TXDONE BIT(15)
39 #define NRM_TX_ST_TMREXP BIT(14)
41 #define NETSEC_REG_NRM_RX_STATUS 0x440
42 #define NETSEC_REG_NRM_RX_INTEN 0x444
43 #define NETSEC_REG_NRM_RX_INTEN_SET 0x468
44 #define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c
45 #define NRM_RX_ST_RC_ERR BIT(16)
46 #define NRM_RX_ST_PKTCNT BIT(15)
47 #define NRM_RX_ST_TMREXP BIT(14)
49 #define NETSEC_REG_PKT_CMD_BUF 0xd0
51 #define NETSEC_REG_CLK_EN 0x100
53 #define NETSEC_REG_PKT_CTRL 0x140
55 #define NETSEC_REG_DMA_TMR_CTRL 0x20c
56 #define NETSEC_REG_F_TAIKI_MC_VER 0x22c
57 #define NETSEC_REG_F_TAIKI_VER 0x230
58 #define NETSEC_REG_DMA_HM_CTRL 0x214
59 #define NETSEC_REG_DMA_MH_CTRL 0x220
60 #define NETSEC_REG_ADDR_DIS_CORE 0x218
61 #define NETSEC_REG_DMAC_HM_CMD_BUF 0x210
62 #define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c
64 #define NETSEC_REG_NRM_TX_PKTCNT 0x410
66 #define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414
67 #define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418
69 #define NETSEC_REG_NRM_TX_TMR 0x41c
71 #define NETSEC_REG_NRM_RX_PKTCNT 0x454
72 #define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458
73 #define NETSEC_REG_NRM_TX_TXINT_TMR 0x420
74 #define NETSEC_REG_NRM_RX_RXINT_TMR 0x460
76 #define NETSEC_REG_NRM_RX_TMR 0x45c
78 #define NETSEC_REG_NRM_TX_DESC_START_UP 0x434
79 #define NETSEC_REG_NRM_TX_DESC_START_LW 0x408
80 #define NETSEC_REG_NRM_RX_DESC_START_UP 0x474
81 #define NETSEC_REG_NRM_RX_DESC_START_LW 0x448
83 #define NETSEC_REG_NRM_TX_CONFIG 0x430
84 #define NETSEC_REG_NRM_RX_CONFIG 0x470
86 #define MAC_REG_STATUS 0x1024
87 #define MAC_REG_DATA 0x11c0
88 #define MAC_REG_CMD 0x11c4
89 #define MAC_REG_FLOW_TH 0x11cc
90 #define MAC_REG_INTF_SEL 0x11d4
91 #define MAC_REG_DESC_INIT 0x11fc
92 #define MAC_REG_DESC_SOFT_RST 0x1204
93 #define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500
95 #define GMAC_REG_MCR 0x0000
96 #define GMAC_REG_MFFR 0x0004
97 #define GMAC_REG_GAR 0x0010
98 #define GMAC_REG_GDR 0x0014
99 #define GMAC_REG_FCR 0x0018
100 #define GMAC_REG_BMR 0x1000
101 #define GMAC_REG_RDLAR 0x100c
102 #define GMAC_REG_TDLAR 0x1010
103 #define GMAC_REG_OMR 0x1018
105 #define MHZ(n) ((n) * 1000 * 1000)
107 #define NETSEC_TX_SHIFT_OWN_FIELD 31
108 #define NETSEC_TX_SHIFT_LD_FIELD 30
109 #define NETSEC_TX_SHIFT_DRID_FIELD 24
110 #define NETSEC_TX_SHIFT_PT_FIELD 21
111 #define NETSEC_TX_SHIFT_TDRID_FIELD 16
112 #define NETSEC_TX_SHIFT_CC_FIELD 15
113 #define NETSEC_TX_SHIFT_FS_FIELD 9
114 #define NETSEC_TX_LAST 8
115 #define NETSEC_TX_SHIFT_CO 7
116 #define NETSEC_TX_SHIFT_SO 6
117 #define NETSEC_TX_SHIFT_TRS_FIELD 4
119 #define NETSEC_RX_PKT_OWN_FIELD 31
120 #define NETSEC_RX_PKT_LD_FIELD 30
121 #define NETSEC_RX_PKT_SDRID_FIELD 24
122 #define NETSEC_RX_PKT_FR_FIELD 23
123 #define NETSEC_RX_PKT_ER_FIELD 21
124 #define NETSEC_RX_PKT_ERR_FIELD 16
125 #define NETSEC_RX_PKT_TDRID_FIELD 12
126 #define NETSEC_RX_PKT_FS_FIELD 9
127 #define NETSEC_RX_PKT_LS_FIELD 8
128 #define NETSEC_RX_PKT_CO_FIELD 6
130 #define NETSEC_RX_PKT_ERR_MASK 3
132 #define NETSEC_MAX_TX_PKT_LEN 1518
133 #define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018
135 #define NETSEC_RING_GMAC 15
136 #define NETSEC_RING_MAX 2
138 #define NETSEC_TCP_SEG_LEN_MAX 1460
139 #define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960
141 #define NETSEC_RX_CKSUM_NOTAVAIL 0
142 #define NETSEC_RX_CKSUM_OK 1
143 #define NETSEC_RX_CKSUM_NG 2
145 #define NETSEC_TOP_IRQ_REG_CODE_LOAD_END BIT(20)
146 #define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4)
148 #define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20)
149 #define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19)
151 #define NETSEC_INT_PKTCNT_MAX 2047
153 #define NETSEC_FLOW_START_TH_MAX 95
154 #define NETSEC_FLOW_STOP_TH_MAX 95
155 #define NETSEC_FLOW_PAUSE_TIME_MIN 5
157 #define NETSEC_CLK_EN_REG_DOM_ALL 0x3f
159 #define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28)
160 #define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27)
161 #define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3)
162 #define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2)
163 #define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1)
164 #define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0)
166 #define NETSEC_CLK_EN_REG_DOM_G BIT(5)
167 #define NETSEC_CLK_EN_REG_DOM_C BIT(1)
168 #define NETSEC_CLK_EN_REG_DOM_D BIT(0)
170 #define NETSEC_COM_INIT_REG_DB BIT(2)
171 #define NETSEC_COM_INIT_REG_CLS BIT(1)
172 #define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \
173 NETSEC_COM_INIT_REG_DB)
175 #define NETSEC_SOFT_RST_REG_RESET 0
176 #define NETSEC_SOFT_RST_REG_RUN BIT(31)
178 #define NETSEC_DMA_CTRL_REG_STOP 1
179 #define MH_CTRL__MODE_TRANS BIT(20)
181 #define NETSEC_GMAC_CMD_ST_READ 0
182 #define NETSEC_GMAC_CMD_ST_WRITE BIT(28)
183 #define NETSEC_GMAC_CMD_ST_BUSY BIT(31)
185 #define NETSEC_GMAC_BMR_REG_COMMON 0x00412080
186 #define NETSEC_GMAC_BMR_REG_RESET 0x00020181
187 #define NETSEC_GMAC_BMR_REG_SWR 0x00000001
189 #define NETSEC_GMAC_OMR_REG_ST BIT(13)
190 #define NETSEC_GMAC_OMR_REG_SR BIT(1)
192 #define NETSEC_GMAC_MCR_REG_IBN BIT(30)
193 #define NETSEC_GMAC_MCR_REG_CST BIT(25)
194 #define NETSEC_GMAC_MCR_REG_JE BIT(20)
195 #define NETSEC_MCR_PS BIT(15)
196 #define NETSEC_GMAC_MCR_REG_FES BIT(14)
197 #define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c
198 #define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c
200 #define NETSEC_FCR_RFE BIT(2)
201 #define NETSEC_FCR_TFE BIT(1)
203 #define NETSEC_GMAC_GAR_REG_GW BIT(1)
204 #define NETSEC_GMAC_GAR_REG_GB BIT(0)
206 #define NETSEC_GMAC_GAR_REG_SHIFT_PA 11
207 #define NETSEC_GMAC_GAR_REG_SHIFT_GR 6
208 #define GMAC_REG_SHIFT_CR_GAR 2
210 #define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2
211 #define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3
212 #define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0
213 #define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1
214 #define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4
215 #define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5
217 #define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000
218 #define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000
220 #define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000
222 #define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31)
223 #define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30)
224 #define NETSEC_REG_DESC_TMR_MODE 4
225 #define NETSEC_REG_DESC_ENDIAN 0
227 #define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1
228 #define NETSEC_MAC_DESC_INIT_REG_INIT 1
230 #define NETSEC_EEPROM_MAC_ADDRESS 0x00
231 #define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08
232 #define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C
233 #define NETSEC_EEPROM_HM_ME_SIZE 0x10
234 #define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14
235 #define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18
236 #define NETSEC_EEPROM_MH_ME_SIZE 0x1C
237 #define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20
238 #define NETSEC_EEPROM_PKT_ME_SIZE 0x24
242 #define NETSEC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
243 #define NETSEC_RXBUF_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \
245 #define NETSEC_RX_BUF_NON_DATA (NETSEC_RXBUF_HEADROOM + \
246 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
247 #define NETSEC_RX_BUF_SIZE (PAGE_SIZE - NETSEC_RX_BUF_NON_DATA)
249 #define DESC_SZ sizeof(struct netsec_de)
251 #define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000)
253 #define NETSEC_XDP_PASS 0
254 #define NETSEC_XDP_CONSUMED BIT(0)
255 #define NETSEC_XDP_TX BIT(1)
256 #define NETSEC_XDP_REDIR BIT(2)
272 struct xdp_frame *xdpf;
280 struct netsec_desc_ring {
282 struct netsec_desc *desc;
285 u16 xdp_xmit; /* netsec_xdp_xmit packets */
286 struct page_pool *page_pool;
287 struct xdp_rxq_info xdp_rxq;
288 spinlock_t lock; /* XDP tx queue locking */
292 struct netsec_desc_ring desc_ring[NETSEC_RING_MAX];
293 struct ethtool_coalesce et_coalesce;
294 struct bpf_prog *xdp_prog;
295 spinlock_t reglock; /* protect reg access */
296 struct napi_struct napi;
297 phy_interface_t phy_interface;
298 struct net_device *ndev;
299 struct device_node *phy_np;
300 struct phy_device *phydev;
301 struct mii_bus *mii_bus;
302 void __iomem *ioaddr;
303 void __iomem *eeprom_base;
309 bool rx_cksum_offload_flag;
312 struct netsec_de { /* Netsec Descriptor layout */
314 u32 data_buf_addr_up;
315 u32 data_buf_addr_lw;
319 struct netsec_tx_pkt_ctrl {
321 bool tcp_seg_offload_flag;
322 bool cksum_offload_flag;
325 struct netsec_rx_pkt_info {
331 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)
333 writel(val, priv->ioaddr + reg_addr);
336 static u32 netsec_read(struct netsec_priv *priv, u32 reg_addr)
338 return readl(priv->ioaddr + reg_addr);
341 /************* MDIO BUS OPS FOLLOW *************/
343 #define TIMEOUT_SPINS_MAC 1000
344 #define TIMEOUT_SECONDARY_MS_MAC 100
346 static u32 netsec_clk_type(u32 freq)
349 return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ;
351 return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ;
353 return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ;
355 return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ;
357 return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ;
359 return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ;
362 static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask)
364 u32 timeout = TIMEOUT_SPINS_MAC;
366 while (--timeout && netsec_read(priv, addr) & mask)
371 timeout = TIMEOUT_SECONDARY_MS_MAC;
372 while (--timeout && netsec_read(priv, addr) & mask)
373 usleep_range(1000, 2000);
378 netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
383 static int netsec_mac_write(struct netsec_priv *priv, u32 addr, u32 value)
385 netsec_write(priv, MAC_REG_DATA, value);
386 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
387 return netsec_wait_while_busy(priv,
388 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
391 static int netsec_mac_read(struct netsec_priv *priv, u32 addr, u32 *read)
395 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
396 ret = netsec_wait_while_busy(priv,
397 MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY);
401 *read = netsec_read(priv, MAC_REG_DATA);
406 static int netsec_mac_wait_while_busy(struct netsec_priv *priv,
409 u32 timeout = TIMEOUT_SPINS_MAC;
413 ret = netsec_mac_read(priv, addr, &data);
417 } while (--timeout && (data & mask));
422 timeout = TIMEOUT_SECONDARY_MS_MAC;
424 usleep_range(1000, 2000);
426 ret = netsec_mac_read(priv, addr, &data);
430 } while (--timeout && (data & mask));
435 netdev_WARN(priv->ndev, "%s: timeout\n", __func__);
440 static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
442 struct phy_device *phydev = priv->ndev->phydev;
445 value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON :
446 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON;
448 if (phydev->speed != SPEED_1000)
449 value |= NETSEC_MCR_PS;
451 if (priv->phy_interface != PHY_INTERFACE_MODE_GMII &&
452 phydev->speed == SPEED_100)
453 value |= NETSEC_GMAC_MCR_REG_FES;
455 value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE;
457 if (phy_interface_mode_is_rgmii(priv->phy_interface))
458 value |= NETSEC_GMAC_MCR_REG_IBN;
460 if (netsec_mac_write(priv, GMAC_REG_MCR, value))
466 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr);
468 static int netsec_phy_write(struct mii_bus *bus,
469 int phy_addr, int reg, u16 val)
472 struct netsec_priv *priv = bus->priv;
474 if (netsec_mac_write(priv, GMAC_REG_GDR, val))
476 if (netsec_mac_write(priv, GMAC_REG_GAR,
477 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
478 reg << NETSEC_GMAC_GAR_REG_SHIFT_GR |
479 NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB |
480 (netsec_clk_type(priv->freq) <<
481 GMAC_REG_SHIFT_CR_GAR)))
484 status = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
485 NETSEC_GMAC_GAR_REG_GB);
487 /* Developerbox implements RTL8211E PHY and there is
488 * a compatibility problem with F_GMAC4.
489 * RTL8211E expects MDC clock must be kept toggling for several
490 * clock cycle with MDIO high before entering the IDLE state.
491 * To meet this requirement, netsec driver needs to issue dummy
492 * read(e.g. read PHYID1(offset 0x2) register) right after write.
494 netsec_phy_read(bus, phy_addr, MII_PHYSID1);
499 static int netsec_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
501 struct netsec_priv *priv = bus->priv;
505 if (netsec_mac_write(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB |
506 phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA |
507 reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR |
508 (netsec_clk_type(priv->freq) <<
509 GMAC_REG_SHIFT_CR_GAR)))
512 ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR,
513 NETSEC_GMAC_GAR_REG_GB);
517 ret = netsec_mac_read(priv, GMAC_REG_GDR, &data);
524 /************* ETHTOOL_OPS FOLLOW *************/
526 static void netsec_et_get_drvinfo(struct net_device *net_device,
527 struct ethtool_drvinfo *info)
529 strlcpy(info->driver, "netsec", sizeof(info->driver));
530 strlcpy(info->bus_info, dev_name(net_device->dev.parent),
531 sizeof(info->bus_info));
534 static int netsec_et_get_coalesce(struct net_device *net_device,
535 struct ethtool_coalesce *et_coalesce)
537 struct netsec_priv *priv = netdev_priv(net_device);
539 *et_coalesce = priv->et_coalesce;
544 static int netsec_et_set_coalesce(struct net_device *net_device,
545 struct ethtool_coalesce *et_coalesce)
547 struct netsec_priv *priv = netdev_priv(net_device);
549 priv->et_coalesce = *et_coalesce;
551 if (priv->et_coalesce.tx_coalesce_usecs < 50)
552 priv->et_coalesce.tx_coalesce_usecs = 50;
553 if (priv->et_coalesce.tx_max_coalesced_frames < 1)
554 priv->et_coalesce.tx_max_coalesced_frames = 1;
556 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
557 priv->et_coalesce.tx_max_coalesced_frames);
558 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
559 priv->et_coalesce.tx_coalesce_usecs);
560 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
561 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
563 if (priv->et_coalesce.rx_coalesce_usecs < 50)
564 priv->et_coalesce.rx_coalesce_usecs = 50;
565 if (priv->et_coalesce.rx_max_coalesced_frames < 1)
566 priv->et_coalesce.rx_max_coalesced_frames = 1;
568 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
569 priv->et_coalesce.rx_max_coalesced_frames);
570 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
571 priv->et_coalesce.rx_coalesce_usecs);
572 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
573 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
578 static u32 netsec_et_get_msglevel(struct net_device *dev)
580 struct netsec_priv *priv = netdev_priv(dev);
582 return priv->msg_enable;
585 static void netsec_et_set_msglevel(struct net_device *dev, u32 datum)
587 struct netsec_priv *priv = netdev_priv(dev);
589 priv->msg_enable = datum;
592 static const struct ethtool_ops netsec_ethtool_ops = {
593 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
594 ETHTOOL_COALESCE_MAX_FRAMES,
595 .get_drvinfo = netsec_et_get_drvinfo,
596 .get_link_ksettings = phy_ethtool_get_link_ksettings,
597 .set_link_ksettings = phy_ethtool_set_link_ksettings,
598 .get_link = ethtool_op_get_link,
599 .get_coalesce = netsec_et_get_coalesce,
600 .set_coalesce = netsec_et_set_coalesce,
601 .get_msglevel = netsec_et_get_msglevel,
602 .set_msglevel = netsec_et_set_msglevel,
605 /************* NETDEV_OPS FOLLOW *************/
608 static void netsec_set_rx_de(struct netsec_priv *priv,
609 struct netsec_desc_ring *dring, u16 idx,
610 const struct netsec_desc *desc)
612 struct netsec_de *de = dring->vaddr + DESC_SZ * idx;
613 u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) |
614 (1 << NETSEC_RX_PKT_FS_FIELD) |
615 (1 << NETSEC_RX_PKT_LS_FIELD);
617 if (idx == DESC_NUM - 1)
618 attr |= (1 << NETSEC_RX_PKT_LD_FIELD);
620 de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
621 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
622 de->buf_len_info = desc->len;
626 dring->desc[idx].dma_addr = desc->dma_addr;
627 dring->desc[idx].addr = desc->addr;
628 dring->desc[idx].len = desc->len;
631 static bool netsec_clean_tx_dring(struct netsec_priv *priv)
633 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
634 struct xdp_frame_bulk bq;
635 struct netsec_de *entry;
636 int tail = dring->tail;
640 spin_lock(&dring->lock);
643 xdp_frame_bulk_init(&bq);
644 entry = dring->vaddr + DESC_SZ * tail;
646 rcu_read_lock(); /* need for xdp_return_frame_bulk */
648 while (!(entry->attr & (1U << NETSEC_TX_SHIFT_OWN_FIELD)) &&
650 struct netsec_desc *desc;
653 desc = &dring->desc[tail];
654 eop = (entry->attr >> NETSEC_TX_LAST) & 1;
657 /* if buf_type is either TYPE_NETSEC_SKB or
658 * TYPE_NETSEC_XDP_NDO we mapped it
660 if (desc->buf_type != TYPE_NETSEC_XDP_TX)
661 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
667 if (desc->buf_type == TYPE_NETSEC_SKB) {
668 bytes += desc->skb->len;
669 dev_kfree_skb(desc->skb);
671 bytes += desc->xdpf->len;
672 if (desc->buf_type == TYPE_NETSEC_XDP_TX)
673 xdp_return_frame_rx_napi(desc->xdpf);
675 xdp_return_frame_bulk(desc->xdpf, &bq);
678 /* clean up so netsec_uninit_pkt_dring() won't free the skb
681 *desc = (struct netsec_desc){};
683 /* entry->attr is not going to be accessed by the NIC until
684 * netsec_set_tx_de() is called. No need for a dma_wmb() here
686 entry->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD;
687 /* move tail ahead */
688 dring->tail = (tail + 1) % DESC_NUM;
691 entry = dring->vaddr + DESC_SZ * tail;
694 xdp_flush_frame_bulk(&bq);
698 spin_unlock(&dring->lock);
703 /* reading the register clears the irq */
704 netsec_read(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT);
706 priv->ndev->stats.tx_packets += cnt;
707 priv->ndev->stats.tx_bytes += bytes;
709 netdev_completed_queue(priv->ndev, cnt, bytes);
714 static void netsec_process_tx(struct netsec_priv *priv)
716 struct net_device *ndev = priv->ndev;
719 cleaned = netsec_clean_tx_dring(priv);
721 if (cleaned && netif_queue_stopped(ndev)) {
722 /* Make sure we update the value, anyone stopping the queue
723 * after this will read the proper consumer idx
726 netif_wake_queue(ndev);
730 static void *netsec_alloc_rx_data(struct netsec_priv *priv,
731 dma_addr_t *dma_handle, u16 *desc_len)
735 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
738 page = page_pool_dev_alloc_pages(dring->page_pool);
742 /* We allocate the same buffer length for XDP and non-XDP cases.
743 * page_pool API will map the whole page, skip what's needed for
744 * network payloads and/or XDP
746 *dma_handle = page_pool_get_dma_addr(page) + NETSEC_RXBUF_HEADROOM;
747 /* Make sure the incoming payload fits in the page for XDP and non-XDP
748 * cases and reserve enough space for headroom + skb_shared_info
750 *desc_len = NETSEC_RX_BUF_SIZE;
752 return page_address(page);
755 static void netsec_rx_fill(struct netsec_priv *priv, u16 from, u16 num)
757 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
761 netsec_set_rx_de(priv, dring, idx, &dring->desc[idx]);
769 static void netsec_xdp_ring_tx_db(struct netsec_priv *priv, u16 pkts)
772 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts);
775 static void netsec_finalize_xdp_rx(struct netsec_priv *priv, u32 xdp_res,
778 if (xdp_res & NETSEC_XDP_REDIR)
781 if (xdp_res & NETSEC_XDP_TX)
782 netsec_xdp_ring_tx_db(priv, pkts);
785 static void netsec_set_tx_de(struct netsec_priv *priv,
786 struct netsec_desc_ring *dring,
787 const struct netsec_tx_pkt_ctrl *tx_ctrl,
788 const struct netsec_desc *desc, void *buf)
790 int idx = dring->head;
791 struct netsec_de *de;
794 de = dring->vaddr + (DESC_SZ * idx);
796 attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) |
797 (1 << NETSEC_TX_SHIFT_PT_FIELD) |
798 (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) |
799 (1 << NETSEC_TX_SHIFT_FS_FIELD) |
800 (1 << NETSEC_TX_LAST) |
801 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) |
802 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) |
803 (1 << NETSEC_TX_SHIFT_TRS_FIELD);
804 if (idx == DESC_NUM - 1)
805 attr |= (1 << NETSEC_TX_SHIFT_LD_FIELD);
807 de->data_buf_addr_up = upper_32_bits(desc->dma_addr);
808 de->data_buf_addr_lw = lower_32_bits(desc->dma_addr);
809 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len;
812 dring->desc[idx] = *desc;
813 if (desc->buf_type == TYPE_NETSEC_SKB)
814 dring->desc[idx].skb = buf;
815 else if (desc->buf_type == TYPE_NETSEC_XDP_TX ||
816 desc->buf_type == TYPE_NETSEC_XDP_NDO)
817 dring->desc[idx].xdpf = buf;
819 /* move head ahead */
820 dring->head = (dring->head + 1) % DESC_NUM;
823 /* The current driver only supports 1 Txq, this should run under spin_lock() */
824 static u32 netsec_xdp_queue_one(struct netsec_priv *priv,
825 struct xdp_frame *xdpf, bool is_ndo)
828 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX];
829 struct page *page = virt_to_page(xdpf->data);
830 struct netsec_tx_pkt_ctrl tx_ctrl = {};
831 struct netsec_desc tx_desc;
832 dma_addr_t dma_handle;
835 if (tx_ring->head >= tx_ring->tail)
836 filled = tx_ring->head - tx_ring->tail;
838 filled = tx_ring->head + DESC_NUM - tx_ring->tail;
840 if (DESC_NUM - filled <= 1)
841 return NETSEC_XDP_CONSUMED;
844 /* this is for ndo_xdp_xmit, the buffer needs mapping before
847 dma_handle = dma_map_single(priv->dev, xdpf->data, xdpf->len,
849 if (dma_mapping_error(priv->dev, dma_handle))
850 return NETSEC_XDP_CONSUMED;
851 tx_desc.buf_type = TYPE_NETSEC_XDP_NDO;
853 /* This is the device Rx buffer from page_pool. No need to remap
854 * just sync and send it
856 struct netsec_desc_ring *rx_ring =
857 &priv->desc_ring[NETSEC_RING_RX];
858 enum dma_data_direction dma_dir =
859 page_pool_get_dma_dir(rx_ring->page_pool);
861 dma_handle = page_pool_get_dma_addr(page) + xdpf->headroom +
863 dma_sync_single_for_device(priv->dev, dma_handle, xdpf->len,
865 tx_desc.buf_type = TYPE_NETSEC_XDP_TX;
868 tx_desc.dma_addr = dma_handle;
869 tx_desc.addr = xdpf->data;
870 tx_desc.len = xdpf->len;
872 netdev_sent_queue(priv->ndev, xdpf->len);
873 netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf);
875 return NETSEC_XDP_TX;
878 static u32 netsec_xdp_xmit_back(struct netsec_priv *priv, struct xdp_buff *xdp)
880 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX];
881 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
885 return NETSEC_XDP_CONSUMED;
887 spin_lock(&tx_ring->lock);
888 ret = netsec_xdp_queue_one(priv, xdpf, false);
889 spin_unlock(&tx_ring->lock);
894 static u32 netsec_run_xdp(struct netsec_priv *priv, struct bpf_prog *prog,
895 struct xdp_buff *xdp)
897 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
898 unsigned int sync, len = xdp->data_end - xdp->data;
899 u32 ret = NETSEC_XDP_PASS;
904 act = bpf_prog_run_xdp(prog, xdp);
906 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
907 sync = xdp->data_end - xdp->data_hard_start - NETSEC_RXBUF_HEADROOM;
908 sync = max(sync, len);
912 ret = NETSEC_XDP_PASS;
915 ret = netsec_xdp_xmit_back(priv, xdp);
916 if (ret != NETSEC_XDP_TX) {
917 page = virt_to_head_page(xdp->data);
918 page_pool_put_page(dring->page_pool, page, sync, true);
922 err = xdp_do_redirect(priv->ndev, xdp, prog);
924 ret = NETSEC_XDP_REDIR;
926 ret = NETSEC_XDP_CONSUMED;
927 page = virt_to_head_page(xdp->data);
928 page_pool_put_page(dring->page_pool, page, sync, true);
932 bpf_warn_invalid_xdp_action(act);
935 trace_xdp_exception(priv->ndev, prog, act);
936 fallthrough; /* handle aborts by dropping packet */
938 ret = NETSEC_XDP_CONSUMED;
939 page = virt_to_head_page(xdp->data);
940 page_pool_put_page(dring->page_pool, page, sync, true);
947 static int netsec_process_rx(struct netsec_priv *priv, int budget)
949 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
950 struct net_device *ndev = priv->ndev;
951 struct netsec_rx_pkt_info rx_info;
952 enum dma_data_direction dma_dir;
953 struct bpf_prog *xdp_prog;
959 xdp_init_buff(&xdp, PAGE_SIZE, &dring->xdp_rxq);
962 xdp_prog = READ_ONCE(priv->xdp_prog);
963 dma_dir = page_pool_get_dma_dir(dring->page_pool);
965 while (done < budget) {
966 u16 idx = dring->tail;
967 struct netsec_de *de = dring->vaddr + (DESC_SZ * idx);
968 struct netsec_desc *desc = &dring->desc[idx];
969 struct page *page = virt_to_page(desc->addr);
970 u32 xdp_result = NETSEC_XDP_PASS;
971 struct sk_buff *skb = NULL;
972 u16 pkt_len, desc_len;
973 dma_addr_t dma_handle;
976 if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) {
977 /* reading the register clears the irq */
978 netsec_read(priv, NETSEC_REG_NRM_RX_PKTCNT);
982 /* This barrier is needed to keep us from reading
983 * any other fields out of the netsec_de until we have
984 * verified the descriptor has been written back
989 pkt_len = de->buf_len_info >> 16;
990 rx_info.err_code = (de->attr >> NETSEC_RX_PKT_ERR_FIELD) &
991 NETSEC_RX_PKT_ERR_MASK;
992 rx_info.err_flag = (de->attr >> NETSEC_RX_PKT_ER_FIELD) & 1;
993 if (rx_info.err_flag) {
994 netif_err(priv, drv, priv->ndev,
995 "%s: rx fail err(%d)\n", __func__,
997 ndev->stats.rx_dropped++;
998 dring->tail = (dring->tail + 1) % DESC_NUM;
999 /* reuse buffer page frag */
1000 netsec_rx_fill(priv, idx, 1);
1003 rx_info.rx_cksum_result =
1004 (de->attr >> NETSEC_RX_PKT_CO_FIELD) & 3;
1006 /* allocate a fresh buffer and map it to the hardware.
1007 * This will eventually replace the old buffer in the hardware
1009 buf_addr = netsec_alloc_rx_data(priv, &dma_handle, &desc_len);
1011 if (unlikely(!buf_addr))
1014 dma_sync_single_for_cpu(priv->dev, desc->dma_addr, pkt_len,
1016 prefetch(desc->addr);
1018 xdp_prepare_buff(&xdp, desc->addr, NETSEC_RXBUF_HEADROOM,
1022 xdp_result = netsec_run_xdp(priv, xdp_prog, &xdp);
1023 if (xdp_result != NETSEC_XDP_PASS) {
1024 xdp_act |= xdp_result;
1025 if (xdp_result == NETSEC_XDP_TX)
1030 skb = build_skb(desc->addr, desc->len + NETSEC_RX_BUF_NON_DATA);
1032 if (unlikely(!skb)) {
1033 /* If skb fails recycle_direct will either unmap and
1034 * free the page or refill the cache depending on the
1035 * cache state. Since we paid the allocation cost if
1036 * building an skb fails try to put the page into cache
1038 page_pool_put_page(dring->page_pool, page, pkt_len,
1040 netif_err(priv, drv, priv->ndev,
1041 "rx failed to build skb\n");
1044 page_pool_release_page(dring->page_pool, page);
1046 skb_reserve(skb, xdp.data - xdp.data_hard_start);
1047 skb_put(skb, xdp.data_end - xdp.data);
1048 skb->protocol = eth_type_trans(skb, priv->ndev);
1050 if (priv->rx_cksum_offload_flag &&
1051 rx_info.rx_cksum_result == NETSEC_RX_CKSUM_OK)
1052 skb->ip_summed = CHECKSUM_UNNECESSARY;
1056 napi_gro_receive(&priv->napi, skb);
1057 if (skb || xdp_result) {
1058 ndev->stats.rx_packets++;
1059 ndev->stats.rx_bytes += xdp.data_end - xdp.data;
1062 /* Update the descriptor with fresh buffers */
1063 desc->len = desc_len;
1064 desc->dma_addr = dma_handle;
1065 desc->addr = buf_addr;
1067 netsec_rx_fill(priv, idx, 1);
1068 dring->tail = (dring->tail + 1) % DESC_NUM;
1070 netsec_finalize_xdp_rx(priv, xdp_act, xdp_xmit);
1077 static int netsec_napi_poll(struct napi_struct *napi, int budget)
1079 struct netsec_priv *priv;
1082 priv = container_of(napi, struct netsec_priv, napi);
1084 netsec_process_tx(priv);
1085 done = netsec_process_rx(priv, budget);
1087 if (done < budget && napi_complete_done(napi, done)) {
1088 unsigned long flags;
1090 spin_lock_irqsave(&priv->reglock, flags);
1091 netsec_write(priv, NETSEC_REG_INTEN_SET,
1092 NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1093 spin_unlock_irqrestore(&priv->reglock, flags);
1100 static int netsec_desc_used(struct netsec_desc_ring *dring)
1104 if (dring->head >= dring->tail)
1105 used = dring->head - dring->tail;
1107 used = dring->head + DESC_NUM - dring->tail;
1112 static int netsec_check_stop_tx(struct netsec_priv *priv, int used)
1114 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
1116 /* keep tail from touching the queue */
1117 if (DESC_NUM - used < 2) {
1118 netif_stop_queue(priv->ndev);
1120 /* Make sure we read the updated value in case
1121 * descriptors got freed
1125 used = netsec_desc_used(dring);
1126 if (DESC_NUM - used < 2)
1127 return NETDEV_TX_BUSY;
1129 netif_wake_queue(priv->ndev);
1135 static netdev_tx_t netsec_netdev_start_xmit(struct sk_buff *skb,
1136 struct net_device *ndev)
1138 struct netsec_priv *priv = netdev_priv(ndev);
1139 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
1140 struct netsec_tx_pkt_ctrl tx_ctrl = {};
1141 struct netsec_desc tx_desc;
1142 u16 tso_seg_len = 0;
1145 spin_lock_bh(&dring->lock);
1146 filled = netsec_desc_used(dring);
1147 if (netsec_check_stop_tx(priv, filled)) {
1148 spin_unlock_bh(&dring->lock);
1149 net_warn_ratelimited("%s %s Tx queue full\n",
1150 dev_name(priv->dev), ndev->name);
1151 return NETDEV_TX_BUSY;
1154 if (skb->ip_summed == CHECKSUM_PARTIAL)
1155 tx_ctrl.cksum_offload_flag = true;
1157 if (skb_is_gso(skb))
1158 tso_seg_len = skb_shinfo(skb)->gso_size;
1160 if (tso_seg_len > 0) {
1161 if (skb->protocol == htons(ETH_P_IP)) {
1162 ip_hdr(skb)->tot_len = 0;
1163 tcp_hdr(skb)->check =
1164 ~tcp_v4_check(0, ip_hdr(skb)->saddr,
1165 ip_hdr(skb)->daddr, 0);
1167 tcp_v6_gso_csum_prep(skb);
1170 tx_ctrl.tcp_seg_offload_flag = true;
1171 tx_ctrl.tcp_seg_len = tso_seg_len;
1174 tx_desc.dma_addr = dma_map_single(priv->dev, skb->data,
1175 skb_headlen(skb), DMA_TO_DEVICE);
1176 if (dma_mapping_error(priv->dev, tx_desc.dma_addr)) {
1177 spin_unlock_bh(&dring->lock);
1178 netif_err(priv, drv, priv->ndev,
1179 "%s: DMA mapping failed\n", __func__);
1180 ndev->stats.tx_dropped++;
1181 dev_kfree_skb_any(skb);
1182 return NETDEV_TX_OK;
1184 tx_desc.addr = skb->data;
1185 tx_desc.len = skb_headlen(skb);
1186 tx_desc.buf_type = TYPE_NETSEC_SKB;
1188 skb_tx_timestamp(skb);
1189 netdev_sent_queue(priv->ndev, skb->len);
1191 netsec_set_tx_de(priv, dring, &tx_ctrl, &tx_desc, skb);
1192 spin_unlock_bh(&dring->lock);
1193 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
1195 return NETDEV_TX_OK;
1198 static void netsec_uninit_pkt_dring(struct netsec_priv *priv, int id)
1200 struct netsec_desc_ring *dring = &priv->desc_ring[id];
1201 struct netsec_desc *desc;
1204 if (!dring->vaddr || !dring->desc)
1206 for (idx = 0; idx < DESC_NUM; idx++) {
1207 desc = &dring->desc[idx];
1211 if (id == NETSEC_RING_RX) {
1212 struct page *page = virt_to_page(desc->addr);
1214 page_pool_put_full_page(dring->page_pool, page, false);
1215 } else if (id == NETSEC_RING_TX) {
1216 dma_unmap_single(priv->dev, desc->dma_addr, desc->len,
1218 dev_kfree_skb(desc->skb);
1222 /* Rx is currently using page_pool */
1223 if (id == NETSEC_RING_RX) {
1224 if (xdp_rxq_info_is_reg(&dring->xdp_rxq))
1225 xdp_rxq_info_unreg(&dring->xdp_rxq);
1226 page_pool_destroy(dring->page_pool);
1229 memset(dring->desc, 0, sizeof(struct netsec_desc) * DESC_NUM);
1230 memset(dring->vaddr, 0, DESC_SZ * DESC_NUM);
1235 if (id == NETSEC_RING_TX)
1236 netdev_reset_queue(priv->ndev);
1239 static void netsec_free_dring(struct netsec_priv *priv, int id)
1241 struct netsec_desc_ring *dring = &priv->desc_ring[id];
1244 dma_free_coherent(priv->dev, DESC_SZ * DESC_NUM,
1245 dring->vaddr, dring->desc_dma);
1246 dring->vaddr = NULL;
1253 static int netsec_alloc_dring(struct netsec_priv *priv, enum ring_id id)
1255 struct netsec_desc_ring *dring = &priv->desc_ring[id];
1257 dring->vaddr = dma_alloc_coherent(priv->dev, DESC_SZ * DESC_NUM,
1258 &dring->desc_dma, GFP_KERNEL);
1262 dring->desc = kcalloc(DESC_NUM, sizeof(*dring->desc), GFP_KERNEL);
1268 netsec_free_dring(priv, id);
1273 static void netsec_setup_tx_dring(struct netsec_priv *priv)
1275 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_TX];
1278 for (i = 0; i < DESC_NUM; i++) {
1279 struct netsec_de *de;
1281 de = dring->vaddr + (DESC_SZ * i);
1282 /* de->attr is not going to be accessed by the NIC
1283 * until netsec_set_tx_de() is called.
1284 * No need for a dma_wmb() here
1286 de->attr = 1U << NETSEC_TX_SHIFT_OWN_FIELD;
1290 static int netsec_setup_rx_dring(struct netsec_priv *priv)
1292 struct netsec_desc_ring *dring = &priv->desc_ring[NETSEC_RING_RX];
1293 struct bpf_prog *xdp_prog = READ_ONCE(priv->xdp_prog);
1294 struct page_pool_params pp_params = {
1296 /* internal DMA mapping in page_pool */
1297 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1298 .pool_size = DESC_NUM,
1299 .nid = NUMA_NO_NODE,
1301 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
1302 .offset = NETSEC_RXBUF_HEADROOM,
1303 .max_len = NETSEC_RX_BUF_SIZE,
1307 dring->page_pool = page_pool_create(&pp_params);
1308 if (IS_ERR(dring->page_pool)) {
1309 err = PTR_ERR(dring->page_pool);
1310 dring->page_pool = NULL;
1314 err = xdp_rxq_info_reg(&dring->xdp_rxq, priv->ndev, 0, priv->napi.napi_id);
1318 err = xdp_rxq_info_reg_mem_model(&dring->xdp_rxq, MEM_TYPE_PAGE_POOL,
1323 for (i = 0; i < DESC_NUM; i++) {
1324 struct netsec_desc *desc = &dring->desc[i];
1325 dma_addr_t dma_handle;
1329 buf = netsec_alloc_rx_data(priv, &dma_handle, &len);
1335 desc->dma_addr = dma_handle;
1340 netsec_rx_fill(priv, 0, DESC_NUM);
1345 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1349 static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg,
1350 u32 addr_h, u32 addr_l, u32 size)
1352 u64 base = (u64)addr_h << 32 | addr_l;
1353 void __iomem *ucode;
1356 ucode = ioremap(base, size * sizeof(u32));
1360 for (i = 0; i < size; i++)
1361 netsec_write(priv, reg, readl(ucode + i * 4));
1367 static int netsec_netdev_load_microcode(struct netsec_priv *priv)
1369 u32 addr_h, addr_l, size;
1372 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_H);
1373 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_ADDRESS_L);
1374 size = readl(priv->eeprom_base + NETSEC_EEPROM_HM_ME_SIZE);
1375 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF,
1376 addr_h, addr_l, size);
1380 addr_h = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_H);
1381 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_ADDRESS_L);
1382 size = readl(priv->eeprom_base + NETSEC_EEPROM_MH_ME_SIZE);
1383 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF,
1384 addr_h, addr_l, size);
1389 addr_l = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_ADDRESS);
1390 size = readl(priv->eeprom_base + NETSEC_EEPROM_PKT_ME_SIZE);
1391 err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF,
1392 addr_h, addr_l, size);
1399 static int netsec_reset_hardware(struct netsec_priv *priv,
1405 /* stop DMA engines */
1406 if (!netsec_read(priv, NETSEC_REG_ADDR_DIS_CORE)) {
1407 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
1408 NETSEC_DMA_CTRL_REG_STOP);
1409 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
1410 NETSEC_DMA_CTRL_REG_STOP);
1412 while (netsec_read(priv, NETSEC_REG_DMA_HM_CTRL) &
1413 NETSEC_DMA_CTRL_REG_STOP)
1416 while (netsec_read(priv, NETSEC_REG_DMA_MH_CTRL) &
1417 NETSEC_DMA_CTRL_REG_STOP)
1421 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
1422 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
1423 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
1425 while (netsec_read(priv, NETSEC_REG_COM_INIT) != 0)
1428 /* set desc_start addr */
1429 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
1430 upper_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1431 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
1432 lower_32_bits(priv->desc_ring[NETSEC_RING_RX].desc_dma));
1434 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
1435 upper_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1436 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
1437 lower_32_bits(priv->desc_ring[NETSEC_RING_TX].desc_dma));
1439 /* set normal tx dring ring config */
1440 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
1441 1 << NETSEC_REG_DESC_ENDIAN);
1442 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
1443 1 << NETSEC_REG_DESC_ENDIAN);
1446 err = netsec_netdev_load_microcode(priv);
1448 netif_err(priv, probe, priv->ndev,
1449 "%s: failed to load microcode (%d)\n",
1455 /* start DMA engines */
1456 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
1457 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
1459 usleep_range(1000, 2000);
1461 if (!(netsec_read(priv, NETSEC_REG_TOP_STATUS) &
1462 NETSEC_TOP_IRQ_REG_CODE_LOAD_END)) {
1463 netif_err(priv, probe, priv->ndev,
1464 "microengine start failed\n");
1467 netsec_write(priv, NETSEC_REG_TOP_STATUS,
1468 NETSEC_TOP_IRQ_REG_CODE_LOAD_END);
1470 value = NETSEC_PKT_CTRL_REG_MODE_NRM;
1471 if (priv->ndev->mtu > ETH_DATA_LEN)
1472 value |= NETSEC_PKT_CTRL_REG_EN_JUMBO;
1474 /* change to normal mode */
1475 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1476 netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
1478 while ((netsec_read(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) &
1479 NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0)
1482 /* clear any pending EMPTY/ERR irq status */
1483 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1485 /* Disable TX & RX intr */
1486 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1491 static int netsec_start_gmac(struct netsec_priv *priv)
1493 struct phy_device *phydev = priv->ndev->phydev;
1497 if (phydev->speed != SPEED_1000)
1498 value = (NETSEC_GMAC_MCR_REG_CST |
1499 NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON);
1501 if (netsec_mac_write(priv, GMAC_REG_MCR, value))
1503 if (netsec_mac_write(priv, GMAC_REG_BMR,
1504 NETSEC_GMAC_BMR_REG_RESET))
1507 /* Wait soft reset */
1508 usleep_range(1000, 5000);
1510 ret = netsec_mac_read(priv, GMAC_REG_BMR, &value);
1513 if (value & NETSEC_GMAC_BMR_REG_SWR)
1516 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
1517 if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1))
1520 netsec_write(priv, MAC_REG_DESC_INIT, 1);
1521 if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1))
1524 if (netsec_mac_write(priv, GMAC_REG_BMR,
1525 NETSEC_GMAC_BMR_REG_COMMON))
1527 if (netsec_mac_write(priv, GMAC_REG_RDLAR,
1528 NETSEC_GMAC_RDLAR_REG_COMMON))
1530 if (netsec_mac_write(priv, GMAC_REG_TDLAR,
1531 NETSEC_GMAC_TDLAR_REG_COMMON))
1533 if (netsec_mac_write(priv, GMAC_REG_MFFR, 0x80000001))
1536 ret = netsec_mac_update_to_phy_state(priv);
1540 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1544 value |= NETSEC_GMAC_OMR_REG_SR;
1545 value |= NETSEC_GMAC_OMR_REG_ST;
1547 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1548 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1550 netsec_et_set_coalesce(priv->ndev, &priv->et_coalesce);
1552 if (netsec_mac_write(priv, GMAC_REG_OMR, value))
1558 static int netsec_stop_gmac(struct netsec_priv *priv)
1563 ret = netsec_mac_read(priv, GMAC_REG_OMR, &value);
1566 value &= ~NETSEC_GMAC_OMR_REG_SR;
1567 value &= ~NETSEC_GMAC_OMR_REG_ST;
1569 /* disable all interrupts */
1570 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1571 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1573 return netsec_mac_write(priv, GMAC_REG_OMR, value);
1576 static void netsec_phy_adjust_link(struct net_device *ndev)
1578 struct netsec_priv *priv = netdev_priv(ndev);
1580 if (ndev->phydev->link)
1581 netsec_start_gmac(priv);
1583 netsec_stop_gmac(priv);
1585 phy_print_status(ndev->phydev);
1588 static irqreturn_t netsec_irq_handler(int irq, void *dev_id)
1590 struct netsec_priv *priv = dev_id;
1591 u32 val, status = netsec_read(priv, NETSEC_REG_TOP_STATUS);
1592 unsigned long flags;
1594 /* Disable interrupts */
1595 if (status & NETSEC_IRQ_TX) {
1596 val = netsec_read(priv, NETSEC_REG_NRM_TX_STATUS);
1597 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
1599 if (status & NETSEC_IRQ_RX) {
1600 val = netsec_read(priv, NETSEC_REG_NRM_RX_STATUS);
1601 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
1604 spin_lock_irqsave(&priv->reglock, flags);
1605 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1606 spin_unlock_irqrestore(&priv->reglock, flags);
1608 napi_schedule(&priv->napi);
1613 static int netsec_netdev_open(struct net_device *ndev)
1615 struct netsec_priv *priv = netdev_priv(ndev);
1618 pm_runtime_get_sync(priv->dev);
1620 netsec_setup_tx_dring(priv);
1621 ret = netsec_setup_rx_dring(priv);
1623 netif_err(priv, probe, priv->ndev,
1624 "%s: fail setup ring\n", __func__);
1628 ret = request_irq(priv->ndev->irq, netsec_irq_handler,
1629 IRQF_SHARED, "netsec", priv);
1631 netif_err(priv, drv, priv->ndev, "request_irq failed\n");
1635 if (dev_of_node(priv->dev)) {
1636 if (!of_phy_connect(priv->ndev, priv->phy_np,
1637 netsec_phy_adjust_link, 0,
1638 priv->phy_interface)) {
1639 netif_err(priv, link, priv->ndev, "missing PHY\n");
1644 ret = phy_connect_direct(priv->ndev, priv->phydev,
1645 netsec_phy_adjust_link,
1646 priv->phy_interface);
1648 netif_err(priv, link, priv->ndev,
1649 "phy_connect_direct() failed (%d)\n", ret);
1654 phy_start(ndev->phydev);
1656 netsec_start_gmac(priv);
1657 napi_enable(&priv->napi);
1658 netif_start_queue(ndev);
1660 /* Enable TX+RX intr. */
1661 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1665 free_irq(priv->ndev->irq, priv);
1667 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1669 pm_runtime_put_sync(priv->dev);
1673 static int netsec_netdev_stop(struct net_device *ndev)
1676 struct netsec_priv *priv = netdev_priv(ndev);
1678 netif_stop_queue(priv->ndev);
1681 napi_disable(&priv->napi);
1683 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1684 netsec_stop_gmac(priv);
1686 free_irq(priv->ndev->irq, priv);
1688 netsec_uninit_pkt_dring(priv, NETSEC_RING_TX);
1689 netsec_uninit_pkt_dring(priv, NETSEC_RING_RX);
1691 phy_stop(ndev->phydev);
1692 phy_disconnect(ndev->phydev);
1694 ret = netsec_reset_hardware(priv, false);
1696 pm_runtime_put_sync(priv->dev);
1701 static int netsec_netdev_init(struct net_device *ndev)
1703 struct netsec_priv *priv = netdev_priv(ndev);
1707 BUILD_BUG_ON_NOT_POWER_OF_2(DESC_NUM);
1709 ret = netsec_alloc_dring(priv, NETSEC_RING_TX);
1713 ret = netsec_alloc_dring(priv, NETSEC_RING_RX);
1717 /* set phy power down */
1718 data = netsec_phy_read(priv->mii_bus, priv->phy_addr, MII_BMCR);
1719 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR,
1722 ret = netsec_reset_hardware(priv, true);
1726 /* Restore phy power state */
1727 netsec_phy_write(priv->mii_bus, priv->phy_addr, MII_BMCR, data);
1729 spin_lock_init(&priv->desc_ring[NETSEC_RING_TX].lock);
1730 spin_lock_init(&priv->desc_ring[NETSEC_RING_RX].lock);
1734 netsec_free_dring(priv, NETSEC_RING_RX);
1736 netsec_free_dring(priv, NETSEC_RING_TX);
1740 static void netsec_netdev_uninit(struct net_device *ndev)
1742 struct netsec_priv *priv = netdev_priv(ndev);
1744 netsec_free_dring(priv, NETSEC_RING_RX);
1745 netsec_free_dring(priv, NETSEC_RING_TX);
1748 static int netsec_netdev_set_features(struct net_device *ndev,
1749 netdev_features_t features)
1751 struct netsec_priv *priv = netdev_priv(ndev);
1753 priv->rx_cksum_offload_flag = !!(features & NETIF_F_RXCSUM);
1758 static int netsec_xdp_xmit(struct net_device *ndev, int n,
1759 struct xdp_frame **frames, u32 flags)
1761 struct netsec_priv *priv = netdev_priv(ndev);
1762 struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX];
1765 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1768 spin_lock(&tx_ring->lock);
1769 for (i = 0; i < n; i++) {
1770 struct xdp_frame *xdpf = frames[i];
1773 err = netsec_xdp_queue_one(priv, xdpf, true);
1774 if (err != NETSEC_XDP_TX)
1777 tx_ring->xdp_xmit++;
1780 spin_unlock(&tx_ring->lock);
1782 if (unlikely(flags & XDP_XMIT_FLUSH)) {
1783 netsec_xdp_ring_tx_db(priv, tx_ring->xdp_xmit);
1784 tx_ring->xdp_xmit = 0;
1790 static int netsec_xdp_setup(struct netsec_priv *priv, struct bpf_prog *prog,
1791 struct netlink_ext_ack *extack)
1793 struct net_device *dev = priv->ndev;
1794 struct bpf_prog *old_prog;
1796 /* For now just support only the usual MTU sized frames */
1797 if (prog && dev->mtu > 1500) {
1798 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP");
1802 if (netif_running(dev))
1803 netsec_netdev_stop(dev);
1805 /* Detach old prog, if any */
1806 old_prog = xchg(&priv->xdp_prog, prog);
1808 bpf_prog_put(old_prog);
1810 if (netif_running(dev))
1811 netsec_netdev_open(dev);
1816 static int netsec_xdp(struct net_device *ndev, struct netdev_bpf *xdp)
1818 struct netsec_priv *priv = netdev_priv(ndev);
1820 switch (xdp->command) {
1821 case XDP_SETUP_PROG:
1822 return netsec_xdp_setup(priv, xdp->prog, xdp->extack);
1828 static const struct net_device_ops netsec_netdev_ops = {
1829 .ndo_init = netsec_netdev_init,
1830 .ndo_uninit = netsec_netdev_uninit,
1831 .ndo_open = netsec_netdev_open,
1832 .ndo_stop = netsec_netdev_stop,
1833 .ndo_start_xmit = netsec_netdev_start_xmit,
1834 .ndo_set_features = netsec_netdev_set_features,
1835 .ndo_set_mac_address = eth_mac_addr,
1836 .ndo_validate_addr = eth_validate_addr,
1837 .ndo_do_ioctl = phy_do_ioctl,
1838 .ndo_xdp_xmit = netsec_xdp_xmit,
1839 .ndo_bpf = netsec_xdp,
1842 static int netsec_of_probe(struct platform_device *pdev,
1843 struct netsec_priv *priv, u32 *phy_addr)
1847 err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_interface);
1849 dev_err(&pdev->dev, "missing required property 'phy-mode'\n");
1853 priv->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1854 if (!priv->phy_np) {
1855 dev_err(&pdev->dev, "missing required property 'phy-handle'\n");
1859 *phy_addr = of_mdio_parse_addr(&pdev->dev, priv->phy_np);
1861 priv->clk = devm_clk_get(&pdev->dev, NULL); /* get by 'phy_ref_clk' */
1862 if (IS_ERR(priv->clk)) {
1863 dev_err(&pdev->dev, "phy_ref_clk not found\n");
1864 return PTR_ERR(priv->clk);
1866 priv->freq = clk_get_rate(priv->clk);
1871 static int netsec_acpi_probe(struct platform_device *pdev,
1872 struct netsec_priv *priv, u32 *phy_addr)
1876 if (!IS_ENABLED(CONFIG_ACPI))
1879 /* ACPI systems are assumed to configure the PHY in firmware, so
1880 * there is really no need to discover the PHY mode from the DSDT.
1881 * Since firmware is known to exist in the field that configures the
1882 * PHY correctly but passes the wrong mode string in the phy-mode
1883 * device property, we have no choice but to ignore it.
1885 priv->phy_interface = PHY_INTERFACE_MODE_NA;
1887 ret = device_property_read_u32(&pdev->dev, "phy-channel", phy_addr);
1890 "missing required property 'phy-channel'\n");
1894 ret = device_property_read_u32(&pdev->dev,
1895 "socionext,phy-clock-frequency",
1899 "missing required property 'socionext,phy-clock-frequency'\n");
1903 static void netsec_unregister_mdio(struct netsec_priv *priv)
1905 struct phy_device *phydev = priv->phydev;
1907 if (!dev_of_node(priv->dev) && phydev) {
1908 phy_device_remove(phydev);
1909 phy_device_free(phydev);
1912 mdiobus_unregister(priv->mii_bus);
1915 static int netsec_register_mdio(struct netsec_priv *priv, u32 phy_addr)
1917 struct mii_bus *bus;
1920 bus = devm_mdiobus_alloc(priv->dev);
1924 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(priv->dev));
1926 bus->name = "SNI NETSEC MDIO";
1927 bus->read = netsec_phy_read;
1928 bus->write = netsec_phy_write;
1929 bus->parent = priv->dev;
1930 priv->mii_bus = bus;
1932 if (dev_of_node(priv->dev)) {
1933 struct device_node *mdio_node, *parent = dev_of_node(priv->dev);
1935 mdio_node = of_get_child_by_name(parent, "mdio");
1939 /* older f/w doesn't populate the mdio subnode,
1940 * allow relaxed upgrade of f/w in due time.
1942 dev_info(priv->dev, "Upgrade f/w for mdio subnode!\n");
1945 ret = of_mdiobus_register(bus, parent);
1946 of_node_put(mdio_node);
1949 dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1953 /* Mask out all PHYs from auto probing. */
1955 ret = mdiobus_register(bus);
1957 dev_err(priv->dev, "mdiobus register err(%d)\n", ret);
1961 priv->phydev = get_phy_device(bus, phy_addr, false);
1962 if (IS_ERR(priv->phydev)) {
1963 ret = PTR_ERR(priv->phydev);
1964 dev_err(priv->dev, "get_phy_device err(%d)\n", ret);
1965 priv->phydev = NULL;
1969 ret = phy_device_register(priv->phydev);
1971 mdiobus_unregister(bus);
1973 "phy_device_register err(%d)\n", ret);
1980 static int netsec_probe(struct platform_device *pdev)
1982 struct resource *mmio_res, *eeprom_res, *irq_res;
1983 u8 *mac, macbuf[ETH_ALEN];
1984 struct netsec_priv *priv;
1985 u32 hw_ver, phy_addr = 0;
1986 struct net_device *ndev;
1989 mmio_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1991 dev_err(&pdev->dev, "No MMIO resource found.\n");
1995 eeprom_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1997 dev_info(&pdev->dev, "No EEPROM resource found.\n");
2001 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2003 dev_err(&pdev->dev, "No IRQ resource found.\n");
2007 ndev = alloc_etherdev(sizeof(*priv));
2011 priv = netdev_priv(ndev);
2013 spin_lock_init(&priv->reglock);
2014 SET_NETDEV_DEV(ndev, &pdev->dev);
2015 platform_set_drvdata(pdev, priv);
2016 ndev->irq = irq_res->start;
2017 priv->dev = &pdev->dev;
2020 priv->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV |
2021 NETIF_MSG_LINK | NETIF_MSG_PROBE;
2023 priv->ioaddr = devm_ioremap(&pdev->dev, mmio_res->start,
2024 resource_size(mmio_res));
2025 if (!priv->ioaddr) {
2026 dev_err(&pdev->dev, "devm_ioremap() failed\n");
2031 priv->eeprom_base = devm_ioremap(&pdev->dev, eeprom_res->start,
2032 resource_size(eeprom_res));
2033 if (!priv->eeprom_base) {
2034 dev_err(&pdev->dev, "devm_ioremap() failed for EEPROM\n");
2039 mac = device_get_mac_address(&pdev->dev, macbuf, sizeof(macbuf));
2041 ether_addr_copy(ndev->dev_addr, mac);
2043 if (priv->eeprom_base &&
2044 (!mac || !is_valid_ether_addr(ndev->dev_addr))) {
2045 void __iomem *macp = priv->eeprom_base +
2046 NETSEC_EEPROM_MAC_ADDRESS;
2048 ndev->dev_addr[0] = readb(macp + 3);
2049 ndev->dev_addr[1] = readb(macp + 2);
2050 ndev->dev_addr[2] = readb(macp + 1);
2051 ndev->dev_addr[3] = readb(macp + 0);
2052 ndev->dev_addr[4] = readb(macp + 7);
2053 ndev->dev_addr[5] = readb(macp + 6);
2056 if (!is_valid_ether_addr(ndev->dev_addr)) {
2057 dev_warn(&pdev->dev, "No MAC address found, using random\n");
2058 eth_hw_addr_random(ndev);
2061 if (dev_of_node(&pdev->dev))
2062 ret = netsec_of_probe(pdev, priv, &phy_addr);
2064 ret = netsec_acpi_probe(pdev, priv, &phy_addr);
2068 priv->phy_addr = phy_addr;
2071 dev_err(&pdev->dev, "missing PHY reference clock frequency\n");
2076 /* default for throughput */
2077 priv->et_coalesce.rx_coalesce_usecs = 500;
2078 priv->et_coalesce.rx_max_coalesced_frames = 8;
2079 priv->et_coalesce.tx_coalesce_usecs = 500;
2080 priv->et_coalesce.tx_max_coalesced_frames = 8;
2082 ret = device_property_read_u32(&pdev->dev, "max-frame-size",
2085 ndev->max_mtu = ETH_DATA_LEN;
2087 /* runtime_pm coverage just for probe, open/close also cover it */
2088 pm_runtime_enable(&pdev->dev);
2089 pm_runtime_get_sync(&pdev->dev);
2091 hw_ver = netsec_read(priv, NETSEC_REG_F_TAIKI_VER);
2092 /* this driver only supports F_TAIKI style NETSEC */
2093 if (NETSEC_F_NETSEC_VER_MAJOR_NUM(hw_ver) !=
2094 NETSEC_F_NETSEC_VER_MAJOR_NUM(NETSEC_REG_NETSEC_VER_F_TAIKI)) {
2099 dev_info(&pdev->dev, "hardware revision %d.%d\n",
2100 hw_ver >> 16, hw_ver & 0xffff);
2102 netif_napi_add(ndev, &priv->napi, netsec_napi_poll, NAPI_POLL_WEIGHT);
2104 ndev->netdev_ops = &netsec_netdev_ops;
2105 ndev->ethtool_ops = &netsec_ethtool_ops;
2107 ndev->features |= NETIF_F_HIGHDMA | NETIF_F_RXCSUM | NETIF_F_GSO |
2108 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2109 ndev->hw_features = ndev->features;
2111 priv->rx_cksum_offload_flag = true;
2113 ret = netsec_register_mdio(priv, phy_addr);
2117 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)))
2118 dev_warn(&pdev->dev, "Failed to set DMA mask\n");
2120 ret = register_netdev(ndev);
2122 netif_err(priv, probe, ndev, "register_netdev() failed\n");
2126 pm_runtime_put_sync(&pdev->dev);
2130 netsec_unregister_mdio(priv);
2132 netif_napi_del(&priv->napi);
2134 pm_runtime_put_sync(&pdev->dev);
2135 pm_runtime_disable(&pdev->dev);
2138 dev_err(&pdev->dev, "init failed\n");
2143 static int netsec_remove(struct platform_device *pdev)
2145 struct netsec_priv *priv = platform_get_drvdata(pdev);
2147 unregister_netdev(priv->ndev);
2149 netsec_unregister_mdio(priv);
2151 netif_napi_del(&priv->napi);
2153 pm_runtime_disable(&pdev->dev);
2154 free_netdev(priv->ndev);
2160 static int netsec_runtime_suspend(struct device *dev)
2162 struct netsec_priv *priv = dev_get_drvdata(dev);
2164 netsec_write(priv, NETSEC_REG_CLK_EN, 0);
2166 clk_disable_unprepare(priv->clk);
2171 static int netsec_runtime_resume(struct device *dev)
2173 struct netsec_priv *priv = dev_get_drvdata(dev);
2175 clk_prepare_enable(priv->clk);
2177 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |
2178 NETSEC_CLK_EN_REG_DOM_C |
2179 NETSEC_CLK_EN_REG_DOM_G);
2184 static const struct dev_pm_ops netsec_pm_ops = {
2185 SET_RUNTIME_PM_OPS(netsec_runtime_suspend, netsec_runtime_resume, NULL)
2188 static const struct of_device_id netsec_dt_ids[] = {
2189 { .compatible = "socionext,synquacer-netsec" },
2192 MODULE_DEVICE_TABLE(of, netsec_dt_ids);
2195 static const struct acpi_device_id netsec_acpi_ids[] = {
2199 MODULE_DEVICE_TABLE(acpi, netsec_acpi_ids);
2202 static struct platform_driver netsec_driver = {
2203 .probe = netsec_probe,
2204 .remove = netsec_remove,
2207 .pm = &netsec_pm_ops,
2208 .of_match_table = netsec_dt_ids,
2209 .acpi_match_table = ACPI_PTR(netsec_acpi_ids),
2212 module_platform_driver(netsec_driver);
2214 MODULE_AUTHOR("Jassi Brar <jaswinder.singh@linaro.org>");
2215 MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
2216 MODULE_DESCRIPTION("NETSEC Ethernet driver");
2217 MODULE_LICENSE("GPL");